RL-970 Silicon-Based Micromachined Packaging Techniques for High Frequency Applications Rashaunda Monique Henderson April 1999 RL-970 = RL-970

SILICON-BASED MICROMACHINED PACKAGING TECHNIQUES FOR HIGH FRQUENCY APPLICATIONS by Rashaunda Monique Henderson A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in The University of Michigan 1999 Doctoral Committee: Professor Linda P. B. Katehi, Chairperson Assistant Professor Liwei Lin Assistant Professor Clark Nguyen Associate Professor Kamal Sarabandi Research Scientist Jack R. East

Rashaunda Monique Henderson 1999 ~ All Rights Reserved

d To my family. ii

ACKNOWLEDGMENTS I would like to give glory, honor, and praise to my Heavenly Father for His faithfulness and love which sustains me. Not only have I had the opportunity to complete my dissertation but I have been able to grow in the Lord and receive peace and wisdom. God's divine plan allowed me to meet my advisor, Prof. Linda P. B. Katehi who has been an excellent example. Her diligence and passion for microwave circuits have created an environment where one can learn and grow, thank you. The following organizations have supported have provided financial support throughout my time at Michigan: Rackham, The EECS Dept., GEM, Intel, Raytheon (E-Systems), ARO, and ONR. I thank my dissertation committee for being patient with my efforts. The faculty, staff, and students in the Radiation Lab and SSEL have helped solve numerous problems to reduce the many challenges found in this research environment. I thank my office mates, John Papapolymerou and Sergio Pacheco for providing comfort, food, and conversation during the stressful days. Friends like Katherine Herrick who know just how you're feeling and can offer that special support will never be forgotten. I thank Kavita and Ude Goverdhanam for their friendship and sleeping bag. iii

TABLE OF CONTENTS DED ICATION............................................... ii ACKNOWLEDGMENTS...................................... iii LIST OF FIGURES.......................................... vii LIST OF TABLES.......................................... xvi LIST OF APPENDICES.............................xviii CHAPTER I. INTRODUCTION......................................... 1 1.1 Motivation....................................... 1 1.2 Dissertation Overview................................ 3 II. BACKGROUND......................................... 5 2.1 Why Silicon for Packaging?............................5 2.1.1 Silicon Properties............................ 6 2.1.2 Other Packaging Materials....................... 7 2.1.3 Ceramics..................................... 7 2.2 The Design Cycle..................................... 9 2.2.1 Anisotropic Etchants.......................... 12 2.3 Sum m ary......................................... 14 iv

III. DEVELOPMENT OF CONFORMAL PACKAGES FOR MONOLITHIC APPLICATIONS................................. 15 3.1 Introduction....................................... 15 3.2 Design........................................... 18 3.2.1 Transm ission Lines........................... 21 3.2.2 Microstrip Patch Antenna.........................26 3.3 Fabrication...........................................29 3.3.1 Substrate Thinning............................. 29 3.3.2 Convex Corner Compensation.....................32 3.4 Measurements...................................... 40 3.4.1 Transmission Line Characteristics.................40 3.4.2 Noise Floor/Coupling.......................... 45 3.4.3 Cross Coupling and Isolation......................46 3.4.4 Antenna Feed Performance.......................49 3.5 Sum m ary............................................ 53 IV. DESIGN OF A SI-BASED CHIP CARRIER FOR DISCRETE, COM PONENTS........................................ 54 4.1 Introduction........................................ 54 4.2 Chip Carrier Design.................................. 56 4.3 Fabrication and Assembly..............................63 4.4 M easurem ents..................................... 65 4.5 Summary.......................................... 74 V. HYBRID TECHNIQUES INTEGRATING CONFORMAL PACKAGING WITH FLIP-CHIP TECHNOLOGY.................. 75 5.1 Introduction......................................... 75 5.2 Circuit and Package Design............................ 78 5.3 Fabrication and Assembly...............................82 5.4 Measurements........................................84 5.4.1 Transmission Line Characteristics................ 84 5.4.2 RF Components................................ 88 5.4.3 DC Bias Components............................92 5.4.4 Single Transistor Measurements................. 96 5.4.5 LNA Measurements.........................100 5.5 Summary........................................ 104 v

VI. PACKAGING FOR THREE-DIMENSIONAL INTEGRATION................................................ 108 6.1 Introduction....................................... 108 6.2 FGC Lines in Multiconductor Environments............ 112 6.3 Initial Design...................................... 115 6.4 Optimization of CPW Distribution Network............. 117 6.4.1 Fabrication Improvements.....................118 6.5 Multiconductor Circuit Performance...................121 6.5.1 Impact on Distribution Network................ 133 6.5.2 Impact on Cross Coupling...................... 135 6.6 Summary........................................ 137 VII. CONCLUSIONS......................................... 139 7.1 Conclusions....................................... 139 7.2 Recommendations.................................140 APPENDICES.............................................. 143 BIBLIOGRAPHY.............................................. 183 vi

LIST OF FIGURES Figure Fig. 2.1:Basic design cycle for microwave circuit..................... 10 Fig. 2.2:Microstrip and coplanar waveguide transmission lines......... 11 Fig. 2.3:Cross-section of <100> Si wafer..............................'13 Fig. 3.1:Concept of cavity widths needed to shield a bending line. The package width on the left is larger than the one on the right by the bend length, Lbend.............................................. 17 Fig. 3.2:Conceptual drawing of packaged microstrip line.............. 19 Fig. 3.3:Circuit topology: (a) Conventional microstrip on full thickness Si. (b) Packaged microstrip on reduced thickness wafer. Dimensions: h=500, W=420, w=210, t=690, L=2300, c=400, d=165, f=140, H=180, g=380, U=1250, T=1300 rm....................................... 20 Fig. 3.4:Layout configurations. (a) Design Layout A: a through line and backto-back right angle bend. (b) Design Layout B: two back-to-back right angle bends.............................................. 20 Fig. 3.5:Dimensions for 50 Q CPW structure analyzed using the pointmatching method.......................................... 23 Fig. 3.6:Structures compared in LineCalc for initial packaged microstrip dimensions.(a) Conventional microstrip, and (b) conductor-backed CPW.. 23 Fig. 3.7:Layout of CPW-to-microstrip transition for probe measurements: a=500, b=985, c=285, d=200, e=1970, f=378<8~, g=385, h=420, i=375, j=385, k=350, 1=150, m=150, n=100, o=p=220, q=132<229~, r=78<320~, s=60, t=10O im.............................................. 25 vii

Fig. 3.8:Layout of CPW-to-packaged microstrip transition: a= 165, b=220, c=435, d=250, e=2470, f=388<15~, g=150, h=210, i=540, j=120, k =114<299~, 1=150 m....................................... 25 Fig. 3.9:The input match (S11) for a patch (W=2.9 mm and L=2 mm) with bending feedline (with and without mitering) compared to a patch with a straight feedline. The patch length was increased to incorporate the frequency shift caused by mitering. See Fig. 3.21 for feedline dimensions..................................................... 28 Fig. 3.10:Fabrication process for lower wafer development.......... 31 Fig. 3.11:Front view drawing of a microstrip line printed on an inverted lower package with dimensions, A=850, B=100, C=400, D=150, E=210, F=380, G=750, H=148 rm. The conductors are indicated with hashed lines. This is a SEM photo of the inverted lower package developed during the two-step etch procedure............................... 32 Fig. 3.12:Micromachined packaged back-to-back right-angle bends. (a) The upper cavity package with probe windows for on-wafer testing. (b) Circuit layout of microstrip line which is printed on the frontside of (c) the lower cavity, which shows the reduced thickness regions in the center with the lower package channels seen as white regions............ 33 Fig. 3.13:Illustration of convex and concave corners in a right-angle bend....................................... 34 Fig. 3.14:Underetching of a convex corner is caused by the fastest etching plane 1211} according to Lee [43]............................. 35 Fig. 3.15:Layout masks showing compensations at convex corners. (a) Lower cavity wafer. (b) Upper cavity wafer. The large squares form the package channels and the small squares form the reduced thickness regions.. 36 Fig. 3.16:Corner compensation marks: (a) CAD drawing of the mask layout, showing the corner compensation required for the formation of the lower cavity package (a=400, b=850, c=1286.5, d=2536.5, e=2351.5, f=400, g=800, h=4687, i=3437 J=100, k=2393.5, 1=2098.5, m=1178, n=800,o=210, p=2068,q=2478,r=4978,s=2098.5) mm. (b) Good compensation from the etch. (c) Poor compensation due to the extended amount of time for the etch.......................................38 Fig. 3.17:Effect of etching on square compensation for a right angle bend. 39 Fig. 3.18:HFSS simulation of 7 mm microstrip line in open and lower shielded configuration........................................... 41 viii

Fig. 3.19:Measurement of 8 mm microstrip line in open and lower shield configuration.......................................... 41 Fig. 3.20:Microstrip effective dielectric constant..................... 42 Fig. 3.21:Electrical response of open microstrip circuits for a delay line and right angle bend (L=13.392 mm).............................. 43 Fig. 3.22:Electrical response of a packaged back-to-back right angle bend and microstrip delay line of similar length (L=13.392 mm)......... 43 Fig. 3.23:(a) Dimensions of open and packaged back-to-back right angle bends: (a=1970, b=2468.5, c=2078.5, d=1898.5, e=2258.5, f=848<31.5, h=5148, I=3648, j=2498.5, k= 2470, 1=4464, m=1709, n=2198.5, o=424<315, p=3163.5, q=2194, r=2288, w=2483.5) pLm. (b) Electrical response of an open and packaged back-to-back right angle bend (L=13.392 mm). The total loss of each line is compared to a delay line of equal physical length (13.392 mm).............................44 Fig. 3.24:Layout for contact noise characterization. The boxes represent probe windows in Design Layout B (Figure 3.4) for the bend-to-bend arrangement. Probing points in the contact noise measurement are indicated by starts at Port 1 for the input signal onto the conducting line at Port 2................................................... 45 Fig. 3.25:Noise data from contact and non-contact measurements......46 Fig. 3.26:Comparison of cross-coupling effects in open microstrip structures for design Layout A and B (See Fig. 3.3)....................... 47 Fig. 3.27:Cross -coupling effects in Design Layout B for two back-to-back right angle bends in open, lower half packaged, and full packaged designs.(See Fig. 3.3)......................................... 48 Fig. 3.28:Comparison of coupling between two packaged back-to-back right angle bends and the contact noise measurement of the packaged system.................................................... 48 Fig. 3.29:HFSS simulation of cross coupling between two straight microstrip lines in the conventional and packaged configurations where 1=7 mm. 49 Fig. 3.30:Conceptual drawing of packaged antenna configuration....... 51 Fig. 3.31:Layout of antennas: (a=1140, b=789, c=2900, d=2200, e=105, f=8135.5, g=2673, h=750, I=970, j=210, K=8835.5, 1=2470, m=183<55, ix

n=7123.5, o=6900, p=2000) Atm................................ 52 Fig. 3.32:Return loss for a patch antenna with open and packaged microstrip feedlines................................................. 52 Fig. 4.1:Actual photograph of K/Ka-Band ceramic package for phase shifter chip.................................................57 Fig. 4.2:Schematic drawing of K/Ka-Band package for phase shifter chip. Courtesy of Yook [58].................................... 58 Fig. 4.3:Transmission lines used in RF input/output interconnects: microstrip, stripline, and shielded microstrip....................... 58 Fig. 4.4:3-Dimensional rendering of Si package...................... 61 Fig. 4.5:Process layers superimposed.......................... 62 Fig. 4.6:Pyramidal via micromachined with anisotropic etchant and Cr/Au overlay pad................................................... 63 Fig. 4.7:Designs for Si package: Design #1-Shifted vias and I/O line, Design #2-Shifted vias and centered I/O line, Design #3-Aligned vias and centered I/O line............................................. 64 Fig. 4.8:Cross-section A'-A of package layers........................ 65 Fig. 4.9:Cross section B-B' shows the assembly of the IC into the package. 66 Fig. 4. 10:Top view of Si package without metal layer or vias filled....... 67 Fig. 4.11:Block diagram of the package interconnects used in the Libra simulation.................................................68 Fig. 4.12:RF input feedthrough with CPW-to-microstrip transition for onwafer measurements....................................... 68 Fig. 4.13:S-Parameters for Libra interconnect simulation, alumina package (within test fixture), and shielded Si package.................... 70 Fig. 4.14:Computed vertical electric field distribution (dB scale) in the asymmetric alumina package at 29.5 GHz. Courtesy of Yook [601........ 71 Fig. 4.15:Cross-section (A'-A) of the alumina and Si package illustrating the cavity side wall created by the vias. (Units in microns.)........... 71 x

Fig. 4.16:Comparison of attenuation for two metal thicknesses for an 8 mm long microstrip line. the typical length with two metal thicknesses.. 73 Fig. 4.17:S-Parameters for a symmetrical package with and without lid added.................................................... 74 Fig. 4.18:S-Parameters for different package designs: Completely symmetric (Design #3), shifted vias (Design #2), asymmetric (Design #1)....... 75 Fig. 5.1:Substrate area for MCM versus substrate area for 3-D technology [68]................................................. 77 Fig. 5.2:Si micromachined two-layer packaged circuit. The upper wafer shields conductors and provides support for vertical integration..... 78 Fig. 5.3:Cross-section of packaged FGC line and upper shielding cavity (with or without metallization) of height hc=275, wg=500, w=53, s=94, hl=500, h2=400, d=385, g=200, wc=800 m......................,79 Fig. 5.4:Schematic diagram of microstrip and FGC 3-stage LNA........ 81 Fig. 5.5:Libra simulated insertion gain for original design (Libra-Ideal) and corrected design (Libra-corrected) for fabrication................. 82 Fig. 5.6:FGC mask layers for LNA.................................83 Fig. 5.7:Photograph of 1/4 of a 4 inch wafer used for fabricating LNA circuit. Notice two circuits in the center with test devices and cal standards on the edges....................................................84 Fig. 5.8:Attenuation for different packaging environments............. 86 Fig. 5.9:Cross-section for conventional, dielectric shielded, and metal shielded FGC lines..............................................87 Fig. 5. 10:Effective dielectric constant for different packaging environments...................................... 87 Fig. 5.11:Cross coupling measurements for different two planar FGC lines (Dimensions in microns)...................................... 88 Fig. 5.12:HFSS simulation of similar FGC layout where the ground planes edges are separated by 871 microns.............................88 Fig. 5.13:Cross coupling between planar lines separated 774 microns edgeto-edge.............................................. 89 xi

Fig. 5.14:0pen balanced stub with dimensions: L1=753, L2=1752, L3=2485, L4=630, L5=698. Units are in microns........................... 90 Fig. 5.15:Photograph of shunt stub and corresponding shielding cavity inverted to show etching and convex corners..................... 90 Fig. 5.16:Comparison between measured and simulated S-parameters for balanced open shunt stubs. The simulation considers air bridges and Tjunctions............................................. 91 Fig. 5.17:Comparison of S-parameters for the balanced open shunt stubs for the fabricated cases (no shield, dielectric shield, metal shield) versus the simulated case............................................ 91 Fig. 5.18:0pen series stub resonator used for DC block. The stub length is 1568 microns for the design frequency of 23 GHz................. 92 Fig. 5.19:Comparison of reflection and transmission coefficients of the open series stub for calculated (Momentum), open (no shield), metal shield, and dielectric shield environments............................ 92 Fig. 5.20:Loss comparisons between measured open-end series stubs.... 93 Fig. 5.21:Layout of resistors in parallel and series................... 94 Fig. 5.22:Cross-section and top view of capacitor structure used in LNA circuits with dimensions: a=500, b=200, c=226, d=160, e=2640, f=220, g=627, h=94 ngm.............................................. 96 Fig. 5.23:Equivalent circuit for capacitors across FGC line............. 97 Fig. 5.24:RF capacitance measurements before and after adding airbridges. 97 Fig. 5.25:Insertion gain for single transistor. Measured on InP wafer (transistor only), mounted without shielding (No shield), and mounted with metal shield covering transmission lines....................... 98 Fig. 5.26:Layout for solder well and flip-chip device (a=1000, b=1000, c=1200, d=200, e=500, f=500: All units in microns).............. 99 Fig. 5.27:Device and pad after bonding to the Si substrate............ 100 Fig. 5.28:The SEC model 410 aligns and attached the flip chip die onto the machine................................................... 100 xii

Fig. 5.29:Measured insertion gain of amplifier using two calibrations with VDS(123)=3 V, VGS(123)=-1.1 V, IDS(TRL)=145 mA, IDS(SOLT)=143 mA................................................. 102 Fig. 5.30:Comparison of insertion gain for Libra_corrected and LibraIE3D simulations........................................... 106 Fig. 5.31:Comparison of measured LNA performance with LibraIE3D simulation.............................................. 07 Fig. 5.32:Comparison of measured LNA with Libra-Physical simulation. 108 Fig. 6.1:Conceptual 3-D view of the W-Band power cube showing the micromachined wafers and metal layers............................... 110 Fig. 6.2:Layout of initial design of distribution network with antenna feed and patch shown. The vertical interconnect is on the bottom side of t]e MMIC layer while the slots and patch antenna are on the feed and antenna layer, respectively.................................. 1.12 Fig. 6.3:3-D environment geometries for the transmission lines........ 114 Fig. 6.4:Attenuation for line architectures........................ 115 Fig. 6.5:Effective dielectric constant for line architectures............115 Fig. 6.6:Single 1 x 4 distribution network: (a) CPW-based Wilkinson distribution network design, (b) Coupled CPW Wilkinson distribution network design.................................................... 117 Fig. 6.7:Performance of first iteration distribution networks where (a) is the CPW-based design and (b) is the CPW/slotline design............ 117 Fig. 6.8:Layout of distribution network and coupling between adjacent ground planes separated by 300 jim.......................... 118 Fig. 6.9:Layout of two 100 Q resistors in parallel to create the 50 9Q termination impedance used in the distribution network. a) Poor alignment, b) additional FGC circuit metal to keep pad dimensions. (Not drawn to scale)................................................. 120 Fig. 6.10:Airbridge arrangement for CPW-based power divider........ 121 Fig. 6.11:Photograph of individual dividers. The ground planes in (a) have been truncated (b) to reduce parasitic effects in the return loss of the in xiii

dividual device............................................... 122 Fig. 6.12:Cross-section of FGC lines used for distribution network design. The wafer thickness if 100 mm and the metal thickness is approximately 1 mm............................................... 123 Fig. 6.13:Layout of final distribution network design................ 124 Fig. 6.14:S-Parameter measurements of the distribution network in a conductor backed environment................................125 Fig. 6.15:Four architectures for individual component measurements... 126 Fig. 6.16:Single divider isolation, input port matched................ 126 Fig. 6.17:Single divider isolation measurements for four architectures.. 127 Fig. 6.18:Tee junction isolation with input port terminated......... 127 Fig. 6.19:Tee junction isolation measurements for four architectures... 128 Fig. 6.20:Tee junction input match for four architectures............. 129 Fig. 6.21:Insertion loss for tee plus bend circuit in four architectures... 129 Fig. 6.22:Tee with bend S parameters for conductor backed and packaged environments............................................130 Fig. 6.23:Measured insertion loss of back-to-back dividers for four architectures...................................................131 Fig. 6.24:Measured S parameters of back-to-back divider for packaged and conductor backed environments............................... 131 Fig. 6.25:Measured insertion loss of double bend circuit for four architectures.................................................... 132 Fig. 6.26:Measured S parameters of double bend in packaged and conductor backed environments........................................ 132 Fig. 6.27:Insertion loss of single divider in four architectures......... 133 Fig. 6.28:S Parameters of single divider for packaged and conductor backed environment......................................... 133 Fig. 6.29:Measured S parameters for distribution network in conductor xiv

backed and packaged environments............................134 Fig. 6.30:Distribution loss for all four outputs is approximately -1.5 +/- 0.3 dB and phase balance is +/- 2 degrees......................... 135 Fig. 6.31:Cross-coupling measurements of layout with metal backed structure and no upper shielding cavity............................. 136 Fig. 6.32:Cross-coupling measurements of layout with upper shielding cavity and Si carrier..............................................137 Fig. 7. 1:Simulated response of coupling between 50 Q microstrip lines separated by the distances of 1.58, 2.58, and 4.58 mm................ 142 Fig. 7.2:Simulated response of coupling between 50 0 FGC lines separated by no distance, 0.87 mm, and 1.6 mm......................... 142 p xv

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LIST OF APPENDICES Apendix A. HOW MMIC PROCESSING AFFECTS THE ATTENUATION OF FGC LINES AT W-BAND..................................... 144 A.1 Introduction.......................................... 144 A.2 Methods......................................... 145 A.3 Results............................................ 146 A.4 Summary.......................................... 149 B. FABRICATION OF PACKAGED MICROSTRIP................. 150 B.1 Introduction........................................ 50 B.2 Circuit Wafer with Lower Cavity........................ 150 B.3 Shielding Cavity Fabrication............................... 156 C. FABRICATION OF SILICON CHIP CARRIER.................. 160 C.1 Introduction............................................160 C.2 Fabrication Steps........................................160 D. FABRICATION OF A 3-STAGE LNA CIRCUIT................. 165 D.1 Introduction...........................................165 D.2 Circuit Wafer Fabrication.............................. 165 D.3 Shielding Cavity Fabrication............................ 171 E. FABRICATION OF W-BAND OUTPUT DISTRIBUTION NETWORK...............................................175 E.1 Introduction...........................................175 E.2 Circuit Wafer Fabrication.............................. 175 E.3 Shielding Cavity Fabrication............................ 179 xviii

CHAPTER I INTRODUCTION 1.1 Motivation Once used exclusively by the defense industry, the technology for radio frequency (RF), microwave, and millimeter-wave systems is now becoming more important to the commercial sectors, automotive, medical, and communications (ground- and space-based) industries [1]. Performance, cost, and reliability of the product are three factors which govern the type of technology used in production. Space communications and medical industries desire reliable high performance components. The ground-based communications sector emphasizes a low-cost solution. It is estimated that by the year 2003, approximately one-third of the U.S. population will use wireless phone services. Therefore, the development of high-performance, low-cost circuits is important. Circuit design and integrated circuit (IC) fabrication techniques have become so advanced that components are being developed that meet single circuit specifications, but limit overall performance when incorporated into a system. In recent years, however, it has been shown that the electronic packaging for many of these components is a primary source of system degradation [2]. Thus, poor design and fabrication of packages have led to increased cavity resonances and cross-talk between neighboring circuits. 1

2 Everyone in the semiconductor industry will admit to neglecting package design to improve circuit performance and to considering the package after the component has been optimized [3], [4], [5]. Now that the package has become a limiting factor in high-frequency system development, it is very important to include package development within the circuit design cycle. An electronic package must provide electrical, mechanical, and thermal support for a circuit. The package design must also be amenable to the circuit it is protecting by providing low loss interconnects. The mechanical structure of the package should provide stability for the circuit and protect it from harsh environmental conditions. Because electrical circuits dissipate energy in the form of heat, thermal properties of the packaging material are important. Materials which function as heat sinks are desired for high-frequency highpower applications. These characteristics have been quantified as material properties and ultimately are useful if the material can be machined to protect the electronic device. Given these basic requirements in addition to the fact that the circuits are operating at high frequencies, novel packaging schemes are needed. Not until industry decides on a standard technology, will batch fabrication be used to realize low-cost packages for millimeter-wave applications. Plastic packages are low in cost but offer high electrical protection only up to 5 GHz [6]. Despite the fact that alumina package performance is better, it begins to degrade beyond 10 GHz and provides inadequate thermal protection [7],[8]1. The research question this dissertation addresses is: Can silicon (Si) be used as an electronic packaging material for high-frequency circuits? Although the electrical properties of Si have resulted in it being the choice as the standard for very large scale integration (VLSI) design, microelectromechanical systems (MEMs) research has taken advantage of the mechanical

3 properties and developed low-cost, high-performance sensors and actuators [91, [10]. Within the last 10 years, Si micromachining techniques have been used to improve high-frequency circuit performance and to develop monolithic packages that mechanically protect circuits [11], [12]. The excellent electrical results obtained from these efforts have been the stimulus for continued exploration of Si as a packaging material for high-frequency applications. This research is important because it will show the feasibility of using packaged Si circuits for millimeter wave three-dimensional on-wafer systems. 1.2 Dissertation Overview The experimental characterization of Si-based packages for high-frequency applications is presented in this dissertation. Designs have been developed using simulation tools and low-frequency models. Prototype packaged circuits have been fabricated and tested for electrical performance. Results for transmission line characteristics and cross-coupling are used to extend the designs to high-frequency microwave and millimeter-wave systems. Following is an overview of the organization of the dissertation. Chapter 2 explains the evolution of Si from an electrical material to a mechanical material in microwave circuit design. The properties of Si are presented and compared to currently used packaging materials. Chapter 3 presents the characterization of an integrated conformal package for monolithic applications. Parasitic radiation typical in microstrip and due to bending geometries is reduced by incorporating the package design with the circuit. Cross-talk between neighboring microstrip lines is eliminated and allows for increased circuit density on the substrate. Variable substrate thick

4 ness wafers are developed which offer an additional degree of freedom for the circuit designer, when posed with the challenge of incorporating circuits and antennas on one substrate for optimal performance. Chapter 4 presents the development of a Si-based package for discrete components. This effort is intended to show that Si micromachining techniques can be used to realize single-chip as well as on-wafer packages that offer highperformance capability up to 40 GHz. The package can be scaled to higher frequency applications and if batch-fabricated, cost an order of magnitude less than it's conventional alumina counterpart. Chapter 5 presents a study of on-wafer packaging for K-Band circuits. The influence of metal and dielectric shielding on finite ground coplanar (F(ITC) lines is compared to a conventional unshielded line. Si micromachining is incorporated with flip chip bonding techniques to realize a three-stage lownoise amplifier (LNA) circuit with monolithic packaging. Chapter 6 reports on an extensive study of three-dimensional. environment effects on high-frequency planar circuits. The development of on-wafer packaging for a 94 GHz multi-level antenna array system is demonstrated with detailed characterization on the performance of four (1 x 4) output distribution networks in various packaging architectures. Chapter 7 summarizes the work presented in the dissertation with concluding remarks and recommendations for future research.

CHAPTER II BACKGROUND 2.1 Why Silicon for Packaging? Silicon (Si) has been the material of choice for ICs in the semiconductor industry since the late 1950s. It surpassed germanium in the area of electrical performance and high-temperature processing for transistors. The first planar IC process with a monolithic transistor was demonstrated by Noyce in 1959 at Fairchild Semiconductor [13] and started the microelectronics revolution. Because Si is used for 90% of all ICs today, characterization and development of the material have resulted in low-cost wafer processes which produce excellent individual circuit performance. With the advent of World War II and the use of radar (Radio Detection and Ranging), an extensive amount of research was conducted in the area of microwave engineering. In the 1940s the Radiation Laboratory was established at MIT where microwave network theory and experimental and theoretical studies of waveguides were developed by top physicists [14]. Although the introduction of the waveguide revolutionized the microwave industry, this transmission line was large, expensive, and limited in bandwidth. The development of planar transmission lines began as far back as the 1930s but research in earnest came in the 1950s with the invention of the stripline by R. M. Barrett [15]. With the advances seen in the semiconductor industry, micro 5

6 wave engineers decided to incorporate those techniques to develop miniaturized microwave integrated circuits for communication and radar applications in the early 1960s. Because the processing techniques in the semiconductor industry were automated, performance of microwave circuits improved tremendously. These microwave integrated circuits (MICs) offered a reduction in size, volume, and cost. While extensive Si research was taking place in the electronics industry, the transducers industry was investigating Si for various reasons as well. Micromachining techniques were used to create low-cost, high volume, miniaturized visible image sensors (1960s), pressure sensors (1970s), and microsystems (1980s), devices which integrate mechanical and signal-processjng electronics. In the late 1980s, microwave engineers became aware of how micromachining techniques could be useful in removing material in Si circuits and thereby reducing parasitic effects observed at high frequencies. Efforts were begun at California Institute of Technology [161 and the University of Michigan [17] [18], [19] to incorporate micromachining techniques to develop high-performance interconnects, antennas, and passive circuits. TIb reduce high-frequency measurement errors, Drayton and Katehi proposed a micromachined package circuit for Si-based circuits [20]. By incorporating an upper shielding cavity, Drayton and Katehi reduced radiation loss and could measure the true effects of the circuit within a packaged environment. Since that time, efforts have been made to develop Si-based packages for high-frequency circuits and antennas.

7 2.1.1 Silicon Properties Materials for electronic packages are very important to the microwave engineer. In addition to providing the electronic circuit with physical support and thermal protection, the package transfers energy from the rest of the system to the individual circuit. In high-frequency applications where it has been proven that the package limits performance of the circuits, it is very important to incorporate the electrical characteristics of the packaging material when designing a microwave system. The electrical properties of Si have enabled the semiconductor industry to use it as the primary dielectric material in developing ICs [1-21] while the mechanical properties of Si have been utilized to develop high performance MEMs structures. These two properties in addition to the thermal characteristics of Si make it a potential candidate for packaging high-frequency circuits. 2.1.2 Other Packaging Materials The most commonly used packaging materials are plastics and ceramics. Thermoplastic and thermoset plastics are the least expensive packaging materials and work well at low frequencies. As the frequency increases to approximately 3 GHz, this material is no longer useful because of performance limitations. In addition, defense-related applications require extensive testing and long-lifetime capabilities, while most plastic packages experience early failure in adverse environment conditions.

8 2.1.3 Ceramics Ceramics are more popular for applications up to 20 GHz, with aluminum oxide, beryllium oxide, and aluminum nitride (AMN) the materials ordinarily used. Aluminum oxide (alumina) is by far the most characterized of these materials and provides excellent insulation and mechanical support for low power circuits. High-power applications require packaging materials with thermal conductivity values that allow it to function as a heat sink for the circuit. Beryllium oxide (beryllia) is the material of choice for high power specifications because its thermal conductivity is ten times greater than that of alumina. The cost of beryllia and toxicity of the material limit its use to extreme situations where high-power efficiency is very important. The t~lermal coefficient of expansion (TCE) for alumina is another limiting factor of this packaging material, especially when varying temperature conditions exist for circuit applications. The TCE of AMN is very close to that of Si and other semiconductor materials, while the TCE of alumina is greater, which implies the packaging material will expand more easily due to temperature changes. AMN is an expensive and relatively new material which is being used for specific applications but has still not been firmly adopted by industry. No one ceramic material can satisfy all the requirements for high-frequency circuit packages and the introduction of another potential substrate will provide the industry with more design options. Table 2.1 lists mechanical and thermal properties of alumina (A1203) and Si.

9 Properties Si Al203 Thermal conductivity, W/m"K 150 20 CTE from 25-400 ~C 3.5 7.1 Density, g/cm3 2.33 3.75 single 5 Grain size, gm sie 5.0 crystal Yield Strength, 1010 dyne/cm2 7.0 15.4 Bonding strength, kg/mm2 10-50 25-35 Young's modulus, 1012 dyne/cm2 1.9 5.3 Poisson ratio 0.2782 0.22 Sintering temperature, ~C 1412 (MP) 1300 Knoop Hardness, kg/mm2 850 2100 Max. use temp. (nonoxidizing 1400 1500 atmosphere), ~C Dielectric constant 11.7 8.9-10.2 Table 2.1: Mechanical and thermal properties of alumina and Si. 2.2 The Design Cycle The design cycle for conventional high-frequency circuits typically incorporates packaging requirements after circuit performance optimization. Lowfrequency cavity resonances and incompatible thermal characteristics are two common problems which limit the performance of the circuits. By including package requirements along with circuit specifications in the initial design, the chances of developing a component which will perform as expected is much higher. Figure 2.1 shows the design cycle used in developing the packaged circuits presented in this dissertation.

10 Fig. 2.1: Basic design cycle for microwave circuit. Design specifications typically include a proposed budget, time-line, and performance requirements. Depending on the application, a designer may be

11 limited in the line architecture which can be used. The two transmission lines most commonly used for circuit design in this dissertation are microstrip and coplanar waveguide (CPW). Center Conductor Ground Plane Microstrip Ground Planes Center Conductor Coplanar Waveguide Fig. 2.2: Microstrip and coplanar waveguide transmission lines. Both lines can be easily fabricated using photolithographic techniques and propagate a single mode. A large library of closed form expressions have been derived for microstrip and make it easier to simulate and optimize the line for circuit design. Higher order modes, parasitic radiation, and losses are introduced when discontinuities exist along the line, or it is operating near the cut

12 off frequency which is dictated by the line geometry and substrate thickness. Variations of the microstrip line have been introduced to accommodate for the wide range of design needs. With CPW transmission lines the conductors are printed on the top side of the substrate material and mounting devices in shunt or series arrangements can be easily done. Micromachining techniques can be combined with standard planar transmission line processing to develop on-wafer shielding cavities for circuits and interconnects. These cavities provide a packaged environment which helps reduce the parasitics most commonly found in these structures. This technique increases the number of options for the designer when low loss and high isolation may be major design concerns. I 2.2.1 Anisotropic Etchants The anisotropic etchants used to micromachine Si are listed in Table 2.2:. The fastest and most toxic etchant is ethylene diamine pyracathecol (EDPf) with an etch rate of 80 pm/hr on the <100> crystal plane [22], [231. By adjusting the chemical composition and reducing the temperature, the etch rate can be reduced to 40 gm/hr a more controllable rate for etching very thin Si (<200 gim). Potassium hydroxide (KOH) is a safer etchant with a slower etch rate (30 Im/hr) but etches silicon dioxide (SiO2) a common masking film [24]. Tetramethyl ammonium hydroxide (TMAH) is also very safe and etches Si at a rate of 35 gm/hr [25]. The etch rate can be increased by adding deionized water (DI water) but hillocks can be formed and ruin the smooth sidewall profile. The <111> crystal plane acts as an etch stop and realizes the pyramidal shape shown in Fig. 2.3.

13 EtchantCo osition Temp. Etch Rate Masking Safetv Etchant Composition C m Films ~C ((im/hr) Films Ethylene Diamine 150mL EDPf Pyraztne 0.9 g 110 80 Si Toxic Catechol 48 g Si3N4 DI Water 48 mL Ethylene Diamine 150mL EDPS Pyrazine 0.9 g 100 40 SiO2, Toxic DS Catechol 32 g Si3N4 DI Water 48 mL KOH OH80 g 65 30 Si Safe DI Water 80 mL 65 4 TMAH TMAH, 25 wt.% 100 35 Si02, Safe Tal_22_____ eSi3N4 V Table 2.2: Anisotropic etchants. Anisotropic Etchants (EDP, KOH, TMAH) Dielectric Etch Mask (SiO2, Si3N4) <100> A <111> A -74 Fig. 2.3: Cross-section of <100> Si wafer.

14 2.3 Summary The following four chapters give technical detail about the design, fabrication, and testing of micromachined Si packaged circuits and interconnects Kto W-Band applications. Electronic packages for discrete, monolithic, and hybrid applications will be presented. The common theme in each design is the integration of standard IC processing with Si micromachining techniques to produce a high performance package for circuits which can be batch-fabricated to reduce manufacturing costs.

CHAPTER III DEVELOPMENT OF CONFORMAL PACKAGES FOR MONOLITHIC APPLICATIONS 3.1 Introduction Dense circuit and antenna layouts in many high-frequency applications suffer from poor performance due to cross-talk between neighboring elements.. In fact, as the criteria for high-performance circuits require better cost-effective solutions that are small, lightweight, and compact, techniques to reduce crosstalk will have an even larger impact on improving the overall performance of circuits implemented in on-chip configurations. Low-cost solutions that produce compact circuit designs heavily depend on the ability to utilize existing circuit space. Unfortunately, as more circuits are located in close proximity to each other, cross-talk effects become more pronounced, especially as the operating frequency increases. In the past, design solutions focused on reducing system size and weight, but were limited in overall success because of failure to achieve high electronic circuit isolation. Using advanced computational methods and high-speed computer resources, simulations were employed to predict individual circuit performance. Complex layouts were implemented using CAD tools for system realization, however, the measured electrical perfor 15

16 mance was degraded because the simulations did typically consider electromagnetic interactions between closely spaced components. Cross-talk occurred from unwanted signal propagation within the circuit environment either in air or through the substrate and reduced the systethm performance. Several design approaches have been investigated to reduce the interactions between elements placed in close proximity within a given circuit layout. One approach uses sophisticated numerical models to determine the appropriate component placement for a variety of planar geometries [26]. While the results offered layout solutions which address performance requirements, space and size criteria were not met by these designs. Another approach separates large systems into smaller units with comparable circuit functions (similar to multi-chip-modules) [27] to minimize the interactions. Although effective for large scale integrated (LSI) circuits, this approach does not address the issues associated with electromagnetic field interactions due to the excitation of waves in the substrate. In addition to the above, conventional packaging in high-frequency circuit designs, however, suffer from parasitic coupling between the circuit and package due to low-frequency resonances created by the large package housing. With the advances in semiconductor integrated circuit (IC) and monolithic microwave IC (MMIC) processing today, novel solutions can be implemented so that both the design specifications and electrical performance requirements can be met. In the early eighties, Petersen [21] predicted that Si as a mechanical material could be used to develop high-precision, miniaturized structures that offer high performance. Since then, RF micromachining of Si has become an enabling technology to high-frequency circuit design [28]. Si micromachined packages for CPW circuits have been characterized with miniature upper and/or lower cavities that shield the circuit conductor and

17 dielectric to reduce parasitic radiation and substrate modes [20]. In this study, micromachined conformal packages are designed to shield meander microstrip lines commonly found in high density layouts. These monolithic housings offer a shielded environment to each transmission line, and have package resonances at much higher frequencies than rectangular packages (Fig. 3.1) [29]. In an effort to explore the effectiveness of packaging individual lines to reduce cross-talk and improve high-frequency propagation, performance comparisons are made between conventional and packaged microstrip. Two meander lines are placed less than an inch away from each other to study how cross coupling is reduced with upper and lower shielding cavities. I i... JLJ^ - r ) ~U I I I^ I i i i i i i.. —. I I _____ I Fig. 3.1: Concept of cavity widths needed to shield a bending line. The package width on the left is larger than the one on the right by the bend length, Lbend.

18 3.2 Design This section presents the development of a conformal package for microstrip-based circuits. Microstrip is one of the most commonly used transmission line media in high-frequency planar circuits and antennas due to its small size, low profile, and ease in formability, as well as the benefits offered by the availability of circuit design models and simulation tools. Although this line is one of the most popular, it is highly susceptible to radiation loss caused by discontinuities and substrate mode leakage [39]. Radiation loss can be eliminated by adding a miniaturized shield to the line when micromachined packages are included. A packaged microstrip transmission line consists of an air-filled upper cavity and a Si-filled lower cavity (Fig. 3.2). The microstrip signal line and ground plane are printed on the front- and backside of the lower cavity wafer, respectively. The upper cavity is metallized and the two wafers are placed into direct metal contact by printing ground pads and etching vias in the lower cavity. For alignment purposes metal crosses are printed on the lower cavity and appropriately sized windows are etched in the upper cavity to align the two wafers with 20 ~ 5 ptm accuracy. Silver epoxy is placed on the lower cavity wafer for adhesion to the upper cavity. The transmission line layout is classified either by topology and/or layout configuration. The two topologies (Fig. 3.3) considered are: (1) conventional microstrip, referred to as "open," or (2) micromachined shielded microstrip, referred to as "packaged." The description of transmission line cross-coupling can be distinguished by the layout configurations (Fig. 3.4), A and B, where (A) includes an adjacent straight through line and back-to-back (B-B) right

19 angle bend referred to as "through-to-bend", and (B) includes two adjacent back-to-back right-angle bend geometries referred to as "bend-to-bend". Metallized Micromachined Micromachined / -. ||- \Upper Cavity Lower Cavity s: B round pad / Shielding groove/ Microstrip Ground plane via trench Signal line Fig. 3.2: Conceptual drawing of packaged microstrip line.

20 f i.U; t I i w.4 1 c —p I? A II Ihi } 2h HSV~a d (a) (b) Fig. 3.3: Circuit topology: (a) Conventional microstrip on full thickness Si. (b) Packaged microstrip' on reduced thickness wafer. Dimensions: h=50 W=420, w=210, t=690, L=2300, c=400, d=165, f=140, H=180, g=380, U=1250, T=1300 Cim. CPW Probe Pads I 1. Ki I __ I j -- 5.23mm i 2.55mm __ 4 - i i / 3.30 mm - L di q~i r - CPW-to-Microstrip Transition (a) (b) Fig. 3.4: Layout configurations. (a) Design Layout A: a through line and back-to-back right angle bend. (b) Design Layout B: two back-to-back right angle bends.

21 3.2.1 Transmission Lines The dimensions of the conventional microstrip have been calculated from the following closed-form expression developed by Hammerstad and Jensen [321 for the characteristic impedance (Zoair) as a function of substrate thickness and conductor width: + 1 + 2]Zoair(() = Infu + (3.1) where f(u) = 6+(2r -6)exp[- (306667528 (3.2) and u=W/h and r=120n 0Q. The effective dielectric constant (Ere) is expressed as: ~r+ Er - ( 10 -a(u)b(r,) e = + 2 + (3.3) where a(u) = + 1 n(u 4+(u/52)2 1 n[l +( ] a(u) = 49 u4 + 0.432 ) 18.2 (3.4) and,

22 6 r-0.9 0.053s b(~r) = 0.564[ j ) j3. The characteristic impedance for the line printed on a dielectric material, ZOm is: Z7 air (3.6) LOm = Ere Given these expressions, the width and ere for a 50 Q line on 500 ugm-thlck Si is found using HP Libra [30] to be, W=420 m, ~re=8.42 at 20 GHz. The bottom wafer of the packaged microstrip cross-section looks similar to conductor-backed CPW because ground pads are printed to make contact between the lower ground plane and metallized upper shielding cavity wafer (Fig. 3.2). A code developed by Dib using the point matching method is used to determine the line geometry for the packaged circuit [31]. For a 500 nim thick Si wafer, the packaged line geometry would require a 420 jim microstrip conductor width and ground pads placed 1150 gim away. This cavity width for such a structure would be 3 mm wide and would reduce the high frequency performance of the line. By reducing the substrate thickness to 350 im a narrower 50 Q line and package can be fabricated. Using the point-matching method a 50 Q CPW structure was realized with the predicted dimensions shown in Fig. 3.5. Closed form expressions in HP Libra for open conductor-backed CPW [34] and shielded microstrip confirm the predicted will produce a 50 Q line. Table 3.1 lists the impedance and effective dielectric con

23 stant values obtained with the new geometry. The CPWG and microstrip expressions produced a line with an impedances between 53 and 55 Q and after adding a cover and sidewalls, the microstrip line impedance approached 50 2 exactly. To ease on-wafer measurements, CPW probe pads have been fabricated at the feed point and transitioned to the 50 Q microstrip line geometry to minimize mismatch [35]. The vias and shielding grooves required for ground plane equalization in each structure are identified in Fig. 3.7 by the shaded regions. 500 350 350 1000 Fig. 3.5: Dimensions for 50 QC CPW structure analyzed using the point-matching method. W. X,.,.- \:i.......,A........: -:''..,-..'. *:.., -- - - -. ---. -.-. I A;::::-'::a:j:~~:::~ i: I:;;:.':ri'~~ IT.~~, ""I~~~~ I~ ~,~~ ~ ~ ~ ~ '. h~;;~..~.. W G + — * 4-* h (a) (b) Fig. 3.6: Structures compared in LineCalc for initial packaged microstrip dimensions.(a) Conventional microstrip, and (b) conductor-backed CPW.

24 Package Line Type Zo(2) eff W(gm) G(gm) h(4m) Width (mm) Microstrip 50 8.42 420 n/a 500 n/a CPWG 50 7.80 420 1150 500 3 Microstrip 57 7.86 210 n/a 350 n/a CPWG 54.6 7.14 210 380 350 1.3 Microstrip w/ 350 gm cover 51 6.84 210 n/a 350 1.3 and 380 gm wall Microstrip 55 7.87 210 n/a 320 n/a CPWG 53 7.234 210 380 320 1.3 Microstrip w/ 400 gm cover 49.6 6.93 210 n/a 320 1.3 and 380 gm wall Table 3.1: Dimensions for lines developed using LineCalc on Si at 20 GHz.

25 e,& 1 i I I 1 iI i i i i i i i i I 4 - 4 d 1 * —Oo. b - v i h i ': i!: i:: I i: PW 4- i r i q: I I Fig. 3.7: Layout of CPW-to-microstrip transition for probe measurements: a=500, b=985, c=285, d=200, e=1970, f=378<8', g=385, h=420, i=375, j=385, k=350, 1=150, m=150, n=100, o=p=22'O, q=132<2290. r=78<3200, s=60, t=100 gim. g Id ME4/ a Fig. 3.8: Layout of CPW-to-packaged microstrip transition: a=165, b=220, c=435, d=250, e=2470, f=3 88< 150, g= 150, h=21I0, i540 j 120, k= 114<2990, 1= 150 gm.

26 As shown by Wadell [36], the cutoff frequency, f, for microstrip lines is based on the following equation: = C (3.7) which indicates for full thickness Si (h=500 rmn, r=11.7), fc = 45.96 GHz, while for a thinner substrate (h=350 gm) f, = 65.6 GHz. 3.2.2 Microstrip Patch Antenna The microstrip patch antenna is popular for low profile antenna applications where size, weight, and cost are important parameters. Narrow bandwidth and poor efficiency limit the performance of the antenna but can be overcome by using thicker substrates and implementing an array of elements, respectively. Thinning the substrate increases the frequency of operation of the line, however, printing a patch antenna on a thinner substrate reduces the bandwidth of the antenna. [37]. Narrow bandwidth and poor efficiency limit the performance of the antenna but can be overcome by using thicker substrates and implementing an array of elements, respectively. The designer is forced to make a choice to either limit the performance of the feedline or the antenna. Six microstrip antenna designs (four with quarter wavelength (d/4) feeds and two with inset feeds) have been developed using PCAAD [38] as listed in Table 3.2. Photolithography limitations prevent the Xd/4 fed patches from being used because the widths of those sections were between 10 and 20 gm while the feedline width was 420 gum. At that time, the layout masks were processed using rubylith and the resolution of the system using a one times exposure would not realize such a contrast in widths. Consequently, the inset fed

27 patch, with slot widths of 105 mun, was chosen for the design. To better predict the performance and make adjustments to the design of the patch with rightangle bend feedlines, a 3 GHz microwave model has been developed using stycast and copper tape. The measured input match on one straight and two bending patch antennas is shown in Fig. 3.9. Notice the additional low-frequency resonance due to the local reflections at the bends with no miters. Mitering the corner removes the parasitic resonance and shifts the resonant frequency from 3.12 GHz to 2.96 GHz [39]. The length in the straight feed patch has been increased by 200 gm to shift the resonance of the antenna to 2.95 GHz. To increase design flexibility, the patch is fabricated on full thickness, Si while the feedline is printed on an area of the wafer which has been thinned locally to 320 gmn. Ztrans, Design W L Znd Inset )/ Wrans Type (gm) (igm) (42) (GHz) (gim) eeff (gim) W=1.5L 4000 1940 49.3+j5.5 20.03 715 n/a n/a Inset *W=2L 2900 2000 49.4+j5.5 20.01 775 n/a n/a Inset W=1.5L 3070 1990 391+j5.5 20.01 n/a 140/ 10 A4 6.6 122/ W=2L 4100 1940 300+j5.5 19.99 n/a 22/ 20 V4 6.7 W=1.5L(oe) 3070 1593 391+j5.5 20.01 n/a 140/ 10 4 6.6 122/ W=2L(oe) 4100 1535 300+j5.5 19.99 n/a 22 20 k4 6.7 Table 3.2: Proposed microstrip patch antenna designs for Si (~r=11.7) on 500 jm thick substrate with a design frequency of 20 GHz. The design used for the project is shaded.

28 -- 1.. 6 f straight no miter with mite = 2.96GHz = 3.12 GHz s 2.96 G = 2.96 GHz ers 0 -5 -10 la -15 U X -20 -W S -25 C -30 -35 -40 2.6 2.8 3 3.2 3.4 Frequency (GHz) Fig. 3.9: The input match (S 11) for a patch (W=2.9 mm and L=2 mm) with bending feedline (with and without mitering) compared to a patch with a straight feedline. The patch length was increased to incorporate the frequency shift caused by mitering. See Fig. 3.21 for feedline dimensions. W L fd Inset L Inset W Feed W Thickness Er (mm) (mm) (GHz) (mm) (mm) (mm) (mm) Stycast 10 19.14 14.53 3.03 52.07 6.909 2.77 33 Silicon 11.7 0.29 0.22 20 7.89 0.105 0.42 0.5 Table 3.3: Microwave model and actual patch dimensions.

29 3.3 Fabrication The approach for the packaged microstrip architecture incorporates the two-wafer fabrication technique described in [20]. Grounding pads are printed 380 im away from the microstrip line for bonding and ground plane equalization of the package. The substrate beneath the lines is locally thinned to 320 gm while the remaining substrate thickness is 500 Am. The conventional microstrip line and circuit/lower cavity of the packaged line (Fig. 3.3) are fabricated on high-resistivity 500 Rm-thick Si, while the upper cavity is developed on low-resistivity 500 km-thick Si. The masking dielectrics on the circuit wafer are a tri-layer of SiO2/Si3N4/SiO2 with a total thickness of 1.5 gm, while the upper cavity substrate uses a thermal SiO2 mask of 7500A. In the fabrifcation process, standard lift-off, and electroplating techniques are used for Au circuit metal definition of 3 gim. The shielding cavities and vias are defined by removing the masking dielectrics with reactive ion etching (RIE) and wet etching techniques while they are etched using bulk micromachining processes with EDP water solution that has an etch rate of 1.2 gm per minute. Details of the process can be found in Appendix C. 3.3.1 Substrate Thinning In order to realize a locally thinned region of Si on a full thickness wafer and create packages which conform to bending transmission lines, processing steps have been developed to: (1) reduce the wafer thickness under the conducting line, and (2) realize convex corners around bends in the upper and lower cavity regions. One way to realize a thinned area is by etching the shielding grooves/ trenched vias completely in one step and then etching the thinned area in a

30 second step. Currently this is only possible if the shielding grooves are 100 ptm-thick or less due to limitations of the photolithography techniques available. When using a wet etchant such as EDP, the sample must be thoroughly recleaned using a piranha etch1 before it can be taken back into the lab. After vias are etched in a wafer, it is sometimes difficult to post-process and achieve a vacuum on the sample. It must be mounted on a carrier to complete the fabrication. These additional steps add time and money to the processing of the packaged microstrip. The method used in this work involves a two-step etching process using multiple masking dielectrics where the material in the deeper etched area (shielding grooves/trenched vias) is removed "enough" so that when the thinner etched area is exposed with a specific time constraint, both areas are etched for the desired thicknesses. As mentioned in Chapter 2, pyramidal vias in Si are realized by defining an etch aperture width based on the substrate thickness and the size of the final width desired. The via is etched from the bottom of the wafer and bounded by the <111> crystal planes. The lower cavity wafer is shown in Fig. 3.12 where the aperture needed to realize a 100 im (narrowest width) shielding groove is 850 jim. For the lower cavity three adjacent regions are defined on the bottom of the circuit wafer. The two outer areas create the shielding grooves and must be etched completely (H=500 gm) while the inner area defines the locally thinned substrate and h=180 glm will be removed. With one mask the first two dielectric layers are removed on all three regions, and with a second mask the third dielectric is removed from the shielding groove regions only (Fig. 3.11). After 70% (5 hours, 360 jim) of the shielding groove Si has been etched, the remaining feedline dielectric (SiO2) is 1. Piranha etch: 1: 1.2 H-,02: H2SO4

31 removed and the sample is etched for an additional 2 hours (180 aum) to realize the thinned area and complete the shielding grooves. Thinned Region l S A 1Tri-layer dielectric Single layer dielectric Etched Si "-Unetched Si Shielding Grooves 1. Define grooves and thinned region. 2. Remove dielectric in grooves using RIE. 4. Remove dielectric in thinned region. 5. Etch all three regions. 0.8H / 3. Etch channels. -Ill Pedestal Fig. 3.10: Fabrication process for lower wafer development. In the scanning electron microscope (SEM) photo of the fabricated lower package (shown in Fig. 3.11), the shielding grooves and thinned substrate are shown with 100 gm wide pedestals necessary to overcome the limitations of the wet anisotropic etchant and realize a flat, smooth etched surface. Fabrication tests have been performed with pedestal widths equal to 10, 20, 30, and

32 100 pjm. If a pedestal is smaller than 100 4m, the Si surface directly beneath the microstrip conductor is very rough after etching. A A' AC ( D E F G i - Fig. 3.11: Front view drawing of a microstrip line printed on an inverted lower package with dimensions, A=850, B=100, C=400, D=150, E=210, F=380, G=750, H=148 rm. The conductors are indicated with hashed lines. This is a SEM photo of the inverted lower package developed during the two-step etch procedure. 3.3.2 Convex Corner Compensation The fabrication of locally thinned straight packages has been achieved using the aforementioned procedure, however, several problems arise when developing structures with bends (Fig. 3.13). The etch rate along the (100) crystal plane versus the (111) plane allows for the realization of grooves/vias in (100) Si. Higher order crystal planes (found in convex corners) have higher etch rates and become overetched very quickly. Fig. 3.12 shows a photograph of Layout B "bend-to-bend" for the packaged microstrip with a top view of the lower cavity (circuit metal) and bottom views of the upper and lower cavities.

33 (a) (b) Metallized Micromachined Upper Cavity w I Circuit Metal \ (c) il Micromachined Lower Cavity Fig. 3.12: Micromachined packaged back-to-back right-angle bends. (a) The upper cavity package with probe windows for on-wafer testing. (b) Circuit layout of microstrip line which is printed on the frontside of (c) the lower cavity, which shows the reduced thickness regions in the center with the lower package channels seen as white regions. f > Notice that certain corners in the lower cavity wafer suffer from rounding known as undercutting. Figure 3.13 illustrates the convex and concave corners found in a right angle bend. Wu [42] defines a concave corner as one bounded by the slowest etching planes (111) while a convex corner is one bounded by the fastest etching planes. The planes have been defined by Bean as {211} [40], by Abu-Zeid as {331} [411, and Wu as {212} [42]. An example of

34 the higher order plane (2121 being undercut is shown in Fig. 3.14 for a mesa as proposed by Lee [43]. [F~ f Di Silicon i I Dielectric < 110> directionf Fig. 3.13: Illustration of convex and concave comers in a right-angle bend.

35 Undercut convex corer Fig. 3.14: Underetching of a convex corner is caused by the fastest etching plane (211} according to Lee [43]. One method to reduce the excessive undercut of convex corners is to add chemical additives to the etchant [44]. While this technique reduces the undercut rate, it also reduces the anisotropy ratio between crystal planes and may ultimately create problems in the structure development. A more common method is to incorporate compensations in the mask to protect the convex corner [42]. Although sophisticated algorithms and techniques have been developed to predict the best compensation geometry for a given problem ([45], [46], [47], [48], [49], [50]), simple square compensations have been used and are centered at the endpoint of each expected convex corner found in the original mask (Fig. 3.15) [41]. The compensations protect the corners by providing the etchant with excess material to attack until the desired depth has been achieved.

36 The -design rules in the literature indicate that compensation squares of approximately 1.2 times the etched depth are sufficient to produce the quality of corners seen in Fig. 3.12a for the upper cavity package. For cases where the sample must be etched for a longer period of time, the simple compensation techniques break down as shown in Fig. 3.16b. In the initial fabrication, the upper cavity compensation has been designed as described above, however, the lower cavity wafer suffers from noticeable undercutting in the shielding grooves region and beneath the microstrip line. Since high-frequency planar circuits are highly geometry dependent, a structure as seen in Fig. 3.16b produces non-uniform field distribution under the microstrip feedline and contributes to higher-order moding as well as higher circuit loss [511. Therefore, V in the lower package additional geometrical and etching considerations are required to optimize the etch process. 800 210|!...-, - Etch 500 pn (a) _ L_ L _|_ - Etch 180 pm 500 (b) Etch 400 [lm Fig. 3.15: Layout masks showing compensations at convex corners. (a) Lower cavity wafer. (b) Upper cavity wafer. The large squares form the package channels and the small squares form the reduced thickness regions.

37 Separate compensation corners are required to develop the shielding grooves/trenched vias (500.tm) and locally thinned regions (:180 Lim) with, square sizes of 800 im an 210 Arm, respectively. Table 3.4 lists the estimated etching schedule for the lower cavity wafer. In order to preserve the compensation in the shielding grooves area, the total etch time must be considered. In general it takes 7 hours to etch an entire 500 gim wafer from one side. Process Time Process Step (hour) (hour) Begin etching (Step 1) 0 Monitor sample 1-4 Remove samples, rinse, measure etched depth in grooves, remove 5.5 dielectric Begin etching thinned region (Step 2) 0 Monitor sample 6.5 Remove samples, measure etched 7.5 depth in local thinned area Table 3.4: Etching schedule for lower cavity. Fig. 3.17 shows the effect etching has on the mask compensations for a right angle bend in the lower package. The CAD mask and photographs of the etched sample after 5 hours and 7.5 hours are shown. After the first 5 hours of etching one compensation square has been completely etched while some material still remains on the other two.

38 r t --- —------—. i *, i 0 (a) L_ -i -- — i i -- L.. (c) Fig. 3.16: Corner compensation marks: (a) CAD drawing of the mask layout, showing the corner compensation required for the formation of the lower cavity package (a=400,b=850,c=1286.5,d=2536.5,e=235 1.5,f=400,g=800,h=4687,i=3437,j=100,k=2393.5,=2098.5 =1 178,n=800,o=210,p=2068,q=2478,r=4978,s=2098.5) pm. (b) Good compensation from the etch. (c) Poor compensation due to the extended amount of time for the etch. Poor compensation due to the extended amount of time for the etch.

39 No etching 800 [im Compensation Etched 5 hours Compensation etched partially 7'HI r " Etched 7.5 hours Compensation adequate 800 Jm Compensation etched Compensation inadequate Compensation completely Fig. 3.17: Effect of etching on square compensation for a right angle bend. f Identification and design of the compensation corners must account for the depth that the convex corner will be etched (as in the case of the upper cavity wafer and reduced thickness region area in lower wafer), but also the total etch time to preserve corners if a longer etch is required. A quantitative expression for a simple (one-step etch) square compensation, c, is c = 1.2 d (3.8) and the complex compensation square, C, for a two-step etch is defined by: C = 1.2*d+26-h (3.9)

40 where d is the etched depth, h is the total etch time in hours and 26 is the linear approximation of the time dependence factor in units of microns per hour. 3.4 Measurements To RF characterize the micromachined circuits accurately, the following test equipment has been used: (1) two coplanar waveguide based GGB PicoProbes (150 gm pitch), (2) an Alessi High Frequency Probe Station, and (3) an HP 8510C Network Analyzer. All circuits were measured after performing a Short-Open-Load-Through (SOLT) calibration method in which the test probes were de-embedded from the circuit. The measured performance of the open and packaged circuits will be shown in the following sections describing the electrical characteristics of each line. Coupling mechanisms associated with different circuit layouts are evaluated and compared to a "reference" minimum noise value for the packaged system. 3.4.1 Transmission Line Characteristics Hewlett Packard's high frequency structure simulator (HFSS) has been used to simulate the performance of the microstrip lines [33]. The S-parameters for a 7 mm-long line are shown in Fig. 3.18 and the measured response for a 9.4 mm-long line (including transitions) is shown in Fig. 3.19. The measured return loss is 10 dB worse due to the mismatch caused by the CPW- to-microstrip transition and system calibration.

41 W ih i m 7 4a E ca v; -10 -20 -30 -40 -50 -60 5 10 15 20 25 30 35 40 Frequency (GHz) simulation of 7 mm microstrip line in open and lower shielded Fig. 3.18: HFSS configuration. L. ua E 0 -10 -20 -30 -40 -50 -60 5 10 15 20 25 30 35 40 Frequency (GHz) Fig. 3.19: Measurement of 8 mm microstrip line in open and lower shield configuration. The effective dielctric constant (Ere) predicted by Libra and the code based on the point matching technique for the conventional and packaged microstrip structures is 8.42 and 6.3, respectively. Fig. 3.20 compares the ere for a through line in the open and packaged configuration based on a Libra simula

42 tion and the measured data. Notice that when the line becomes packaged, the slope of Ere reduces indicating less frequency dependence. The effect of the lower shielding and complete shielding are indicated by the reduction in Are. 1 0.Ii I I, I I i I I I I i i T I T Measured (Open) 9 ' Libra (Open) -^ EFFECTIVE 8: E DIELECTRIC o wer shielded (Measured) CONSTANT 7 Completely shielded - - (Measured) 6 ' 5 10 15 20 25 30 35 40 FREQUENCY (GHz) Fig. 3.20: Microstrip effective dielectric constant. The electrical response of the interconnects for Layout A and B in the conventional and packaged microstrip configurations will be presented herein. Measurements for the insertion loss are shown illustrating the transmission properties in the various circuits. The performance of a right-angle bend (L=13.392 mm) and a straight delay line (L=13.392 mm) for a conventional microstrip design is shown in Fig. 3.21. The insertion loss is similar for both lines at lower frequencies, however, above 15 GHz the comers in the bending line radiate and excite substrate modes. The bending line oscillates above 30 GHz with total loss (1- I S]1 12 S12 12) ashighas 65%.

43 Figure 3.22 shows that the total loss of a packaged bend and delay line of equal length is very similar. Although the packaged bend exhibits higher losses due to the metallization of upper cavity, the parasitic radiation associated with the open bend is eliminated by the shielding cavities. A comparison between the open and packaged bend is shown in Fig. 3.23. 1 r I T -' 0.8 -: s i - 0.6 ' W 0.4 I/ Bend -— "- Deluy Line 0 0a C t fwLi 0.2 Of 0 5 10 15 20 25 30 35 40 Frequency (GHz) Fig. 3.21: Electrical response of open microstrip circuits for a delay line and right angle bend (L=13.392 mm). 1 ^_'., 0.8 fcn = 0.6 1 W' 0.4 i f I T I I I I I i I I l I I I I I I I I I I I T I T I I Delay Line. Bend -'u, J I I I l, 0 5 10 15 20 25 Frequency (GHz) 30 35 40 Fig. 3.22: Electrical response of a packaged back-to-back right angle bend and microstrip delay line of similar length (L=13.392 mm).

44 ^ // -? ------- iL I in ii e h r m ] k ' 0.8 -% -- Open Bend 4 0.6 -6 5 10 15 20 25 30 35 40 Frequency (GHz) Fig. 3.23: (a) Dimensions of open and packaged back-to-back right angle bends: (a=1970, b=2468.5, 0.4 c=2078.5, d=1898.5, e=2258.5, f=848<31.5, h=5148, I=3648, j=2498.5, k= 2470, 1=4464, m=1709, n=2198.5, o=424<315, p=3163.5, q=2194, r=2288, w=2483.5) mm. (b) Electrical response of an 0.2 " -12 0 _-14 5 10 15 20 25 30 35 40 Frequency (GHz) open and packaged back-to-back right angle bend (L=13.392 mm). The total loss of each line is compared to a delay line of equal physical length (13.392 mm).

45 3.4.2 Noise Floor/Coupling Two types of noise measurements are defined: (1) "non-contact": probe-toprobe in air and (2) "contact": packaged system noise floor. The non-contact noise is measured when the probes are elevated 20 mm above the package surface and separated by 8.3 mm in the x-y plane (Fig. 3.24). This distance is equal to the separation found in the bend-to-bend layout (Fig. 3.4). The contact noise measurement is an average of different measurements obtained when the transmission line is excited at one port and the propagating signal is measured at different locations on top of the circuit package environment, as indicated in Fig. 3.24 [29]. Figure 3.25 compares the two noise measurements and shows good agreement between them. -~Port 1 - & Window for 3 " - RF Probe Access ~ I,- Port 2 Fig. 3.24: Layout for contact noise characterization. The boxes represent probe windows in Design Layout B (Figure 3.4) for the bend-to-bend arrangement. Probing points in the contact noise measurement are indicated by starts at Port 1 for the input signal onto the conducting line at Port 2.

46 O, --- - -— i r - -. -f r_ - -20 - - "".-Non-Contact Noise F - Average Contact Noise 0 -60 0 I -80 i 1 -1 00 I I I 5 10 15 20 25 30 35 40 Frequency (GHz) Fig. 3.25: Noise data from contact and non-contact measurements. 3.4.3 Cross Coupling and Isolation This section focuses on the measured cross coupling in the two layouts presented earlier (see Figure 3.4). Figure 3.26 shows a comparison of cross coupling between Layout A and B for conventional microstrip. Coupling is as high as -20 dB for the through-to-bend arrangement (Layout A) while it is even higher (-10 dB) for the bend-to-bend arrangement (Layout B). These results indicate that the amount of coupling seen in open structures is highly dependent upon the layout configuration. Figure 3.27 shows that the addition of the integrated lower cavity reduces the coupling by approximately 20 dB for the bend-to-bend arrangement. Inclusion of the upper cavity achieves an additional 10 dB reduction. These results demonstrate that advanced monolithic packaging can reduce coupling between elements to the noise level. The contact noise and cross coupling response of the completely packaged bend-to-bend arrangement are compared in Fig. 3.28 and show very good

47 agreement up to 33 GHz. The increased coupling in the packaged bends is associated with leakage that occurs at the input and output ports of the packaged line, which are left open (Fig. 3.25). A HFSS simulation of two parallel microstrip lines in an open lower shielded and completely shielded topologies (Fig. 3.3) are shown in Fig. 3.29. The edge-to-edge spacing for the packaged microstrip is 2.82 mm and 2.58 mm for the conventional line. The coupling levels differ by approximately 20 dB across the band. The measured coupling levels increase with frequency and the simulated levels decrease. This is due to the complexity of the measured layout (bend-to-bend arrangement) in comparison to parallel lines in the simulation. Fewer frequency points are used in the packaged line simulations and are not as smooth as the conventional results. I 0 I I I I; iI l l ^ I I I I -20 Layout 7, I I I,,, Layout A, 5 1 30 35 40 Frequency (G H z) Fig. 3.26: Comparison of cross-coupling effects in open microstrip structures for design Layout A and B (See Fig. 3.3). Layout A and B (See Fig. 3.3).

48 0 (A -20 -40 -60 -80 -100 I I I ' II I I I i i l I I I U 5 10 15 20 25 30 35 40 Frequency (GHz) Fig. 3.27: Cross -coupling effects in Design Layout B for two back-to-back right angle bends in open, lower half packaged, and full packaged designs.(See Fig. 3.3) 0 10 0 W -20 -40 -60 -80 -100 5 10 15 20 25 Frequency (GHz) 30 35 40 Fig. 3.28: Comparison of coupling between two packaged back-to-back right angle bends and the contact noise measurement of the packaged system.

49 0 j- -. r-w~;~- - -. n. 0 m a 0 o o (i cn U i ------— ~ -20 L i f r -40 - i/ -60 -80 -- -100 ",, 5 C, -,v-onai:s=2.58 rmm Lower Shieided (S=2.82 mm) -4 I i 1 '- 1 32 mm) 1 i,35 4I, 35 40:1 m-I s- s I 7,... Completely Shielded (S=2.E -tv1:..A Pon 2 T I 10 15 20 25 30 Frequency (GHz) Fig. 3.29: HFSS simulation of cross coupling between conventional and packaged configurations where 1=7 mm. two straight microstrip lines in the 3.4.4 Antenna Feed Performance To illustrate the packaging approach for an antenna element, a shielding cavity has been developed around the feedline of a microstrip patch antenna (Fig. 3.30). The antenna window has dimensions of 7.1 mm x 6.9 mm, including a distance separation of 2 mm (Fig. 3.31). By separating the antenna edges from the package by 4 times the substrate height, the interactions between the feedline shielding cavity wafer and antenna element are reduced [52]. The packaged feedline is printed on a thinner substrate (320 tim) to ensure a dominant microstrip mode and the patch is printed on a thicker substrate (500 gm) to increase the frequency bandwidth [37]. As observed from the data in Fig. 3.31, the 3 dB bandwidth of the packaged antenna is approximately

D50 12.8% while the bandwidth of the open antenna is approximately 6.4%c, an increase of 200%. 3dBBandwidth = Frequpper- Freqlowe ) Freqcenter Since the two antennas only differ in feeding structures, the antenna with a better input match will achieve higher antenna efficiency as shown in Equation 3.11 where the total antenna efficiency, et, is: et = ecd(l- l2) (3.11) where ecd is the antenna radiation efficiency due to conduction and dielectric losses and F accounts for reflections between the feedline and antenna. The magnitude of the reflection coefficients of the patch input are 0.058 and 0.0186 for the conventional and packaged feedlines, respectively. A higher antenna efficiency for the packaged feedline can be attributed to the fact that the propagation characteristics (v) and characteristic impedance (ZO) are less sensitive to frequency due to the improved TEM propagation on the line as shown in previous transmission line measurements. In the case of high density antenna arrays where feedline cross coupling limits performance, this packaging scheme can improve feedline isolation and propagation.

51 m. y1Microstrip Antenna Air s';;rna Wi ndow Probe Window Fig. 3.30: Conceptual drawing of packaged antenna configuration. O

52.4 0 4~t~ d Via H le 0 I C Antenna Window rn Grounding Pad H [4 Ii K, Reduced 1Thickness Region 1 Fig. 3.31: Layout of antennas: (a=1140, b=789, c=2900, d=2200, e=105, f=8135.5, g=2673, h=750, 1=970, j=21 0, K=8835.5, 1=2470, m= 183<55, n=7123.5, o=6900, p=2000) im -10 -2 07 -25.....p L. Wk -30 -35 1 6 1 7 1 8 1 9 20 Frequency (GHz) 2 1 22 Fig. 3.32: Return loss for a patch antenna with open and packaged microstrip feedlines.

53 3.5 Summary The work presented in this chapter has demonstrated the substantial benefits of advanced monolithic packaging concepts in high density planar circuit and antenna design. Specifically, cross-talk and parasitic radiation in circuit components and antenna feed networks can be eliminated through selectively packaging sections of planar circuits. The packaging technology is based on integrating Si micromachining techniques with standard IC processing techniques. Circuit performance for components generally demonstrating high radiation is improved substantially with the inclusion of a package environment. This packaging scheme also reduces interactions between neighboring elements in dense layouts and creates an environment similar to the package system noise. The findings from the circuit interconnect problem make the inclusion of such packages into antenna array applications beneficial by isolating the functions of the feeding networks and antenna element. In addition to the aforementioned benefit of improved performance, monolithic micromachined packages for high-frequency circuit designs are lightweight and small, as well as low in volume and cost. Novel micromachining techniques have been used to develop low-cost package solutions for microstrip lines; to further study cross-talk behavior in open and packaged geometries; to characterize the noise associated with monolithic packages; and to demonstrate the integration of a package with planar elements common in array applications.

5p-4

CHAPTER IV DESIGN OF A SI-BASED CHIP CARRIER FOR DISCRETE COMPONENTS 4.1 Introduction This chapter presents an approach to discrete component package design that uses processes compatible with IC fabrication techniques to develop highprecision, miniaturized, high-frequency housings which do not limit device performance. With low cost Si as the packaging material and anisotropic etching as the technique for machining the packages, this design can be easily scaled to millimeter-wave frequencies, an option not available for conventional packaging materials. The excellent mechanical and thermal properties of Si lead to a very competitive packaging technology which offers improvements in high-frequency performance and reductions in long-range production costs. In the early eighties, Petersen extensively reported on the properties of Si and emphasized that its mechanical strength is comparable to the strength of many metals [21]. Although Si is a brittle material, wafer chips on the order of 6 mm x 6 mm are quite rugged under normal handling conditions. The excellent properties of Si along with the numerous micromachining techniques available have allowed engineers to develop high-performance miniature elec 55

tromechanical devices [53], and membrane-type transmission lines which can operate at frequencies as high as 1000 GHz [54]. GigaBit Logic developed a. Sibased package for GaAs circuits and compared the performance to a multilayer ceramic one [55]. The Si-chip carrier provided shielding for signal lines, lower cross-talk, and lower thermal resistance when compared to the ceramic package. While chip capacitors were mounted on the ceramic substrate to reduce power supply disturbs, they were monolithically integrated in the Si substrate. This capability gives an engineer more design options and reduces the amount of potential loss associated with hybrid circuits. Si technology has been implemented in a high density, 3-dimensional cardon-board package for a Josephson technology experiment [56]. The substrates for the thin film-circuits, circuit boards, and structural supports were all made from Si and eliminated thermal mismatch problems. Table 4.1 lists the thermal conductivity values for common III-V materials compared to Si 157]. The thermal properties of Si are very good compared to those of ceramic materials and allow for excellent heat transfer between the semiconductor and package, thus making Si an excellent candidate for high-frequency MMICs. Thermal Material conductivity (W/(m OK)) GaAs 80 InP 65 Ge 68 Si 135 Table 4.1: Thermal conductivity for MMIC substrates [57].

57 In the following sections, the design, fabrication, assembly, and testing of a Si package that can provide on-wafer or discrete shielding to ICs is described. The package performance is evaluated and compared to a Ka-Band ceramic package for a MMIC phase shifter chip. RF 1/0 line Microstrip 4 --- — -- RFVO line.. '- Stripline 7.112 mm it -l -- ------- -- DC Bias line *'.; --- —--- - - Shielded microstrip 4- - - - - - - - - - - - - - ~ - - - - - - - - - - - - - - -- - 7.112 mm Fig. 4.1: Actual photograph of K/Ka-Band ceramic package for phase shifter chip. 4.2 Chip Carrier Design The Si-based single-chip carrier layout (Fig. 4.1) originated from a design fabricated by Hughes Aircraft Company for NASA Lewis Research Center using high temperature co-fired ceramic (HTCC) techniques with 92% alumina [58]. The package is designed around a K/Ka-Band MMIC phase shifter chip with ten bias lines perpendicular to the RF input/output line. The width and length of the package is 7.112 mm and 7.112 mm, respectively, and the

58 multi-layer assembly includes a seal frame, RF substrate, base, and top metal lid which create a microstrip-stripline-shielded microstrip interconnect for the MMIC device (Fig. 4.2). RF 19It0 t Grmound Pte Fig. 4.2: Schematic drawing of K/Ka-Band package for phase shifter chip. Courtesy of Yook [58]. The characteristic impedance of the transmission lines is 50 Q and the dimensions of the lines were obtained using LineCalc (Fig. 4.3). The impedance for the microstrip is based on the Hammerstad and Jensen formulas (see Chapter 3) while the impedance for the stripline is based on Wheeler's approximate formula [59]. For the design frequency of 29 GHz the cross-section dimensions and lengths of the interconnect at the input are shown in Table 4.2. mhic1 L L hi Shield............ -------------— i Fig. 4.3: Transmission lines used in RF input/output interconnects: microstrip, stripline, and shielded microstrip.

Zo = r io Inw 1.0 + ' 4.O7 c r L L ^H' + (0b + 6.27] j rI8 ):: (4.0) where, Aw W = W+ -t t (4.1) and Aw 1.0 t t.-o[5 F( ( 1.0 -2 n.0/(4t+) ] t L-In2.0(b - t)/(t+ 1.0)) Kw/t+ 1. J (4.2) If 6.0 (4.3) m = 2.Ot 3.0 + -t (b -t) Transmission Material Conductor Lengthy/ Line E.Eff Thickness wionduct Lengthpe Zo (S) Line 4tm) " /width (4m) Z (Q) (gm) (gmP) Microstrip 11.7/8.49 350 320 469/48 48.93 Shielded MicrosShielded Micros- 11.7/7.33 350 250 305/29 50.06 trip Balanced Strip- 11.7 700 100 559/67 49.12 line Table 4.2: Dimensions for interconnects used in Si package, obtained from Linecalc where fd=29GHz.

60 To compare electrical performance between the different materials (Si and alumina), the micromachined package design is kept the same with the ceramic one. The thickness of the substrate and seal frame layers for the alumina package is 381 gim while the Si wafer thicknesses are 350 ~25 in. Table 4.3 lists the redesign parameters for the Si chip carrier. PARAMETER 92% ALUMINA MICROMACHINED Si Permittivity 9.5 11.7 Wafer Thickness (gm) 381 350 Metal Thickness (gm) 4 3 Vias (gm) 203.2 diameter (circular) 150/side (square) Process HTCC Si micromachining Bias Line width (gim) 457 350 Wirebonds (number) 4 3 Table 4.3: Redesign parameters for discrete package. The Si-based package is comprised of six layers (4 dielectric and 2 metal): the carrier (1), the substrate (2), the seal frame (3), and the top cover (4) as shown in Fig. 4.4 and Fig. 4.5. The carrier wafer has a metal layer on the top side (Metal 1, Fig. 4.4) which provides the ground for the package. The substrate wafer supports the input and output RF lines, the DC bias lines, and the lower part of the shielding vias. The seal frame includes the upper part of the shielding vias and two probe windows which allow access to the input and output RF lines for on-wafer measurements. In addition, the seal frame supports a metal layer which provides the upper ground plane for electromagnetic (E-M) shielding (Metal 2, Fig. 4.4).

61 4 Si Cover Wafer (4) Ground Plane - Probe Window I IC/Through Line ':* 4 - Metal Layer (2) Si Seal Frame Wafer (3) I/O Lines DC Bias Lines Ground Plane -- ~T~p -% _rP I -n.~;i+ Si RF Substrate Wafer (2) Metal Layer (1) Si Carrier Wafer (1) w4 4 Fig. 4.4: 3-Dimensional rendering of Si package. The package layout has been developed using AUTOCAD and Fig. 4.5 shows the process layers superimposed. To provide mechanical support and connect the two metal layers, a set of 12 vias are processed in the substrate and seal frame wafers on the Si package (Fig. 4.5 and Fig. 4.6).

2540!4! Through Line - Via Hole - 350 Bias Line 300 BJ 3 Fi 150 Overlay -- A Pad 3570 3000 Fig. 4.5: Process layers superimposed. In normal HTCC processing, the interconnecting vias are stamped and then filled with a conductive paste by screen printing. In the Si-based approach, selective etching along the <111> crystal plane in a <100> Si wafer is used to create vias with a pyramidal shape, as shown in Fig. 4.6. The wide square aperture of each via is equal to 640 x 640 (im2, which results in a narrow aperture of 150 x 150 am2 on the other side of the wafer after etching. Metal over

63 lay pads are electroplated over the narrow via aperture to provide electrical contact between the conducting layers [61]. I 600 Metal Overlay Pad - -. — 4-.-.~ ~ i. X=150 Substrate I IIS D 54~ T=640 / Subsunic 600 Back of via I 1 640 300 I Ground Plane Fig. 4.6: Pyramidal via micromachined with anisotropic etchant and Cr/Au overlay pad. The wide via aperture width, T, is related to the narrow width, X, and depth of the via, Y, by the following equation, T = X+2 D (4.4) and, (4.5) D = 0.7 Y The original HTCC package design is asymmetric to accommodate the layout of the MMIC phase shifter, with the I/O feedlines displaced 178 jim from the center axis of the cavity while the two outer vias on the left side of the package are displaced 105 gim from the others, as shown in Fig. 4.7. In addition to the original design, two more variations have been fabricated and measured to determine the sensitivity of the electrical performance to layout asymmetries. In design #2, I/O lines have been placed along the center axis of the package to study the effects of feedline symmetry while the vias have been

64 left at their original location as in the ceramic package. In design #3, both I/O lines and shielding vias have been symmetrically placed with respect to the center axis. Shifted 1/0 C / Centered I/O Centered 1/0 cm/ M Cet I/O L2 = { t * *i I I I - - 0 7. 7. i - Shifted Shifted Aligned Vias Via Via Design #1 Design #2 Design #3 Fig. 4.7: Designs for Si package: Design #1-Shifted vias and I/O line, Design #2 -Shifted vias and centered I/O line, Design #3-Aligned vias and centered I/O line. 4.3 Fabrication and Assembly A 500-gm, high-resistivity, <100>, Si wafer with 7500A of thermal SiO2 is used to fabricate the package. The process flow consisted of wafer preparation, circuit metallization, and via formation (etching), and metallization as detailed in Appendix D. The wafers were assembled using Epotek silver epoxy as detailed in the following steps. Figures 4.8 and 4.9 and show the cross-sections of the package assembly.

65 Step Process Attach RF Fill the vias in the RF wafer with silver epoxy. Place the RF 1. Attach RF wafer on the metallized carrier. Cure epoxy for 15 minutes at wafer to carrier. 1200C. Place epoxy on backside of through line. Place it within the. tac IC aperture on RF wafer onto the carrier wafer. Align intermlcro strp connect and through line and cure epoxy for 15 minutes at through line. 120C. 3. Wirebond Attach Au bondwires between the interconnect and through 3. Wirebond ine. 4. Align and Place epoxy on the RF wafer metal overlay pads. Align seal attach seal frame. o attach seal frame frame and RF wafers. Cure epoxy for 15 minutes at 120 C. wafer. 5. Attach top Fill vias in the seal frame wafer and add the top cover to the cover assembly. Cure epoxy for 15 minutes at 120~C. Table 4.4: Assembly of micromachined package. i A' A I 5080 jI Upper via K 300 150 M X1 N I I I I -- 350I v, I |E -A Overlay 0vpads 350 Lower via Metallized cover Seal frame Silver epoxy Substrate Metallized carrier o*4v Bias line Fig. 4.8: Cross-section A'-A of package layers.

66 B - B |559 4064 Wirebond Reference 672 3250 508 864 ri 25 Fig. 4.9: Cross section B-B' shows the assembly of the IC into the package. 4.4 Measurements The micromachined packages have been evaluated for electrical performance and are compared to the ceramic package. Figure 4.10 shows the top view of an assembled Si package without the top metal layer and cover attached [62]. Measurements have been performed on a microstrip through line representing the phase shifter integrated circuit. On-wafer high-frequency measurements have been conducted using a HP 8510C network analyzer with an Alessi Probe Station and 150-gm pitch ground-signal-ground (GSG) GGB Picoprobes. The network analyzer is calibrated with microstrip TRL standards which shift the reference plane location, thereby eliminating the effect of the GCPW-to-microstrip transition (Fig. 4.12). For on-wafer characterization, the CPW-to-microstrip transition presented in Chapter 3 is used with the microstrip width equal to 320 plm. Probe windows are etched in the seal-frame wafer to access the transmission lines (Fig. 4.10).

67 RF I/0 line Microstrip ' — Stripline 7.112 mm A DC Bias line Shielded microstrip I Via 7.112 mm Fig. 4.10: Top view of Si package without metal layer or vias filled. The feedthrough transitions between microstrip, stripline, and shielded microstrip including steps in width that taper to reduce the effects of the discontinuities. As the wave propagates along the feedthrough, the field lines must transition as well. Figure 4.13 compares the insertion loss and return loss for the Si (best performing) and alumina package (within a test fixture) along with a Libra simulation of the package interconnects using Si as the substrate material. The physical dimensions of the package interconnect were used to model the effect of the interconnects (Fig. 4.11).

68 INPUT -- Feedthrough DUT Feedthrough - OUTPUT Feedthrough Strip Shielded Bondwire Microstrip line Microstrip Fig. 4.11: Block diagram of the package interconnects used in the Libra simulation. Shielded 305 508 Microstrip Stripline 559 Microstrip 469 672 Reference Plane \ } CPW-to-microstrip ' transition Fig. 4.12: RF input feedthrough with CPW-to-microstrip transition for on-wafer measurements.

69 The lossless discontinuity effects are shown in the Libra data and indicate that the return loss for the interconnect design can be as high as -20 dB at certain frequencies. The two resonances in the simulated return loss at 30 and 37 GHz imply correlation to the two resonances in the measured Si package at 28 and 34 GHz despite the frequency shift. The alumina package has been modeled by Yook [60] using a finite element method (FEM) technique where the package detail geometry including bias lines, bondwires, geometrical asymmetries, and vias are considered in modeling. The vertical electrical field of the package is calculated to locate EM field leakage and spurious resonances (Fig. 4.14). Although the vias within the package do not provide total EM shielding for the MMIC, the leakage in the 12 vias suppresses the cavity resonances in the package as shown at 29.5 CGHz. Notice the voltage standing wave pattern of the EM field along the I/O line. In Fig. 4.15 the cross-section of the vias indicates the exposed substrate width where EM field leakage occurs. In the alumina package, the width is 1016 gm and in the Si package that width is 376 gim. This implies more isolation can be achieved in the Si package as a result of wet anisotropic etching.

70 *n 0I c 0 w rA Cf 0 -0.5 -1 -1.5 -2 -2.5 -3...-.... --- —----- -----—................................... -i I1 + 1 7 1 1 i: i I I Y I.: i! 7 m 28 30 32 34 36 38 Frequency (GHz)......... Libra for Si 1 — rusJIrced.Si ------- Measured Alumina --- FEM for Alumina 40 10 I — 0 -10 -20 -30 -40 -50 28 30 32 34 36 38 40 Frequency (GHz) Fig. 4.13: S-Parameters for Libra interconnect simulation, alumina package (within test fixture), and shielded Si package.

71 Electric Field Distribution in Package at 29.5 GHz u -10 7n -30 -ZI"- 0 -70 -E0 Fig. 4.14: Computed vertical electric field distribution (dB scale) in the asymmetric alumina package at 29.5 GHz. Courtesy of Yook [60]. A' A E 203 1016 Cylindrical vias in ceramic package 640 376 Pyramidal vias in Si package Fig. 4.15: Cross-section (A'-A) of the alumina and Si package illustrating the cavity side wall created by the vias. (Units in microns.)

72 As listed in Table 4.5, the process steps for ceramic packages require hightemperature firing which alters the surface of the conducting materials and increases RF interconnect losses. A post-firing metallization step can be added to HTCC processing to reduce conductor loss, but it increases production costs. Figure 4.16 shows the attenuation as a function of frequency for a 8 mm-long 50 ~ Au electroplated microstrip line (typical package length). Attenuation is calculated as, S21 (4.6) Attenuation =- 21 (4.6 LineLength It can be seen from the measurements that conductor loss can be reduced by increasing circuit metal thickness during electroplating [55]. The skin depth, 6, is defined as, 6 2= (4.7) coga where co is the angular frequency,,g is the permeability, and a is the conductivity of the metal. For Au at 20 GHz, 6 is equal to 0.55 gim and the two metal thicknesses represent 14.5 and 5.4 skin depths for 8 and 3 gim of plated Au, respectively. Notice that the additional 5 gm of Au reduces the attenuation by a factor of two up to 26 GHz. By virtue of the processing capabilities alone, thin-film techniques are the best alternative for low-cost mm-wave packages. The use of micromachining techniques not only improves electrical performance but also provides a simplified method of fabrication.

73 PROCESS THIN FILM THICK FILM Circuit Metal Electroplating Screen Printing Via Formation Micromachining Punching Package Assembly Bonding High Temp Stacking and Firing Via Metallization Evaporting/Epoxy Epoxy before Firing Chip Insertion Micromachining Pedestal/Solder Preform Metal Cover Bonding Low Melting Point Solder Table 4.5: Process steps for thick and thin film packages. 0.12 0.1 A 0.08 E E i X 0.o0 -J o 0.04 0.02 10 15 20 25 30 Frequency (GHz) Fig. 4.16: Comparison of attenuation for two metal thicknesses for an 8 mm long microstrip line. the typical length with two metal thicknesses. The following measurements compare Si structures and are more lossy than the best performing Si package due to misalignment of the through line and interconnects. Figure 4.17 shows how placement of the top lid affects performance of the package. Slight frequency shifts and more loss are due to the

74 conductor metal on the backside of the cover. Finally, the three designs are compared in Fig. 4.18. There is fairly good agreement between the three measurements in S21 which shows the design asymmetries do not significantly impact performance. 0 -5 -10 -u a -15 - -20 '-4 -25 -30 -35 w -2 5 1 *3 - -4 -4 -5 28 30 32 34 36 Frequency (GHz) 38 40 Fig. 4.17: S-Parameters for a symmetrical package with and without lid added.

75 0 I I I* I T I I I -! I: f I I ' I T 0 -5 I -20 ~-60: Symmetr -40 -10 28 30 32 34 36 38 40 Frequency (GHz) Fig. 4.18: S-Parameters for different package designs: Completely symmetric (Design #3), shifted' vias (Design #2), asymmetric (Design #1). 4.5 Summary It has been shown that a Si-based package for Ka-Band discrete circuits can offer improved electrical performance as compared to its ceramic counterpart, when thin-film and micromachining techniques are applied to develop the housing for the electronic device. The proposed packaging concept involves the same processing techniques used to realize the electronic devices they are protecting. Performance degradation associated with package and circuit incompatibilities can be reduced when both are manufactured simultaneously and eliminated when the package and circuit are the same material. Batch-fabrication of the Si-based packages can reduce production costs by as much as a factor of 30. These advances can significantly impact the wireless industry as it strives to produce low-cost, high-performance, microwave communication systems.

CHAPTER V HYBRID TECHNIQUES INTEGRATING CONFORMAL PACKAGING WITH FLIP-CHIP TECHNOLOGY 5.1 Introduction For the commercial industry to take advantage of the recent reallocation of bandwidth at mm-wave frequencies [63], high performance systems at extremely low costs must be realized. Currently mm-wave MMICs are quite expensive due to low yield in performance and the high cost of III-V material. Passive components and active devices are fabricated on the same wafer resulting in inefficient use of the active substrate. This costly process results in even lower circuit yield when multiple devices are incorporated. An alternative to developing monolithic ICs at microwave frequencies is using hybrid techniques where the active device is wire bonded to a low-cost substrate. At mm-wave frequencies however, the parasitics associated with bondwires inhibit circuit performance due to uncontrollable inductance. Consequently, flip-chip mounting of active devices onto low-cost substrates with coplanar transmission lines has become a promising solution producing high yield connections with low parasitics [64], [65]. 76

77 Along with a cost-effective fabrication methodology for high performance commercial MMICs, there must be an equally developed packaging technique in place to transfer the performance to the system in which it was designed. For most hybrid or monolithic designs, packaging is still being considered at the end of the design cycle and results in low overall system performance due to package resonances and parasitics. By designing monolithic integrated circuits with integrated packages, performance yields will ultimately increase. The concept of packaged circuits based on Si micromachining techniques have been demonstrated by Robertson [66], and Drayton [20] and is extended here to more complex designs. V As reported by Al-sarawi three-dimensional (3-D) packaging is the future technology for VLSI applications because it offers significant reductions in weight and volume over multi-chip module and discrete packaging technologies [67]. The development of a mature 3-D packaging technology provides great promise for high frequency applications where low power consumption, low weight, and compactness are high priorities. As mentioned previously, vertical integration is a way in which wafer real estate can be increased by reducing the total substrate area needed for a circuit layout. Figure 5.1 shows a schematic indicating how Si circuit density is increased by implementing 3-D packaging technology. Fig. 5.1: Substrate area for MCM versus substrate area for 3-D technology [68].

78 In most high-frequency applications, planar circuits are designed and fabricated using standard IC (thin-film) processing techniques. With the requirement for increased density in planar circuits, the need to develop vertical integration for thin-film circuits technology is becoming more important. In multi-layer circuits, conductor metal strips are separated by dielectric layers. Si micromachining can be used to isolate and shield conductors while prc)viding a support for additional interconnect circuits printed on vertically stacked substrates as shown in Fig. 5.2. The two-wafer packaged circuit with shielding cavity is a fundamental element which can be used in a Si multi-layer circuit technology. Fig. 5.2: Si micromachined two-layer packaged circuit. The upper wafer shields conductors and provides support for vertical integration. The objectives of this chapter are to study the effects of on-wafer shielding of interconnects and circuits appropriate for 3-D integration in an effort to demonstrate the cost-effective option of integrating Si packaged circuits with flip chip mounting for mm-wave applications. The performance, of transmission lines and circuits using two different shields (dielectric and metal) is studied to determnine the usefulness of the additional metal layer for packaged circuits [68]. As an application example for this concept, a low noise amplifier (LNA) circuit is designed and fabricated.

79 5.2 Circuit and Package Design An integrated packaged circuit consists of two Si wafers bonded together as shown in Fig. 5.3. The interconnecting geometry is a finite ground coplanar waveguide (FGC) because of the excellent propagation characteristics [69]. Si micromachining techniques is used to develop the air cavity wafer. The air cavity is 275 jim away from the circuits and the two wafers are bonded together with silver epoxy. The cavity width is 800 im and the total transmission line width is 1200 im. micromachined air cavity wafer. metal Wl A, s; hc E dielectric h2{ substrate wafer Fig. 5.3: Cross-section of packaged FGC line and upper shielding cavity (with or without metallization) of height hc=275, wg=500, w=53, s=94, hl=500, h2=400, d=385, g=200, wc=800 gim. Excellent noise figure measurements and the highest possible cutoff frequencies for useful gain at frequencies above 100 GHz are performance traits which have identified Indium Phosphide high electron mobility transistors (InP HEMTs) as the best device for mm-wave low-noise applications [70]. Herein a 3-stage LNA circuit has been designed using discrete devices which are bonded onto the substrate using flip-chip attachment with tin/lead solder bumps. The InP HEMT device has been developed at HRL Laboratories, and the structure consists of a 250 nm undoped AlInAs buffer with a 40 nm

80 GaInAs channel, a 1.5 nm undoped spacer, an 8 nm AlInAs donor layer, and a 7 nm GaInAs doped cap. The gate length and total gate width are 0.15 fm and 300 gim, respectively, and a 100 nm Si nitride layer protects the device from particulates and moisture [71]. Tin/lead (Sn/Pb) solder bumps make contact between the chip and the substrate. In the original microstrip-based design developed at HRL [73] (~r=3, t=250 gm), radial stubs and 20 pF lumped element capacitors isolate the DC from the RF along the bias paths. Coupled line filters block the DC and radial stubs provide matching for the gate and drain (Fig. 5.4). The stub lengths in each stage have been optimized using Libra to produce maximum gain given for low noise matching conditions. 0 High and low impedance sections (125 Q and 50 Q2) are designed on a low dielectric constant material (E.=3). When implemented in Si (er=11.7) the high impedance line widths are difficult to realize with contact photolithography. In addition, changing from high to low impedance sections (change in width) increases the number of discontinuities and limits overall circuit performance. For these two reasons in addition to the advantage of flip-chip bonding onto coplanar lines, the design has been converted to 50 Q finite ground coplanar waveguide (FGC) on high resistivity Si (~r=11.7, t=400 uim) and the lumped elements are replaced with monolithic components [73]. The radial stubs are replaced with balanced shunt open stubs [74] and the coupled line filters are replaced with series open-end stubs. Libra has been used to optimize the transmission line lengths for high bandwidth. Figure 5.4 shows the schematic diagram for both designs and Fig. 5.5 compares the expected performance based on Libra simulations for the original design and the "corrected" design which includes the new layout dimensions.

81 Microstrip Design VD:, VD VDZ VDV Ll"C O-W 125 a 125 LI 750 so a L 12 LI12 a I r Sr soLI LI 12 Wr L- L^ Out ~a no VDI '~ GVD2 V03C~ RF In zUSa MD SC 1250 1w 26pr VG so RF In no sr I", 530.son so l so a I 06. so a RF Out Fig. 5.4: Schematic diagram of microstrip and FGC 3-stage LNA. VG3

82 - Corrected 0 - -.-.- - - -.... -.................................\.. - S / 50 I, -150 0 - -................... ------- ----........................... -150 5 10 15 20 25 Frequency (GHz) Fig. 5.5: Libra simulated insertion gain for original design (LibraIdeal) and corrected design (Libra_corrected) for fabrication. To prevent circuit crowding in the layout, additional transmission line lengths have been added in the RF and bias paths of the FGC design (Fig. 5.6). The transmission line extending from each bias circuit tee has been set to a fixed length of 2845 pgm to isolate the ground planes. An additional kg/2=3062 pn has been included along the RF path to accommodate for the shunt stub lengths in the DC bias network. On-wafer biasing is included with the gate and drain DC lines routed to one location onto the substrate (see Fig. 5.6). A customized six-lead DC bias probe has been designed so that all devices can be probed at one time. Libra was used to optimize the transmission line lengths to improve the bandwidth of the circuit. The overall size of the on-wafer packaged structure including bias routing is 33.4 x 12.6 mm2 while the estimated size of the microstrip circuit without packaging is 23 x 4.5 mm2. The microstrip circuit would have a size of 34 x 10 mm2 when packaged in a discrete chip carrier without bias routing included.

83 Bias line w/shielding \. ____..' cavity _ _ _ Bias circuits I ias circuits DC probe RF probe window i i I. window 1 6 tI -r t ci -. \ I12.6 mm Input OLu '-,- - =i - ' - l, Output, Bonding pad - Drain.- - _ I' r Gate --- -- * * — j -— 33.24 mm Comer Compensation Fig. 5.6: FGC mask layers for LNA. 5.3 Fabrication and Assembly The process steps for the circuit wafer include the development of tantalum nitride (TaN) resistors, gold (Au) electroplated circuit metal, nickel (Ni) solderable pads, polyimide solder wells, alumina (A1203) metal-insulator-metal (MIM) capacitors, and Au electroplated airbridges. The interconnects and circuits are fabricated on 400 gn-thick high-resistivity Si using standard lithographic steps detailed in Appendix D. The upper shield is fabricated on 500 gn-thick low-resistivity Si with an 8500 A thermal SiO2 masking layer. Since right-angle bends are used in the mask layout (Fig. 5.5), compensation squares (500 pm) have been added at each convex corner. The air cavities and access windows for alignment, RF probing, DC biasing, and flip-chip mounting, are etched using (EDP) water solution. Th wafer is etched from both sides simultaneously so the access windows (500 gm) and cavity (275 gm) can be realized at the same time and reduce the total etch time from 6.25 to 3.5 hours.

84 A photograph of the fabricated circuit wafer is shown in Fig. 5.7. There are two circuits, a set of TRL calibration standards, and individual passive components including capacitors, shunt stubs, series stubs, and resistors. After fabricating the circuit wafer, the individual passive components are tested for DC and RF performance. It is necessary to verify that the airbridges and capacitors have not been damaged in processing. Using a multimeter, airbridge locations are tested for short circuits. Using a HP LCR meter, the capacitance values are measured within the circuit. RF performance of the capacitors and stubs is recorded as well. The Si02 layer is removed from the micromachined wafer using BHF (dielectric shield) and Au electroplated (metal shield) for bonding. Silver epoxy is placed along the cavity wafer and it is inverted and aligned over the circuit wafer with a hotplate, micrometer, and microscope vacuum system typically used for wafer-to-wafer bonding [751. The wafers are cured at 120~C for 15 minutes and the flip-chip HEMT devices are mounted off-site at HRL Laboratories with a bonding machine manufactured by Semiconductor Equipment Corporation [76]. LNA1 LNA2 - ITest Circuits Calibration Standards Fig. 5.7: Photograph of 1/4 of a 4 inch wafer used for fabricating LNA circuit. Notice two circuits in the center with test devices and cal standards on the edges.

85 5.4 Measurements The S-parameters of the circuits are measured on a HP8510C Network Analyzer, using 150 gm pitch GGB Picoprobes from 2 to 40 GHz. A TRL calibration method using NIST's Multical program is performed to shift the reference plane directly to the packaged circuit [77]. The following sections detail the design and performance of the individual components and conclude writh the measurement of the LNA. 5.4.1 Transmission Line Characteristics Line losses due to parasitic radiation can be eliminated by adding shielding cavities, leaving ohmic loss and dielectric loss as the contributors to line attenuation. FGC input lines for the amplifier circuits have been designed for a characteristic impedance (Z0) of 50 2 (s = 94 1rm, w = 53 gim, wg = 500 gim). These lines are intrinsically lower in loss because the field lines propagate within the slot apertures, offer higher isolation, and provide better compactness when compared to conventional CPW. Although there is no need for via hole processing, airbridge technology is needed to equalize the ground planes of such a complex layout (Fig. 5.6). The effective dielectric constant (Eeff) and attenuation (a) of FGC lines used in this circuit design have been extracted using the Multical program. Figure 5.8 compares the attenuation for the "conventional" (unshielded) line with the dielectric and metal shield lines. Results show that the attenuation is greater in the metal shield due to the additional conductor metal on the package walls (Fig. 5.9). The Seff for FGC line when operating in an open and shielded by a dielectric cavity is very similar, however, the FGC line shielded

86 by a metallic cavity exhibits higher dielectric constant due to increased line capacitance. The cross coupling between two parallel lines separated 774 ptm edge-toedge is shown in Figures 5.11 and 5.13. The longer line is excited at Port 1 and the induced standing wave on the coupled line is measured from Port 4. The other two ports (2, 3) are left open [29]. HFSS simulated a similar response for two parallel FGC lines of the same cross-sections (Fig. 5.12). To reduce processing time, the longer line length is reduced to of 4.55 mm and the shorter line length is reduced to 1.8 mm and placed 2.75 mm away from the longer line (similar to the layout in Fig. 5.11). Port 2 is shorted and port 3 is left open. The coupling for all three architectures is comparable with the best performance within the design bandwidth from the conventional line. 0.25.......... 0.2 i - ^ E^ E 0.15 -5 c 0.15 - No Shield 0.05 - - Dielectric Shield - Metal Shield 5 10 15 20 25 Frequency (GHz) Fig. 5.8: Attenuation for different packaging environments.

87 Fig. 5.9: Cross-section for conventional, dielectric shielded, and metal shielded FGC lines. The increase in coupling observed in the lines with metal shielding is due to the continuous ground between the lines, provided by the shield. Figure 5.13 shows that shielding by dielectric cavities can reduce coupling at the lower frequencies by as much as 5-10 dB to provide isolation as high as -60 dB [29]. The coupling measured is 6 dB higher than that expressed when the lines are matched. Figure 5.13 shows the measured and average level of coupling for each case separately. Notice the increase in coupling above 25 GHz for the lines covered with the metal shield. 6.5 5 0 Uo o No Shield - -- Non-metallized -o-Metallized c 5 10 15 20 25 Frequency [GHz] Fig. 5.10: Effective dielectric constant for different packaging environments.

88 0 If ' - T i -20 - -40 I \ 'o c Cn o 2 -60 -80 -100 5 10 15 20 25 Frequency (GHz) 30 35 40 20000 — N -- Port 1 Port 2 5500 10900 Fig. 5.11: Cross coupling measurements for different two planar FGC lines (Dimensions in microns). 0 -20 A. -40 a. o * -60 -80 -100 5 10 15 20 25 Frequency (GHz) 30 35 40 Fig. 5.12: HFSS simulation of similar FGC layout where the ground planes edges are separated by 871 microns.

89 s=7741.m No Shield s=774gm e0 cm 0 0 0 U co - 0 o CL 0 0 0 ro -5. 0 0 a 0 h. 0,..... I.... I, I.. I I I I, I........ -10 -20 -30 -40 -50 -60 -70 -80 5 10 15 20 25 30 35 40 Frequency (GHz) Dielectric Shield -10 -20 -30 -40 -50 -60 -70 -80 0 -10 -20 -30 -40 -50 -60 -70 -80 5 10 15 20 25 30 35 40, Frequency (GHz) s=774im:', I.... I,..... I.... I ,,, I. . I -M I I I -4 I I I. I.... I.... I.... I - - -, I.... I.... I I I I Ai Metallic Shield 5 10 15 20 25 30 35 40 Frequency (GHz) Fig. 5.13: Cross coupling between planar lines separated 774 microns edge-toedge. 5.4.2 RF Components In addition to studying the transmission lines characteristics, individual components incorporated in the circuit have been characterized. When converting the design from microstrip to FGC, radial stubs are replaced by balanced open shunt stubs for matching and biasing. In order to predict the performance of the biasing stubs in the presence of the FGC tee and airbridges, a stub design for 14 GHz has been modeled using a full wave simula

90 tor (IE3D) [78] (Fig. 5.14). The IE3D modeling considers the stub in an open environment but does not take into account ohmic losses. A photograph of the stub and corresponding shielding cavity (inverted) is shown in Fig. 5.15. There is good agreement between the simulated and measured results in Fig. 5.16. The effects of the metal shield on the stub performance in Fig. 5.17 indicate a resonant shift of 1 GHz. Two 100 Q TFR in // tL5 I F r - - --. l L,.4 L3 10 l I Ll D 11 Port 1 I II I HId I1 I,1 Port 2 A Airbridges Fig. 5.14: Open balanced stub with dimensions: L1=753, L2=1752, L3=2485, L4=630, L5=698. Units are in microns. Port I Port 2 Termination resistor RF Probe Access Window Fig. 5.15: Photograph of shunt stub and corresponding shielding cavity inverted to show etching and convex comers.

91 m la 0 I0 E a 0 i O" 0 -5 -10 -15 -20 -25 -30 2.1 \ /: S ^ - 11. -........Sim ulated Measure -35 5 10 15 Frequency [GHz] 20 25 O Fig. 5.16: Comparison between measured and simulated S-parameters for balanced open shunt stubs. The simulation considers air bridges and T-junctions. 0 -5 S' L. 0 a. i, -10 -15 ' ' '< s ~ f ' ' ~ \,/: 11 \. / No Shield \\ - -Non-metallized \ \ * * Mettiiz -20 -25 -30 5 10 15 Frequency [GHz] 20 25 Fig. 5.17: Comparison of S-parameters for the balanced open shunt stubs for the fabricated cases (no shield, dielectric shield, metal shield) versus the simulated case.

92 The microstrip DC block is replaced by a series open-end stub series openend stub The stub (Fig. 5.18) is modeled using HP Momentum 1[79] at a design frequency of 23 GHz. A plot of measured and modeled performance is shown in Fig. 5.19 with good agreement. Figure 5.20 shows there is more loss in the circuit with the metal shield due to the continuous ground plane. Fig. 5.18: Open series stub resonator used for DC block. The stub length is 1568 microns for the design frequency of 23 GHz. # 0 -5 m -10 0) (0 -15 -20 5 10 15 20 25 Frequency (GHz) Fig. 5.19: Comparison of reflection and transmission coefficients of the open series stub for calculated (Momentum), open (no shield), metal shield, and dielectric shield environments.

93 0.2.. T. "? -, ' - ''! ' II — — ' ' --- Dielectric Shield 1 -- Metal Shield - 1 '- - - No Shield,- 0.15 r, 7 H 0.05 / \ 5 10 15 20 25 Frequency (GHz) Fig. 5.20: Loss comparisons between measured open-end series stubs. 5.4.3 DC Bias Components RF shunt stubs along with thin-film resistors and MIM capacitors have been used for matching and biasing the gate and drain of the transistors. The thin film resistor is realized when TaN is deposited onto the substrate and the circuit metal provides metal contact as shown in Fig. 5.21. The resistance value R of a rectangular pattern is defined as: RsL R = W (5.1) where Rs is the sheet resistivity of the resistor (Rs=p/t) in Q/sq, L is the length of the film, W is the width of the film, and L/W is the aspect ratio of the resistor which defines the number of squares needed to realize a certain resistance value [801. Figure 5.21 shows the layout of a resistor in a parallel or

94 series configuration with the square defined by the FGC aperture width. Table 5.1 gives the dimensions of the resistors which exhibit a sheet resistivity of 33 2/sq. 500 500 94 94 Resistor in parallel Resistor in series Fig. 5.21: Layout of resistors in parallel and series. Table 5.1: Dimensions for resistors used in LNA circuits.

95 MIM capacitors are fabricated by sandwiching a thin alumina layer between two conductive layers. The capacitance value C is defined by C = rA (5.2) d where d is the thickness of the dielectric, A is the area of the overlapping electrodes, and co and er are the permittivity values for free space and the dielectric material, respectively. The capacitor dielectric constant ranges from 8 to 10 and the thickness of deposited alumina to realize 20 pF shunt capacitors is 1500A. Based on the fabrication process described by Robertson [68], three individual capacitors are realized, two across the ground planes (Cg) and one across the center conductor (Cc) (Fig. 5.22). According to the equivalent capacitance formula for the circuit (Fig. 5.23) the overall capacitance value is a function of the center conductor capacitance as long as the ground capacitances are at least twice as large as the center conductor capacitance. The measured RF performance of the capacitor is shown in Fig. 5.24.

96 Capacitor Metal Circ Su:uit Metal Insulator (Alumina) ibstrate Fig. 5.22: Cross-section and top view of capacitor structure used in LNA circuits with dimensions: a=500, b=200, c=226, d=160, e=2640, f=220, g=627, h=94 am.

97 Cc e = 2CcCg Cc + 2Cg (5.3) Cg Fig. 5.23: Equivalent circuit for capacitors across FGC line. 0 -10 -20 * -30 -50 -70 -60 -70 5 10 15 20 25 Frequency (GHz) Fig. 5.24: RF capacitance measurements before and after adding airbridges. 5.4.4 Single Transistor Measurements In Fig. 5.25 there is a photograph of the flip-chip high electron mobility transistor (HE.MT) developed at HRL Labs. Sn/Pb solder bumps which are 25 Ium high and 50 gim in diameter have been used to mount the transistor on the Si substrate. 'The gain of a single transistor measured on-wafer (InP) com

98 pares well to the gain of a similar device after it has been flip-chip bonded onto the Si substrate. The reduction in gain for the unmounted and mounted case can be attributed to the effects of the solder bumps and the transition to the device when measuring it in a bumped configuration [81]. Introducing a series resistance and inductance in parallel with a capacitor models the loss due to the solder bumps. Table 5.2 lists the bias point conditions and associated gain for the device on InP and the Si substrate with a dielectric shield. 1.9 5.3 n 2.4 pF f 20 ' 15 (3 C o, L-a c 0 0 10 c 5 4 8 12 16 Frequency [GHz] 20 24 Fig. 5.25: Insertion gain for single transistor. Measured on InP wafer (transistor only), mounted without shielding (No shield), and mounted with metal shield covering transmission lines.

99 Dielectric Parameter InP Dielectr Shield Si Gate Voltage (V) -0.388 -0.7 Drain Voltage (V) 1 1 Gate Current (mA) -.009 -0.5 Drain Current (mA) 45.04 42.3 Insertion Gain at 94 7.86 20 GHz (dB) Table 5.2: Bias conditions for maximum gain of individual transistor. V c Solder well NN Nickel pad / a d e b Circuit metal Polyimide Solder bump +.,.1 INI/ Fig. 5.26: Layout for solder well and flip-chip device (a=1000, b=1000, c=1200, d=200, e=500, f=500: All units in microns).

100 Tin/Lead solder bump Drain Drain Source S so Source Gate Gate Device after bonding Pad after bonding Fig. 5.27: Device and pad after bonding to the Si substrate. Fig. 5.28: 'The SEC model 410 aligns and attached the flip chip die onto the machine.

101 5.4.5 LNA Measurements The LNA circuit has been measured at HRL laboratories using two calibrations (SOLT and TRL). Using a SOLT calibration up to the probe tips, the gates and drains of each stage are tied together and biased at different conditions to obtain maximum gain. The recorded gain values and the corresponding frequencies are listed in Table 5.3. The maximum gain (S21=12.9 dB at 17.5 GHz) is achieved when the VDS1=VDS2= VDS3= 3 V and VGS1=VGS2=VGS3 = -1.1 V. The corresponding total drain current, IDS=143 mA and corresponds to a value of 47 mA for each device. Using the same bias conditions with a TRL on-wafer calibration, the measured insertion gain increases to 15.7 dB at 17.9 GHz as shown in Fig. 5.29. Total Total F Name VDS VGS SF CaD S, (V) (V) DS (GHz) type (dB) Name < | ^^ > (mA) (mA) AB 2 -1 -10 89 18.5 SOLT 7.5 AC 2.5 -1 -10 11.7 18.5 SOLT 9.7 AD1 2.5 -0.7 -7 129 17.5 SOLT 6.2 AD2 2.5 -1.2 -12 110 n/a SOLT 10.5 AD3 2.5 -1.4 -14 102 n/a SOLT 8.6 AE 3 -1.2 -12 137 18.5 SOLT 12.6 AF 3 -1 -10 147 17.5 SOLT 12.1 AG 3 -1.1 -11 143 17.5 SOLT 12.9 BA 3 -1.1 -11.2 145 17.91 TRL 15.7 Table 5.3: Bias conditions and associated gain of amplifier when all transistors are biased together.

102 I,I I-, I C................................................. Fig. 5.29: Measured insertion gain of amplifier using two calibrations with VDS(123)=3 V, VGS(123)=-11 V, 'DS(TRL)'4S mA, IDS(SOLT)143 mA. To realize more gain, the gate of each stage has been individually biased and the drain voltage is fixed to 3 V. Table 5.4 shows the insertion gain, total currents, for varying gate bias points. The optimum gate bias voltages resulting in S21 > 16 dB are VGS1=-1.3 V, VGS2=-1.3 V, and Vog3=-1.OV at approximately 17.9 GHz. -28 5 10 15 20 25 30 Frequency (GHz) Fig. 5.29' Measured insertion gain of amplifier using two calibrations with VDS(123)=3 V, VGS(123)=-1-" V, IDS(TRL)=145 mA, IDS(SOLT)=143 mA. and the drain voltage is fixed to 3 V. Table 5.4 shows the insertion gain, total currents, for 'varying gate bias points. The optimum gate bias voltages resultmately 17.9 G'rHz.

103 VGFreq. VG 2 VG3 IGT IDT S21 (GrHz) (V) (V) (V) (mA) (mA) (dB) 17.757 -1.1 -1.1 -1.1 -11.2 145 15.795 17.757 -1.2 -1.1 -1.1 -11.5 143 16.1 17.,757 -1.3 -1.1 -1.1 -11.8 142 16.39 17.757 -1.4 -1.1 -1.1 -12.2 144 16.30 17.757 -1.0 -1.1 -1.1 -10.9 146 15.12 17.905 -1.1 -1.0 -1.1 -10.9 147 15.73 17.905 -1.1 -1.1 - 1.1 -11.2 148 16.03 17.905 -1.1 -1.2 -1.1 -11.6 144 16.40 17.905 -1.1 -1.3 -1.1 -11.9 144 16.48 17.905 -1.1 -1.4 -1.1 -12.2 142 16.42 17.905 -1.1 -1.5 -1.1 -12.5 140 16.24 17.757 -1.1 -1.1 -1.1 -11.2 148 15.9 17.757 -1.1 -1.1 -1.2 -11.6 145 15.85 17.905 -1.1 -1.1 -1.2 -11.6 143 15.98 17.905 -1.1 -1.1 -1.3 -11.9 140 15.84 17.905 -1.1 -1.1 -1.4 -12.2 137 15.71 17.905 -1.1 -1.1 -1.0 -10.9 147 16.07 17.757 -1.1 -1.1 -0.9 -10.6 151 15.92 17.757 -1.1 -1.1 -0.8 -10.2 152 15.43 Table 5.4: Gain at different bias points for amplifier. O The flip-chip devices are incorporated in a 3-stage LNA design which uses the interconnects and stubs presented earlier. Figure 5.30 shows the measured and simulated gain results. On this figure three different sets of data derived by Libra [301 and IE3D [781 are compared. The bias conditions are VGS=-0.388 V, VDS=l V, IGS=-0.009 mA, and IDS=45 mA The Libra-Ideal sim

104 ulation treats the passive components as ideal and models the original design on substrate material Er=3 using microstrip. The LibraCorrected simulation, Er=3 on microstrip, converts the electrical lengths and passive components converted to that of the FGC layout. With Libra_IE3D the transmission line is FGC with airbridges included on Si (er=11.7). The results are based on a Libra harmonic simulation where all the passive components have been replaced by the S-Parameters modeled using IE3D and do not consider ohmic loss. The LibraPhysical simulation considers the physical dimensions, effective dielectric constant sef=5.7, and attenuation constant, a=0.104 dB/mm (the true loss on a FGC line) at 20 GHz (see Table 5.3)... Transmission Simulation nin Airbridges e Losses Line E LibraIdeal Microstrip No 3 No LibraConverted Microstrip No 3 No Libra_IE3D FGC Yes 11.7 No Physical Libra_Physical Transmis- No Seff=5.7 Yes sion Line Table 5.5: Libra simulations for low noise amplifier circuit. The three simulations predict a maximum gain of approximately 28 dB centered at 20 GHz. Figures 5.29, 5.30 and 5.31 show comparisons of simulations with the measured LNA. In comparing Libra_IE3D with Libra_Corrected, there is a decrease in gain at the lower frequencies. This can be attributed to the effects of the airbridges and FGC line geometry which have been accounted for in the Libra_IE3D simulation. The predicted low frequency decrease in loss is confirmed in the measured LNA (Fig. 5.31). Although 7 dB

105 lower in insertion gain, the shape of the two curves agree very well. To account for the overall reduction in insertion gain for the measured circuit, the Libra-Physical simulation is compared with the measured response. When the normal loss for a FGC line on high resistivity is included in the Libra model (0.1 db/mm at 20 GHz), the maximum gain achievable for this layout is approximately 19 dB at 19 GHz. The continuous masking dielectric SiO2 is not removed from the circuit and contributes to a reduction in insertion gain. In addition, the suggested biasing conditions for the transistor (Table 5.3) have been changed for the actual circuit because a 20 Q resistor is in series with a drain and source. This changes the drain voltage from 1 V to 3 V. We believe this also affects the maximum gain which can be measured for the circuit. 5.5 Summary Si-micromachined, on-wafer shielded circuits have been fabricated for Kband operation and the performance in various shielding environments has been studied. The shielding cavity is a primary component in vertically integrated circuits and its effect on the performance of these circuits has been analyzed. Dielectric shields outperform metal shields with continuous ground planes in loss and cross coupling. Active devices can be flip-chip mounted onto a Si substrate to create low-cost alternatives to MMICs but the parasitics of the solder bumps and the substrate can reduce the expected performance of a large size circuit. Alternatives to reducing line attenuation are presented in Appendix A.

106 50,-,.50 - 50 0 - — ^ — -. — - - - - -. — - - -- - - - ---- - - - - - - - - - - - -- -- - - - - - - - - -- - - - - - - o / X --- LibraCorrected - -- Libra_IE3D -100 -150 - 5 10 15 20 Frequency (GHz) Fig. 5.30: Comparison of insertion gain for Libra_corrected and Libra_IE3D simulations 25

107 50 I. I I I I [ -0 en 0 Um go,,,[d c3 C..., 0 -50. —.. --- —------- ------,. -- - -- \ / / / -100 -150 I II II I I I I i 't Measued LNA Libra lE3D II. II I I I i a - I I I I 5 10 15 Frequency (GHz) 20 25 Fig. 5.31: Comparison of measured LNA performance with Libra_IE3D simulation.

108 50,! l m50I — ------- -------------- 0. ---, -50: - LibraP, hysical: i -'- Measured -100 - 1 0 0 C - ' - - ~ ~- — ' ' - - - - '- - - - - - - - - - - - - - - - - - T - - '- - - - - - - - - - -- - - - --- -.- - - - - - - - - - - - - - - -- - - - - - - - - - - - - --—, ----150 - --------- -------------- ' ----- l -150 5 10 15 20 25 Frequency (GHz) Fig. 5.32: Comparison of measured LNA with LibraPhysical simulation. "il I

CHAPTER VI PACKAGING FOR THREEDIMENSIONAL INTEGRATION 6.1 Introduction In order to develop high-frequency solid-state transmitters with moderate output power levels, multiple transistors and power combining techniques have been proposed. There are two types of combining techniques, commonly used, spatial combining and circuit combining methods. With the desire to reduce front-end size and volume, it is necessary to develop miniaturized three-dimensional transmitter systems which use planar circuits for power combining. Not only does circuit power combining offer size reductions and more flexibility in system design, but it provides more ability to obtain uniform amplitude and phase at each element [82]. However, the loss found in combining stages and sensitivity to matching networks are two important factors which have led to designs using other combining methods [83]. This research focuses on the development of a conformally packaged distribution network to be used in a three-dimensional (3-D) planar power cube linear array transmit tile module (Fig.6.1) appropriate for spatial power combining. We seek to reduce size and volume using this method and minimize loss by integrating on-wafer packaging while developing the 3-D structure. 109

110 Micromachined High Resistivity Si Layers #4 #3 \ #2 \ ' #1\ Radiating Elements Ground Plane/ Coupling Slots Output Distribution Input Distribution f,MMIC Power Amplifiers Fig. 6.1: Conceptual 3-D view of the W-Band power cube showing the micromachined wafers and metal layers.

1ll The -power cube is made of separate Si wafers each (Fig.6.1) one responsible for separate functions as listed in Table 6.1 The W-Band signal is amplified by four MMICs flip chip bonded at the lower part of the vertical structure and then distributed vertically to 16 radiating elements via four 1 x 4 distribution networks using novel vertical interconnects and low loss CPW-to-microstrip transitions (Fig.6.2). Each microstrip antenna element is 750 gm x 750 gm and separated 850 gim from an adjacent one. The total area available for distributing power to the antenna feed layer is 6 mm x 6 mm. For this reason high performance FGC lines are used to develop the network. Airbridges have been included to suppress unwanted mode excitation at discontinuities [841. To preserve the integrity of the airbridges when bonding layers, micromachined packages are monolithically developed along with the circuits. Layer Si Metal 1 Heat sink/MMIC access Input distribution.2 Si micromachined layer/on- Output distbution 2 >,.... Output distribution wafer packaging cavities 3 Si micromachined layer/on- Antenna feed wafer packaging cavities 4 Antenna/micromachined layer Patch antenna for reduction of surface waves array Table 6.1:Function of power cube layers. Presented herein are details involving the design, fabrication, and testing of the output distribution network. Along with the development of the network on FGC, we investigate the effects of packaging on transmission line propagation, individual circuit, and sub-system performance.

112 H-Slot feed divider FGC-to-microstrip transition Microstrip patch antenna / 3-Via vertical interconnect Fig. 6.2: Layout of initial design of distribution network with antenna feed and patch shown. The vertical interconnect is on the bottom side of the MMIC layer while the slots and patch antenna are on the feed and antenna layer, respectively.

113 To the best; of my knowledge, this is the first uniplanar design of a W-Band 4, 1 x 4 distribution network. The next section presents the study of the FGC line performance in a 3-D environment. 6.2 FGC Lines in Multiconductor Environments The FGC line dimensions are chosen using design rules established by Herrick [85]. Limited to a total line width of 300 gnm, the aspect ratio necessary to realize 50 Ql is, = 0.45 (6.1) s + 2w f where s is the center conductor width and w is the aperture width. This aspect ratio generates an 8eff of approximately 6.34. The dimensions chosen for the line are s=40, w=24, wg=106, and t=100 gim. In order not to excite higher order modes the total line width has to be less than Xg/2 where Xg corresponds to a wavelength well above the maximum operating frequency, 2Wg+2w+s<g/2 (6.2) For the center frequency, fc=94 GHz, Xg/2= 632 gim, a value much greater than the total line width of 300 gm. Xg/2 = - =632gm 2f JEff

114 Because the network is placed in a 3-D environment where metal layers can be placed above and/or below the circuit metal layer, the impact of conductor metal on line characteristics must be considered. s w s w.d-.A&b i" k ^"'^"S..1 }... c....l l ' '-'r- ~ >r 5 t:^ i sY -~' - In r So -;j{~a t Conventional FGC Conventional FGC on Carrier s w 2t 2t; I s w St Conductor-backed FGC........... - -----.. Shielded FGC Fig. 6.3: 3-D environment geometries for the transmission lines. Conductor Backed FGC on Carrier Packaged FGC Figure 6.3 shows six line architectures in which an FGC line may be placed. Conventional FGC represents a line isolated from vertical metal layers. Conductor backed FGC lines have two metal layers separated by 100 gLm of pure Si. The conventional and conductor backed FGC lines are placed on a carrier to represent structures which have substrate thicknesses greater than 100 grn. Shielded FGC represents isolated lines with a micromachined cavity 40

115 mm away from the circuit metal. Packaged FGC lines have two metal layers separated by a 40 Lim micromachined air cavity. All data is measured using a HP8510C Network Analyzer with 100 tlmpitch GGB Picoprobes on an Alessi probe station. Attenuation and effective dielectric constant are extracted from the on-wafer calibration using Multical. Notice that the attenuation constant for lines on the left have a periodic ripple in Fig.6.4 That ripple is suppressed in thicker substrates and packaged lines. 'i E IB a c 9 z 2 c 2 ^~ i c 0.36 0.34 0.32 0.3 0.28 0.26 0.24 0.38 0.36 I 0.34 0 a c S 0.32 c c 0.3 0.28 0.26 -- Packaged - Condcutor backed wl carer r —....... Convntional with camrrr.f.. — r' t1 110 75 0 10 tO 100 105 110 Frequency (aHz) Fig. 6.4: Attenuation for line architectures. 75 80 85 90 95 100 105 Frequency (QHx) i c o u o 6.4 6.2 1 - F - '- -- - -- Conductor backed --- Conventional - Shielded....I....i....i.. 6.4 P;I I I ~ I I I I l ~,,,, r I I I 7, I cJ LU a I3 6.2 6 5.1 5.6 -- Packaged......... Conductor backed w/ carrir - Conventional w/ carrier 5.8.............................................. 75 S0 85 90 96 100 105 110 Frequency (GHz) 75 80 85 0 95 100 105 110 Frequency (GHz) Fig. 6.5: Effective dielectric constant for line architect tures.

116 Measurements show that lines with thinner substrates have an effective dielectric constant value closer to the value predicted by Herrick (~eff=6.34). Lines with air cavities have propagation characteristics similar to the thinner substrate lines while thicker substrates have lower dielectric constant values (see Fig.6.5). From the transmission line data, a packaged FGC line with metal conductors separated by an air/dielectric cavity has propagation and loss values which agree very well to a conventional FGC line completely isolated from metal conductors. A packaged FGC line is less sensitive to environmental conditions (metal layer location) than a conductor backed line. The next two sections focus on the design and fabrication of the distribution network. 6.3 Initial Design Two 50 0Q Wilkinson power divider geometries have been considered for use in the distribution network: a coupled CPW/slotline (Fig.6.6a) and a FGC design (Fig.6.6 b). In the coupled CPW/slotline Wilkinson design, fewer discontinuities are needed and the total width is 300 pm. The CPW-based Wilkinson is larger in width by approximately 200 plm and requires five additional airbridges to suppress higher order mode excitation at the discontinuities. Both designs are measured in the conventional FGC with carrier environment (see Fig.6.3). Figure 6.7 shows the insertion and return loss for the network with the three output ports terminated with 50 Q2 thin-film resistors. At the design frequency (94 GHz), the insertion loss is approximately -7.5 dB for both designs. Lateral/horizontal coupling for the two designs is measured in the layout and results in levels as high as -26 dB for the CPW-based design shown in Fig.6.8. The distance between adjacent networks is 1600 gLm, although ground-to-ground spacing is 300 lim.

117 (b) (a) Fig. 6.6: Single 1 x 4 distribution network: (a) CPW-based Wilkinson distribution network design, (b) Coupled CPW Wilkinson distribution network design..35.- I-. -; -' -.5 - i-I-15.20 I i.2li0 d ' -25 5.35 ~ 75 8 85 90 95 100 105 110 75 80 s 90 95 100 105 110 Frquency (GHz) Frquency (GHz) (a) (b) and (b) is the CPW/slotline design.

118 -10,,s No floor Coupling e1 -20 40 -70 40 75 80 85 90 96 100 106 110 After it was proven that distribution networks with good performance could be developed for W-Band applications, a second design effort was implemented to further improve performance of the CPW-based design by shift the resonant frequency to 94 GHz. 6.4 Optimization of CPW Distribution Network The tee junction and Wilkinson dividers are standard equal division 50 i designs with airbridge step compensations to improve circuit response. TaN thin-film resistors are used in the Wilkinson design (100 Q) and 50 Q resistors are used to terminate three of the four output ports in the distribution network. The distribution network is fabricated on high-resistivity bare Si (>2000 Qcm). 700 A of TaN (Rs=45 iQ/sq) is sputtered onto the substrate and selectively

119 etched using reactive ion etching for the resistor metal. 9500 A of Au is evaporated for the circuit metal and 3 km Au airbridges are electroplated to equalize the ground plane potential. The shielding cavity is fabricated on a 100 km-thick Si substrate with 8500 A SiO2 masking layer. Probe access windows are etched into the substrate for on-wafer measurements. The 40 gm cavity and access windows are defined using photolithography and etched using EDP water solution. The metal conductor evaporated on the cavity is 2000 A Au. The two wafers are aligned using a bonding station with 10 ~ 5 gm accuracy. Details of the process are found in Appendix F. 6.4.1 Fabrication Improvements The two most sensitive steps of the process are the airbridges and thin-film resistors. For the FGC line dimensions used in the distribution network (wg=106 pim, w=24 gm, s=40 gLm), 50 Q termination resistors are formed by placing two 100 Q resistors in parallel (Fig.6.9). The resistance, R is related to the dimensions of the resistor and sheet resistance, Rs by the following formula: L\ (6.3) R = RsW) where Rs = 50 J/so, W = 12 gm and L = 24 gn. A variation in circuit metal or resistor pad dimensions can affect the return loss of a terminated line or the performance of the Wilkinson. The original resistor and circuit metal masks did not include compensations for misalign

120 ment and a 3-5 jtm shift can result in the structure shown in Fig.6.9a which effectively has a larger resistor pad area and therefore a smaller resistor value. By adding a 5 Jim overlap on the FG(C circuit metal and an edge bead removal process step [681 this problem is eliminated. When one typically spins photoresist on a sample, thick beads of resist gather near the edge of the wafer and preclude the best contact lithography step. Removing the beads of resist at the edge of the sample ensure better transfer of the resistor pattern from the mask to the wafer. (a) (b) Fig. 6.9: Layout of two 100 Q resistors in parallel to create the 50 Q termination impedance used in the distribution network. a) Poor alignment, b) additional FGC circuit metal to keep pad dimensions. (Not drawn to scale) In addition to improving the reliability of the resistor process, efforts are made to develop repeatable airbridges. As mentioned earlier, airbridges, due to capacitive loading, affect the attenuation and phase velocity in coplanar lines. Figure 6.10 shows a SEM of the airbridges used in the power divider.

121,. -.. - r- i - - -,.-. I (hi (a) kwJ Fig. 6.10: Airbridge arrangement for CPW-based power divider. The integrity of the airbridges is very good as seen from the SEM phpto. The bridge width is designed to be 20 gm wide but measures 25 gmin due to processing. In order to compensate for the additional airbridge capacitance, adjustments are made to the circuit metal mask. Given the height and width of the airbridge, the compensation width and length on the center conductor of the T-junction and right-angle bend are reduced to shift the resonance to the center frequency of 94 GHz. In the second design iteration, the ground plane widths in the vicinity of the divider are truncated to reduce parasitic effects (Fig.6.11). Improvements in the return loss for a single divider resulted from this adjustment.

122 (a) (b) Fig. 6.11: Photograph of individual dividers. The ground planes in (a) have been truncated (b) to reduce parasitic effects in the return loss of the individual device. 6.5 Multiconductor Circuit Performance According to Ponchak [69], the propagation characteristics of FGC lines are not subject to the substrate thickness or location of a ground plane. With that in mind the vertical layout of the distribution network or location of ground planes should not be a large concern. According to the layout shown in Figure 6.1 the power combining network distributes power to the antenna with a microstrip line through an H-shape slot which requires a continuous conductor plane. The true environment in which the distribution network resides is similar to the conductor backed architecture shown in Fig.6.12. A 40 pUm cavity has been etched into the next layer Si wafer which supports the feeds to the antenna (Fig.6.12).

123 s -w - - gori_ lft iAir,,__ ---_____= _ _f_- _ _ -_ —___ ^_-_^ *_ x_ - _ - t-Y Conductor-backed FGC Packaged FGC Fig. 6.12: Cross-section of FGC lines used for distribution network design. The wafer thickness if 100 gm and the metal thickness is approximately 1 gnm. In the second design iteration of the distribution network using CPW-based Wilkinson dividers, Cr/Au metal is evaporated on the backside of the sample to simulate the conductor backed environment. Distribution network results (Fig.6.14) show the same parasitic effect demonstrated in the F'GC line attenuation measurements (Fig.6.4). The continuous ground plane attracts the fields of the FGC line into the substrate and increases the parasitic capacitance of the network. Presented herein are measurements of the individual circuit components in four different line architectures. The sensitivity of the individual elements to circuit environment is clearly shown with performance degradation caused by the presence of neighboring circuit metal. Table 6.2 lists the components which will be shown in the next several pages. The Wilkinson divider is characterized by isolation, back-to-back, and single divider response. The tee-junction is characterized by isolation, input match, and a tee with bend circuit. The right-angle bend is characterized by a double bend circuit. The tee with bend represents the input of the distribution network and the Wilkinson with bend represents the output (Fig.6.13). Comparisons are made between the conductor backed, packaged, conventional, and shielded circuits (Fig.6.15). In the conventional architecture circuit metal lines are isolated from additional conducting layers and produce a reference measurement. The shielded architecture represents the conventional circuits in an on-wafer packaging environment without additional conducting

124 layers and simulates the effects of the shielding cavity on performance. The conductor backed architecture represents a circuit in a multiconductor unpackaged environment. The packaged architecture represents a circuit in a multiconductor environment with on-wafer packaging integrated into the 3-D system. Circuit components Divider isolation Tee-junction isolation Tee input match Tee plus bend Back-to-back dividers Double bend Single divider Table 6.2:Individual circuit components. Output Wilkinson divider 250 50 n 50 Q 430 Tee-Junction 875 Input Fig. 6.13: Layout of final distribution network design.

125 co 10 0) 0) -5 -10 -15 -20 -25 -30 -35 o.. ~... '~~......l - S21. L..~:,..,,,,,, i,,,, I,,, I I ^,,,, I,,,, V 75 80 85 90 95 100 105 1110 Frequency (GHz) of the distribution network in a conductor backed Fig. 6.14: S-Parameter measurements environment.

126 I 2t t Sr 7 r. '' Ajr Sel -- FG r — =-. —e d: — ed -: —;-r — FG -" ' -,... -~s -..-, '^. S-.~i - -.?s-.-: i! -- _'-X Shielded FGC s w -- 4 7 - -; - i '': ' ' - ".: - t'. *. ^-. -: - w L.- - u, 7. =.. ^.r*...:.: - - Conventional FGC 2t j.::::. Packaged FGC,easurements..easurements. s w Conductor-backed FGC Fig. 6.15: Four architectures for individual component m Figure 6.16 shows the single divider circuit with input ports matched. The measured response for each architecture is shown in Figure 6.17. An unwanted resonance occurs at 96 GHz which increases the coupling to -10 dB in the conductor backed circuit. In the other environments the coupling is -20 dB and below for the entire bandwidth. Fig. 6.16: Single divider isolation, input port matched.

127 a 3 * o 3 ea a1 0 -10 -30 -40 -50 - Pcalagec S; ---— Packaged S22 0 C- - - Cco' o - 5' ~1.10 - Conventional S22 i -'\ -20 I i i -i II I qi 'n' i I — ---------- - ----- -0o.......I. I.... I.... I............ I I.. 75 s0 I5 0 0 100 105 110 Frequency (QHz) 75 s0 15 00 9S 10, 10S 110 Frequency (QHz) 0 -10 -20 -30 a A I 2 la la - -- -- - - I ~.- i I I- I, - I - I, - - I -- Shiatdea S2 - - Shi*dWa S21 --—.Shielded S22 I a a aC x1 0 -10 -20 -30 -40 - Conduc!or 3aced SI 11 - - Conductor Backed S21 - Conductor Backed S22 '* \ ^'~ V -40 ) -SO ~ ~ ~ ~ ~ ~ ~......... 1 1~ ~ ~ ~ -...... - 40 75 s0 IS t0 Os 100 105 110 75 o0 *5 Frequency (GHz) Ft Fig. 6.17: Single divider isolation measurements for four architectures. I0 96 100 105 110 requeney (QHz) Figure 6.18 shows the layout for the tee-junction isolation measurement. The coupling levels are consistent for each architecture although a ripple is seen in the conductor-backed circuit (Figure 6.18). 575 Fig. 6.18: Tee junction isolation with input port terminated.

128 - - - - -Sh-ed 5' 1. -— t --- -- ----- 4~ -- j - - 5- S2 - c -5 - -- - — * - -, I Snhe. ad S2 1 -20 - -' - -.,.20.....c Pagr cd 522S 70 0o 1 o s 100 10 110 7a0 0 o 100 1000 110 Fr-4e" (aHz) Frut1ey (QHz) -.0 S2 t 1 - Condntionl 022- n S 220 5 S S 00 S 100 10 110?l O I 0 31 100 110 110 Fmuq.y ( 0Hz) F,Qooy (Os) Fig. 6.19: Tee junction isolation measurements for four architectures. The input match for the tee-junction is shown in Figure 6.20. The packaged circuit has the best performance in the frequency band. The shielded circuit measurement corresponds and the conventional circuit appears to perform best outside of the measurement spectrum. The conductor backed circuit has a high frequency resonance and is more noisy.

129 1 150 -.5 C - onventional _ — ne aaed - en ]~na~uc'e BaCKec 3r' f - - - - -10 - Packaged 530 '. - 2.20 ' ---'d ' 20 s,'. \ * - 415 /.25. -30 ',,.... 1.......,,,.,. I,,.,!-.. -35 75 so as 90 95 100 105 110 Frequency (GHz) Fig. 6.20: Tee junction input match for four architectures. Figure 6.21 shows the insertion loss for the tee with bend. The conventional circuit is best performing followed by close agreement between the packaged and shielded architectures. The ripple in the conductor backed circuit introduces an additional 2 dB of insertion loss within the operating frequency. A comparison of the two multiconductor environments clearly indicates the effectiveness of the package in removing the parasitic ripple (Figure 6.22). 90 _. 600 -3.5 - -Cndc — B" 10 1150 -4 \. — 45 720 415 -\ ' U jConventional -6 -_ -- Packaged / - - Conductor Backed - Shielded -6.5 -7 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.21: Insertion loss for tee plus bend circuit in four architectures.

130 0 ' --- ' 1 ' '; --- —---------------------- -5 -10,.. I -15 -20 Conductor Backed - - - Packaged " -25 -30 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.22: Tee with bend S parameters for conductor backed and packaged environments. Measurements of the back-to-back bend show similar performance with the conventional and shielded lines agreeing very well and a small amount of loss in the packaged circuit (Figure 6.23). An additional 3 dB of insertion loss is caused by the ripple in the conductor backed circuit. A frequency shift is introduced in the conductor backed-circuit in addition to the reduction in insertion loss (Figure 6.24).

131 a * - c t c1 0 -I -2 -3.4 *6 Paccagedb - Conluctor Bacxea Shietdod 4 75 *0 a* 90 S 100 10 110 Frequency (QHz) Fig. 6.23: Measured insertion loss of back-to-back dividers for four architectures. m 03 c. -5 -10 -15 -20 -25 -30 -35 75 80 85 90 95 Frequency (GHz) 100 105 110 Fig. 6.24: Measured S parameters of back-to-back divider for packaged and conductor backed environments. The double bend circuit in Figure 6.25 shows good agreement between the conventional and packaged circuits, with 0.01-0.03 dB reduction in insertion loss for the packaged bends. Additional insertion loss of 1 dB is indicated by

132 the conductor backed circuit. The return loss for the bends is more uniform in the packaged circuit than the conductor backed (Figure 6.26). 830 -0.5 m o a 0 C.1 -1.5 -2 F 75 80 85 90 95 Frequency (GHz) 100 105 110 Fig. 6.25: Measured insertion loss of double bend circuit for four architectures. - ' - - I I I -10 -10 Packaged X ---— Conductor Backed -15 *o L-,-20 -25 -30 -35 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.26: Measured S parameters of double bend in packaged and conductor backed environments.

133 Single divider insertion loss is shown in Figure 6.27. The package response, although higher in insertion loss compared to the shielded and conventional circuits, is more flat and less sensitive. The ripple in the conductor backed circuit affects performance at 100 GHz with this circuit. A resonance occurs in the conductor backed circuit but the return loss is more reasonable for this component (Figure 6.28)..... I... ' '" ' i,,.. 830 | - — h.d. 0 | -4.5 300 Shielded 5 - cPackaged -5\/ - Conductor Backed % ' 35 ' I Conventional 85 90 95 100 105 110 Frequency (GHz) Fig. 6.27: Insertion loss of single divider for parchite ctures. -10 -15 -30.. Conductor Backed -35 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.28: S Parameters of single divider for packaged and conductor backed environment.

134 From observing the measurements, some components are more sensitive to the conductor backed environment than others. In each case the insertion loss was worsened by the presence of the ground plane. Non-packaged circuits demonstrate a varying performance due to parasitic effects that are sensitive to circuit environment. By placing an air/dielectric cavity between the two conducting planes, the parasitic effects are eliminated. 6.5.1 Impact on Distribution Network Individual component performance is critical to feed network efficiency and warrants the extensive measurements for different line architectures. Figure 6.29 shows a comparison between two distribution networks in a conductor backed and packaged environment. The individual component parasitics combine to produce the measured response with insertion loss as low as -"11 dB within the frequency of operation. The response of the packaged circuit is less dependent on frequency (smooth response) and produces an insertion loss of approximately -6.9 dB across the band of interest. Conductor Backed Packaged ________ 30 -.7 Fg M * Conductor Backed p.15 e r -n Packaged. * 0 S 1 -h,/:\ U)-25 -109 cmI 2 -11............. 75 80 85 90 95 100 105 110 90 91 92 93 94 95 Frequency (GHz) Frequency (GHz) Fig. 6.29: Measured S parameters for distribution network in conductor backed and packaged environments.

135 The insertion loss for each output of the distribution network in the conventional architecture is shown in Figure 6.30. The loss of the circuits is -1.5 ~ 0.3 dB with phase balance of ~20 from 90 to 95 GHz. The best results for the distribution network occurs when it is placed in the packaged environment. An insertion loss value of -0.7 dB can be achieved which is equivalent to approximately 85% efficiency. -6 1 ' - ' ' I ' 'I- I I i I I, I T I V I I I -o 0 rmI 0 -8 -10 -12 -14.,,,a. - Output 1 Output 2 I Output 3 Output 4....I!.... I..! ~ i i ' I.. I. I. I i I I.. If -16 75 80 85 90 95 Frequency (GHz) 100 105 110 200 150 100 0 50 0 O) I -s -150 -200 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.30: Distribution loss for all four outputs is approximately -1.5 +/ 0.3 dB and phase balance is +/ 2 degrees.

136 6.5.2 Impact on Cross Coupling Figure 6.31 shows the cross-coupling between unshielded transmission lines in the 4 x 4 array as shown in Figure 6.32. Arrangement A and B refer to nearest neighbor coupling where the lines are separated from the input by approximately 1.5 mm, but in opposite directions. In Arrangement C, the lines are separated by 2.1 mm. 4) Cl) wI cr 0 -10 -20 -30 -40 -50 -60 -70 -80 f 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.31: Cross-coupling measurements of layout with metal backed structure and no upper shielding cavity.

137 Distribution Network Conformal Package f m 0 c3.-. 0) (l c 0 -10 -20 -30 -40 -50 -60 -70 -80 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. 6.32: Cross-coupling measurements of layout with upper shielding cavity and Si carrier.

138 6.6 Summary The technology presented in this chapter can be used to realize high performance low loss W-Band distribution networks using FGC lines. On-wafer packaging provides excellent integration options for 3-D circuits. It is not only useful in providing high isolation between laterally coupled circuits, but it provides excellent solutions for vertical parasitic coupling.These results demonstrate the capability of this technology to provide superior integration options in addition to excellent performance compared to any other planar technology. I

CHAPTER VII CONCLUSIONS 7.1 Conclusions A novel concept of Si micromachined electronic packages for microwave and millimeter-wave applications has been presented in this thesis. The processing techniques are compatible with standard IC technology and help realize low cost, high-precision, integrated on-wafer housings for circuits and interconnects. Conformal shielding cavities have been fabricated around microstrip transmission lines (packaged microstrip) to provide high isolation and reduce coupling levels between neighboring lines to the system noise level. Procedures to thin a standard 500 gm Si wafer in local regions to increase high frequency microstrip performance have been developed. These custom lines compare well with conventional microstrip impedance values and show a reduction in parasitic radiation due to discontinuities. A micromachined Ka-Band Si chip carrier for discrete component packaging has been fabricated and demonstrates superior performance in comparison to its alumina counterpart. The capability of scaling this package to WBand or higher and using it for discrete or on-wafer applications is possible using Si micromachining techniques. Batch-fabrication of the Si-based package can reduce production costly by as much as 30 times the current amount. 139

140 In conjunction with conformal packaging techniques, a comparative study of on-wafer packaging with metal and dielectric shields has been presented. The performance of lines and circuits is compared and indicates that dielectric shielding is sufficient for FGC based circuits. The integration of on-wafer packaging with another enabling technology, flip-chip bonding has been demonstrated in the realization of a 3-stage low noise amplifier circuit. Measurements show that additional FGC line loss caused by the masking dielectric can significantly reduce the expected performance and should be taken into account during the circuit design when a large substrate area is employed. Finally on-wafer packaging has been extended to three-dimensional integration. An extensive study of FGC line performance as a circuit is placed in multiconductor packaging environments is presented. Novel micromachining techniques have been presented to reduce parasitic vertical coupling affects caused by metal layers. The success of this technique is demonstrated in the performance of a complex distribution network for a Si micromachined WBand linear transmitter tile array. 7.2 Recommendations High density circuits and multi-level integration is an important area of research which will greatly benefit from the packaging technology developed within this research. The work presented has been very useful in advancing the RF Si micromachining technology. Fabrication techniques for vertical integration are currently underway in order to make on-wafer packaging a real option for high performing 3-D systems. No standard bonding process exists for this technology and it must be put in place to realize the proposed vertically stacked structures.

More characterization of the mechanical and thermal strength of the packaged circuits should be investigated to give a better comparison to the currently available technologies. It has been shown in Chapter 6 that coupling (vertical and horizontal) can have adverse affects on the performance of circuits. It is important to take advantage of simulation tools to predict coupling trends for simple lines and extend that information to circuit and system design. Figures 7.1 and 7.2 show simulated coupling responses for conventional microstrip and FGC lines. The microstrip line dimensions are obtained from the circuit in Chapter 3 and the FGC dimensions are obtained from the circuit in Chapter 5. HFSS is used to simulate the response with the layouts and methods similar to those described earlier. In Fig. 7.1, the microstrip line coupling level is fairly constant over the frequency band for edge separations up to 2.6 mm (0.42 Xg at 20 GHz). A more pronounced reduction is observed at the higher frequency range when the lines is separated by 4.58 mm (0.75 Xg at 20 GHz). Coupling for the FGC lines is much lower and less sensitive to separation distance. The highest coupling occurs when the ground planes have no separation space and varies with separation distances of 0.87 mm and 1.6 mm (0.25 Xg at 20 GHz) by as much as 20 dB at the design frequency (Fig. 7.2). Modeling of vertical coupling can be used to improve single- and multi-layer circuit and designs in multiconductor environments [86]. 141

0 0 0 2 C -10 -20 -30 -40 -50 60 -70 -80......... 1.58 rryn m —5m - 58.8 mmmm -. -V ^..... I ",,.. \. -— 2.58mmm 5 10 15 20 25 30 35 40 Frquency (GHz) Fig. 7.1: Simulated response of coupling between 50 Q microstrip lines separated by the distances of 1.58, 2.58, and 4.58 mm. 0 I I T V I I, I ] I VI FI I I r r I I V I. I T I I I I I -20 k m I) O -40 40 - 1.6 mm ---- no separation -.87 mm 8 12 16 20 24 28 32 36 Freqnncy (GHz) -0 -100 Fig. 7.2: Simulated response of coupling between 50 Q2 FGC lines distance, 0.87 mm, and 1.6 mm. separated by no 142

of APPENDICES 143

144 APPENDIX A How MMIC Processing Affects the Attenuation of FGC Lines at W-Band A.1 Introduction This section presents a study of the change in loss of finite ground coplanar (FGC) lines on high resistivity Si (HRS), as a result of various MIMIC processing steps. Because coplanar lines are becoming more popular for millimeterwave applications and being used in MMIC fabrication, it is important to determine if any of these steps actually increase the attenuation of the transmission line. We present how metal thickness, high temperature exposure, and masking dielectric presence affect the attenuation of FGC lines at WBand. The cross section of the 50 Q FGC line is shown in Fig. A.1 where wg=106, w=24, s=40 gim. The height, h, of the substrate is either 500 gum or 600 gm and the skin depth of gold (Au) at fc=94 GHz is 0.25 im. Lines are indicated as having no dielectric (no dieletric on wafer prior to processing), a discontinuous dielectric (dielectric removed after metal deposition), or a continuous dielectric (dielectric remains after processing). Discontinuous dielectric No dielectric Continuous dielectric s w s W s W -...... -.................... w. w. i w. h Si Si Si ~ - - -- 1 -........I I I I I II iiii ii l.... Fig. A.1: FGC lines with dimensions wg=106, w=24, s=40 prm.

145 A.2 Methods A set of TRL calibration standards is printed on two thicknesses (500 im and 100 im) of HRS (greater than 2000 ohm-cm). Three different metal thicknesses are printed on the 500 jum-thick wafers with an 8500A thermally grown silicon dioxide (SiO2) etch masking layer. Three micron lines are Au electroplated while lines with one micron or less metallization (0.95 and 0.83 gjm) are evaporated using a lift-off technique. In each case, chromium (Cr) is used as the adhesion layer. The 100 jFm-thick wafer had no dielectric material (Pure Si) and after processing it is attached to a full thickness (500 im) Si carrier using photoresist. Finally, wafers are placed in an oven at 300 ~C for 30 minutes to simulate a wafer-to-wafer bonding process. Table A.1 summarizes the various process environments that might impact the line attenuation. Substrate Metal thickness SiO2 Heated thickness (gam) (tim) 500 3 yes no 500 3 no no 500 0.95 yes yes 500 0.95 no yes 600 1 no yes 600 1 no yes 500 0.83 yes yes 500 0.83 no yes Table A. 1: Different processing environments for the transmission line.

146 A.3 Results The standards are measured from 75-110 GHz with an HP 8510C Network Analyzer using 150 gm pitch G.G.B. Picoprobes on an Alessi Probe Station at room temperature and the attenuation is extracted using NIST's MultiCal program. Figure A.2 shows the loss difference between 3 |m of electroplated Au, with and without SiO2, continuous and discontinuous dielectric, respectively. Because the field lines are primarily confined within the thick metal layer, there is only a small variation (0.3 dB/mm) in attenuation when the oxide is removed. 0.38 0.36 I,,I I, I I I I, I I I I I I I, I I I I TI,,I I I I,,, I I I I, I', I 0.34 - 1 -I I 0 a 0 go 0 12 4. 0.32 03 0.28 0.26 n0 A with oxide..,'. a ~ 4 without oxide I" / q" I~, I / /t I 1 4 I ' J i l. I, i I 1 L I l., L., l l l l I 1 i l I L i V OM" 75 80 85 90 95 Frequency (GHz) 100 105 110 Fig. A.2: The attenuation of 3 micron thick Au electroplated lines with and without 8500 A of SiO2. In the line where less metal is printed, the difference in attenuation is more pronounced and in agreement with results for 1.46 pin-thick Al lines [871. Figure A.3 shows the loss for a 0.95 In-thick metal layer, with and without SiO2.

147 0.5 -. —................- '.......... ' *.. 0.45.-... _..-* '"..,, - 0.4?.-4. with oxide - 035t - j - * - - -" without oxide 0.25 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. A.3: The attenuation of 0.95 micron thick Au evaporated lines with and without 8500 A of SiO2. In addition to determining the effects caused by oxide removal, we show how thicker circuit metal affects the line performance at W-Band. Figure A.4 shows attenuation for varying metal thicknesses with a discontinuous dielectric. The thicker metal circuit (12 skin depths) is lowest in loss while the thinner metals have comparable values. Although the 0.83 im (3.3 skin depths) lines have lower loss than the 0.95 nm (3.8 skin depths) line, it is believed to be due to excessive probing and the measurement error of the system. Figure A.5 shows the attenuation for substrates before and after heating in an oven at 3000C for 30 minutes. Measurements presented herein show that a decrease in attenuation on the order of 0.1 dB/mm occurs for heated wafers (during processing) with SiO2 not yet removed, while wafers without SiO2 removed have only a minor reduction in attenuation.

148 0.4 0.38 0.36 i 3034 co a 032 | 032 0.28 0.26 0.24 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. A.4: Attenuation for three different metal thicknesses on 500 gm-thick HRS. I - Heated ----- Not Heated 0.55 0.5 j 0.45 0 -# a 0.4 < 0.35 0.3 0.25 75 80 85 90 95 100 105 110 Frequency (GHz) Fig. A.5: Attenuation for thicknesses 1 gm or less after being heated for 30 minutes at 300 ~C. Unless noted, the lines still have a continuous dielectric.

149 A.4 Summary It has been shown that certain IC processing steps can affect the attenuation of FGC lines on HRS at W-Band. Removing the masking layer after Si micromachining realizes a discontinuous dielectric between the conductor metal and substrate and reduces the attenuation by approximately 0.1 dB/mm at fc for one micron thick lines. Placing a sample with continuous SiO2 in a 300 "C oven for approximately 30 minutes can reduce loss by as much as 0.1 dB/mm as well. Finally, adding thicker conductor metal by electroplating, a more costly option, can reduce attenuation only by approximately 0.03 dB/ mm. This measurement confirms the design rule that only 3-5 skin depths is necessary to obtain low-loss results [88]. The information presented herein can be useful to a designer when presented with the dilemma of reducing transmission line loss to obtain better circuit performance.

APPENDIX B FABRICATION OF PACKAGED MICROSTRIP B.1 Introduction The fabrication steps of the K-Band conformal package for microstrip transmission lines are presented in this appendix. Two 500 im, double-side polished Si wafers, one high resistivity for the circuit and lower cavity and another low resistivity for the upper shielding cavity are used. All processing steps except etching are conducted in a clean room environment with deionized water (DI H20) for rinsing. At the time of this fabrication, the dielectric masking layers consisted of a membrane tri-layer (SiO2/Si3N4/SiO2), (8500A/3500A/4500A). The photoresist used during that time, PR1400-37 manufactured by Shipley, Inc., has been discontinued. The recommended replacement is PR1827. Unless otherwise indicated, all baking is done using a hotplate. B.2 Circuit Wafer With Lower Cavity ALIGNMENT MARKS DEFINITION 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Spin HMDS, PR AZ5214 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose alignment mark mask for 6.5 seconds. 150

4. Hardbake resist in for 1 minute at 130~C. 5. Image reversal flood expose wafer for 90 seconds. 6. Develop wafer in AZ 327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 7. Inspect lithography using light filtered microscope. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 8. Evaporate Ti/Au (500A/2000A) on wafer. 9. Lift-off unwanted metal in warmed ACE for approximately 2 hours. 10. Rinse in IPA. Dehydrate bake at 130~C for 2 minutes. DC CONTACT (DIELECTRIC REMOVAL) FABRICATION To provide DC contact between the front and back side of Si wafers. 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Protect the dielectric on the backside of the wafer by spinning HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes. 3. Flip wafer over and spin HMDS and PR 1400-37 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 4. Align and expose dielectric removal mask for 15 seconds. 5. Develop wafer in MF351 for 40-70 seconds. Rinse for 2 minutes and dry with N2. 6. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 151

7. Etch 4500A SiO, with BHF (etch rate 1000lAmin) for 5-6 minutes. Rinse for 3 minutes and dry with N2. 8. Etch nitride with plasma etcher using 02 (0.5 sccm) and CF4 (20 sccm) at 250 mT with RF power of 100W for 8 minutes. 9. Etch SiO2 with BHF (etch rate 1000lAmin) for 8-9 minutes. Rinse for 3 minutes and dry with N2. 10. Remove excess resist with ACE/IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. CIRCUIT METAL FABRICATION (PLATING 3 iLm) This mask also covers the areas exposed for DC contact. 1. Descum wafer for 0.6 minutes at 80 W, of 02 at 250 mT. 2. Evaporate Ti/Au/Ti (500A/1000lA/500A) seed layer on wafer. 3. Spin PR1400-37 at 3.5 krpm for 30 seconds. Softbake at 105 ~C for 1 minute. 4. Align and expose circuit metal mask for 15 seconds. 5. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 6. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. Using an ACE dipped swab, expose a small corer of Ti to provide contact when placing sample in the plating station set-up. 7. Dektak to measure height of resist. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 152

8. Plate circuit metal 3 im thick. Dektak to measure height of plated Au. Continue plating until the difference between plated Au and PR height is < 5000A. 9. Remove resist in ACE/IPA. Dry with N2. 10. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. Etch Au seed layer in TFA Gold etchant for 30-45 seconds. Rinse for 2 minutes and dry with N2.Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. CAVITY DEFINITION FOR CIRCUIT WAFER 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Protect the frontside of the wafer by spinning HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes on hotplate. 3. Flip wafer over and spin HMDS and PR 1400-37 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 4. Align and expose cavity mask (1) for 15 seconds. 5. Develop wafer in MF351 for 40-70 seconds. Rinse for 2 minutes and dry with N2. 6. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 7. Etch SiO2 with BHF (etch rate 1000A/min) for 5-6 minutes. Rinse for 3 minutes and dry with N2. 8. Etch nitride with plasma etcher using 02 (0.5 sccm) and CF4 (20 sccm) at 250 mT with RF power of 100W for 8 minutes. The single layer of oxide will be left on the wafer to protect the locally thinned regions. 153

9. Remove excess resist with ACE, IPA. Dry with N2. Remove excess solvents by baking at 130~C for 2 minutes. THINNED REGION PROTECTION 1. Protect the frontside of the wafer by spinning HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes on hotplate. 2. Flip wafer over and spin HMDS and PR 1400-37 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose dielectric removal (1) mask for 15 seconds. 4. Develop wafer in MF351 for 40-70 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 6. Etch 8500A SiO2 with BHF (etch rate 1000A/min) for 8-9 minutes. Rinse for 3 minutes and dry with N2. At this point, the shielding grooves are completely exposed while the locally thinned areas are protected with the final layer of SiO2. WAFER ETCHING (USING EDP) 1. Solution recipe for 1 X batch: 48mL of DI water, 48g of catechol, 0.9g of pyrazine, and 150mL of ethylenediamine. Heat the solution to 11 0~C and let stabilize for 30 minutes. The solution color should be a golden honey color. The etch rate is 72gm/hour. 2. Place the samples in BHF for 20 seconds to remove the native oxide layer and rinse for 3 minutes. Immediately place the samples in the solution and cover with aluminum foil. After five hours, at least 350gm 154

of Si should be removed in the cavity areas. Remove the samples from the solution and rinse in DI water for 5 minutes. Re-cover the solution with foil. 3. Inspect cavity depth with a microscope in a dirty (non-clean room environment) room and calculate the true etch rate. If the cavities have etched the estimated thickness, place the samples in BHF to remove the locally thinned regions. 4. Rinse for 5 minutes and immediately place the samples back in the EDP solution to etch the locally thinned regions and complete the cavity etch. For this case the desired thinned region is between 150 and 180 gm, which implies an additional etch time of 2 hours if the estimated etch rate is 72gm/hr. 5. After etching, remove the samples from the solution and rinse in DI water for 5 minutes. 6. Inspect the thinned region depth with a microscope in a dirty (non-clean room environment) room. At this point the samples are contaminated and can not be taken back into the clean room until after a 6 hour cleansing process which removes EDP residue. The total etch time for this process is in excess of 8 hours if the inspection and rinse times are included. It is important to cover the EDP with foil because 02 exposure can alter the solution etch rate. The longer one etches, the dirtier the solution becomes and the more residue will be left on the wafer. 7. Place the samples in methanol for at least six hours. Rinse with ACE, IPA and then dry with N2. CAVITY METALLIZATION Mount circuit wafer on a Si carrier with circuit metal facing down to expose 155

cavities for deposition. 1. Obtain Si carrier wafer (larger than circuit wafer) and small pieces of Si for standoff purposes. 2. Place small drops PR on the bottom of the standoff pieces and mount them to the carrier wafer. Hardbake at 130~C for 3 minutes. Using tweezers, try to move standoff. If secure move on, if not, add more resist and reheat. 3. Place PR on top of standoff pieces and mount inverted circuit wafer onto carrier. Hardbake at 130~C for 3 minutes. Test for movement. 4. Evaporate Ti/Al/Ti/Au (500A/12000A/500A/3000A) on backside of wafer. 5. Place sample in ACE for 20-30 minutes for dismounting. Rinse with IPA and dry with N2. B.3 Shielding Cavity Fabrication ALIGNMENT MARKS 1. Spin HMDS, PR AZ5214 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 2. Align and expose alignment mark mask for 6.5 seconds at 20 mW/cm2. 3. Hardbake resist in for 1 minute at 130~C. 4. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 5. Develop wafer in AZ 327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 156

6. Inspect lithography using light filtered microscope. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 7. Evaporate Ti/Au (500A/2000A) on wafer. 8. Lift-off unwanted metal in warmed ACE for approximately 2 hours. 9. Rinse in IPA. Dehydrate bake at 130~C for 2 minutes. PROBE WINDOW DEFINITION (BACKSIDE) 1. Protect the frontside of the wafer by spinning HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes. 2. Flip wafer over and spin HMDS and PR 1400-37 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose probe window (1) mask for 15 seconds at 20 mW/cm2 using the infrared option on the mask aligner. The marks deposited earlier will be used for alignment. 4. Develop wafer in MF351 for 40-70 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 6. Etch SiO2 with BHF (etch rate 1000A/min) for 5-6 minutes. Rinse for 3 minutes and dry with N2. 7. Etch nitride with plasma etcher using 02 (0.5 sccm) and CF4 (20 sccm) at 250 mT with RF power of 100W for 8 minutes. 8. Etch SiO2 with BHF (etch rate 1000lA/min) for 7-8 minutes. Rinse for 3 minutes and dry with N2. 157

9. Remove excess resist with ACE/IPA. Dry with N1. Dehydrate bake at 130~C for 2 minutes. CAVITY DEFINITION (FRONTSIDE PROCESSING) 1. Protect the backside of the wafer by spinning HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes. 2. Flip wafer over and spin HMDS and PR 1400-37 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose probe window/cavity (2) mask for 15 seconds at 20 mW/cm2. 4. Develop wafer in MF351 for 40-70 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 6. Etch SiO2 with BHF (etch rate lOOOAmin) for 5-6 minutes. Rinse for 3 minutes and dry with N2. 7. Etch nitride with plasma etcher using 02 (0.5 sccm) and CF4 (20 sccm) at 250 mT with RF power of 100W for 8 minutes. 8. Etch SiO2 with BHF (etch rate 1000A/min) for 7-8 minutes. Rinse for 3 minutes and dry with N2. 9. Remove excess resist with ACE/IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. WAFER ETCHING (USING EDP) 1. Use same solution recipe as described in earlier section. 158

2. Place the samples in BHF for 20 seconds to remove the native oxide layer and rinse for 3 minutes. Immediately place the samples in the solution and cover with aluminum foil. After 3.5 hours, the probe windows should be exposed and the cavities should be etched the appropriate depth of approximately 400 gm. Remove the samples from the solution and rinse in DI water for 5 minutes. Re-cover the solution with foil. 3. Inspect the cavity regions using a microscope in a dirty (non-clean room environment) room. If the cavity depth is correct and the probe windows are open, the wafer is done. At this point the samples are contaminated and can not be taken back into the clean room until after a 6 hour cleansing process which removes EDP residue. 4. Place the samples in methanol for at least six hours. Rinse with ACE, IPA and then dry with N2. CAVITY METALLIZATION 1. Evaporate Ti/Al/Ti/Au (500A/12000A/500A/3000A) on backside of wafer. 159

APPENDIX C FABRICATION OF SILICON CHIP CARRIER C.1 Introduction This section contains the fabrication steps for the Ka-Band Si chip carrier and test circuit. Four wafers are used to fabricate the chip carrier. The masking dielectric on the wafers is SiO2. Three hundred fifty micron-thick, double-side polished high resistivity Si wafers are used for the RF substrate wafer and seal frame wafer. The carrier and top cover can be fabricated using low resistivity Si. All processing steps except etching are done in a clean room environment with deionized water (DI H20) for rinsing. Unless otherwise indicated, all baking is done using a hotplate. In order to process one on-wafer package, five individual wafers must be fabricated and then assembled. The microstrip through line wafer (for package characterization) needs circuit metal and ground plane definition in addition to alignment marks for dicing. C.2 Fabrication Steps WAFER PREPARATION 1. Measure the wafer thickness using Mituyoto gauge and the dielectric thickness with the SP. 2. Scribe wafer into appropriate pieces for processing. 3. Clean the samples with hydrogen peroxide: sulfuric acid (1:1.2) for 15 minutes. Rinse in DI water. Dry with nitrogen (N2). 160

DC CONTACT (UPPER VIA APERTURE) FABRICATION 1. Spin HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Softbake at 105~C for 1 minute. 2. Align and expose dielectric removal mask for 15 seconds at 20 mW/ cm2. 3. Develop wafer in MF351 for 40-70 seconds. Rinse for 2 minutes and dry with N2. 4. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 5. Etch SiO2 with BHF (etch rate 1000A/min) for 7-8 minutes. Rinse for 3 minutes and dry with N2. 6. Remove excess resist with ACE/IPA. Dry with N2. Remove excess solvents by baking at 130~C for 2 minutes. CIRCUIT METAL AND OVERLAY PADS 1. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 2. Evaporate Ti/Au/Ti (500A/1000A/500A) on wafer. 3. Spin PR1400-37 at 3.5 krpm for 30 seconds. Softbake at 105 ~C for 1 minute. 4. Align and expose circuit metal mask for 15 seconds at 20 mW/cm2. 5. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 6. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute. 161

7. Dektak to measure height of resist. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 8. Plate circuit metal 3 gim-thick. Dektak to measure height of plated Au. 9. Remove resist in ACE/IPA. Dry with N2. 10. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. Etch Au seed layer in TFA Gold etchant for 30-45 seconds. Rinse for 2 minutes and dry with N2. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. IC APERTURE DEFINITION 1. Protect the frontside of the wafer by spinning HMDS and PR 1400-37 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes on hotplate. 2. Flip wafer over and spin HMDS, AZ5214 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose IC aperture mask for 4 seconds at 20 mW/cm2. 4. Hardbake resist in oven for 1 minute at 130~C. 5. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 6. Develop wafer in AZ 327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 7. Inspect lithography using light filtered microscope. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 8. Evaporate Cr/Au (500A/2500A) on wafer. 9. Lift-off circuit metal in warmed ACE for approximately 2 hours. WAFER ETCHING 162

1. Solution recipe for 1 X batch: 48mL of DI water, 48g of catechol. 0.9g of pyrazine, and 150mL of ethylenediamine. Heat the solution to 110~C and let stabilize for 30 minutes. The etch rate for this recipe and temperature is 72gm/hour. 2. Place the samples in BHF for 20 seconds to remove the native oxide layer and rinse for 3 minutes. Immediately place the samples in the solution and cover with aluminum foil. 3. After etching, remove the samples from the solution and rinse in DI water for 5 minutes. 4. Inspect cavity depth with a microscope in a dirty (non-clean room environment) room. At this point the samples are contaminated and can not be taken back into the clean room until after a 6 hour cleansing process which removes EDP residue. 5. Place the samples in methanol for at least six hours. Rinse with ACE, IPA and then dry with N2. VIA METALLIZATION 1. Obtain carrier Si wafer and standoff pieces. Spin PR AZ4620 at 2krpm for 30 seconds. 2. Place standoffs in strategic locations near the edge of where inverted circuit wafer will lay. 3. Place small drops of photoresist on standoffs and add inverted circuit. Bake carrier on hotplates of temperatures, 80 and 130~C for 2 minutes each. 4. Evaporate 1.55 mm Ti/Al/T/Au (0.05/1.2/0.05/0.3) for DC contact. 163

CARRIER AND TOP COVER METALLIZATION 1. Metallize the top cover and carrier with 1.55.tm Ti/AL/Ti/Au (0.05/1.2/ 0.05/0.3). 2. Dice the top cover wafer into 7.112 mm x 7.112 mm square pieces. MICROSTRIP THROUGH LINE 1. The through line can be defined with two masks, one for microstrip and the other for dicing alignment marks. Three microns of electroplated Au can be deposited on the upper ground while the backside ground is formed by evaporating 1.55 gtm Ti/Al/Ti/Au. 164

APPENDIX D FABRICATION OF A 3-STAGE LOW NOISE AMPLIFIER CIRCUIT D.1 Introduction This appendix describes the process steps for the three-stage low noise amplifier circuit designed at K-Band using FGC lines. Two five hundred micron-thick, double-side polished high resistivity Si wafers are used for the circuit wafer and cavity wafer. All processing steps except etching are done in a clean room environment with deionized water (DI H20) for rinsing. Unless otherwise indicated, all baking is done using a hotplate. In order to reduce line loss, and if no etching is to occur on a wafer, it is important to remove the masking dielectric before circuit processing. D.2 Circuit Wafer Fabrication WAFER PREPARATION 1. Measure the wafer thickness using Mituyoto gauge and the dielectric thickness with the SP. 2. Scribe wafer into appropriate sample sizes for processing. 165

166 3. Clean the sample with hydrogen peroxide: sulfuric acid (1:1.2) for 15 minutes. Rinse in DI water. Dry with nitrogen (N2). RESISTOR METAL WITH TANTALUM NITRIDE 1. Sputter tantalum nitride (TaN), titanium-tungsten (10%) (Ti/W) (3.5 minute deposition/I minute deposition) on samples. This is equivalent to a sheet resistance Rs of approximately 332/square. 2. Spin PR 1813 at 4krpm for 30 seconds. Softbake at 105 ~C for 1 minute. 3. Align and expose resistor mask for 6 seconds at 20 mW/cm2. 4. Develop wafer in MF351:DI (1:5) for 20-30 seconds only. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Measure the width of the resistors using the micrometer in the microscope eyepiece. 6. Hard bake resist at 130 ~C for 1 minute. 7. Etch TaN/TiW in RIE using SF6 (10 sccm) and Ar2 (5 sccm) at 10 mT with RF Power of 100mW for 6 minutes. 8. Descum in 02 plasma asher with 150mW of RF power at 250mT for 3 minutes. 9. Strip PR and dismount samples in hot PRS2000 for 20-30 minutes. Rinse for 2 minutes and dry with N2. 10. Clean samples in HCl:DI (1:10) for 2 minutes. Rinse for 2 minutes and dry with N2. CIRCUIT METAL (AU ELECTROPLATING) 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes.

167 2. Descum for 0.6 minutes at 80 W, of 0 at 250 mT. 3. Evaporate Ti/Au/Ti (500A/1000A/500A) on wafer. 4. Spin PR1827 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 5. Align and expose circuit metal mask for 15 seconds at 20 mW/cm2. 6. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 7. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute on hotplate. 8. Dektak to measure height of resist. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 9. Plate circuit metal 3 microns thick. Dektak to measure height of plated Au. 10. Remove resist in ACE/IPA. Dry with N2. 11. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. Etch Au seed layer in TFA Gold etchant for 30-45 seconds. Rinse for 2 minutes and dry with N2.Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 12. Etch Ti/W in H202 for 5 minutes. Rinse for 2 minutes and dry with N2. NICKEL (NI) SOLDERABLE PADS (Optional) 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Spin HMDS, AZ5214 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute.

168 3. Align and expose Ni pad mask for 4 seconds at 20 mW/cm2. 4. Hardbake resist in oven for 1 minute at 130~C. 5. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 6. Develop wafer in AZ 327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 7. Inspect lithography using light filtered microscope. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 8. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 9. Evaporate Ti/Ni/Au (250A/1800A/250A) on wafer. 10. Lift-off metal in warmed ACE for approximately 2 hours. POLYIMIDE SOLDER WELLS 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Spin adhesion promoter at 3.5 krpm and PI 2545 at 3.5 krpm for 30 seconds. Softbake at 140~C for 30 minutes in "dirty" oven. 3. Spin PR 1813 at 4 krpm for 30 seconds. Softbake at 105~C for 1 minute. 4. Align and expose Ni pad mask for 5 seconds at 20 mW/cm2. 5. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. The solution is developing the pattern and while etching the polyimide. After the first development and rinse, inspect the sample to see how much polyimide has been removed. Perform 15 second etches in developer until complete. The developer tends to overetch the polyimide if close attention is not given during this step.

169 6. Place sample in "dirty" oven at 150~C. increase temperature to 300~C. Hardbake polyimide at 300~C for 3 hours. Decrease temperature and take sample out when oven is at 150~C. Let sample cool for 20-30 minutes. MIM CAPACITORS WITH ALUMINA 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Spin PR1827 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose capacitor post mask for 15 seconds at 20 mW/cm2. 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake at 130~C for 1 minute on hotplate. 6. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 7. Evaporate 700A Ti on wafer. 8. Spin AZ5214 at 3.5 krpm for 30 seconds. Softbake at 105"C for 1 minute. 9. Align and expose capacitor span mask for 4 seconds at 20 mW/cm2. 10. Hardbake resist for 1 minute at 130~C. 11. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 12. Develop wafer in AZ 327 for 30-50 seconds. Rinse for 2 minutes and dry with N2.

170 13. Inspect lithography using light filtered microscope. Descurn for 0.6 minutes at 80 W, of 02 at 250 mT. 14. Evaporate Al203/Ti/Au (1500A/500A/4000A) on wafer. 15. Lift-off layers in warmed ACE overnight. AIRBRIDGES 1. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. 2. Spin HMDS and PR1827 at 3 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose airbridge post mask for 10 seconds at 20 mW/cm2. 4. Develop wafer in MF35 1 DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Descum in 02 plasma asher with 80mW of RF power at 250mT for 1 minute. 6. Evaporate Ti/Au/Ti (500A/1000A/500A) seed layers on wafer. 7. Spin PR1827 at 3 krpm for 30 seconds. Softbake at 80~C for 20 minutes in oven. 8. Align and expose airbridge span mask for 22 seconds at 20 mW/cm2. 9. Develop wafer in MF35 1:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 10. Inspect lithography using light filtered microscope. Descum in 02 plasma asher with 80W of RF power at 250mT for 1 minute. 11. Dektak to measure height of resist. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2.

171 12. Plate airbridges 2 to 3 microns thick. Dektak to measure height of plated Au. 13. Flood expose wafer for 3 minutes at 20 mW/cm2. Develop resist in MF35 1 DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with No. 14. Etch Ti seed layer in HF:DI (1: 10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. Etch Au seed layer in TFA Gold etchant for 30-45 seconds. Rinse for 2 minutes and dry with N2. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 15. Strip final resist layer and remove wafers from Si carrier by placing them in hot PRS2000 for 20-30 minutes. Rinse 3-5 minutes and dry with N2. D.3 Shielding Cavity Fabrication ALIGNMENT MARKS 1. Spin HMDS, AZ5214 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 2. Align and expose alignment mark mask for 4 seconds at 20 mW/cm2. 3. Hardbake resist for 1 minute at 130~C. 4. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 5. Develop wafer in AZ 327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 6. Inspect lithography using light filtered microscope. Descum for 0.6 minutes at 80 W, of 02 at 250 mT. 7. Evaporate Ti/Au (500A/2000A) on wafer.

172 8. Lift-off metal in warmed ACE for approximately 2 hours. PROBE WINDOW DEFINITION (BACKSIDE) 1. Protect the backside of the wafer by spinning HMDS and PR 1827 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes. 2. Flip wafer over and spin HMDS and PR 1827 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose probe window (1) mask for 12 seconds at 20 mW/cm2 using the infrared option on the mask aligner. The marks deposited earlier will be used for alignment. 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake resist in oven for 1 minute at 1300C. 6. Etch the dielectric (SiO2) with buffered hydrofluoric acid (BHF) according to the thickness and etch rate of 1000A/minute. Rinse for 2 minutes and dry with N2. PROBE WINDOW/CAVITY DEFINITION (FRONTSIDE) 1. Protect the backside of the wafer by spinning HMDS and PR 18:27 at 3.0 krpm for 30 seconds. Hardbake at 130~C for 2 minutes. 2. Flip wafer over and spin HMDS and PR 1827 at 3.5 krpm for 30 seconds. Softbake at 105~C for 1 minute. 3. Align and expose probe window/cavity mask for 12 seconds at 20mW/ cm2. This mask protects the cavity, while exposing the probe windows so etching can occur from both sides of the wafer to reduce the probe window etch time by a factor of two

173 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake resist in oven for 1 minute at 130~C. 6. Etch the dielectric (SiO2) with (BHF) at an etch rate of 1000lA/minute. Rinse for 2 minutes and dry with N2. 7. Clean wafer with ACE, IPA. Dry with N2. Dehydrate bake at 130~C for 2 minutes. WAFER ETCHING (USING EDP) 1. Solution recipe for 1 X batch: 48mL of DI water, 48g of catechol, 0.9g of pyrazine, and 150mL of ethylenediamine. Heat the solution to 110~C and let stabilize for 30 minutes. The etch rate for this recipe and temperature is 72gm/hour. 2. Place the samples in BHF for 20 seconds to remove the native oxide layer and rinse for 3 minutes. Immediately place the samples in the solution and cover with aluminum foil.Place the samples in the solution and cover with aluminum foil. It should take no more than 45 minutes to etch the probe windows. Remove the samples from the solution and rinse in DI water for 5 minutes. 3. Place the samples in BHF at an etch rate of 10OOA/minute to expose the cavities and rinse for 5 minutes. 4. Immediately place samples back in the EDP solution and etch the desired cavity height based on the etch rate of 72gm/hour. 5. After etching, remove the samples from the solution and rinse in DI water for 5 minutes.

174 6. Inspect cavity depth with a microscope in a dirty (non-clean room environment) room. At this point the samples are contaminated and can not be taken back into the clean room until after a 6 hour cleansing process which removes EDP residue. 7. Place the samples in methanol for at least six hours. Rinse with ACE, IPA and then dry with N2.

APPENDIX E FABRICATION OF W-BAND OUTPUT DISTRIBUTION NETWORK E.1 Introduction The fabrication steps for the W-Band output distribution network with a conformal package are listed in this appendix. One hundred micron-thick high resistivity bare Si (HRS) wafers are used to fabricate the circuit and cavity layers. The wafers have been thinned from 500 to 100 pum with a mirror polish on both sides by Addison Engineering, Inc. [89]. All processing steps except etching are performed in a clean room environment with deionized water (DI H20) for rinsing. Some common processing steps will be placed in this section so as not to repeat unnecessary steps. WAFER PREPARATION 1. Measure the wafer thickness using the Mituyoto gauge and the dielectric thickness with the SP. 2. Scribe the wafer into appropriate sample sizes for processing (dependent on mask layout). 3. Clean the samples with hydrogen peroxide: sulfuric acid (1:1.2) for 15 minutes. Rinse for 3 minutes. Dry with nitrogen (N2). E.2 Circuit Wafer Fabrication RESISTOR DEVELOPMENT 175

1. Sputter TaN/TiW (900A= 2.5 minute deposition/ 100A=1 minute deposition) on samples. This is equivalent to a sheet resistance, Rs = 44 Q/ square. 2. Mount samples on Si carrier wafers for ease of handling. Spin photoresist (PR) AZ4620 at 2krpm for 30 seconds. Place sample on carrier and bake on hotplates of temperatures, 80~C and 130~C for 2 minutes each. 3. Spin PR 1813 at 4krpm for 30 seconds. Softbake at 105 ~C for 1 minute. 4. Align and expose resistor mask for 6 seconds at 20 mW/cm2. 5. Develop wafer in MF351:DI (1:5) for 20-30 seconds only. Rinse for 2 minutes and dry with N2. 6. Inspect lithography using light filtered microscope. Measure the width of the resistors using the micrometer in the microscope eyepiece. 7. Hard bake resist at 130~C for 1 minute. 8. Etch TaN/TiW in RIE using SF6 (10 sccm) and Ar2 (5 sccm) at 10 mT with RF Power of 100 W for 5 minutes. 9. Remove resist with ACE, IPA. Dry with N2. 10. Descum in 02 plasma asher with 150 W of RF power at 250 mT for 3 minutes. 11. Strip PR and dismount samples in hot PRS2000 for 20-30 minutes. Rinse for 2 minutes and dry with N2. 12. Clean samples in HCl:DI (1:10) for 2 minutes. Rinse for 2 minutes and dry with N2. CIRCUIT METAL DEPOSITION 1. Mount samples on glass slide carriers. 176

2. Spin HMDS and PR AZ5214 at 2.5 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose circuit metal mask for 5 seconds at 20 mW/cm2. 4. Hardbake resist in oven for 1 minute at 130~C. 5. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 6. Develop wafer in concentrated AZ327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 7. Inspect lithography using light filtered microscope. Measure the aspect ratio of the circuit metal. Descum in 02 plasma asher with 80 mW of RF power at 250 mT for 1 minute. 8. Evaporate Cr/Au (500A/9500A) on wafer. 9. Lift-off circuit metal in warmed ACE for approximately 2 hours. AIRBRIDGES 1. Mount samples on Si carrier wafers. 2. Spin HMDS and PR1827 at 3 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose airbridge post mask for 10 seconds at 20 mW/cm2. 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Descum in 02 plasma asher with 80 W of RF power at 250 mT for 1 minute. 6. Evaporate Ti/AuTTi (500dA/1000/500A) seed layers on wafer. 7. Spin PR1827 at 3 krpm for 30 seconds. Softbake at 80~C for 20 minutes in oven. 177

8. Align and expose airbridge span mask for 22 seconds at 20 mW/cm2. 9. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 10. Inspect lithography using light filtered microscope. Descum in 02 plasma asher with 80 mW of RF power at 250 mT for 1 minute. 11. Dektak to measure height of resist. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 12. Plate airbridges 2 to 3 microns thick. Dektak to measure height of plated Au. 13. Flood expose wafer for 3 minutes at 20 mW/cm2. Develop resist in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 14. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. Etch Au seed layer in TFA Gold etchant for 30-45 seconds (etch rate of 28A/sec). Rinse for 2 minutes and dry with N2. Etch Ti seed layer in HF:DI (1:10) for 3-5 seconds. Rinse for 2 minutes and dry with N2. 15. Strip final resist layer and remove wafers from Si carrier by placing them-in hot PRS2000 for 20-30 minutes. Rinse 3-5 minutes and dry with N2. E.2.1 Backside Metallization 1. Obtain carrier Si wafer and standoff pieces. Spin PR AZ4620 at 2 krpm for 30 seconds. 2. Place standoffs in strategic locations near the edge of the carrier wafer where the inverted circuit wafer will lie. 178

3. Place small amounts of resist on standoffs using swabs and mount inverted circuit wafer. Bake carrier on hotplates of temperatures, 80~C and 130~C for 2 minutes each. 4. Evaporate Cr/Au (500A/4000A) on backside of circuit wafer. 5. Place sample in hot PRS2000 for 20-30 minutes for dismounting. Rinse 3-5 minutes and dry with N2. E.3 Shielding Cavity Fabrication ALIGNMENT MARKS (FRONTSIDE) 1. Mount samples on glass slide carriers. 2. Spin HMDS and PR AZ5214 at 2.5 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose alignment mark mask for 5 seconds at 20 mW/cm2. 4. Hardbake resist in oven for 1 minute at 130~C. 5. Image reversal flood expose wafer for 90 seconds at 20 mW/cm2. 6. Develop wafer in concentrated AZ327 for 30-50 seconds. Rinse for 2 minutes and dry with N2. 7. Inspect lithography using light filtered microscope. 8. Evaporate Cr/Au (500A/2000A) on wafer. 9. Lift-off metal in warmed ACE for approximately 2 hours. PROBE WINDOW DEFINITION (BACKSIDE) 1. Mount samples on glass slide carriers. 179

2. Spin HMDS and PR1827 at 3 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose probe window (1) mask for 12 seconds at 20 mW/cm2 using the infrared option on the mask aligner. The marks deposited earlier will be used for alignment. 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake resist in oven for 1 minute at 130~C. 6. Etch the dielectric (SiO2) with buffered hydrofluoric acid (BHF) according to the thickness and etch rate of 1000/Aminute. Rinse for 2 minutes and dry with N2. 7. Place sample in hot PRS2000 for 20-30 minutes for dismounting and resist removal. Rinse 3-5 minutes and dry with N2. CAVITY DEFINITION (FRONTSIDE) 1. Mount samples on glass slide carriers. 2. Spin HMDS and PR1827 at 3 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose cavity mask for 12 seconds at 20 mW/cm2. This mask exposes the cavity and probe windows from the frontside of the wafer. 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake resist in oven for 1 minute at 130~C. 180

6. Etch only half of the dielectric (SiO2) thickness with buffered hydrofluoric acid (BHF) at an etch rate of lOOOA/minute. Rinse for 2 minutes and dry with N2. 7. Place sample in hot PRS2000 for 20-30 minutes for dismounting and resist removal. Rinse 3-5 minutes and dry with N2. PROBE WINDOW DEFINITION (FRONTSIDE) 1. Mount samples on glass slide carriers. The alignment marks should be visible. 2. Spin HMDS and PR1827 at 3 krpm for 30 seconds. Softbake at 105~C for 1 minute on hotplate. 3. Align and expose probe window (2) mask for 12 seconds at 20mW/cm2. This mask protects the cavity, while exposing the probe windows so etching can occur from both sides of the wafer to reduce the probe window etch time by a factor of two 4. Develop wafer in MF351:DI (1:5) for 60 seconds. Rinse for 2 minutes and dry with N2. 5. Inspect lithography using light filtered microscope. Hardbake resist in oven for 1 minute at 130~C. 6. Etch the remaining dielectric (SiO2) thickness in the probe windows with BHF. Rinse for 2 minutes and dry with N2. 7. Place sample in hot PRS2000 for 20-30 minutes for dismounting and resist removal. Rinse 3-5 minutes and dry with N2. WAFER ETCHING (USING EDP) 181

1. Solution recipe for 1 X batch: 48mL of DI water, 48g of catechol, 0.9g of pyrazine, and 150mL of ethylenediamine. Heat the solution to 1 10~C and let stabilize for 30 minutes. The etch rate for this recipe and temperature is 72 gm/hour. 2. Place the samples in BHF for 20 seconds to remove any native oxide layer that may have formed. Rinse for 3 minutes and immediately place the samples in the solution and cover with aluminum foil. It should take no more than 45 minutes to etch the probe windows because the probe windows. Remove the samples from the solution and rinse in DI water for 5 minutes. 3. Place the samples in BHF to expose the cavities and rinse for 5 minutes. 4. Immediately place samples back in the EDP solution and etch the desired cavity height based on the etch rate of 72 gm/hour. 5. After etching, remove the samples from the solution and rinse in DI water for 5 minutes. 6. Inspect cavity depth with a microscope in a dirty (non-clean room environment) room. At this point the samples are contaminated and can not be taken back into the clean room until after a 6 hour cleansing process which removes EDP residue. 7. Place the samples in methanol for at least six hours. Rinse with ACE, IPA and then dry with N2. 182

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