ENGN UMR0001 lc~ aD 0 Research and Development Technical Report ECOM -0138-29-T Modeling and Analysis of:. Tuned Power Amplifiers _Technical Report No. 218 by Ned E. Abbott 0 * November 1971 0 * DISTRIBUTION STATEMENT *~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~ Distribution limited to U.S. Government agencies only; Test and Evaluation; 30 Auig 71 Other requests for this document must be referred to Commanding, General, U. S. Army Electronics Command, ATTN: AMSEL-WL-S, Fort Monmouth, N. J. 07703 UNITED STATES ARMY ELECTRONICS COMMAND' FORT MONMOUTH, N.J. CONTRACT DAAB07-68-C-0138 COOLEY ELECTRONICS LABORATORY Department of Electrical and Computer Engineering The University of Michigan Ann Arbor, Michigan 48105

NOTICES Disclaimers The findings in this report are not to be construed as an official Department of the Army position, unless so designated by other authorized documents. The citation of trade names and names of manufacturers in this report is not to be construed as official Government indorsement or approval of commercial products or services referenced herein. Disposition Destroy this report when it is no longer needed. Do not return it to the originator. i4~RAWV~

Technical Report ECOM- 0138- 29- T November 1971 MODELING AND ANALYSIS OF TUNED POWER AMPLIFIERS C. E.L. Technical Report No. 218 Contract No. DAAB07- 68-C- 0138 DA Project No. 1H021101 A042.01.02 Prepared by Ned E. Abbott COOLEY ELECTRONICS LABORATORY Department of Electrical and Computer Engineering The University of Michigan Ann Arbor, Michigan for U. S. Army Electronics Command, Fort Monmouth, N. J. DISTRIBUTION STATEMENT Distribution limited to U.S. Government agencies only; Test and Evaluation; 30 Aug 71 Other requests for this document must be referred to Commanding, General, U. S. Army Electronics Command, ATTN: AMSEL-WL-S, Fort Monmouth, N. J. 07703 THE UNIVERSITY OF MICHIGAN ENGI NEERI.NG.,I LIBRAR~,i

ABSTRACT The desire to understand and describe the characteristics of tuned power amplifiers has stimulated the research summarized in this report. The principal objective of the research is to provide analytical methods for use in the design of transistorized class C VHF amplifiers. The analysis methods employed are numerical in nature allowing the removal of simplifying assumptions required by purely analytical methods. Several transistor models compatible with digital computations are introduced to facilitate the study. Experimental techniques for establishing the parameter values for the models are also presented. Each of the model forms is used to study various aspects of class C/D amplifiers. Basic amplifier characteristics such as output power and efficiency dependencies on frequency, load resistance, supply voltage, nonlinear capacitance, and tuning configuration are investigated with a simple ideal switch representation of a transistor. An intrinsic voltage controlled transistor model and an extended voltage controlled model are used to study several large signal amplifiers. For purposes of comparison these amplifiers are also constructed and investigated experimentally. The intrinsic transistor model is found to provide moderate simulation accuracy for class C amplifiers in which the

ranges of signal swing, load impedance, and supply voltages are limited. For accurate simulations of high frequency, large signal amplifiers over wide ranges of operating conditions a more complete device description such as the extended model is required.

FOREWORD This report was prepared by the Cooley Electronics Laboratory of The University of Michigan under United States Army Electronics Command Contract No. DAAB07- 68-C- 0138, "Countermeasures Research."

TABLE OF CONTENTS Page ABSTRACT iii FOREWORD v LIST OF ILLUSTRATIONS x LIST OF TABLES xx CHAPTER 1: INTRODUCTION 1.1 Purpose 1 1.2 Statement of Problem 5 CHAPTER 2: MODELING 12 2. 1 Introduction 12 2.2 Introduction of Model 12 2.3 Determination of Model Parameters 16 2.3.1 UF and aR From Curve Tracer Measurements 17 2.3.2 Charge Parameters Determined with Pulse Transient Measurements 19 2. 3.3, QFS' and QRS from DC Behavior of Junctions 24 2.4 Numerical Difficulty with Charge Controlled Model 27 2.4.1 Numerical Approximation with Shunt Resistance 28 2.4.2 Numerical Approximation with Shunt Capacitance 30 2.4.3 Transformation to Voltage-Control Model 32 2.5 Extended Voltage Controlled Transistor Model 34 2.5.1 Model Capacitances 36 2.5.1.1 Package Capacitances 37 2.5.1.2 Diffusion and Depletion Capacitances 40 2.5. 1.3 Limiting of Depletion Capacitances 40 2.5.1.4 Determination of Depletion Capacitance Parameters 42 vi

TABLE OF CONTENTS (Cont.) Page 2.5.2 Emitter-Base Avalanche Description 48 2.5.3 Extrinsic Resistances 51 2.5.3.1 Initial Estimates of R 51 2.5.3.2 Initial Estimates of R.B and REE 53 2.5.3. 3 Saturated Resistance Feasurements 54 2.5.3.4 Experimental Observation of Saturation Characteristics 57 2.5.3.5 Effective Resistances Under Transient Conditions 62 2.5. 3. 6 Validation of Multi-Lump Model Transient Behavior 70 2. 5. 3.7 Selecting Equivalent Resistance Values for Single Lump Models 74 2.5. 4 Emitter Lead Inductance 76 CHAPTER 3: ANALYSES WITH IDEAL SWITCH MODEL 80 3.1 Introduction 80 3.2 Numerical Analysis With Ideal Switch and Fixed Capacitance 85 3.2.1 Effect of Switching Period 87 3.2.2 Effect of Load Resistance 87 3.2.3 Effect of Switch Conduction Angle 89 3.2.4 Effect of Circuit Capacitance 107 3.2.5 Effect of Supply Voltage 107 3.3 Ideal Switch with Nonlinear Capacitance 108 3.4 Series RL Tuning 117 3.5 Harmonic Tuning 123 CHAPTER 4: CLASS C AMPLIFIER WITH INTRINSIC TRANSISTOR MODEL 131 4.1 Introduction 131 4.2 Computed Behavior of Low Frequency Amplifier 131 4.2.1 Numerical Difficulties With VoltageControl Model 134 4.2.2 Results of Computer Analysis With Voltage-Control Model 136 vii

TABLE OF CONTENTS (Cont.) Page 4.3 Experimental Verification of Computer Analysis 139 4.4 Experimental 100 MHz Class C Amplifier 139 4.4.1 Effect of Collector Supply Voltage 142 4.4.2 Effects of Load Resistance and Period of Driving Source 145 4.5 Computer Analysis of 100 MHz Class C Amplifier 148 4.6 Comparisons and Conclusions 150 CHAPTER 5: CLASS C AMPLIFIER ANALYSIS WITH EXTENDED TRANSISTOR MODEL 153 5.1 Introduction 153 5.2 Experimental Amplifier 154 5.3 Amplifier Analysis with Extended Transistor Model 154 5.3.1 Effects of Signal Source Amplitude 165 5. 3.2 Computed Performance 167 5.4 Amplifier Sensitivities 175 5.5 Conclusions 179 CHAPTER 6: COMPARISON OF AMPLIFIER RE PRESENTATIONS 180 6.1 Introduction 180 6.2 Waveform Comparisons 186 6. 3 Frequency Response Comparisons 192 6.4 Comparisons of Load Resistance Effects 196 6.5 Comparisons of Supply Voltage Effects 201 6. 6 Computed Effects of Signal Amplitude 205 6.7 Conclusions 205 CHAPTER 7: REVIEW, SUGGESTIONS, AND CONCLUSIONS 210 7.1 Introduction 210 7.2 Summlary of Models 211 7.2.1 Ideal Switch Models 211...

TABLE OF CONTENTS (Cont.) Page 7.2.2 Intrinsic Voltage Controlled Transistor Model 213 7.2.3 Extended Voltage Controlled Transistor Model 215 7.3 Computational Costs 219 7.4 Improvement to Ideal Switch Models 224 7.5 Improvements to Intrinsic Model 225 7.6 Improvements to Extended Model 225 7.7 Amplifier and Device Optimization 230 7.8 Conclusions 232 APPENDIX A: EXPERIMENTAL MEASUREMENT OF CHARGE PARAMETERS 2 33 APPENDIX B: TRANSFORMATION FROM CHARGE CONTROL TO VOLTAGE CONTROL 243 APPENDIX C: ALGORITHM FOR CLASS C AMPLIFIER ANALYSIS 246 B B LIOGRAPHY 2 67 DISTRIBUTION LIST 273 ix

LIST OF ILLUSTRATIONS Figure Title Page 1.1 Circuit configuration for tuned power amplifier 6 1.2 Progression of device and circuit models 8 2.1 Intrinsic charge-controlled model of NPN transistor 15 2.2 Forward current gain 18 2.3 Inverse current gain 18 2.4 Effect of junction potential on forward gain 18 2.5 Effect of junction potential on inverse gain 18 2.6 Charge storage measurement 20 2.7 Forward charge storage 23 2.8 Inverse charge storage 23 2.9 Static behavior of junctions 26 2.10 Diode with shunt resistance to avoid numerical limit 29 2.11 Diode with shunt capacitance to avoid numerical limit 31 2.12 Intrinsic voltage controlled model of NPN transistor 33 2.13 Extended voltage controlled model of NPN transistor 35 2.14 Components of emitter-base capacitance of 2N3866 38 2.15 Components of collector-base capacitance of 2N3866 39

LIST OF ILLUSTRATIONS (Co(lt.) Figure Title Page 2.16 Collector-base depletion and case capacitance 44 2.17 Emitter-base depletion and case capacitance 44 2.18 Logarithmic C-v behavior 45 2.19 Graphical determination of collector depletion capacitance parameters 47 2.20 (a) Measurement circuit - low frequency saturated resistance (b) Y connection representation of saturated transistor small signal behavior 55 2.21 Low frequency saturated resistance measurements 56 2.22 Measurement circuit for VHF saturated impedances 58 2.23 Real parts of VHF saturated impedances 58 2.24 Switching test circuit 60 2.25 Turn-on characteristics of 2N3866 61 2.26 (a) Cross sectional view of overlay transistor structure (b) Expanded view of overlay transistor 64 2.27 Lumped equivalent transistor model 65 2.28 Total 2N3866 representation 68 2.29 Turn-on characteristics of 2N918 71 2.'30 Two-lump equivalent circuit using 2N918 transistors 72 2.31 Turn- on characteristics of two-lump equivalent 7 3 xi

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 2. 32 Reactive parts of VHF saturated impedances 78 3.1 Idealized class C circuit 82 3.2 Flow chart illustrating analysis of ideal switch circuit 86 3. 3 Output voltage and inductor current waveforms 86 3.4 Effect of switching period on power output and efficiency 88 3. 5 Effect of switching period on harmonic content 88 3. 6 Effect of load resistance on output power and efficiency 88 3.7 Effect of load resistance on harmonic content 88 3.8 Influence of switch conduction time on output power and efficiency 91 3. 9 Influence of switch conduction time on harmonic content 91 3.10 Effect of switch duty factor on frequency behavior of output power (expanded scale) 93 3.11 Effect of switch duty factor on frequency behavior of output power 93 3.12 Effect of switch duty factor on frequency behavior of efficiency (expanded scale) 94 3.13 Effect of switch duty factor on frequency behavior of efficiency 94 3.14 Output voltage 97 3.15 Harmonic content 99 3.16 Output voltage 99 xii

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 3.17 Center frequency and bandwidth 101 3.18 Maximum output power and maximum efficiency vs switching duty factor 101 3.19 Switching periods for maximum power and maximum efficiency 101 3.20 Scaled output power 106 3.21 Selection of nominal value for CEQVCC 111 3.22 Response of nonlinear circuit 111 3.23 Frequency response of output power and efficiency 112 3.24 Frequency behavior of harmonic content 112 3.25 Effect of load resistance on output power and efficiency 112 3.26 Effect of load resistance on harmonic content 112 3.27 Effect of conduction angle on output power and efficiency 113 3.28 Sensitivity of output power and efficiency to capacitance barrier potential 113 3.29 Sensitivity of output power and efficiency to capacitance exponential constant 113 3.30 Fundamental output power vs switching period 114 3. 31 Efficiency vs switching period 114 3. 32 Effect of supply voltage on output power 115 3. 33 Effect of supply voltage on efficiency 115 xiii

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 3.34 Classical forms of output matching circuits 118 3. 35 Idealized output circuit 119 3.36 Response of high Q circuit 120 3.37 Response of low Q circuit 120 3. 38 Frequency response of output power and efficiency 122 3.39 Frequency behavior of harmonic content 122 3.40 Effect of load resistance on output power and efficiency 122 3.41 Equivalent amplifier with harmonic tuning 125 3. 42 Effect of switching period on output power with harmonic tuning 127 3.43 Effect of switching period on efficiency with harmonic tuning 127 3.44 Computed waveforms with harmonic tuning 127 3.45 Experimental amplifier with harmonic tuning 129 3.46 Experimental collector-emitter voltage waveforms with harmonic tuning 130 4.1 Amplifier circuit with voltage- controlled model 1 32 4.2 Waveforms from amplifier analysis 138 4.3 Low-frequency amplifier 140 xiv

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 4.4 Behavior of low-frequency amplifier 141 4.5 Experimental amplifier and measurement circuitry 143 4. 6 Collector circuit behavior of low-frequency class C amplifier 144 4.7 Effect of collector supply voltage on gain 146 4.8 Effect of collector supply voltage on efficiency 146 4.9 Effect of load resistance on gain 146 4.10 Effect of load resistance on efficiency 147 4.11 Effect of driving period on gain 147 4.12 Effect of driving period on efficiency 147 4.13 Equivalent circuit for computer analysis 149 5.1 Experimental amplifier and measurement circuit 155 5.2 Waveforms for 100-MHz experimental amplifier 156 5.3 Effect of driving period on output power 157 5.4 Effect of driving period on efficiency 157 5.5 Effect of driving period on base current 157 5.6 Effect of driving period on collector current 157 5.7 Effect of load resistance on output power 158 5.8 Effect of load resistance on efficiency 158 5.9 Effect of load resistance on base current 158 XV

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 5.10 Effect of load resistance on collector current 158 5.11 Effect of supply voltage on output power 159 5.12 Effect of supply voltage on efficiency 159 5.13 Effect of supply voltage on base current 159 5.14 Effect of supply voltage on collector current 159 5.15 Scaled equivalent amplifier representation with extended transistor model 160 5.16 Effect of source amplitude on output power 166 5.17 Effect of source amplitude on efficiency 166 5.18 Effect of source amplitude on base and collector current 166 5.19 Typical waveforms with extended model analysis 168 5.20 Computed output power spectrum 169 5.21 Collector circuit limit cycle 171 5.22 Limit cycle of junction potentials 171 5.23 Experimental class A1 wideband amplifier circuit 173 5.24 Swept frequency response of experimental amplifiers; available input powers are 4.23, 2.12, and 0.841 mW 174 5.25 Output waveform change associated with "mode jump" at 190 MHz. Vertical scale 3 V per division; horizontal scale 2 ns per division 174 xvi

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 6.1 100 MHz experimental amplifier, measurement circuit and collector voltage waveform 181 6.2 Measured equivalent output circuit 183 6. 3 Scaled equivalent output circuit for ideal switch analysis 183 6.4 Scaled output circuit for analysis with ideal switch and depletion layer capacitance 183 6.5 Scaled equivalent amplifier representation with intrinsic transistor model 184 6.6 Scaled equivalent amplifier representation with extended transistor model 185 6.7 Output voltage waveforms 187 6.8 Inductor current waveforms 189 6.9 Emitter-base voltage waveforms 190 6.10 Base waveforms 191 6.11 Collector current waveforms 191 6.12 Frequency response of output power 193 6.13 Frequency response of efficiency 195 6.14 Frequency response of base current 197 6.15 Frequency response of collector current 197 6.16 Effect of load resistance on output power 198 6.17 Effect of load resistance on efficiency 199 6.18 Effect of load resistance on base current 200 xvii

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page 6.19 Effect of load resistance on collector current 200 6.20 Effect of supply voltage on output power 202 6.21 Effect of supply voltage on efficiency 204 6.22 Effect of supply voltage on base current 206 6. 23 Effect of supply voltage on collector current 206 6.24 Effect of source amplitude on output power 207 6. 25 Effect of source amplitude on collector efficiency 207 6.26 Effect of source amplitude on base and collector current 208 7. 1 Convergence behavior with changing excitation period 221 7.2 Convergence behavior with changing resistance 221 7. 3 Model with split of depletion capacities 227 7.4 (a) Photomicrograph of 2N3866 before metallization (from Ref. C4) (b) Example for estimating capacitance split by surface areas of planar device 228 A. 1 Basic circuit for charge storage measurement 234 A. 2 Typical waveshapes for charge storage measurement 2 35 A. 3 System for TF charge storage measurements 237 A.4 Sweep generation and pulse integration circuitry for charge storage measurement 240

LIST OF ILLUSTRATIONS (Cont.) Figure Title Page A.5 System for TR charge storage measurement 241 A. 6 Pulse driver and sync delay circuits used for 7R charge storage measurement 242 C.1 Flow chart for class C amplifier analysis algorithm 248 xix

LIST OF TABLES Table Title Page 2.1 Summary of extrinsic resistance estimates -59 5.1 Sensitivities with extended transistor 177model analysis 178 7.1 Averaged sensitivities 217 7.2 Guide to model selection 224 C.1 Program listing for class C amplifier analysis 249 C. 2 Sample data set for class C amplifier analysis 264 XX

CHAPTER 1 INTRODUCTION 1.1 Purpose The desire to understand and design circuits for efficient conversion of electrical energy over a wide frequency range has prompted this study of large-signal high-frequency transistor amplifiers. The problems associated with the design of RF power amplifiers to achieve various performance criteria have received considerable attention in the past. Due to the nonlinear behavior often associated with such large-signal amplifiers, there are very few specific design rules that can be used in their development. At the present time, large-signal RF power amplifiers are typically designed by laboratory determination of "average" large-signal device characteristics, design of simple linear matching circuitry to fit these "average" characteristics, and laboratory cut-and-try procedures to optimize the circuit performance. Unfortunately, the cut-and-try approach is only useful for relatively simple circuits. In addition, such approaches do not allow the engineer to determine what circuit performance could be obtainable if a different device were chosen as a gain element for the circuit. The rapid development of new devices by the semiconductor industry adds to the design problem. Even as the designer selects an appropriate device for a particular task, he is aware of possible

circuit improvements as new devices become available. When considering complex tuning networks, multiple power stages, strip-line networks and integrated high frequency power stages, the designer needs more analytical methods for predicting, studying and optimizing circuit performance. The use of a high-speed digital computer for analyzing complex nonlinear circuits offers one possible method for aiding the solution of these design problems. Computer-aided circuit design and analysis is well-developed in problem areas involving linear circuit models for transistors and other active devices. Many automated analysis programs even provide nonlinear device models for determining transient behavior of nonlinear circuits. There is, however, no general nonlinear transistor model stemming from device measurements that adequately incorporates the high-frequency large-signal characteristics of most RF power transistors. It is therefore desirable to develop models and techniques for determining the model parameters that may subsequently be used for computer analysis of high-frequency large-signal circuits. The main purpose of this research is to further the understanding of high frequency transistorized power amplifiers. This objective involves development of related models and computer analysis techniques. The work is concerned mainly with the behavior

of class C amplifiers operating in the VHF frequency range. Previous analyses of class C amplifiers have been limited by certain assumptions introduced to make hand analysis tractable. The analyses to be presented here are numerical in nature, allowing the power of high speed digital computation to aid in removal of many of the standard assumptions. Previous analyses typically assume that the operating frequency is low in comparison to the transistor limitations, and low frequency models of the transistor are used (Refs. S3, H5, S2, E3). The Q's of the output tuning networks are normally assumed to be high so that output waveforms can be assumed to be purely sinusoidal. Many analyses make the further assumption that the emitter-base and collectorbase junction potentials are sinusoidal (Refs. H5, S3, S4, Wi, S2, E3, P1). In addition, the waveshapes of transistor output current are often assumed to be of some known shape, and the corresponding base currents are calculated by assuming linear or very simple relationships between the two currents (Refs. S2, S3, P1). In keeping with the assumed current waveshapes, the device is assumed always to operate in cut-off or the active region of operation. The device is allowed to approach the edge of saturation but not allowed to enter the saturation region (Refs. H5, S2, S3). For further simplification, extrinsic device resistances and inductances are usually neglected, and depletion capacitances are assumed to be constant or nonexistent (Refs. H5, S2, S3, P1).

Depending on the intended purpose of the amplifier the standard assumptions may or may not be justified. In the class C amplifier design problems to be stressed in this work none of the above assumptions are truly justified. The basic problem to be considered is one of making use of the given device to obtain maximum fundamental output power or maximum efficiency of energy conversion at frequencies near the gain bandwidth limitation of the device. Power gain is of secondary importance, and in general, power gain will be sacrificed to provide operating efficiency and to increase the output power. With such operation in mind the high-frequency characteristics of the transistor must be included in the description of amplifier behavior. Typical values of operating Q lie in the range of I to 10, and as a result, considerable amounts of harmonic content will appear in the output voltage waveforms. The harmonic powers must be included for complete characterization of amplifier performance. The relationships between the terminal currents and voltages of a transistor can be expressed in terms of nonlinear differential equations, and the application of digital computation methods allows a rather complete description to be used instead of relying on linearizing assumptions. By using this more complete description, the current waveshapes need not be assumed but can be determined from input excitation and linear network constraints. A standard method of operation of class C power stages is to provide an excess of input power so that the output power

attains a saturation level. Such operation improves the efficiency of operation of the output circuitry and stabilizes the output power with respect to slight variations in input power (Ref. S4). In this mode of operation the transistor is periodically driven into the saturation region,and saturation effects must be included if an accurate analysis is desired. The large signals encountered in tuned power amplifiers can cause avalanche breakdown of the semiconductor junctions, and this effect is also easily included in computer simulations. 1.2 Statement of Problem As an introduction to the types of problems to be studied, consider the general circuit configuration for a single stage tuned power amplifier shown in Fig. 1.1. In a strict sense, the concept of admittance does not apply to the nonlinear behavior of the input and output characteristics of the transistor under large signal excitation, but artificial admittances Y. and Y are introduced here in'Equiv OEquiv a manner consistent with that currently in use by most manufacturers of VHF power transistors (Refs. C5, H7, H9, L2). That is, with the input and output matching networks of a given configuration adjusted1 for maximizing a given performance criteria (i.e., max power output, max efficiency, etc.) with given bias conditions, signal levels, and frequency; the transistor large-signal equivalent admittances are These adjustments are normally accomplished with low-loss LC networks or double-stub tuners.

1Equiv 0Equiv B I' G'I B' L: 5S,| S bb. Vcc Y' Y? s L Fig. 1.1. Circuit configuration for tuned power amplifier defined in terms of the linear matching networks as: Y. Y yi = Y Equiv s Y Y 0 L Equiv Information about Y. and Y as functions of frequency Equiv 0Equiv and signal level is useful in the practical sense of designing passive circuitry for obtaining a maximum output power over a selected frequency range; however, there are definite limitations to this information. Since the transistor is operating in a nonlinear mode, the overall behavior depends on the effects of the tuning networks on the harmonic components of the signals as well as the fundamental. Hence it is not possible to predict accurately the behavior of the transistor

when it is imbedded in a network that differs from the networks used for determining Y and Y. In addition, this equivalent Equiv Equiv admittance technique does not provide the designer with sufficient information to estimate such characteristics as amplifier bandwidth in wideband situations or the effects of bias conditions on the circuit behavior. It is difficult for the designer to analytically determine the trade-offs possible in power output, bandwidth, and efficiency; and as a result he is often forced into trial-and-error laboratory procedures to determine the level of performance he can expect from a given device in a specified application. Our objective is to increase the understanding of some of the basic characteristics of class C and class D amplifiers, to develop modeling techniques suitable for describing the large-signal highfrequency effects encountered in VHF power transistors, and to develop computer analysis programs for predicting the performance of class C and D amplifiers. Before analyses of the amplifiers are begun, transistor models are selected to provide descriptions of the major dynamic and nonlinear transistor characteristics. Figure 1.2 provides a brief indication of the progression of the model and circuit forms considered by this study. The transistor models to be used in the numerical analyses of tuned power amplifiers are presented in Chapter 2. Each of the model forms presented is then used separately in Chapters 3, 4, and 5 to

8 ~(b) Fi $jjjjj+ L R (a) 8 _ C v + + L R (b) C. V L R iLMR (c) 8 ~ Cal vc c Vcc l a COL (d)B' VC VEB r Fig.1.2 Progrssi of de and VCE EB

study amplifier behavior. Comparisons of the models is provided in Chapter 6 where they are each used to predict the performance features of a common amplifier. Chapter 7 presents the general conclusions of the study and suggests related areas for further consideration. The simplest modeling of class C/D output circuits is shown on Fig. 1. 2a where the transistor is modeled as a simple controlled switch with a fixed shunt capacitance, and the output tuning and matching network is taken to be a parallel RL network. As discussed in Section 3.2 a computer analysis program is used to study the effects of switch duty factor, supply voltage, and frequency in determining the Y's for obtaining maximum fundamental output power and 0Equiv for obtaining maximum efficiency. The relationships among output power, efficiency, bandwidth, and harmonic content are also investigated with the ideal switch transistor representation (Section 3.2). By replacing the fixed shunt capacitance with a nonlinear voltage dependent capacity characteristic of semiconductor junction depletion layers as shown in Fig. 1. 2b, the effects of a first order nonlinearity are investigated. In Section 3.3 the results of this investigation are contrasted to those of the fixed capacitance case which forms a reference standard used throughout this study. The effect of the configuration of the tuning network in determining the equivalent admittances is investigated by changing the

output tuning and matching network to a series RL connection again using the ideal switch with fixed capacitance to represent the output characteristics of the transistor (Section 3.4). The ideal switch representation is also used to investigate the effects of harmonic tuning in the output circuits of RF power amplifiers (Section 3.5). This investigation considers both fixed and nonlinear switch capacitances to determine the significance of a nonlinear element to harmonic energy conversion. With the insight gained through the idealized studies of class C amplifiers, emphasis is directed to predicting behavior of real VHF amplifiers. An intrinsic voltage controlled transistor model (Section 2.4.3) is used to predict the behavior of a low frequency, tuned output, pulsed input amplifier (Section 4.2). This model is also used to analyze a 100 MHz class C amplifier (Section 4.5). Experimental circuits are constructed, and their measured behaviors are used as comparisons to the behaviors predicted with the computed analyses (Sections 4.3 and 4.4). Another 100 MHz amplifier experiment is performed to add the effects of input circuit tuning (Section 5.2), and this amplifier is modeled (Section 5.3) using an extended voltage controlled transistor model (Section 2.5). Again computed behavior is compared and contrasted to experimentally measured behavior. A summary of the computational advantages and limitations of

11 each of the models is presented (Chapter 7). This includes costaccuracy comparisons and computed results for one tuned amplifier example (Chapter 6).

CHAPTER 2 MODELING 2.1 Introduction Several models used in the computer-aided analysis of VHF power amplifiers will be presented in this chapter together with experimental techniques useful for obtaining the model parameters. Many of the elements present in the models were suggested by observations of experimental amplifier behavior and by computer analysis of tuned power amplifiers. Although the models and modeling procedures will be presented here in a self- contained fashion, it was the interactions with the experimental and computed behaviors that prompted the inclusion of many of the model elements and the experimental techniques that are used for obtaining their quantitative descriptions. 2.2 Introduction of Model Quantitative analyses of physical processes require mathematical descriptions of the processes. The circuit models and corresponding mathematical expressions chosen for representing the physical behavior of VHF power amplifiers determine the facility with which an analysis can be performed as well as the accuracy of the analysis. Generally, we can expect to improve analytical accuracy by increasing the size of our circuit and mathematical models. The anticipated

13 price to be paid for improved accuracy is one of increased complexity and time required for the analysis. An apparent practical limit to the maximum size appropriate for a model occurs when further size increases are found to produce insignificant changes in the analytical results, or as a final size limit, when results of further model expansions are lost in computational and measurement noises. There are several popular large-signal circuit descriptions of intrinsic transistor properties. Notable among these are the classical Ebers-Moll voltage-controlled model (Ref. El), the physics oriented Linvill voltage-controlled model (Ref. L3), and the mathematical charge-controlled description of Beaufoy-Sparkes (Ref. B1). For a consistent set of approximations, these models can be shown to be mathematically equivalent (Ref. K1); however, because of the different choices in the controlling independent variables, computational differences in dynamic ranges and severities of nonlinearity in various operating regions can affect the computational advantages of one model relative to another (Ref. Ml). Neglecting these computational differences between the models, a lumped charge-controlled time-domain model is selected initially because it closely resembles the physical process and also lends itself to a succinct circuit representation. This model can be considered as the basis for the formulation of all the other model forms to be presented. The notation used for the

charge-controlled model1 (Fig. 2.1) of an intrinsic NPN transistor and its defining equations (Eqs. 2.1 - 2.4) are basically those of Ref. P2. B = +TF + + qR CEDEP VE'B' - CCDEP VC'B''B F'BR (2.1) cOL TF R TR BR + R + CDEp C'B' (2.2) 4F = QFS (e- E'B' 1) (2.3) qR = QRS (eXVCB -1 (2.4) These equations result from the solution of a lumped representation of a one-dimensional, field-free, diffusion equation approximating minority carrier motion in a narrow base region of a junction transistor. Approximations of space charge neutrality, no carrier recombination or generation in the space charge region, and no potential drops except at the junctions have also been made in the derivation of these charge- conteolled equations. The junction depletion layer capacitances, C and EDEP The elements SF and S are termed the forward and reverse charge stores respectiveIy. A charge store is defined as an electrical element with the property that the store potential is always zero and the current through the store is equal to the time rate of change of the stored charge.

1 5 CCDEP iCOL vC SR )_ VC'B' SR RBB iB I TBR X }qF qR _ F'R B B' F qF qF, V + VE'B' CEDEP E'. qR ~ i + + + qC v iB = TBF + TBR +R CEDEP VE'B' CDEP VC'B COL 7 R'TF R + TBR) CDEP VC'B' CCDEPCB' gF = QFS (XVEEB qR QRS (e - ) Fig~ 20 10 Intrinsic charge- controlled model of NPN transistor

C DEP are appended to the intrinsic model after the solution of the diffusion equation to account for the energy stored in immobile charges in the space charge regions (Ref. P2). A base spreading resistance RBB is often added also to simulate ohmic potential drops that result from transverse majority carrier motion in the base region (Ref. P2). 2.3 Determination of Model Parameters In order to make the model useful for numerical computations relating to a given transistor type, experimental methods can be employed to determine the numerical values and behaviors of the model parameters to describe the specific device. The parameters required for completing the intrinsic charge-controlled model description are:,F' aR ~ common base dc forward and reverse current transport factors 7F' TR: recombination time constants for emitterbase and collector-base junctions QFS' QRS: saturation charge constants for the emitterbase and collector-base junction behaviors CEDEp, CCDEp: emitter-base and collector-base depletion layer capacitances exponential constant KTm RBB: base spreading resistance

with =A ~lF A C~R TBF -IlaF F T OOR BR 1a- ~R R There are various methods that can be used to determine the required parameter values from experimental measurements of device behavior. The following techniques have been used to establish parameter values for a type 2N3866 VHF transistor. 2.3.1 F and aR From Curve Tracer Measurements. The device forward and inverse current gains PF and PR can be determined over a wide range of current-voltage operating conditions with conventional curve tracer measurements (Ref. H3, Chapter 7). The common-base current gains are then obtained by applying the simple relationship a =+i = 1 - +1' Quite often, however, problems with oscillations, excessive power dissipations, junction temperature variations, and accuracy preclude the use of this simple measurement. In such instances more specialized direct or pulsed measurements may,be required, but for present purposes the curve tracer measurements are adequate. Figures 2.2 and 2.3 show the results of forward and inverse beta measurements of three 2N3866 transistors over a wide range of collector and emitter currents. Figures 2.4 and 2.5 illustrate the effects of junction potential variations for one of the transistors.

21N3866 VCE 10 volts #3 (P1/2) cc 2. 5 2.0 2143866 #1 2N3866.1# so tt E 1.0 0 I 0.55 50 00 30 40 50 60 30 00 40 500 10 20 30 40 50 60 Collector Current: tCOL (mA) Emitter Current:'E (mA) FiF 2 2Ec Fof card current gain Fig. 3. Inversecurrentaingain - CE =2 2N3866 #1N86 ~~ 100 2.~~~~~~~25 v ~ EC 2 v 2.0 1.5 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 5 1/ I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~. 4-r.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ v.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~F VCE' 10 v U". 20'E 0.50 4 5 8 7 0 0 0 50 100 150 200 250 300 350 400 450 0 0 20 3 40 5 Collector Current-. ICOL (znA) EmitterCurrent: 1 (mrA) Fig. Z 4. Effect of junction potential on forward gain Fig. 2- 5. Effect of junction potential on inven an

For transistor #1 in the relatively large region 20 ma < ICOL < 150 ma, 5 volts < VCE < 15 volts; we find 70 < OF < 90. Approximating RF as a constant, 80, in this region leads to the value aF = 0. 988 which will be used in the computer simulation studies. Similarly for 20 ma < IE < 150 ma, 0.5 volts < VEC < 2.0 volts, we find 1.5 < OR < 2.0 and approximate aR 0.667. 2.3.2 Charge Parameters Determined with Pulse Transient Measurements. A useful method for determining the time constants of a charge-control model has been proposed by Hegedus (Ref. H6). This method employs pulse transient techniques to identify the time constants of the model and to determine how they vary with regard to terminal voltages and currents. Basically, the technique separates the effects of the two junctions by selectively forward biasing one of them while reverse biasing the other. For example, if the emitterbase junction is forward biased and the collector-base junction is reverse biased, the predominant charge stored in the base region is qF' and qR and qR may be neglected. Thus, the charge-control equations can be approximated by, qF B qR = + qF + q 3 + - q ic qF + qF i i (2.5) TBF EDEP C EDE P C DEP

20 qF 1 + q~OL - qR + COL RF R R CCDEP qF + iC (2.6) 7F CDEP where dVEB,(t) E'B'(t) C e p(t) = CEDEP(vE'Bt) dt EDEP dvc'B (t) IC (t) CCDEP (C'B') dt CDEP If a pulse of collector current is stimulated by an emitter excitation as indicated in Fig. 2.6, the resulting base current (i' ) will be composed of a static term which is the recombination current (qF/BF) and two transient terms: one to build up the stored base charge (qF) and a second to charge the depletion layer capacitances (iC EDEP iCC ). Integration of the base current transient terms yields the CDEP base charge stored in the base and depletion layer regions, viz. Fi. 2. 6 COL Fig. 2. 6. Charge storage nleasuremlent

21 Q i dt Bstored transient B - 4F dt - f iC dt- f ic dt (2.7) EDEP CDEP With the measurement technique used, the collector-base voltage (VCB,) is held constant so that the iC term can be neglected. CDEP As a result QB qF + QC (2.8) stored EDEP with Q( = -A f iC dt EDEP transient EDEP Combining Eqs. 2.6 and 2.8 results in an expression that relates the stored charge linearly to the collector current. QB td FiOL + QC E (2.9) stored EDEP (forward region) Similarly by reverse biasing the emitter-base junction and exciting a known pulse amplitude of emitter current we get: f it dt means integrating the two transient terms of the transient B total base current and excluding the static term. Refer to Appendix A for details of the related experimental technique.

22 QB TR i. e + QC (2.10) stored CDEP (inverse region) The experimental procedure for determining QB involves electronic integration of the transient base current waveform for various levels of steady state collector current (Appendix A). A plot of this stored charge versus the collector current (Eq. 2.9) will then reveal the time constant (TF) as the slope and the depletion capacitance charge (QC ) as the intercept. Experimental measurements of stored charge have been taken at various values of current and junction potentials for the three 2N3866 transistors. The results are shown in Figs. 2.7 and 2.8. For the forward bias measurement the straight-line relationship predicted theoretically is seen to occur experimentally in the region of collector currents from 10 to 200 milliamperes. In this region the slope, TF, is found to be 1.1 x 1010 second. In the region of higher collector currents the value for 7F increases rapidly whenever the current exceeds a threshold value dependent on the external collectorbase bias potential. This rapid increase in time constant can be attributed to saturation of the intrinsic collector-base junction due to a resistive potential drop in the bulk collector region. For example, the knee of the stored charge curve for transistor #1 with a bias voltage of 10. 0 volts occurs at a collector current of approximately 200. 00 milliamperes. From this behavior we might infer an effective collector

23 140 2N3866 I 0 120 /K'C 180 /. / / ~ 60 F,, /' ~~~1~~~~~~~~ ~ "0001 So e r I /,= 80 - 60I / /2 x I-s 650 40 Collector Current: ICO = (mA) 12000 02 0 6000 Slope = 2. 56lx 10 sec / Slope = 5.29 x 10 sec 50 100 150 200 250 300 350 400 450 500 Emitter Current: IC= (mA) Fig. 2. 8. I nverse charge storage

24 bulk resistance of 50.0 ohms. Conversely, the absence of such saturation effects in the inverse measurement implies that the emitter bulk resistance is less than 0.5 volts/350. mA or 1.4 ohm. Further consideration of these bulk resistances will be given in Section -2. 5. 3. From the measurements in the inverse region of transistor operation the reverse charge time constant, TR, appears to be -8 5.29xl8 second for emitter currents less than 80.0 milliamperes and decreases to 2.56x 10 second when the emitter current exceeds 100.0 milliamperes. For convenience single values (TF =.lxlOi and TR = 2.56x10 -8) will be taken as representative of the 2N3866 device behavior in the operating regions anticipated for the large signal simulations. 2.3.3 X, QFS' and QRS from DC Behavior of Junctions. The steady-state base current Ib,c, resulting from an applied basecollector potential Vbc, with an emitter current of zero can be expressed from Eqs. 2.1 - 2.4 as (1-a FOR) QRs (ekWb'c' b % |I'=0,- FR (e.Vb.c (2.11) I' =0R e Similarly, for the base-emitter junction Ib|= (1 - FaR) QFS (eVb'e' 1 (2.12)'e' F r 1-%T

25 For forward bias junctioni potentials greater thaln 100 millivolts, e.'V' 1. In this region, for example, fn [)Qb'cX O R 1 O XV (2.13) n(1- FafR) QRS bc and semi-logarithmic plots of the characteristics for the emitter-base and collector-base junctions are expected to be straight lines with slopes of X. Experimental dataI for a 2N3866 transistor are plotted in Fig. 2.9 and the slopes of both the base-collector and the base-emitter characteristics indicate a X value of 21.3 (volts- ) suitable for base currents greater than 500 microamperes. For base currents less than 500 microamperes, the slope changes to suggest X = 29.3 (volts-l). Evaluation of QRS and QFS can be made by substitution of experimental I- V data points into Eqs. 2.11 and 2.12. c'C _ -AN'C' -18 IbQ (c?~oRR 1.16x10 coulomb Vb'c =0.796 volt b'c' Ibc, =10 mA For this data it is assumed that the junction potentials were the same as the potentials applied to the device terminals; i.e., for the low current levels involved, ohmic potential drops in the bulk semiconductor material can be neglected.

26 2N3866 #1 10 Slope 21;3 - ~_ Vb | (ZCOL, o) Vb) (IE.,O) / 0.1 - -//< |I( b2/1) Slope=: OX =X 29.3 Vb, e- Vb e, b2 e1 0.01 0.5.0.6 0.7 0.8 0.9 1.0 Vbe and'7b'c (volts) Fig. 2.9. Static behavior of junctions

27 Ib'c FF Vb'e 21 QFS - (I C r Fe 4.66x 10 coulomb QFS ~(1- (uFaR) Vbe, =0.808 volt Ibe, =10 mA -10 8 with aF = 0988, R = 0. 667, TF =1. x101, TR 256x10 8 X = 21.3. 2.4 Numerical Difficulty with Charge Controlled Model Computer analysis using the charge controlled transistor model of Fig. 2.1 is subject to a numerical difficulty —the dynamic range of the charge variables can exceed the dynamic range of the computer. This difficulty is easily illustrated by a simple example. For the IBM 360/67 machine the smallest argument permissible for computing natural logarithms is on the order of 10 70. Recalling the form of an equation for one of the junction potentials, e.g., VEB, = -(l/X) n (1 + Q), we see that the largest reverse bias potential that can be computed is limited by the argument of the natural logarithm. In this example, the machine limit of 10-70 for the-argument corresponds to the largest reverse bias potential that can be handled directly. This limit on the potential would be vEB, f- In(10- ) = 4.025 volts max reverse For typical class C amplifiers we expect to encounter reverse

28 junction potentials well in excess of this 4 volt limit, and some technique must be employed to overcome this limitation. Several circuit modifications and the related numerical modifications to extend the dynamic range of the charge control model are suggested in the following three sections. 2.4.1 Numerical Approximation with Shunt Resistance. As one possibility for overcoming the numerical limit to the reverse bias potential, consider shunting each semiconductor junction with a large resistance as the numerical logarithmic limit is approached. Using a single diode junction for an example (Fig. 2.10), the equations to be solved under forward bias and small reverse bias conditions would be CDEpM(). + q/Q] q = - q + i (2.14) v = (1/X) n (1 + q) (2.15) vS - v i = R5 (2.16) 4Now suppose we choose a small limiting value of the logarithmic argument, E, which is slightly larger than the machine limit. LIM> -70 e hi+ > 10 QThis corresponds to determining a limiting value for reverse bias potential.

M4ITI ITJO!aunu pTOA' o0 a0u3fslsa! S unJqs qrl4A apol('O][''O2Q ri~i iNrIA [a........- -...... AMUA,.. = E,,, [ idol=__ E q~ ~~bt~ |Ir b Yuri 9A 1; PI....

30 1 VLIM -X Cn() When this limiting potential is exceeded in the computation, the diode equations can be approximated as: DEP( L RLIM) q + i q = (2 18) LIML v = q + VLIM (2.19) Vo- V i ~ (2.20) where RM = _ |Qs (1 +LIM (2-21) and qLIM - QS(e- 1) This procedure is illustrated graphically in Fig. 2.10 and provides an effective method for extending the computational dynamic range of the charge control model. 2.4.2 Numerical Approximation with Shunt Capacitance. As an alternate procedure we could switch in a limiting value of shunt capacitance instead of the shunt resistance (Fig. 2.11).;In a manner similar to that used for the shunt resistance, we define a capacitance

31 vRs VS q> qLIM q< qLIM CDEP( _ C LIM ii~ ii 60 j LIM Fig. 2.11. Diode with shunt capacitance to avoid numerical limit LIM CLIM = (2.22) LIM v LIM and when the limiting potential is exceeded, we are left with the equations LIM + CDEp(V). [( CLM+CEa) = i (2.23) xQ5( [1. cl)

32 + LIM (2.24) LIM vS- v i = R (2.25) 2.4. 3 Transformation to Voltage-Control Model. A third approach that can be used to circumvent the numerical difficulties involved in dealing with large reverse-bias potentials with the chargecontrol model is to transform the charge-control equations to an equivalent set of voltage-control equations and to shift the state variables from charge to voltage. This change of controlling variable from charge to voltage is demonstrated in Appendix B and results in the intrinsic voltage controlled transistor model described by Eqs. 2.26 - 2.31 and illustrated in Fig. 2.12.'B = (1-cvF)iF- CE VEB, + (l-oR)iR iB F F EDIF El B R) DIFF - CCDIFF VC'B' - CEDEP VEBt CCDEP vC'B, (2.26) i'COL F iF iR CCDIFF VC'B' + CCDEP VCTBR (2.27) iF Q aFS (J EB - (2.28) FS (e-kV E'B' F F =R Ol~RS~ (JxvCB? - R~(2.29) iR aMR TR

33 ) C' COL CDIFF RBB B itB B' CEDE v iR C vE'B' B % EDIFF + E E, iB (1- F) i - CEDIFF E'B' + (1- R) R CCDIFF C'B' CEDEP VEtB, - CCDEP VC'B' iCOL =aFiF iR + CCDIFF VC'B' + CCDEP VC'B' i FSF (e B' - R aR RT - ~-XVEB CEDIFF X QFS e -Av CCDIFF X= QQRS e Fig. 2 12. Intrinsic voltage controlled model of NPN transistor

34 CEDIFF = X QFS e (2.30) CCDIFF = X QRS e (2.31) This model is essentially a dynamic Ebers-Moll model and as mentioned previously is mathematically (but not computationally) identical to the charge controlled model. The parameters have been left in the form of the charge parameters to enhance the relationship between the two models. This transformation from charge control variables to voltage control variables for the transistor model provides a useful method for achieving the numerical range required for analyses of large signal amplifiers and will be used for the analyses considered in this study. 2.5 Extended Voltage Controlled Transistor Model In order to account for several important large-signal and highfrequency characteristics of VHF power transistors not contained in the intrinsic transistor models, the intrinsic model has been extended by the addition of fixed extrinsic elements (RBB, RCC, REE, LEE' CEB, CCB, CCE) and controlled avalanche current elements (iA, CA). The resultant extended voltage controlled transistor model (Eqs. 2.26 - 2.35 and Fig. 2.13) is a nonlinear wideband description of a NPN transistor. CJE EDEP - FE (2.32) (VZE + v....

35 C iCOL RCC C' icoL' CCB'COL: CCB I$D D aFiF Ig RBB B' iF i EDE CEDI RiR iA CA CCE C EB E' REE EE E iB = (1- aF) iFCE VEBI +(l- )iR DIFF CCDIFF VC'.B - CEDEP VE'B' - CCDEp VC'B iCOL = aFF -'R + CCDIFF VC'B' + CCDEP C'B' F aF TF ( QRS -AVc' B' R =cR TR CEDIFF = AQFS e -Xv CCDIFF = AQRS e CE CEDEP = E CFE (VZE + VE B ) C JCjC CCDEP YC FC (VZC + vC,B,)c + CF QFS 1' - 1CAA A -F F L1-(rEB/VA)NA J = VA -EB Fig. 2.13. Extended voltage controlled model of NPN transistor

36 C C + C(2 33JC CDEP F C (2.33) (VZC + vcB,) FS i~ FS [~~~~ 1 N-(2- 34) A aF F F 1- (vE,B,/VA) TF i CA VA - (2.35)_ CA VA. VEB, The expressions for the depletion capacitances (Eqs. 2.32 and 2.33) apply to the intrinsic model as well as this extended model. Experimental determination of the depletion capacitance and the extrinsic element parameters is considered in the following sections. 2.5.1 Model Capacitances. Neglecting the avalanche capacitance, 1 the emitter-base and collector-base capacitances each consist of three components: E = CEDIFF + CEDEP + CECASE (2.36) C =CCI + C + C (237) C CDIFF CDEP CCASE diffusion components, depletion layer components, and fixed mounting or case components. Small-signal low-frequency measurements of'The avalanche capacitance, C is an artificially introduced element to be discussed in Section 2.5.2, and as such ift has no effect on the device capacitances under consideration here.

37 these total capacitances of a 2N3866 transistor as functions of the junction potentials led to the behaviors illustrated in Figs. 2.14 and 2.15. 2.5.1.1 Package Capacitances. The capacitances CEB, CCB, and CCE represent the fixed interelectrode capacities of the transistor package. Their values can be determined directly by opening the device package, disconnecting the internal bonds to the chip, and making low frequency measurements of the remaining package capacitances.; A set of package capacitance measurements of a 2N3866 type TO- 5 case made with a General Radio 1215A Capacitance Bridge yielded the values CEB = 0.16pF CCB 0.26 pF vCB C = 0.26 pF CE With the interelectrode capacities determined, equivalent case capacities can be subtracted from the total capacitances as indicated in Figs. 2.1.4 and 2.15. For this subtraction we have defined ~ Ah CE CC CECASE C + C = 0.29 pF CASE EB C + C CE CB C~CE EB = _ + 0.27 pF CCCASE CCE + CEeB

38, 10. 000 L —-O CE, measured total emitterbase capacitance --.X CEDIFF 0 "" EDEP CECASE 0.29 pF 1000 U_ ECASE 100 ('_ -0.8....-6 -0. 4 -0. o o A4 0. 6 emitter-base voltage (volts) CEQp_ Fig. 2. 14. Components of emitter-base capacitance of 2N3866

39 1,000 -- C, MeaSUred Total CollecC to-base C apacitance. —-- CCDIFF o. —- CcDEP 0 21 pF CCAsE 100'O C cDE:P! - — \ mxC CC ASE 1<o6 -4 ol.2 ~ ~lt Collector-Base Voltag CB o-bax,_ 0 ca' 1 ~~~~~~ 0 -0.4 (volts)~~0. age"~~~~~~. CB 0~~~~~~~o 2N86 _0.4 - ~ { voltsClector-BaseVtae capoCianceo F~. 2.15. Components. of coecr'OTbase

40 The remaining capacitances in Figs. 2.14 and 2. 15 are attributed to the junction diffusion and depletion capacitances. 2.5.1.2 Diffusion and Depletion Capacitances. Analytically the diffusion capacitances have been modeled with exponential voltage dependencies, -XV CEDIFF = QFS e (2.30) CCDIFF = A QRS e (2.31) and the depletion layer capacitances are usually modeled by fractional power inverse voltage dependencies. CJE CEDEP+ CFE (2.32)'YE (VZE + VE,B,) JC CDEP y + CFE (2.33) (V'YC FE (VZC + vC'B') The parameters of the diffusion capacitances:, QFS' and QRS (Eqs-. 2.30 and 2.31), have been determined in Section 2.3.3. 2.5. 1.3 Limiting of Depletion Capacitances. Before establishing the parameter values for the depletion capacitance expressions (Eqs. 2.32 and 2. 33) we find that they must be modified slightly to model the behavior under forward bias conditions. Using Eqs. 2. 32

41 and 2.33 directly for transistor simulation would reveal that the depletion layer capacities are modeled very well for reverse and small forward bias conditions, but they are not valid as vE,B, approaches -VZE or as vCB, approaches -VZC in the forward bias regions. The measurements of CE and CC (Figs. 2.14 and 2.15) for both forward and reverse bias show that C does not become EDEP very large as vE,B, approaches -VZE nor does CCDEp increase without limit as vC,B, approaches -VZC, but on the contrary, the depletion capacitances "limit" at values which are rather low relative to the diffusion capacitances in these regions. Using the semi-logarithmic plots of the junction capacitance data (Figs. 2.14 and 2.15) we can identify linear capacitance components in the forward bias region attributable to the diffusion capacitance terms. These components (and the TO-5 package portion of the total capacitances) can be subtracted leaving the capacitances due to the depletion layers. The maximum values of these components (Figs. 2.14 and 2.15) are used to establish limiting values, AELM and ACLIM, for numerical computations involving the arguments, (VZE + vEB,) and (VZC + vC'B')' in Eqs. 2.32 and 2.33. E.g., AELIM (CEDE C- (2.38) ELIM C - C

42 1/vC C ACLIM = CCDJP CFC (2.39) max Adding the "limiting" requirements to the emitter-base and collectorbase depletion capacitances has led to the following expressions for computer simulation of the depletion capacitances: CJE CEDEp(vEB,) = + CFE (2.40) FE [AE(VE'B')] where Ah ~VE'B' + VZE AE (VE'B') = Supremum ELIM CJC CDEP (vC.B) C+ C FC (2.41) [A C(vCB,)] where a ~~VC'B' +VZC AC(vCB,) = Supremum ACLIM 2.5.1.4 Determination of Depletion Capacitance Parameters. Since the diffusion capacitances rapidly become negligibly small for VEIB? > -0.4 volts and vC,B, > -0.4 volts; it is natural to measure

43 the junction capacitances under reverse bias conditions in order to determine the parameters for the depletion layer capacitances. Characterization of the emitter-base and collector-base depletion capacitances are thus provided conveniently by low-frequency junction capacitance measurements under the desired reverse bias conditions. Experimentally measured characteristics of the transition capacitances of three 2N3866 transistors are plotted in Figs. 2.16 and 2.17. The problem that remains is to extract the constants (CJ, VZ, y, CF) from these experimental curves. If the capacitance relationship is reorganized as CJ C(v)- C = (VZ + v)Y and the logarithm is taken Pn[C(v) - CF] = -yn[VZ + v] + n C, the result is in slope-intercept form as illustrated in Fig. 2.18a. With the assumptions that VZ is small compared with the largest reverse bias voltage, v, and that CF is small compared with the largest C (v) measured, a logarithmic plot of experimental C - v data will appear as indicated in Fig. 2.18b. Thus, if a logarithmic plot of the experimental data is made, VZ and CF values can be determined graphically as those values that shift the experimental data to a straight-line plot on log-log graph paper.

44 2N3866 9 812 109 ~ - 4 3 22 0 0.5 10 15 2.0 3.5 4.0 4.5 ColEmictor-Base Potential: Veb (volts) Fig. 2. 16. Collector-base depletion and case capacitance 12 2N3866 11 9 8 2 - B~~ ~Fg 2.1.Eitrbs eltinadcs aaiac

45 - ~Slope= -y U 2n [VZ + v] (a) U in [v] (b) Fig. 2.18. Logarithmic C-v behavior

46 This graphical procedure is illustrated in Fig. 2.19 where the experimental collector-base capacitance data were first shifted to the right by an amount VZC = 0.5, and then shifted downward by an amount CFC = 1.7 pF. The resulting plot is a straight line whose slope gives a value of yC = 0.474. The value of CJC is read from the final straight-line plot as the value of CCDEP when vCB is 1.0 volt, and, in this example, CJC = 3.41 pF. Returning to Fig. 2.15 we find CCDEP 14.5pF max and from Eq. 2.39 we determine the limiting argument for the collector-base junction to be ACLIM = 0.0625 Summarizing the results for the collector-base depletion capacitance, we have C = 3.41 pF JC CFC = 1.7 pF 7YC = 0.474 V = 0.5 volt ZC A Ci= 0.0625 volt CLIM.

10 9 8 7 6 5 __ 4 C) -4..)3 I \~a~aa~a~a~~a~a~aa~a~a~~a~a~aa~a~a~ Slope =-c=-44; U~~~~~~~~~~~~~~~~~~~ C), o —o fnCC p vs. in VC 2 —-o fn CCDEp vs. i(V nVZC) with VZC =0. 5 v ~nCDEP C in(CCDEp-CFC) vs. kn(VcB+VZC) with VZC = 0. 5 v, CFC 1.7pF 1. Ic I Iii 0.1 1.0 1 Potential (Volts) Fig. 2.19. Graphical determination of collector depletion capacitance parameters

48 Repeating this graphical procedure for determining the emitter-base transition capacitance parameters yields CJE = 10.4 pF CFE = 0.1 pF YrE = 0.314 VZE 0.8 volt ZE AELIM = 0.6 volt 2.5.2 Emitter-Base Avalanche Description. The controlled avalanche breakdown source and the associated avalanche capacitance are additions to the intrinsic portion of the usual transistor model. Their inclusion in the model has been prompted by measurements of an experimental class-C amplifier. It was observed that under conditions of static reverse bias emitter-base potential and large signal excitation, the average base current can be in a direction opposite to the normal direction for forward bias. An explanation for this reversal of the average base current direction at large signal excitation amplitudes is the occurrence of avalanche breakdown of the emitter-base junction whenever the total emitter-base potential exceeds the transistor's emitter-base breakdown voltage. The additions of the avalanch current source, iA, and an avalanche capacitance, CA, were made to the intrinsic model to account for these avalanche effects. It has been assumed that the majority carriers injected into the base region during

49 avalanche conduction recombine sufficiently fast so that their associated storage effects may be neglected. This assumption has been supported by small signal measurements of avalanching junctions. Measured emitter-base impedances in the avalanche region were found to be slightly inductive with Q's of less than unity for frequencies up to 100 MHz. In addition, it is assumed that avalanche carriers injected into the base are not coupled to the collector, i.e., the collectorbase junction will be assumed to be reverse biased when the emitterbase junction is avalanching. Thus the majority carriers (holes) injected into the base region by emitter-base avalanche will be repelled by the electric field at the reverse biased collector-base junction. The voltage dependent forms for these avalanche elements are chosen to be QFS 1 iA = (FV AF (2.42) CA VA,B (2.43) The form of Eq. 2.42 is often used to describe the behavior of avalanching junctions (Ref. P3). The capacitance CA does not model an experimentally observed effect; it was introduced artificially to overcome excessive integration times in the numerical simulation program. The capacitance CA is given a voltage dependency to make the time

50 constant of the avalanching junction large enough to avoid numerical difficulties (excessive computation times) without changing the computed results. Experimental observation of several 2N3866 transistors has indicated unit-to-unit variations and departures from the analytical' form of Eq. 2.42 for small avalanche currents (less than 1 mA). For larger currents, however, the characteristics of all the devices are well modeled by Eq. 2.42. The only significant variation from unit to unit is the value of the avalanche voltage, VA. This value is easily established from static measurements in the avalanche region; a typical value for a 2N3866 is 6.2 volts. Computer analyses of a class C amplifier, using the extended model for a 2N3866 transistor, showed the amplifier behavior to be relatively insensitive to the value chosen for the exponent NA. Values of NA from 2.0 to 6. 0 have no perceptible effect on the computation times or the computed results, and a value of NA = 4.0 was chosen as the representative value for a 2N3866. Several values of the avalanche capacitance weighting constant, KA, were tried in numerical analyses of the class C amplifier. KA controls the time constant of the emitter-base junction during avalanche. If this time constant during avalanche, TA, is allowed to become much less than the recombination time constant for emitter-base minority carriers, TF, computation times for the numerical integration become excessive. It has been found that constraining the avalanche time

constant such that TF < TA < 2TF will prevent the integration difficulties associated with widely separated time constants; at the same time wA will be small enough that the computed results will be unaffected. As TA is increased toward 2rF) the computation time approaches a limiting minimum. Hence TA values greater than 2~F were not tried as these larger time constants are not expected to reduce computation times, and such large artificial time constants would reduce the accuracy of the simulation. In conclusion, as long as the avalanche time constant does not alter the dynamic behavior of the amplifier, its value can be increased to avoid the numerical difficulties associated with very small nondominant time constants (Refs. G1, C2, C3, R3). The values chosen for the bulk of the computer simulations of the emitter-base avalanche behavior are summarized below. VA = 6.2 volts NA = 4.0 KA = 1.0 2.5.3 Extrinsic Resistances. 2.5. 3.1 Initial Estimates of R The extrinsic resistBB ances RBB, RCC, and REE (Fig. 2.13) were added to the intrinsic transistor model (Fig. 2.12) to approximate the resistive potential drops in the bulk semiconductor regions of the transistor. Values for

52 the base spreading resistance, RBB, can be estimatedfrom small signal Yie data and collector-base time constant data. A standard technique for estimating the value of the extrinsic base resistance is to measure the transistor input admittance Yie at high frequencies (Ref. E2, p. 118). Then BB' Re[Yie] fM where fM is the frequency at which Im[Yie] =. From published technical data for a typical 2N3866 (Ref. S1) we find R 20.0 12 BB - 1 20.OX Re[Yie] f = 250 MHz V = 15 volts I = 80 mA COL The same reference source for the 2N3866 gives a typical high frequency figure of merit, RBB CCBO, as RBB CCBO = 8.0 pico second V = 10 volts ce ICOL = 20 mA with CCBO = 2.0 picofarad VCB = 10 volts

53 This data implies RBB = 4.0 f BB The wide disparity between these two values of RBB (20.0 and 4.0 SZ) prompts additional measurements to establish a satisfactory value for the large signal model. Such measurements are considered in Sections 2.5.3.3 through 2.5.3.7. 2.5.3.2 Initial Estimates of R and R In the pulsed, CC- ---— EE t charge storage measurements to determine TF and TR (Section 2.3.2), abrupt changes in stored base charge were observed for large collector and emitter currents. This break in the stored charge characteristics was attributed to saturation of the intrinsic semiconductor junction. This saturation effect was found to be voltage dependent and was caused by potential drops in the extrinsic collector and emitter resistances. From the charge storage measurements the bulk resistances may be estimated as R 50. 0 REE < 1.4 An additional guide to the value of RCC was provided by observed waveforms of a 100 MHz amplifier (Section 5.2) and preliminary simulations of the amplifier (Section 5.3). These simulations indicated that approximately 10.0 52 of extrinsic collector resistance

54 would be required to bring the experimental and computed collector voltage waveforms into agreement. 2.5.3. 3 Saturated Resistance Measurements. In order to resolve the values of RBB, RCC, and REE further independent measurement techniques were considered. To the extent that the bulk resistances of the emitter, base and collector regions can be modeled adequately as single-lumped resistances, it should be feasible to isolate these resistance effects with low frequency measurements. By biasing the transistor in the saturation region as indicated in Fig. 2.20a, and considering the small signal behavior to be represented by a Y connection of resistors as in Fig. 2.20b, the bulk resistances RBB, RCC, and REE can be determined by measurements of terminal resistances at various levels of bias current. The results of this procedure for measurement frequencies of 1 kHz to 100 kHz are shown in Fig. 2.21. As expected the total branch resistances are found to vary inversely with current for small currents. At the higher current levels, the bulk resistances are expected to dominate the total branch resistances and thus can be separated from the total resistances.'Values of RBB < 1. 0, RCC < 0.49S and REE < 0.559i can be inferred from Fig. 2.21. These values are much smaller than expected on the basis of previous information. These low frequency measurements do not seem to be representative of the values that should be used to characterize the transistor at higher frequencies.

55 IE b R 1 8k' 4. 7k 4. 7k loo10f RS _ us (A) 10 mVRMS AC ~-100KHz voltmeter (a) R (Ib Rb(Ib) t2(Ib) B RBB R1 {b) 3 (Ib) Re (Ib), REE E (b) Fig. 2.20. (a) Measurement circuit - low frequency saturated resistance (b) Y connection representation of saturated transistor small signal behavior

56 100.0 Rb - Re e R 10.0 0| C E B/.,. - k 1.00. 1, I l,,,,,,,, 0.1 1.0 10.0 100 base current: Ib (ma) Fig. 2.21. Low frequency saturated resistance measurements

57 One possible reason for the surprising difference between resistance values measured at low frequencies and those inferred from the small-signal high-frequency data, charge storage results, and amplifier measurements might be that these resistance values are frequency dependent at the higher frequencies. For this reason an equivalent set of saturated resistance measurements were made in the VHF frequency band. For these measurements the transistor junctions were again forward biased, and the small signal terminal impedances were measured with a General Radio 1607A Transfer Function and Immittance Bridge (Fig. 2.22). The terminal impedances were separated into three equivalent Y-connected impedances ZBB, Z and Z BB' CC' EE The real components of these impedances, for a 100 MHz measurement frequency, are plotted in Fig. 2.23. From these plots we might estimate saturated bulk resistance values of RBB =.42, RCC =.24 2, and R =.35. These values are of the same order as EE those determined at low frequencies (Fig. 2.21) and again are too small to correctly predict the observed behavior of the VHF power amplifier as mentioned in Section 2.5. 3.2. 2.5. 3.4 Experimental Observation of Saturation Characteristics. The differences among the resistance values obtained by the preceding measurements (summarized in Table 2. 1) led to supplementary investigations of the characteristics of the 2N3866 transistor operating as a high speed saturated switch. The nature of the turn- on

58 Ie c e c = e GR 1607A Bias Isolation Section GR 1607A (RF Measurement Section) Fig. 2.22. Measurement circuit for VHF saturated impedances 10.0 5.0 Rb U)R f = 100 MHz 0.1 1 5 10 50 100 Ib (ma) - Fig. 2.23. Real parts of VHF saturated impedances

59 Description of Measurement Element Values Determined yie Data RBB 20.0 D Collector-Base Time Constant R 4.0 6 BB Pulsed Charge Storage Measurement RCC 50.0 t2 REE < 1.42l 100 MHz Class C Amplifier Waveforms CC Low-Frequency Saturated RBB < 1, RC < Resistances REE < 0 55 EEHigh- Frequency Saturated 0.24, Impedances R 0.35 EE Table 2.1. Summary of extrinsic resistance estimates characteristics of several transistors was observed by utilizing the test circuit of Fig. 2.24. The saturation characteristics of several 2N3866 transistors all displayed a definite break in turn- on time constant as the device entered the edge of saturation (Fig. 2.25). The collector voltage at which the break in turn- on time constant occurred was found to vary-rather linearly with changes in supply voltage, VCC indicating that the phenomena can be explained by a linear (resistive) effect. Thus the saturation characteristics may be used to establish

Vcc RL (15,) iluf Channel B vC 50nb Fast Pulse Source CE 50 fl +lOv Sampling Oscilloscope Channel A vBE 506 Fig. 2.24. Switching test circuit

61 Vcc = 10V VBE 1 V/cm - OV VCE: 5 V/cm (a) Horiz.: 50 ns/cm Vcc =lOV 10V VCE:2 V/cm (b) Horiz: 5 ns/cm Vcc = 10V i _-" —"'_' ~, 10 V vCE: 1V/cm (c) Horiz 1 ns/cm Vcc = 5V 5V vCE:1 V/cm (d) Horiz: 1 ns/cm 5 ns, 2.42 V 2 ns, 2.95 V Fig. 2.25. Turn-on characteristics of 2N3866

62 effective resistance values, but these values should be dependent on the length of time the device is expected to be in saturation. For example, for a 100 MHz amplifier, the transistor switching duty factor can be expected to be about 40 percent or less; therefore, the transistor may be in saturation for approximately 4 nanoseconds. An average saturation resistance can be estimated from the results of the switching test using an average saturation voltage observed during the first 4 nanoseconds. For the transistor used in the RF power amplifiers discussed in Chapters 5 and 6 RV* RL = 13.27 ohms (2.44) sat cc e avg where V = 2 (2.42V + 2.95V) From Fig. 2.25d ce avg RL (15Q)+ (506) From Fig. 2.24 L (15 ) + (50 ) This saturation resistance is much larger than suggested by the saturated resistance values of Section 2.5.3. 3. A discussion of the transient behavior of the 2N3866 transistor is given in the next section to resolve these differences in saturation resistance. 2.5.3.5 Effective Resistances Under Transient Conditions. The 2N3866 is an NPN planar overlay type transistor with 16 separate emitter sites. An illustrative cross sectional view of a portion of such a transistor structure is shown in Fig. 2.26a. For our purposes we may consider that the behavior of charge distribution is identical under each of the separate emitters, and we can concentrate on the characteristics of one such region remembering that the current flow through the total

63 device will include a summed effect of the sixteen separate emitters. The curretnt distribution benleath any one emitter site is adumbrated in Fig. 2.26b. There are several reasons for the nonuniformity of the current distribution in the various regions of the transistor. The principal reasons for this non-uniform current flow are (a) current crowding at the periphery of the emitter-base junction due to the transverse ohmic potential drop along the emitter-base junction which results from large transverse flow of carriers in the base region under large signal conditions, and (b) the transverse potential drop due to the distributed R-C structure of the base region resistance and the emitter-base diffusion capacitance (Ref. C6, pp. 23-38). It is this second effect of requiring majority carrier motion in the base region to charge the diffusion capacitance (stored charge) that develops a non-uniform emitter-base bias whenever the emitter-base potential is required to change in a dynamic sense. As a result of this dynamic effect, the edges of the emitter-base junction provide the majority of the longitudinal carrier motion. As a net result it appears as though only a small portion of the total active transistor area is responsible for handling the majority of the current during transient conditions. If we were to think of one emitter-base-collector portion of the transistor as a distributed structure, and then model this distributed structure as several discrete lumps, we would be led to an equivalent transistor model as illustrated in Fig. 2.27. This structure excludes any effects attributable to the package capacitances, inductances and

Emitter (N+) - Si Base (P) -\ \ / / Base Metalization Base Handle (P ) Emitter Metalization ollector (a) - + Base VEB Emitter Base Metalization Metalization Metalization SiO2 S~2 ~~~~Emitter j I 1 Longii Emt (N+)~~ ~~1 I tudinal lF~~~~ _ -L( _ Transverse Collector (N) Collector Metalization (b) Fig. 2. 26. (a) Cross sectional view of overlay transistor structure (b) Expanded view of overlay transistor

C' @ ~R CC1 2 FFn By i i 2 F iFn $ REE1 $c RE2 ) 2n R BBi RBRBB R BB 1 o 2 2 nR2 Q1 in ~~RE R@ Fig. 2.. L d REEeo2,E" Fig. 2.27. Lumped equivalent transistor model

contact resistances. The initial part of the base resistance, RBB is a representation of the inactive portion of the base, that is, the portion not beneath the emitter and not participating in the useful transistor action. This resistance is normally small (10-50 ohms) for high frequency transistors and is subject to drastic reduction (100:1 ratio) due to conductivity modulation under conditions of high carrier concentrations associated with large static current levels. The lumped equivalent resistances of the distributed active portion of the base region, RBB RBBRBB I also become reduced by con1 2 n ductivity modulation at high current levels and in addition can be expected to increase slightly at large reverse bias collector-base potentials due to base width modulation. The equivalent collector resistances and the equivalent emitter resistances are also current dependent due to conductivity modulation, but the emitter resistances are much smaller than those of the collector because of the relatively high emitter doping concentrations. For our present purposes, each section of the multi-lumped equivalent may be assumed to be identical. If we now take our multi-lumped equivalent model for one emitter-base-collector region and reduce its impedance levels by sixteen, we can account for the total current through the sixteen emitter sites of the 2N3866 overlay transistor. In order to use this structure in a practical package, small values of contact resistance, lead inductance, and case capacitance are inevitable. A total representation of

67 a 2N3866 type device is finally depicted in Fig. 2.28. (Approximate values have been given by each element to indicate their relative magnitudes only and should not be construed as precise descriptions of the device.) This representation will form the basis for explaining the differences obtained in the saturated and transient measurements of the equivalent terminal resistances. With conditions of static bias the multi-lumped transistor model behaves similarly to the single lump nonlinear model we have been using previously. However, if the multi-lumped model is operated in dynamic situations such as presented by the switching test circuit of Fig. 2.24, the effects of the individual lumps become more apparent. Consider operating the multi-lump model in the switching test circuit as the base drive conditions control the device from cutoff, through the active region, and then into saturation. As the device is brought into the active region a transverse potential drop occurs across resistors RBB RBB RBB because of the base cur1 R 2.R n rent flow through them. Because of this transverse potential, the first lump of the model, Q1, is more heavily forward biased than succeeding lumps and thus is responsible for providing a disproportionate share of the total collector current. As the total collector current increases with a time constant TF, the collector potential is reduced at this same rate until the collector-base junction of the first section is brought into saturation. At this point the base charge time constant of this first section changes from approximately TF to

C L C 43 nh RCC - 32 Q~ (contact) CB RCC (Bulk).26 Pf RCC (Bulk) Rcc (Bulk) 1 2.5- 50..5-50..5- 50. F F F FFF 1 2 C~ 1R'II C R 1 1 C2 2 iC in B'm W --- Wv -__ LBB RBB, RBB1 %B CCE 1.5nh.3 - 30..1 - 10. 2R'R I 10..26P1.1 10. (Inactive (Bulk) CE I (Bulk) CE IF (Bulk) CE Bulk) 1.F1 2 2 Q1 Q2 7& REE1 (Buik) REE (Bulk) REE (Bulk) 1 ~~~~~~~~~~2.05 -.5.05-.5.05-.5 CEB _ _ _ _ _ _ _ _ _ C ~ ~ ~ ~ ~ ~ ____________00.16 Pf REE (contact).455 ~1 LEE _1.64 nh E Fig. 2.28. Total 2N3866 representation

69 GF(TF + 0RTR) In effect, further increases in base potential for this first section must then be accompanied by large increases in charge stored in its collector-base diffusion capacitance in addition to the charges stored in the emitter-base diffusion capacitance. Hence, the rate at which the base transverse carrier flow can spread to the inner lumps is retarded by saturation of the first lump. For the model chosen, this change in time constant would occur at an approximate collector potential of R +R CC + REE V V ce cc RL + RCC + REE sat first lump 1 1 As the supplied base charge spreads from the outermost lump to the innermost or last lump of the model, additional sections reach saturation, reducing even more the rate at which remaining lumps can reach saturation. As viewed from the device terminals this spread of saturation from the periphery to the inner portion of the active transistor would appear as a continual monotonic reduction in collector saturation resistance from the time the first portion of the transistor reaches saturation until the entire device has obtained a steady state saturation condition. It seems reasonable that it is this distributed saturation

70 phenomena that has led many designers of high frequency class C amplifiers to state that saturation voltage for RF transistors increases with frequency (Refs. L2, T1). 2.5.3.6 Validation of Multi-Lump Model Transient Behavior. Measurements of the turn-on characteristics of several other types of transistors were performed with the same test circuit as used for the 2N3866 (Fig. 2.24). For the devices observed, overlay and non-overlay planar types, not all displayed a pronounced time constant change at these current levels, and it is not clear as to what geometries and construction techniques will produce devices with the pronounced change in time constant as saturation is approached. In particular, a type 2N918 transistor did not exhibit a double time constant in its turn on characteristics (Fig. 2.29), and this type device was chosen to generate an artificial break in time constant by constructing a two-lump equivalent circuit (Fig. 2.30). This equivalent circuit was used to demonstrate the ability of the chosen lumped model form to predict a double time constant turn-on characteristic similar to that observed for the 2N3866 (Fig. 2.25). The results of the test with the equivalent two-lump transistor formed from two 2N918's are shown in Fig. 2.31, and as can be seen, a clear break in time constant was produced by the circuit. Returning to the multi-lump representation for the 2N3866 (Fig. 2.28) we can consider the effects of applying a static forward bias to

71 V = 10V vBE: 2 V/cm 0 V 10 V vCE: 2 V/cm Horiz: 50 ns/cm 10 V CE: 2 V/cm Horiz: 5 ns/cm — 10V vCE: lv/cm Horiz: 1 ns/cm Fig. 2.29. Turn-on characteristics of 2N918

l50 n'cc CE ChannelB 180 n ions Fast Pulse Source 50 (Z 2N918 2N918 50052 ~~~~~~~~~~~~~Sampling Oscilloscope + 10v ~~~~~~~~~~~~~~~~~~~With High IOv 47o Impedance Probes BE Channel A Fig. 2.30. Two-lump equivalent circuit using 2N918 transistors

73 VBE: 10 V/cm 0OV 10-V VCE: 2 V/cm Horiz: 50 ns/cm VBE: 10 V/cm --. ~0V vCE'2 V/cm Horiz: 5 ns/cm vBE 10 V/cm O. V 10 V vCE: 2 V/cm Horiz: 1 ns/cm Fig. 2.31. Turn- on characteristics of two- lump equivalent

74 the two junctions and measuring the remaining resistances. Not only do the separate collector (and emitter) bulk resistances become paralleled, but their values are also reduced to a very minimum by conductivity modulation. As a result, the predominant resistances remaining in the base, collector, and emitter circuits are those attributable to the contact resistances. These are the resistances that were measured at low and high frequencies under conditions of large forward static bias current. With this multi-lump model, it is clear why the transient measurements yielded equivalent resistance values that were much larger than the resistances measured during static forward bias. 2.5. 3.7 Selecting Equivalent Resistance Values for Single Lump Models. The main purpose of the various resistance measurements has been to establish suitable values for use in the wideband nonlinear transistor model (Fig. 2.13) used in the computer-aided circuit analysis of VHF power amplifiers. For class C operation in the VHF range, a transistor will be in saturation for only a few nanoseconds. During this short saturation time the device characteristics are best described by the resistances occurring just after the break in the initial turn- on time constant. A final set of equivalent resistance values for the single lump nonlinear model have been established in the following manner:

75 1. Due to the'high conductivity of the emitter region the emitter contact resistance is responsible for most of the emitter resistance. Also under transient "turn- on" conditions, the emitter-base junction is expected to become forward biased before the collector-base junction. Thus the emitter-base charge distribution will approach a steady- state distribution prior to device saturation. As a result, REE can be estimated from the average of the values obtained at low and high frequencies (Section 2.5.3. 3) with static forward bias. (0.56+ 0.35) EE 2 2. An average saturation resistance, Rsatj of 13.276 was estimated from the switching test measurements (Eq. 2.44). The effective collector resistance can be estimated from this saturation resistance value. RCC = Rsat- REE = 13.27 -.455 = 12.82 ohms 3. The curves of saturated resistance values as a function of bias current (Figs. 2.21 and 2.23) indicated that the ratio between the collector resistance and the base resistance remains fairly constant over a wide range of bias currents. This ratio can be used to estimate the value of effective

76 base resistance under transient conditions based on the effective value used for the collector resistance. RCC R = aC) = 12.82/(.572) = 22.45 ohms BB R CCsat/ BB These final values RBB = 22.45 2 RCc = 12.82 5 R = 0. 455 2 EE are used in the computer-aided analysis of typical VHF amplifiers to be discussed in following chapters. 2.5.4 Emitter Lead Inductance. A 2N3866 transistor is constructed with approximately 0.109 inch of one mil wire connecting the emitter tab of the semi- conductor chip to the emitter lead of a TO-5 package. An emitter lead self-inductance due to this wire can be estimated by the relationship L, 4S 3 L = 2S n d nanohenries (2.45) where S = length in centimeters d = diameter in centimeters for the inductance of a straight length of circular wire (Ref. G4). For

77 the 2N3866 we estimate an emitter lead inductance of 3. 36 nanohenries. Similarly, a base lead inductance of 2.41 nanohenries results from the internal connection to the base region, but this inductance has not been included in the modeling of the 100 MHz amplifier since its reactance is expected to be small in comparison to the series base resistance BB An alternative method for estimating the device terminal inductances utilizes small signal high frequency saturated impedance data collected as described in Section 2.5.3. 3. Reactance values resulting from such a measurement at a frequency of 100 MHz are plotted in Fig. 2.32. This plot indicates that the minimum terminal reactances are limited by transistor package and wire bond inductances of LBB = 1. 495 nh LC = 0. 43 nh L = 1.64 nh EE Considering the size of the emitter inductance and the empirical! and experimental methods used, this measured value of emitter lead inductance is in moderate agreement with the 3.36 nh value predicted from Alternative empirical relationships (Ref. H2) have been used to predict emitter inductance values ranging from 2.16 nh to the 3. 36 nh predicted by Eq. 2.45.

Reactance (ohms) -ffq S3 O 0 A CAW Cj 1 0 0 0 0 r~~ F^. _ n 0 ~ -~~~~~~~ o 0~~~~~~ CD 0 ) - - A C12 ~u o r~ ~~~~8

79 the physical dimension considerations. The larger value for LEE (3. 36 nh) is considered to be more appropriate for the computer simulated amplifier studies because this larger value helps to compensate for stray emitter circuit inductance that is inevitable in the construction of an experimental common emitter amplifier such as studied in Chapter 5. However, both values were used in computer simulations of a 100 MHz amplifier with no observed difference in computed amplifier performance. The sensitivity of computed amplifier performance to each of the model parameters is considered further in Chapter 5.

CHAPTER 3 ANALYSES WITH IDEAL SWITCH MODEL 3.1 Introduction A primary objective in the design of RF power amplifiers is often that of obtaining the maximum output power from a given device. For a transistor stage, improvements in both output power and efficiency of energy conversion can be achieved by applying an excess of signal input power to drive the device rapidly between states of cutoff and saturation (Refs. S4, W1). In such overdriven situations the static collector-emitter characteristics of an intrinsic NPN transistor (Ref. M2) are useful for estimating the behavior of the transistor and the output circuitry. B B COL S FB COL AFTR(1- aFO'R) VCIE - n (3.1) B + (1- AR) 1COL' + a FR(1Ra- F) 0CYFR(1cFCR) 80 8O~~~~~~~~~32

In the saturation region with an excess base current, IB' > > ICOL /F the saturation voltage, VC'E', can be expected to be a few tenths Sat of a volt or less; and the saturation resistance, rCE,, will be a Sat few ohms or less. Conversely, in the cutoff region, the output characteristics will appear as an open circuit. Thus, the output characteristics of an overdriven power amplifier stage can be expected to vary from a low impedance to a high impedance with the input excitation controlling the impedance variation. This variation between two conduction states can be modeled quite simply as an ideal controlled switch. The capacitive nature of the transistor output admittance can be represented by adding a capacitance in shunt with the controlled switch. An ideal switch representation of a class C1 amplifier output circuit is illustrated in Fig. 3. 1. This representation cannot be used to examine the gain or input behavior of class C amplifiers, but it does model many of the dominant characteristics of the output circuit. Also, performance of this simplified class C circuit can be useful as a reference to gauge other circuits. Understanding of this basic circuit can provide an aid to the understanding of more realistic circuit representations. Some questions concerning the fundamental characteristics of When a device functions as an on-off switch in a tuned circuit, the mode of operation is often referred to as class D instead of Class C.

82 COL L R S C L V _ BAT YL Idealized model of transistor output characteristics 0 0 3r Open Closed U nT (n+)T-T (n+.)T Time Fig.nT (n+. Idea l)T- (n+)T Time Fig. 3. 1. Idealized class C circuit

83 class C amplifiers that we have examined with the ideal switch representation are listed below: (1) What value of R should be chosen to maximize the fundamental output power? (2) What value of R should be chosen to maximize the output efficiency? (3) How do the choices of R depend on the duty cycle (T/T) of the switch? (4) For a given R and C, what output bandwidth will be obtained? (5) What harmonic power is expected, and how is it affected by other parameters? (6) What is the effect of changing Vc? (7) How does the circuit behavior change if the output capacitance C is given a nonlinear voltage dependency? (8) What is the influence of the configuration of the output tuning and matching network on amplifier performance? In general, one cannot obtain closed-form mathematical expressions for answering such questions. However, the answers can be obtained by experimentation using analog or digital simulations. An expression for the steady-state output voltage of the idealized circuit can be written as

84 - 2a~wn + aw -26w t 1 n Vcc 1 +....e n sin -52 t+) for nT - t < (nT- T) v(t) = 0 (3.3) for (nT- T) < t - (n+l)T n = 0, 1, 2, where: 1/L wo - ~~~an..z 6 2R C tan-a (i-) - tn-1 (#7 Evaluation of this expression depends on the inductor current at the start of each cycle (IL ). A separate equation for I can be found o Ll by imposing the condition that the inductor current must be the same at the start and at the end of each cycle. Unfortunately, the resulting

85 equation has IL imbedded in the arguments of transcendental func0 tions, and a direct analytical solution for IL is not possible. Although the IL equation could be solved numerically, such an approach cannot be readily extended to the more realistic circuit representations that will follow. For this reason, analytical expressions for the circuit behavior are not pursued. 3.2 Numerical Analysis With Ideal Switch and Fixed Capacitance An alternate approach for determining the circuit behavior is to solve the network differential equations with the aid of a digital computer. With this approach, an initial guess is taken for IL 0 and an iterative procedure is followed until the correct network behavior is obtained. A. flow chart of the computer algorithm used to determine the limit cycle of the ideal switch circuit is given in Fig. 3.2. After the limit cycle is established and the steady state waveforms are calculated, a Fourier analysis of the load voltage is performed to determine the fundamental output power and the harmonic content. Typical waveforms obtained from numerical analysis of the ideal switch amplifier representation are shown in Fig. 3.3. As indicated, these sample waveforms are for the operating conditions of -/T = 0.1 with a circuit Q of approximately 10. As expected, the output voltage waveform is a damped sinusoid during the time the switch is open and is zero when the switch is closed. With the switch open the inductor current is also a damped sinusoid with negative

Read Circuit Parmeter R. L, C, Vcc T, r, ILO Establish Network Differentlal Equations For nT < t < (nT - r) (et) * fI (Vc' IL' I1o; 0) L(t). g (V., iL' LO; t) T lc | Integrate Numerically I J = o. 1 Until t:(T-t) +2. 0 +2. e0-.| f \ ~~~~~~~L 0.159 0 / / \.L~ 1ereC- 0.159 Establish Network Differential, quatio o For' (aT - ) t: (n l)T T;(t) ~2 (v iL' ILO; t) +1 5 R - 10.0 io -92 IL' I 0I / \ | I~~~~~f~~ 02 0.40 +1.5 6 FgS..2 lwcat illsrtng Compute Fou Fi.3-.Outuog0. 5 Compute Output Power, Hlarmonic Conteot, 8p0ly Power, rtticieuY, and S itch Power 0. 020 0.40 0. 60 0. 80 1.00 Priat sult Time Fig. 3. 2. Flow chart illustrating analysis of Fig. 3.3. Output voltage and inductor current ideal switch circuit waveforms

87 average value for the reference direction chosen. During the time the switch is closed, the constant supply potential is impressed across the inductor, causing a linear region in the inductor current waveform. The conversion efficiency of the circuit is defined as the ratio of fundamental output power dissipated in R to the power supplied by the battery, V -CC cc cc L = C7 C (Vcc)(IAVG) 3.2.1 Effect of Switching Period. The effects of switching period (the circuit frequency response) on the fundamental output power, the efficiency, and the harmonic content of the circuit are illustrated in Figs. 3.4 and 3.5. The natural resonant frequency for the circuit, 1, was scaled to unity for this example, and the 27r ~/LC maximum fundamental output power is found to occur at a driving frequency,., slightly lower than the natural frequency. The efficiency peak is broader than the power peak and occurs at a slightly higher driving frequency. Further consideration of these frequency effects will be given in Section 3.2.3. 3.2.2 Effect of Load Resistance. If the load resistance is reduced below 10.0 ohms, the output power is increased but efficiency is decreased (Fig. 3. 6) and harmonic content of the load voltage is increased (Fig. 3.7). Operation with large load resistances in the range

0.70 0 r/T - 0.1 L L 0.159 0.60 -10 c - 0.159 ~Ve - 1. 0 P2/P1I 0.s50 - R 10.0 -20 - B~~ ~~~~~~~~~~~~~p/ PI/ eflfcieacy/!" / \ cO ~e~ 8-1 / cIT -0.1'~~~~~~~~~~~~~~~~~~ 0.2 0 L-0.150 a~~~ 0.0 - -40.110 *1~ poP~~er./ \\ I I! C~~~O.powe 0.12 -00 o. l - /% -0o --, i I I.I I I.I -7 o, I I! 0.50 0.10 o. 0. 0 0.90 1.00 1.10 1.20 1. 30 1. 40 1.50 0.50 0. 60. 70 0.80 0.90 1. 1.10 1.20.0.0.50 Swtching period: T Scg eod: Fig. 3.4. Effect of switching period on power output and efficiency Fig. 3. 5. Effect of switching period on harmonic content ~~~~~~~~~~+10~~~~~O CO T - 1.0 I. I 1.T -T- 1..0. 1.0 0.5 1. Efficiency 0 -- - 0-159.15 LC - 0.150.. 0. -0.4 V - 1. -10 Pooc P.. Powver Pi p 0 0 - - 0.1 1.0 10.0 100.0 1000.. 0.1 1. P 10/P Load resistance: 0 Load resistasce: R Fig. 3.6. Effect of load resistance on output power and efficiency Fig. 3. 7. Effect of load resistance on harmonic content

89 of 20. 0 to 200. 0 ohms leads to high conversion efficiency but very small output power. The energy delivered to this ideal switch amplifier circuit during each period of operation is proportional to the square of the length of time the switch is closed. This is not surprising since the inductor current changes linearly during this time. In steady-state, most of the net energy added each period is frequency converted by the switching operation and dissipated in the load resistor. A small amount of energy is stored in the capacitor at the instant the switch is closed, and this energy is lost in switching. Thus the efficiency and power output of the circuit depend on the switching duty factor, T/T, as well as the switch driving period, T. 3.2.3 Effect of Switch Conduction Angle. The conduction angle of a class C amplifier is equivalent to the duty cycle of the idealized circuit expressed in degrees. _ 0 viz. 0 T x 360 For a class C amplifier, the conduction angle is normally set by the base bias circuitry and the power level of the input signal. In general, the conduction angle can be expected to increase with increases in input driving power. As will be demonstrated, such changes in the conduction angle can have an effect similar to detuning the output circuit. In an actual transistor amplifier, changes in input power can also shift the operating point of the transistor and produce changes in the

90 "effective" admittances of the device. These admittance changes often cause noticeable detuning of the amplifier. With this idealized amplifier circuit, however, we can examine the effect of conduction angle variations without becoming involved in admittance variations of nonlinear elements. The effect of varying the duty cycle while maintaining a fixed driving frequency is illustrated in Fig. 3.8. Here, the driving frequency was chosen to be the same as the natural frequency of the network when the switch is open (i. e., T = 2,1 1C1). The fundamental output power is observed to increase with the conduction angle as expected. For the larger conduction angles, however, the harmonic content in the output power (Fig. 3.9) begins to increase with the conduction angle. Thus, increasing fundamental output power by means of increases in conduction angle ultimately results in a decrease in output circuit efficiency. The efficiency might be expected to approach unity asymptotically as the conduction angle is reduced to zero; however, Fig. 3.8 shows that the efficiency decreases with conduction angle for the smaller conduction angles. The efficiency Plotted here is the ratio of the fundamental output power to the total power supplied to the circuit. To achieve unit efficiency the harmonic power would have to be zero, that is, the output voltage waveform would be a pure sinusoid at the fundamental frequency, and no energy could be lost in the switch. Such a condition would require high circuit Q in addition to very narrow conduction angles. In addition, for

91 Ideal Switch with Fixed C 1.0 R - 10.0 L - 0.159 0.06- C = 0.159 0.98 Vc 1.0 T = 1.0 0. 04 _0_.90 0.02 0.002 0.01 0.88 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 Switch conduction time T (Seconds) Fig. 3. 8. Influence of switch conduction time on output power and efficiency Ideal Switch with Fixed C R = 10.0 L - 0.159 0 C -= 0.159 Vcc - 1.0 T - 1.0 -10 -20 -30 P -0 -4 -50 0.12 0.14 0.16 0.18 0.120 Switch conduction time T (Seconds) Fig. 3. 9. Influence of switch conduction time on harmonic content

92 unity efficiency the switch must not dissipate energy. In the idealized circuit being considered, an energy loss of (1/2) C [v(T - v7)] z occurs each time the switch shorts the capacitor. Thus, an average power loss of C [v(T - 7)] 2/2T must be attributed to the switch. This can be zero only if the switch closes precisely when the output voltage is zero. In the finite Q, narrow conduction angle case, the output voltage will not return to zero with the switch open, and some power will be lost in the switch. For a fixed Q this switch power does not approach zero as the conduction angle goes to zero, and as a result, the efficiency is degraded at the very small conduction angles. Figure suggests that a conduction angle of about 47 degrees will produce optimum efficiency if the Q of the output circuit is about 10 and the natural frequency of the output circuit is the same as the driving frequency. If the driving frequency is adjusted for each conduction angle, the changes in apparent resonant frequency of the output circuit can be observed. This has been done in Figs. 3.10, 3.11, 3.12 and 3.13 which plot efficiency and output power as a function of the switching period T, where T is just the reciprocal of the driving signal frequency. For these calculations the natural resonant period (TN) of the circuit with the switch open is again chosen to be unity and the circuit Q is 10. TN = 2 LC = 1 (3.5)

3.4 rN 3.2 I I l.I 3.2 I I 3'1 Ideal'Switch with Fixed C ~ I 0.9 3.0_ I3 I I 2.0 I I R: 10.0 L 0.159 V 1.01 2.4 0.7 2-3 2.2 2.2 - 0.20 T~~~~~~~~~~~~~~~~~ 0.6 T2 /0.~~~~~~~ i -) 0.51' 0.47 - 2.3 I 1' 1 I I l ~ ~~~~~~~. I ~~~~~~~~~~~1'0.40 0. 0.2.6 1.'U ~~~~~~~~~~~~~~~~~ C 1 I I I I "* 1 1 e1 fc.20'I 03-E.0 L I 0. II1'I n3 I r~~ ~~~~~~~~~~~~~~~~~~~~~~~~.7 I II 0.21. \1 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 0..-.,, 5 0.1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0.3 0 0.2. c~~~~~~~~~~~~~~~~~~~~~~~~~~~. O-~. 1S222323.... ~ 0.. 12 13 140.0 0..0.2.3.4. 1..7 1. 1. 2.0 2. 2.2 2.20 -Switching Period T (Seconds)'I P T ( ) Fig. 3.10. Effect of switch duty factor on Fig. 3.11 Effect of switch duty fatro frequency behavior of output frequency behavior of otu power (expanded scale) power I/ ~0.3-~~~~~~~ 1 1 0.1 r ~ ~~\ r"0 o., 6.1~~~~i r~~~~~~~~~ 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.t -rqec beavo o., oupu frqec \eairofo p~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~o.Jr ~I'ad scl) ~e

94 Ideal Switch with Fixed C R = 10.0 L = 0.159 C = 0.159 1.0 V = 1.0 cc 0.8 O 0.6 Q 0.4 -1 1.1 1. 01.0.= 40.12 0.2 0.15 0.20 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Switching Period T (Seconds) Fig. 3.12. Effect of switch duty factor on frequency behavior of efficiency (expanded scale) Ideal 905tch wlth Fixed C 0.0 1-\ /1//0. 0. 4.l /02 0.40. 0.0 0.0 1.0 0., 1.2 1.3 1.4..9.6 2.7.0 1. 2.0 1.1 21.21 1. 4 1. ftitbir Peiod T Fig. 3.13. Effect of switch duty factor on frequency behavior of efficiency

95 2 7TRC Q =2'rRC (3.6) N One observes that the fundamental output power and the efficiency always reach a maximum for switch (excitation) periods greater than the natural period of the circuit. The efficiency curves exhibit an unexpected double peak for larger duty factors. The first peak (T-) is always close to TN, and the period of the second peak (T- ) is related to the natural period and duty factor by 1TA. [1+ (T)] TN (3.7) As a consequence of the second peak, one observes that the efficiency stays relatively high over the entire range of excitation periods T < T < T + T. The curves of fundamental output power can also exhibit a double-peak for small duty factors; but in contrast to the efficiency curves, the power curves become double-peaked for small duty factors. It will be seen that when the power response has two peaks (TA and TA ), the period of the second peak T- (the pi P2 P2 longer of the two switching periods) is the more useful of the two. We will adopt the notation T- to designate TA in the cases of doubleP P2 peaked power response curves and to designate the period for peak response in the single-peaked cases. We see that in all cases TA> TA P 772

96 with both TP and T- approaching TN as the duty factor approaches zero. In order to understand the cause of the double peaks in the efficiency and output power response curves, it is helpful to observe the typical load voltage waveforms that occur near the response peaks. The response curves of Figs. 3.11 and 3.13 were obtained from data computed at discrete switching periods from T = 0.8 sec to T = 2. 5 sec in steps of 0.05 sec. Thus the waveforms presented (Fig. 3.14) do not correspond exactly to the switching periods for the response peaks but they are near those periods. Figure 3.14 shows the three voltage waveforms calculated for a duty factor of 0.05 at the two output power peaks and the single efficiency peak. For this example, a switch-driving period of 1.05 sec (T^ ) produces the maximum output circuit efficiency of 0. 925, and a fundamental output power of 0. 0844 watts is developed. Increasing the switching period to 1. 10 (T = T ) P2 P causes the output power to reach its maximum of 0. 140 watts, but the efficiency is reduced to 0. 773. A switching period of 0.85 sec (T- ) produces another power peak, but at this peak the output power is only 0. 0568 watts, and the circuit efficiency is a much lower 0.313. It is clear that this power peak at the shorter switching period is not a useful operating condition. However, it appears that during experimental tuning of an amplifier for maIximlu m output power, one Imight iltadvertently tunlle to this poo performance point and be unaware that a preferable tuning condition exists.

97 Ideal Switch with Fixed C 3= 0. 05 T = 1.1 2 P = 0.140, t1 0.773, Vp - 2.888 2 Pk 2.5 T = 1.05 p1 = 0.0844, qt = 0. 925, Vp 2. 385 T- 0.85 2.0 p P 0.0568, - 0.313, l 1. 952 pk 1.5 0.5 0 0 -0.5 -1.00 0.2 0.4 0.6 0.8 1.0 Time - t - seconds Fig. 3.14. Output voltage

98 The waveform at the maximum efficiency point is that of a damped sinusoid with the switch being closed as the sinusoid passes through zero at the end of one complete cycle. For the maximum output power condition the switch is allowed to remain open longer and is closed when the output voltage is larger thus causing an increase in switching power loss. This relationship between the waveforms for maximum efficiency and maximum power is typical for all the duty factors that have been investigated. An analysis of the harmonic power content of each of the three waveforms is presented in Fig. 3.15. Operation at the maximum efficiency point provides a 4 to 5 dB reduction of harmonic power in comparison to operation at the maximum power point. The larger waveform discontinuities that exist for the maximum power conditions are responsible for the increased harmonic power at the higher frequencies. Typical waveforms for a large duty factor (T/T = 0.3) are shown in Fig. 3.16. In this case only one driving period produces a maximum in output power, but there are two distinct driving periods.that produce peaks in the conversion efficiency. Unlike the small duty factor case, neither of the peak efficiency operating points can be so quickly discounted. However, further considerations will show that the condition yielding the full cycle sinusoid is preferable to the condition for the half cycle sinusoid. The net result is essentially the same for large duty factors as for small duty factors. That is,

99 1deal Switch with Fixed C 0 T 0.05 - T 1.1,; - --- T 0.85, pS -10 -20 \ Power Rd: \'Pnd N S - so -'0 N -40 _ -50 1 I i I - I I, I I 0 1 2 3 4 5 6 7 8 9 10 Hormonic Ntberr N Fig. 3.15. Harmonic content ~~12.0 l~~~~ida Swith with Fixed Caucitaue " 0.3 R a 10.0 P 1.75 L - 0.159 10.0 _ P2' 0.670 C a 0.159 lv V * 1.0'0 - 0.716 ~ / \\ - - T * 1.05 /1 \ P ~-~ T a 1. 40 6. 0 1 T a1.i. 45 0 _ _ _ /f.0 I\ I I I Ij Ti\_.0Fig. Output voltage.. 0.

100 maximum efficiency results if the switch is closed as the output voltage passes through zero after one complete sinusoidal cycle, and maximum output power results if the switch is closed at a slightly later time. It is interesting to see what effect the switch duty factor has in determining the center frequency for peak output power and the half power bandwidth of the idealized output circuit. This information is available in Fig. 3. 11 and is plotted in Fig. 3.17. Both the center frequency f0 and the bandwidth BW. decrease almost linearly p with increases in switch duty factor; but their ratio, Q. = f /BW. remains fairly constant at a value of 5.8 ~ 0.6 over the entire duty factor range. The peak output power, p, and the maximum efficiency obtainable, 71, both depend on the switching duty factor. This variation in p and ir is illustrated in Fig. 3.18. Recall that the curve for p occurs for a different set of tuning conditions than those for 7j, and thus it is not possible to satisfy the conditions of both curves simultaneously. The driving periods of the switch for obtaining maximum power T- and for obtaining maximum efficiency T. are related P to the switch duty factor as shown in Fig. 3.19. Our study shows that we can tune the output circuit to obtain maximum efficiency or maximum output power with a given supply voltage, load resistance, and output capacitance; but we cannot tune for both conditions. Which condition is preferable? Suppose the

Ideal Switch with Fixed Capacitance 1.0 0.06 k' O. 4 0. BpW. I I. I ~ I I 0 0.1 0.2 0.3 0.4 0.5 Duty Cycle T/T Fig. 3. 17. Center frequency and bandwidth 2.0R a 10 L a 0.159 C * 0.159 1.8 - Vce 1 3.2 R 10 L 0.159 C ~ 0.159 3.0 vec a I (Period For Maximum Pow 2.8 1.4 -'2.6 2.4 -1.2 T- (Period For Maximum Eficiency) 2.2 p 2.0 -.1 1.0 1.8 1,.6 0.8 1.40.6~~~~~~~~~~~~~0.6 0.6 0.4 0.2 0.2 0 0.1 0.2 0.3 0.4 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 Switching Duty Factor?/T witch Duty Factr t/T Fig. 3. 18. Maximum output power and maximui', Fig.,.,. Switching periods for maximum power efficiency vs switching duty factor and maximum efficiency

102 design problem is to develop the output tuning network of a single frequency, common emitter, class D transistor amplifier such that fundamental output power will be as large as possible with a given transistor operating with a duty factor of 0.30. Operating at the peak of the output power response, we get (from Figs. 3.11, 3.13, and 3.16) T^ = 1.45 sec P Pa = 1.75 watts p = 0.72 V. = 10. 25 volts At the shorter period efficiency peak TA = 1.05 sec P& = 0.0781 watt 1 = 0.942 VA = 2.34 volts alu at the longer period efficiency peak TA = 1.40 sec 772 PI = 1.58 watts Ti2S

103 712 = 0.716 V- = 9.37 volts 12 If we assume that the power dissipated by the switch, PD, is the same as the total nonuseful dissipated power, 1 then PD = (1- )P P P P = 0.856 watts PDA = 0. 00484 watts PD- = 0. 616 watts 72 In order to compare the three operating points in terms of output power limits due to device dissipation constraints, we can increase the power supply voltage at the 711 and 712 conditions until PD' = PD' = PD 711 772 P The resulting output powers scale to PDP' = P P = 1.38 watts, PDA l In terms of device dissipation considerations this is a rather pessimistic assumption for it asserts that all harmonic energy is dissipated by the switch rather than the load. Nonetheless this assumption is reasonable for high Q'loads and provides a useful standard for comparison of the tuning conditions.

104 PD^ P12 P1 D' — = 2.20 watts, 2 PD2 which should be compared to PA = 1..75 watts p Thus for the same device power dissipation, operation at the longer period of the two periods for peak efficiency will allow larger output power than either of the other operating points considered. Of course, this comparison has been made under the assumption that the peak voltages do not exceed the device breakdown limits at any of the operating points. An alternate form of output power scaling is required in order to compare the three operating points on the basis of output power limits within the constraint of equal peak voltage amplitudes. In this case the supply voltage can be varied at the - 1 and 7 2 operating points such that the scaled peak output voltages V~ "and V " satisfy V^ = Vg " = Vg ". P 71 2 Under these conditions the scaled output powers become PA? P P = 1.49 watts t71(Vn1., 27

105,P _=V.& P) = 1.88 watts Again operation at the longer peak efficiency period yields the most output power under the limiting device constraints. The power output comparison procedure explained above has been conducted for each of the switch duty factors, and the results are shown in Fig. 3.20. The comparison in this figure is only for the power scaling of the peak efficiency points with the longer periods and the peak output power points of the longer periods since these are the useful points from the double-peaked responses. In terms of device dissipation limitations, it is always preferable to operate at the peak efficiency point. In terms of device breakdown voltage limitations, it appears that the choice of tuning condition depends on the switch duty factor. In a design effort to squeeze the maximum output power from a given device, it seems necessary to supplement the usual laboratory adjustment techniques with information gained from computer analysis and constrained optimization of the circuit design. It should be observed that tuning for conditions other than maximum output power with a fixed supply voltage is not free from danger of causing device damage. For example, consider tuning to the maximum efficiency condition and increasing the supply voltage until the device power dissipation limit is reached. If the input driving frequency were to decrease slightly, the output power would

106 4 Ideal Switch with Fixed C R = 10.0 P pa L = 0. 159 /72 C = 0.159 p 3 2 t4 I / 0 o. 1 0.2 0.3 0.4 0.5 Switch Duty Factor T/T Fig. 3.20. Scaled output power

107 increase, the efficiency would decrease, and the device power dissipation limit would then be exceeded. Thus, in this sense, it does not seem to be good engineering practice to design only for conditions of maximum efficiency at the operating frequency. 3.2.4 Effect of Circuit Capacitance. To understand the effect of the capacitance value on circuit performance, consider the effect of doubling the circuit capacitance while halving the inductance to maintain a constant natural frequency. The load resistance for obtaining maximum output power will now be just one half of its original value. If the load resistance is halved, then the entire network impedance will be reduced by a factor of two. Thus for the same supply voltage, the output power will double and the circuit efficiency will remain the same as in the original circuit. 3.2. 5 Effect of Supply Voltage. Since the idealized circuit representation is linear, increases in supply voltage will produce linear increases in the amplitudes of all the circuit voltages and currents. The output power will increase as the square of the supply voltage, and the efficiency will remain unchanged. Because of these simple relationships, the supply voltage parameter need not be considered further until more general nonlinear circuit representations are encountered.

108 3.3 Ideal Switch with Nonlinear Capacitance The ideal switch circuit of Fig. 3.1 can be made more representative of the output circuit of a class C transistor amplifier if the capacitor value is assigned a nonlinear dependence on its terminal voltage. The expression chosen for the depletion layer or barrier capacitance of a junction diode is (see Section 2. 5) CJ CDE (v) + C F (3.8) [A^(v)] v where A(v) - Supremum v V ALIM and CJ is a capacitance constant dependent on the junction area and the semiconductor doping concentrations VZ is the junction barrier potential dependent on the semiconductor material used y is an exponential constant that typically lies in the range of 0.2 to 0. 5 depending on the junction impurity profile CF is a fixed capacitance resulting from overlay and bonding capacities ALIM is a limiting value of the voltage dependent argument chosen to limit the maximum depletion capacitance and to prevent the capacitance from attaining negative values

109 The capacitor current for this capacitance representation is given by d i (t) = C[v(t)] x d- v(t) (3.9) For convenience in entering data into the analysis program an equivalent capacitance is defined as the capacitance present when the output voltage is Vcc cc CEQVCC C (v) + C (3.10) DEP D v=Vcc (V + CF For the following analyses the value of the fixed capacitance was arbitrarily selected to be ten percent of the equivalent capacitance, CF = 0.1 x CEQVCC and the limiting value of the argument was chosen as ALIM = 0.01 volt The remaining parameter values for defining the nonlinear circuit capacitance; CEQVCC, VZ, and y are entered as data in the analysis program so that their significance in the circuit behavior can be investigated. In previous analyses of the linear idealized circuit, values of R = 10, L =0.159, and C = 0.159 produced a maximum in fundamental output power when the switching period T was 1.17. To

110 establish a nominal value for CEQVCC in this nonlinear case, the behavior of output power with CEQVCC was observed under conditions similar to those in the linear circuit (Fig. 3.21). A value of CEQVCC = 0. 159 is seen to produce a fundamental output power peak near T = 1.17, and this value of CEQVCC was taken as the nominal capacitance value in the nonlinear case in order to enhance the similarity with the linear case. Typical waveforms and capacitance variations for this nonlinear circuit near resonance are shown in Fig. 3.22. Here the total circuit capacitance is seen to vary by a ratio of 5 to 1 during one cycle of the periodic output. Even with this large capacitance variation, the dependence of output power, efficiency, and harmonic content on switching period, load resistance, and duty cycle (Figs. 3.23, 3.24, 3.25, 3.26, 3.27) are found to be almost identical to the behaviors observed in the linear case. The circuit performance is also surprisingly independent of the values taken for the parameters VZ and y. In Figs. 3.28 and 3.29 we observe that a 10 to 1 variation in VZ or y produces only about 20 percent variation in fundamental output power and about 10 percent variation in output circuit efficiency. The effects of switching duty factor on the frequency response of output power and conversion efficiency with the nonlinear capacitance case are illustrated in Figs. 3.30 and 3.31. The effects of variation of the DC supply voltage, V, are illustrated in Figs. 3.32 and 3.33. For these analyses an equivalent

Ideal Switch With Depletion Layer Capacitance R = 10.0 L ~ 0.159 V ~ t.0 0.30 y 0.5 V 1.0 cc T 1.17 0.117 0.25 - 0.20 0.15 1.10 3.05 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 Equivalent Capacitance CEQVCC (Farads) Fig. 3. 21. Selection of nominal value for CEQVCC Ideal Switch With Depletilon Lyer Capeltance 5.0 4.0 3.0 0 / IOxs C(v) 2.0 -. 1.0 1.0 I.O R 0 10.0 TL 0.150. -2.0 es e o noliea ~Z I 1.0 ~ "''0.I Vcc' 1.0 T' 1.17 -3.0 r T O. 117. 0.2 O. 4 O. 6 0. 8 1.0 1.2 Ti e: t (Socodl) Fig. 3. 22. Response of nonlinear circuit

hIeal Switch with Depletion Layer Capacitance 0.30 R.10.0 L 0.150 CEQcVCC 0.159 Power 0.15 VZ 1.0 1.20 = 0.0 VCC 1.0 a. iD0 -1.00 0.00 1.00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~L1. Efficietcy 0.00 ~0.05 Vs cc.wt ~0.10 0.60 I I 0e~lo 0.20 0.7 0.0a 0.9 0.0 1.10 1.20 1.30 0.40 1.50 1. 60 0..t 1.t 1.10 tMt.O.0 0 Switching Period T (Secoods) Fig. 3. 23. Frequency response of output power and eff iciency Fig. 3.24. Frequency behavior of harmoniccotn Ideal Switch With Depletion Layer Caiacitance 10Ideal Switch With Depletion Layer Capacitance.0.4 EtCciec150. VZ1. V0.2 Li00. B r r~~~~~~PsP T II 0~~~~~~0 -0.4 Efficiency 0. a 210 02/P0 1.0.3 0.7-20La Ria -0 (oon Load eoan 0 (ohmo) Fig. 3.25. Effect o loa resistnce on output power and efficiency Fg.6 feto odrssac nhroi otn 0.2. 30 *.0.5~~~~~~~~~~~~~~~~~~~~~~~~~ 0. 5 VCC - 1.0 0.0,L_ L~~~~~~~~~~~~~~~~~~~~~~~~~.5-4 -1 V9 0 - 0.4 -50 -CEVC 0.5 0. 0. s q I I I ~ 0-1 1.0 10 100 1000 0.1 1.0 1 r o~~~~~~~~~~~~~~~odReitne om) odRs-IneIt(hs Fi.3 5 feto odrsitneo uptpwradefiinyFg.2.Efc o odrssac nhro

Ideal Scitch With Depletion Layer Capacitance Ideal BelieS With Nelton L~a r CitincO 0.1 I.O 0.~~~~~~~~~~~~~~~~10.066 ida 0.c ihDelto LyrCpaiac RI 10 L - 0.159 1 10 CEQVCC 0.159 L - 0.159 0.09 VZ 1.0 0.5 0.004 CZQVCC = O. 15 VCC 1.0 VCC 1.0 T - 1.0 Efficiency T 1.0 r ~I0.1 0.08 - 0.9 pow rrer Efficiency 0.00 0.0 0.062-007 - 0060' I 1~~~~~~~~~~ 0. 0. 6 00 0.04 ] -0o.7 0.054 - 0.031 1 0.051 0 0.00 0.1 0.2 0.3 0 0.1 0.1 0.3 0.4 0.5 0.6 0.7 0.5 0.0 1.0 Switch Conduction Time t (Seconds) o 01.2.3 0. 0. O 7.8 0. Darrier Potential VZ (Volts) Fig. 3.27. Effect of conduction angle on output power i 3.28 Sensitivity of output power and efiiency and efficiency to capacitance barrier potential Ce3 Ideal Switch With Depletion Layer Capacitance 0.0 0.95 L 0 0.159 Gore - ~~~~~~~~~CEQVCC - O. 159 0.0 0.02 00 1.04.0 Efficiency VCC 1. O I U~~~~~~~~~~~~~~~~~ z 0.93~~~~~~~~t1. 0.0a2 0.00 0.004 0.91 0.02 0.90 G rae 0. 460 - a 0.19 0. O(11 1 I t I 0. so 0 0.1 0.2 0.3 0.4 0.5 0.0 0.7 0.0 0.0 1.0 EXponeial Coastant V Fig. 3.29. Sensitivity of output power and etticiency to capacitance exponential constant

0.5 1.0 R =10 =0.08 R 10 L 0.159 r L - 0.159 CEQVcc =0.159 0.1CEQV = 0.159 ~~~cc cEQvc 0.08 VZ: 1.0'-= 0.12 0.9- VZ= 1.0 = 0.5 0.0.5 4=0.2 Vcc 1.0T 0.= Vc= 1;0 I.... 0~~~~~~~~~~~~~~ (i> 0.72 ~0........ o\6 0.- f.... o~I' 4)~~~~~ 1.2 I I 0. * r8. 0.1 0.2 0.7 0.1 0.2.C r,~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ \/ ~o.3I -I~~ ~ ~0.1 0.8 0.9 1.0 1.1. 1.2 1.3 1.4.1.5 0.8 0.9 1.o0 1.1 1.2 1.3 1. 15 Switching Period T Switching Period T Fig. 3. 30. Fundamental output power vs switching period Fig. 3. 31., Efficiency vs switching pero o/ _~ 0.2-. 0~~~ ~ ~ ~ ~~~~~~~~~~~~~~~~~~~.1 -: 0.8.9 1.0 1.1. 1..2 1.3 1.4,1.5 0. 8 0.9g 1.0 1.1 1.2 1.3 1.4. Sewitching Perrod T SwitchingB Period T Fig. 3. 30. Fundamental output power vs switching period Fig. 3. 31. Efficiency vs switching period

10.0 R = 10. L = 0.159 CF = 0.0159 VZ = 1. T = 1. PVCC 1.0 7 = 0.1 y = 0.5 ALIM= 0.0625 CEQVCC 1v = 0.159 78 4 1x101 / 0 x102x10-2 0.1 0.2 0.5 1.0 10.0 Collector Supply Voltage: VCC (Volts) Fig. 3. 32. Effect of supply voltage on output power 1.0 z 0.8 -- 0.60.4 0.200.1 1.0 10.0 Collector Supply Voltage: VCC (Volts) Fig. 3. 33. Effect of supply voltage on efficiency

capacitance (Eq. 3. 10) of 0. 159 farad was chosen at a reference supply voltage of 1.0 volt. Increasing the supply voltage from this reference value reduces the "effective" circuit capacitance and increases the resonant frequency of the output circuit. As a result of this output tuning effect the output power can be found to increase more rapidly or more slowly than the square of the supply voltage. The variation in output power for this example (Fig. 3.32) indicates that the circuit is tuned slightly below the power resonance frequency when the supply voltage is 1.0 volt because the output power increases faster than the square of Vcc in the region of Vcc from 1.0 to 8.0 volts. With supply voltages greater than 8. 0 volts the circuit seems to be tuned to a frequency higher than the excitation frequency, for in this region, the output power increases less rapidly than V cc2 This departure from square law variation in output power will be observed again in Section 6. 5 where there are again regions of supply voltage in which the output power is not linearly related to V 2 cc The results of the analyses involving the voltage- sensitive depletion capacitance indicate that the circuit performance does not differ greatly from that obtained with the fixed capacitance analyses. The principle effect, for a circuit Q of approximately ten, is a reduction of the peak to peak output voltage with an attendant drop in the maximum values attained for power output and efficiency.

3.4 Series RL Tuning The maximum efficiency, power output, and bandwidth obtainable with a specified transistor as a class C amplifier are dependent on the passive networks chosen for tuning at the amplifier input and output. These passive networks for tuning and matching the transistor output characteristics to the load are usually special forms of the classical LC ladder networks illustrated in Fig. 3.34. In addition to influencing the frequency behavior of the amplifier, these tuning networks also affect the large signal linear "equivalent" admittances (Section 1.2) of the transistor. In this section, the effects of the output network configuration have been investigated by analyzing amplifier behavior with the tuning network of Fig. 3.34b. The actual circuit representation used for the analysis is shown in Fig. 3.3 5. In practical applications, dc-current flow through the load resistor is normally prevented by shunting the load with a large value inductor or by applying the supply voltage, Vcc to another point in the circuit through a large value inductor. The iterative digital computation procedure used for this analysis allows us to dispense with the extra complexity introduced by such biasing inductors. To do this we introduce a variable battery in conjunction with the load resistor. This variable battery voltage is then adjusted automatically to compensate for the dc voltage drop and dc power loss in the load. Typical voltage and current waveforms for the circuit for output

118 T 0o ~L < RL I (a) I (b) I (c) (d) Fig. 3. 34. Classical forms of output matching circuits

rn - -1 t~t) I I x R 1(t) 1 Iavg ] L RI S + C t v(t) C -_'_.Vcc o > Open o: Closed 0 ~~....O I lI, I i Time nT (n+l)T-T (n+l)T Fig. 3.35. Idealized output circuit circuit Q's of ten and one are presented in Figs. 3.36 and 3.37, respectively. For the high Q case, the waveforms are essentially identical to those obtained in previous analyses with the parallel RLC output circuit of Fig. 3.1. The apparent advantage of the series RL configuration is that the shape of the load voltage is the same as the inductor current without the dc component. This current waveshape more closely approximates a sinusoid than does the capacitor voltage, and as a result, less harmonic power is dissipated with this series RL connection than with the parallel RLC connection. For low Q operation the waveforms for the two connections are not as similar,

Capacitor Voltage: vc(t) (volts) Inductor Current: IL(t) (amperes) 4o un n o - n o? I ",? CD,W 3-*\ //o 9 >S o r CO COe CZ)0 /0\ 11' II cD nr Cn, & o o X = 0 0 ~ ~ tn I I ~I ~vI 00 -. ~.c~~~~~~~~~~~~~~~~~~~~~~r H, # I#II## -—,. ~ 0, H "' "'0 " ~~~~~~~~~~~~O~~~~~~~~~ ~ ~ ~

122 0.1L 1.0 R 0.1 L 0.1590 C. 0.1509 V c 090 0.1 t 0.4 - 0.80 0 R 0 L 0.010 ~0.2 | ~ - 01 110 1.1 111 l.1 ^14 1. ~ e~O s' o1O 1.6 All Sl2 l13 11 ~ 1!5 0.40 — 10.1 7: Fu rfm 0.105 1 0.0 ~ 0.09 1.0 1.1 1.2 1.3~ 1.4 1.00~ 0. 0. 1.0aL. I a 1.* 1.0 &wIO00Iug Peiod T (soccuS) Fig. 3.40.Ef0 -of' r/T 01 o4 a 0..O10 i.. 14 lI:~0.01 0.1' Fig. 3. 40. Effect of load resistance on output power and efficiency

123 duty factor to 0.1 and then varying the load resistance over a wide range of values. When the circuit Q is high (Q > 5), the fundamental output power varies almost linearly with R. However, when the Q is low (Q < 1), the output power is seen to vary inversely with load resistance. This behavior is quite different from the behavior observed for the parallel circuit. With the parallel output circuit the output power was found to vary inversely to the load resistance in all Q ranges. For the stated switching conditions, a maximum efficiency of 97 percent was obtained for series load resistances between 0. 02 and 0.05 ohms. This is analogous to an efficiency of 98 percent that occurred for the parallel tuning when the load conductance was between 0.02 and 0.05 mhos. From the numerical analyses we conclude that for a circuit Q of ten, the shift from parallel RLC output tuning to series RL tuning has little effect on circuit performance. However, for the low Q of unity, the series tuning circuit yields larger bandwidth, higher efficiency, and less harmonic content. 3.5 Harmonic Tuning Before leaving the amplifier studies with ideal switch transistor representations, it is interesting to use this model to determine the potential utility of harmonic frequency tuning in a power amplifier output circuit to increase fundamental output power, gain and efficiency.

124 The output powers and efficiencies of class C amplifiers can often be increased by judicious treatment of the harmonic voltages and currents that exist in the output circuitry (Refs. HI 0, H11). The circuit representation of Fig. 3.41 was analyzed to provide an estimate of the utility of harmonic tuning. In this network, the series resonant trap can be adjusted to prevent the appearance of any one harmonic voltage component across the load. Reactive shorting of a harmonic component forces its energy into the fundamental and other harmonic components of the output voltage waveform. A differential equation description of the network (state equations) during the time the switch is open is expressed by 1 1 C1 0 0 0 v -1 0 -1 vC 1 C1 RL 1 L 0 ~ ~ iL2 L~ I L O L 0 0 0 0iL1 L1 - L [XI (3. 11) and during the time the switch is closed by 0 C2 0 vC 0 0 000 v 0 1Ll|L2 C|1 || L 2i | |(3.12) 2 -(312

vcc R 0.0073 0.225 S Closed I Open 1 s Cj vcL 79 T/T = 0.404 To.352 C v + VZ C (v) = + C A = Supremum (At AIM C = 2. 54 CEQVCC = C1(v)l = 1.005 V=V C = 0.17 VZ = 0.5 CC A = 00625 LIM Fig. 3.41. Equivalent amplifier with harmonic tuning

126 The element values for the analysis for this circuit are indicated in Fig. 3.41. The effects of harmonic tuning on the output power, efficiency and frequency response (Figs. 3.42 and 3.43) were determined by numerical integration of Eqs. 3.11 and 3.12 until the steady state operation of the circuit was reached. The Fourier coefficients of the load voltage waveforms (Fig. 3.44) were then determined numerically to evaluate the fundamental components of the output power spectra. The plotted results demonstrate that this form of harmonic tuning can increase output power and efficiency, but the circuit behavior becomes much more sensitive to the excitation frequency as illustrated by the abrupt variations of output power and efficiency in Figs. 3.42 and 3.43 at a switching period of 1.6. It may seem that for effective harmonic tuning the nonlinear capacitance element, C1, is necessary to provide a parametric conversion of harmonic power to the lower fundamental frequency. This necessity of a nonlinear reactive element was investigated by replacing the nonlinear C1 by a fixed capacitor (C1 = 1.005 F, fixed). The results of this linear circuit analysis are also shown in Figs. 3:. 42 and 3.43, and they indicate that the nonlinear reactive element is not required in order to observe the effects of increased output power and efficiency. For example, we will find (Chapter 6) from analyses with the same circuit conditions and fixed switch capacitance but without harmonic tuning (Fig. 6.3), the maximum fundamental output power is 1. 16 watts with an efficiency of 54 percent and a fractional

p, (Computed wit 3.0 L \Nonlinear Capacitance) 2.5 - [ Computed with \ 1.0 P;1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~ _ Computed with Nonlinear Capacitance) 2.0 0.8-; Fixed Capacitanc 0 5.16 0]2 OA8 0.64 0.80 0 0;!0 Q40 Q60 Q80 100. o t I ~ I:1.0 0.4 0. 5 9.x \ TT 10 (Eltperimental) 0teea 0 -- I I 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.4 0.6 08 1.0 1.2 1.4 1.6 1.8 0 2.2 Scaled Switch Driving Period: T/T Scaled Switch Driving Period: T/T Fig. 3.42. Effect of switching period on output power with harmonic tuning Fig. 3.43. Effect of switching period on efficiency with harmonic tuning o3 26.4 a 292 29.1 r 211 21.8 5 17.1 o1 502 0 0.16 0.32 0.48 0.64 0.80 0 0.20 40 560 Q10 100 (a) T/T0 0.8 (b) T/To =1.0 o 91.0 719 b0 52.6 33.6 y 14.5 0 Q26 052 Q78 1.17 1.0 (c) T/To 1. 3 Fig. 3.44. Computed waveforms with harmonic tuning

128 power bandwidth of 45 percent (Figs. 6. 12a and 6. 13a). Addition of harmonic tuning increases the maximum output power to 2.01 watts and the efficiency to 62 percent but reduces the fractional power bandwidth to 22.4 percent. Frequency scaling of the nonlinear harmonic tuning circuit by a factor of 5 x 105 and impedance scaling by 0.958 x 104 leads to the experimental circuit of Fig. 3.45 with an equivalent center frequency of 500 kHz. Waveforms from this experimental circuit (Fig. 3.46) are presented for conditions equivalent to those for the computed waveforms (Fig. 3.44). For further comparison, the experimental results were also presented in Figs. 3.42 and 3.43. The moderately good agreement between the experimental measurements and the computed results verifies the adequacy of the ideal switch representation for analysis of this low frequency, overdriven circuit.

4-10V ectrum 53 lyzer 140 1Ct ~~~~~~~~50' 055k RL Pulse (2.088k) Source Ak(~sk OV 0 L 2M702 hMotorola 500 kHz + MMV2115 0. 4 Duty Factor 470pF Epicaps 343ih 2 73.5pF -5v I Meg~ 20O0pF t0 0, 70p F 0 10 20 v Fig. 3.45. Experimental amplifier with harmonic tuning

130 T/TO =.8 Vertical: 20 v/cm Horizontal: 2 /as/cm T/T = 1. Vertical: 10 v/cm Horizontal: 2 gs/cm T/TO = 1.3 Vertical: 20 v/cm Horizontal: 2 As/cm Fig. 3o 46. Experimental collector-emitter voltage waveforms with harmonic tuning

CHAPTER 4 CLASS C AMPLIFIER ANALYSIS WITH INTRINSIC TRANSISTOR MODEL 4.1 Introduction The engineering value of the transistor models developed in the modeling chapter (Chapter 2) lies in their ability to predict the performance of high frequency power amplifiers. In this chapter the intrinsic transistor model (Section 2.4.3) is used to analyze two class C amplifiers. The first circuit is a low frequency amplifier with pulsed input excitation which causes the transistor to function very much like the controlled switch used in Chapter 3. The results computed numerically for this amplifier are verified with a low frequency (5 kHz) experimental amplifier. The second amplifier is studied under conditions of sinusoidal excitation at a frequency of 100 MHz. Comparisons between computed and experimental results for the 100 MHz amplifier indicate the need for extending the intrinsic transistor model to achieve improved simulation. 4.2 Computed Behavior of Low Frequency Amplifier The amplifier circuit of Fig. 4.1 was chosen for initial analyses with the intrinsic voltage controlled transistor model. It is about the simplest possible class C transistor amplifier, since no tuning is employed in the base circuit and simple parallel tuning is employed

132 + V cc L R iL iCOL' + c,,,' C,,, At t 4 V~~CER VCB R aFiF ~~B' ~i' RS RB Fi Vs R V + E +1 5V -15V V~0 0~ ~V4 =0.6 1.0 V = 10.0 -0159 R = 10.0 QFS = 7.81 x 100 L = 0.159 QRS = 1.56x109 C = 0.159 = 39.5 RS = 1.0 CDE = 0.01 XVdB RB = 1.0 CCDIFF = XQRSe aF = 0.98 CEDEP = 0.01 -XVEB CR = CCDIFF + CCDEP aR = 0.5 CEDIFF = XQFSe CF CEDIFF CEDEP F 0.796 Fig. 4.1. Amplifier circuit with voltage-controlled model

133 for the collector. In addition to its simplicity, this configuration has been analyzed by others using analytic methods (Refs. H5, S2, S3, W1) and represents a realistic form of the ideal switch circuits analyzed numerically in Chapter 3. The transistor parameters were chosen to be representative of VHF transistors, but not specifically the 2N3866 because characterization of the 2N3866 had not been completed at the time of this analysis. A. state equation description for the amplifier circuit can be expressed as 1 -CF-CR 0 R 0 V l O VE'B' CR CR+C O vC'E' | -1 VCE, o o L iL 0 1 ~ iL - 1 i 1o 01 -CR 0 + CRF 1 l1 V v (4.1) 0 0 i L 0 1 1 w ith'F =aFS (e E 1) (4.2)

134 QRS ( e-.X(VE'B' + VC'E?) ) -A V t(4.3) -XVE'B' CF = A QFS e + CEDEP (E, (4.4) -k (VEB, + vC E,) C = a QRS e +CCDEp(VEB, VCE) (4.5) The state variables chosen for this analysis are the emitter-base voltage, the output capacitor voltage, and the inductor current. 4.2.1 Numerical Difficulties With Voltage-Control Model. Several different numerical methods were tried for integrating Eqs. 4.1. The basic difficulty encountered by all of the integration schemes was one of obtaining a suitable compromise between integration accuracy or stability and computation time. In this problem, the computation interval is relatively long; but at two times within the interval the state variables undergo rapid transitions which produce abrupt changes of the parameters dependent upon exponential functions. To preserve numerical stability during these rapid transitions, the integration step size of the independent variable must be reduced to a small value (Refs. C3, C2, G1). If this small step size is maintained constant for the entire integration interval the computation becomes long and expensive. Therefore a requirelllent for a practical integration metlhod is the capability of automatically adjusting the integration step size

135 as the computation progresses. Selection or development of such an integration algorithm is not a trivial matter. When the calculation of the system derivatives is extensive, implicit integration routines seem to offer a minimum error-time product (Refs. R3, F2, G2). Two implicit numerical integration algorithms used with moderate success in this study are the Hamming predictor- corrector routine provided in the IBM Scientific Subroutine Package and a variable order integration scheme developed by Gear (Ref. G2). Stability and accuracy problems have been encountered with both algorithms when extreme network values were chosen, but these algorithms have been found to be adequate for realistic circuit descriptions. In addition to the numerical problems associated with the integration of the state equations, there is some difficulty in determining the terminal currents, iB' and i from the state variables and B'COL' their derivatives. For example, there are two obvious ways to compute the collector current from the state variables (vE,B,, vCE,) and their derivatives (vEB,, vcE,). One approach is to use Kirchhoff's current law to express icoL as a function of the currents within the COL transistor iCOL = aFiF iR + (vEB + vC'E) CR alternatively icoL' can be expressed in terms of currents in the

136 passive external circuitry iCOL = -iL- (VC'E- Vcc) C'E' As long as the collector-base junction is reverse biased, the collector current is small in comparison to the relatively large currents in the high-Q collector tuning circuitry. As a result, the numerical errors accumulated in the computations of the external currents become quite significant in the subtractions employed in the second method. In this situation it has been found better to use the model equations directly to compute the collector current. The other computational extreme is encountered when the transistor is saturated. At this time the collector current is of the same order of magnitude as the currents in the external circuitry, and the subtraction process poses no difficulty. However, in this forward bias situation, the collector current is very sensitive to the junction potentials (due to the sensitivity of the exponential functions in iF, iR, and CF for positive exponents), and small errors in junction potential can produce very large errors in the computation of the collector current. Thus, the collector current should be computed from the external circuit constraints whenever the collector-base junction is forward biased. 4.2.2 Results of Computer Analysis With Voltage-Control Model. For the computer analysis of the circuit of Fig. 4. 1, transistor

137 parameters were chosen to represent a device with a 2 GHz gainbandwidth product, fT' operating at a frequency of 1 GHz. The actual values indicated in the circuit resulted after the frequency was scaled down by 109 and the impedance level was reduced by a factor of 10. With this scaling, the values used in the output circuit (L, R, and C) are the same as those used in previous analyses with the ideal switch representations for the transistor. Typical waveforms of the periodic response of the amplifier are given in Fig. 4.2. The output voltage waveform vC,E, is very similar in shape to the output waveforms computed using ideal switch representations of the transistor's output characteristics (Chapter 3). Because of this similarity the analyses with variations in load resistance, supply voltage, driving frequency, etc., were not repeated for this amplifier. The waveforms observed for vE,B, and iB' are what one Et~t B would normally expect from such a circuit configuration; however, the double-peaked behavior of the collector current, ioL, was not anticipated and is not generally predicted by most class C analyses. In most analyses, the collector current is assumed to be rectangular or some smeared reproduction of the injected pulse of base current (Refs. S2, S3, Wi). However, this analysis shows that the transistor saturates and the base current exerts no direct control on the collector current. With a moderately high-Q collector load, the reactive currents can cause the collector current to reduce sharply or even

I.m IL0 LOIG 0.00. Itm *-1 I I I! o.e.mI I I I I I!,, I. I I o000oo o.10 0.00 0.0? 0.4001o o.50 oo oo o..| o.. G oAo o L0 0.100.3ie 0.100 3 0.400 0.oNo 0.3o00 0."0O 0..o 1..00 T(M.. T(S. ). (a) Emitter-base voltage (b) Collector-emitter voltage FgLfi l0.000 -LO -- t IL g.m 0 i 0.I10 L 0 L4 I I00 IM IM C M I.11 _________ ________1___O.____ 0._ _0 _.1_______ 00___ _____ 0_ 70__ ________.; eta lm.m m esa.) oti a:.m (c) Base current (d) collector current Fig. 4.2. Waveforms from amplifier analysis

139 reverse direction during the time that the transistor is in saturation. 4.3 Experimental Verification of Computer Analysis The double-peaked collector current waveform has been observed experimentally with the low-frequency amplifier configuration shown in Fig. 4.3. Typical waveforms observed with this experimental circuit (Fig. 4.4) are much like those predicted by the computer analysis. The transistor used in the experimental circuit had a gainbandwidth product that was much greater than twice the resonant frequency of the output circuit. To help adjust for this difference between the experimental circuit and the circuit used for the computer analysis, capacitances CCB and CEB were added in shunt with the transistor junctions. This is equivalent to increasing the depletion capacitance disproportionately with respect to the diffusion capacitance, but it does reduce the switching speed of the transistor and increase the switching transients observed in the base current waveform. The main conclusion drawn from this experimental amplifier was that the complex collector current waveshape predicted by the numerical analysis with the intrinsic model (Fig. 4.2d) is reasonable. This level of verification is certainly not conclusive but does increase our confidence in the analysis methods employed. 4.4 Experimental 100 MHz Class C Amplifier As stated before, the adequacy of a transistor circuit model

+ cc cOL, R3 10.0 ~~L R IOmH O. 1M FF 1K lCc l 2K | | J \ ~ d %I_ 2N702 R2 C vCE CE + + 001OF M 1N2070 V +8V -8V iB t R1 100.0 Fig. 4.3. Low-frequency amplifier

141 o V vs (10 V/cm) 0 V VBE (5 V/cm) o V VCE (5 V/cm) 0 mA ib (5 mA/cm) O mA coL (50 mA/cm) OL Horizontal -Scale: 50 Vsec/cm (Typical) Fig. 4.4. Behavior of low-frequency amplifier

142 and associated computer analysis programs to predict high-frequency large-signal circuit behavior can be tested best by comparisons to experimentally observed amplifier behavior. The 100 MHz amplifier of Fig. 4.5 was constructed and measured to provide such a comparison base to be used with the simulation using the intrinsic transistor model (Fig. 2.12). The input circuit was not tuned or matched to the 2N3866 characteristics because, for this analysis, the main interest lay in the behavior of the collector circuit. Thus, the interactions and complexities introduced by base circuit tuning were not desired. The effects to be studied with this amplifier are those of collector supply voltage, load resistance, and input driving frequency. The nominal values used for this study are Vcc = W0V, RL = 225~2, f0 = 100 MHz as indicated in Fig. 4.5. 4.4.1 Effect of Collector Supply Voltage. From circuit analyses with ideal switch simulations (Chapter 3) we found that output power increases approximately as the square of the supply voltage, provided that the other circuit parameters remain fixed. At first glance, it may appear that this result is in contradiction to most analyses of class C amplifiers (Refs. S4, T1, R1) which predict linear increases in output power with supply voltage. This linear variation is predicted by low-frequency nonsaturated analysis of the collector circuit. viz (from Fig. 4.6) (Vcc- Vcesat)Z OUT = 2RL

ICAVG 1000 - V RF Choke 1 (10 volts) 1000 p R TV00 ~(225Q).103ph 100l pf R Directional p50 1, 20 dB Coupler Attenuator 1000 pf HP 431 B Power Meter RF Choke HP 431 B O1000 -pf~ 100Power Meter 50f, 10 dB Attenuator Vbb 2 volts Boonton 230 A Power Amplifier GR 1208 B Oscillator Oscillator=~~~~ 1 e Note: Nominal values shovn in parentheses fo0= 100 MHz\'To= 10-8 sec/ Fig. 4.5. Experimental amplifier and measurement circuitry

iE ~cmax bmax iC(O I Il \JCollctor Operating Path 0 T/4 T/2 T Vicesat y~,Vc cstc VC W I Fig0 406. Collector circuit behavior of low-frequency class C amplifier

145 Icmax = 3 Ibmax (fixed by input drive) V -V Vcc cesat L= I cmax For Maximum P OUT (Vcc Vcesat) v Ibmax P bmax OUT 2 2 cc Such analysis assumes that the load resistance, RL, is increased correspondingly with increases in V. However, if RL is not reCC L adjusted with changes in Vcc, we can expect the output power to vary as (1/2RL). Vcc2 when the amplifier is driven into saturation and to remain relatively constant, G ~ Pin, when Vcc becomes large enough to prevent saturation. This expected behavior was observed for the experimental amplifier (Fig. 4.7) except for very large Vcc. For these large supply voltages the output circuit apparently becomes detuned, causing the gain to decrease slightly as Vcc is increased. Figure 4.8 shows the corresponding variations in efficiency with supply voltage variations. 4.4.2 Effects of Load Resistance and Period of Driving Source. The variations in output power and output circuit efficiency resulting from changes in load resistance are shown in Figs. 4.9 and 4. 10. Figures 4. 11 and 4.12 illustrate the frequency dependence of the amplifier. These results have no special significance in terms of desirable amplifier performance, but they do provide the required

2.8 1.4 - 2.86 -. - I4 rwiP(1) Fundamental Output Powerwer 2.6 P(1) hudamental Output Power PCC 2.4 *'SA Available Source Power 1.2\CC 2.2 - 2.0 1.0 0 2.0 q/ G1 (Experimental) G/2 1.8 (Computed) 1.2 x =..',,(Experimental) -X I o'-3. (Computed) f ~ ~.O zO~ 0. 2 0.8 10 0.4 - x,4 0.6 - x 0.4 - 7 0.2 0.2- x0 I0 I 1 I I I \ I I I _ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20 22 24 262830 Collector Supply Voltage: VCC (Volts) Collector Suppl Voltage: VCC (Volts) Fig. 4 9. EffV~~~~olector S u p p lyesistage:CC (ontsi Fig. 4. 7. Effect of collector supply voltage on gain Fig. 4. & Effect of collector supply voltage on efficiency 0) 3.0 2.5 - 2.0G/2 (Computed) 1.5 1t~ ~~~~r'-.0 " ~ G (Experimental) 0.5 - 10:100 1000 Load Resistance: RL (Ohms) Fig. 4.9. Effect of load resistance on gain

0. 7 _(Experimental) G = P = ntOutput ower PU) SA vai e Source Power PSA 0.6 0 2.0 / rl (Computed) 8o{ b ioa; {r;>\N;trl_) 1.8 0.5 1.6..4 - 0.4 1.2G (Comput(Computed) X _' G (C,5/ 0.2~~~~~~~~~~~~~1.0 0.3 -0.8G(Expe, rim 0.8 0.6 -_ 0.2 - 0.4 0.2 0.1 [ I 10 10ioo 1000 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Load Resistance: RL (Ohms) Scaled Driving Period: T/T0 Fig. 4. 10. Effect of load resistance on efficiency Fig. 411 Effect of driving period on gain P(1) Fundamental Outut Power 1.2 - CoPector Supply P ower 1.0 v (Computed) 0.8 i (Experimental) 0.4'x 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Scaled Driving Period: T/TO Fig. 4&12. Effect of driving period on efficiency

148 standard for comparison with the results predicted by computer- aided analyses. 4.5 Computer Analysis of 100 MHz Class C Amplifier The parameters obtained for the intrinsic model of the 2N3866 transistor were combined with a computer-analysis program to study the behavior of a class C amplifier with the same component values as used in the preceding experimental amplifier. The circuit equivalent to the experimental amplifier appears in Fig. 4.13. For numerical convenience the frequency has been scaled down by a factor of 108 and the current levels have been scaled up by 103. The transistor parameters for this simulation were chosen from Sections 2.3, 2. 5.1.4, and 2. 5.3.1. The depletion capacitances were assigned fixed values for the numerical analysis. The values chosen were selected from the capacitance characteristics (Figs. 2.16 and 2.17) at the average junction potentials, i.e., CEDEP CEDEp(VEB, ) 6.5 pf VE'B' =VE Bt = VSDC = 2 v CCDEP = CCDEP(C,B) 2.3 pf VC'Bt =vCB, =VCC + VSDC = 12v The conputed behavior of the amplifier is included with the experimental behavior in Figs. 4.7 through 4.12.

C ~~~~~~C L LL C'~b. I C~~L -p~ L F RL I ~''COL (0. 536 f)'(0.0103h (0.2255) CI CDIF FF1 CCDEP - CC B BB B' ______R I (l0v)'B CEDIF RR (0.05&~) I CEDEP (18834 Vpeak) s T 0 1 10 secl VSDC (2 v) - ~~~I Intrinsic Transistor Model of Section 2.4.3 Q -Xi I aF = 0.988 QFS =4.66x10'0coul FS 7 F FaF -7 R= 0. 667 QRS = 1.16x10 coul _R -XS TF = 0. 011 sec CEDEP = 0.65 f (Fixed) -R (e C'B TR = 2. 56 sec CCDEP = 0.23 f (Fixed) c EDIFFEQFSBe X = 21.3 1/volt R = 0. 020 -X 6VC BE C'~~~~~~~CQ CCDIFF= X RS e Fig. 4.13. Equivalent circuit for computer analysis

150 4.6 Comparisons and Conclusions The intrinsic voltage controlled transistor model has been used in this chapter to study two tuned power amplifiers. The model was found to provide good simulation of a low frequency, pulsed input amplifier in which the transistor action is similar to an ideal switch. Complex base and collector circuit voltage and current waveforms were properly simulated by the model and analysis method as verified by measurements of an equivalent experimental amplifier. A second amplifier employed a 2N3866 transistor at a frequency of 100 MHz. Comparison of the computed and experimental frequency response of the amplifier (Fig. 4.11) indicates that the maximum computed gain was approximately 30 percent greater than the experimentally measured gain. The maximum computed efficiency exceeded the experimental efficiency by only 8 percent, but the computed efficiency peak occurred at a higher frequency than determined experimentally (Fig. 4.12). The measured gain of the 100 MHz amplifier increased approximately as VCC2 for VCC < 15 volts, but leveled off for larger values of supply voltage (Fig. 4.7). Although slightly larger in value, the compute gain behaved similarly to the measured gain for the lower supply voltages. However, the computed gain continued to increase as VCC2 for large supply voltages, implying that the model used for the simulation was driven ilto saturation even at the high current levels

associated with the large supply voltages. The compute efficiency remains relatively coiistaiit for VC 6 volts, but because the transistor in the experimental amplifier does not behave as a saturated switch at the larger supply voltages, the measured efficiency reduces as VCC increases (Fig. 4.8). The characteristics of the computed and measured gain variation with load resistance are approximately the same for RL > 100 Q (Fig. 4.9). For smaller load resistances, the experimental gain is apparently reduced by transistor losses not simulated by the intrinsic model. In addition, the computed and measured efficiencies (Fig. 4.10) do not agree well at all. Improved description of the device losses seems necessary if the effects of load resistance are to be modeled properly. We conclude that the intrinsic voltage controlled transistor model is adequate for many low frequency amplifier simulations that are limited to small ranges in circuit conditions, however, an improved model is desirable for better simulation of high frequency amplifiers subjected to large variations in circuit conditions. One might conjecture that the most essential additions to the model would be a collector resistance to account for losses with small load resistances and base and emitter impedances to limit the base drive current and prevent device saturation during conditions such as large collector supply voltage. Such additions are provided by the extended

152 transistor model (Section 2. 5), and their effects are considered in the next chapter (Chapter 5). Further computations involving the intrinsic transistor model are presented in Chapter 6 for comparison with the other models.

CHAPTER 5 CLASS C AMPLIFIER ANALYSIS WITH EXTENDED TRANSISTOR MODEL 5. 1 Introduction The intrinsic transistor model was expanded in Chapter 2 to provide a more complete description of transistor behavior in highfrequency, large-signal applications. In this chapter the resulting extended transistor model is utilized to simulate numerically a VHF power amplifier. The amplifier simulated in this case employs simple tuning of both input and output. As in the study of the intrinsic model, experimental results are compared to the results of the digital computations. The importance of each of the elements in the extended model has yet to be established. The question of the relative significance of each element of the model in predicting the overall behavior of a class C amplifier arises in the attempt to describe a transistor's highfrequency large- signal characteristics with a nonlinear dynamic circuit model. Using the VHF amplifier simulation, the sensitivities of several performance factors to variations in transistor model parameters and external circuit parameters have been computed to estimate the significance of each parameter. The sensitivities are presented 153

154 in this chapter and are useful for indicating the precision to which each circuit and model parameter value needs to be determined in order to accurately compute RF power amplifier behavior. 5.2 Experimental Amplifier The experimental amplifier and measurement circuitry (Fig. 5.1) is very similar to that of Fig. 4. 5. This amplifier is more representative of practical tuned power amplifiers in that the base input circuit is tuned as well as the collector output circuit. As with the previous amplifier analyses, our interest lies in determining the computational utility of the model to predict experimentally measured behavior. The experimental parameters chosen for a wide range of variation were the source driving frequency, the load resistance, and the collector supply voltage. The nominal values of these variable parameters were: f0 = 100. MHz, RL = 225. ohms, and Vcc = 10. volts, respectively. The experimentally observed performance of this amplifier is given in Figs. 5.2 through 5.14. 5.3 Amplifier Analysis with Extended Transistor Model An equivalent circuit representation for the amplifier with the extended transistor model is shown in Fig. 5.15. For this equivalent circuit, the element values have been scaled to reduce the frequency by 108 and to increase the current by 103. A dynamic description of the resulting seventh order nonlinear system is given by the following

- ICOL AVG 1000 pF Vc (10 volts) RF Choke 1000 pL 75 nH R, 10001PFL R 1000 pF 2N3866 PRL bi (788 W) #1 CL L 50 n'Pbr Directional 1I10pF t Meter 4, jAttenuator cie1bMeter l0 _I Incident Or. Base Voltaqe Tektronic *cV,|3S76,3T77| RF Choke Samplier 50 5 10dB Sp 100pF P 431 B HP 8551 A Boonton- 230 A] AV G Aiayzr Power Amplifier Vbb (-2 volts) GR 1208 B z} Oscillator to _ 100MHzet Bai se l Fig. 5.1. Experimental amplifier and measurement circuit

156 Incident Base Voltage (-15.5Db) 0.5 v/cm, Total Base Voltage Vertical: 5'v/cm Horizontal: 2 ns /cm Incident Base Voltage (-1 5. 5Db) */ ~' _0. 5 v/cm Collector Voltage Vertical: 10 v/ cm Horizontal: 2 ns/cm _00 MHz 00 MHz Load Power Spectrum Vertical: 10 dB/cm Horizontal: 100 MHz/cm Fig. 5.2. Waveforms for 100-MHz experimental amplifier

600 1.2 udm~tr ae 6001 -- tL (Computed) 1.2 = to6, 500 r' L (irI m- t0) 1.0 - fi (Computed) o* 6 *- — *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~i (Experimentral) B400 0.8 - 300 - 0.6 0 0.4 100 0.2 0 L0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Scaled Driving Period: T/T Scaled Driving Period: T/To Fig. 5.3. Effect of driving period on output power Fig. 5. 4. Effect of driving period on efficiency 10 300 TCOL ( 0 250 ( X.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~. e -20 ~(Computed) 150 "-p)oN~jCr: ~- (Experimental). -30-40 50 KA C1 I I -AI i 0.4 0.6 0.6 1.0 i..2 1.4 1.6 1.8 2.0 0.4 0.6 0.8 1.0 1.2 1.4 1.8 2.0 Scaled Driving Period: T/T Scaled Driving Period: T/T0 0 Fig. 5. 5. Effect of driving period on base current Fig. -5. 6. Effect of driving period on collectrcurn

500 50. 0. - 0.t 4o00 ) (o mt. ed (C t t xperlmed) L (Cput d, Model) JL M \(ode) i (), 0 o I.J.!,..... I I. I I.... 0. I......., 20 50 100 200 500 1000 20 0 100 200 SO 000 Load Resietance: RL (ohms) Lod Ret: RL (ott) Fig. 5. 7. Effect of load resistance on output power Fig. 5.8. Effect of load resistance on efficiency t~~~~~~~o 0~~~~~~~~~~~~~~~~~~~~~~c 10 M 2)0 100 -30 - so SCOL (CompUt4d Mode (, -40 - 0I C ~~~~~~~~~~~~~~~~~~~~~0 _ 1:,,, 1' -~!'ql ~.ido''' i 20 so 100 200 S00 1000 20 100' 50 1 Load ResIstance: R (ohms) Load Remstace R3L (ohm) Fig. 5. 9. Effect of load resistance on base current Fig. 5. 10. Effect of load resistance on collector current

w PL (Computed) - iic (Computed) 500' -X P (Experimental) 1. q % (Experimental), 400 - 0. 300 - 0.I A. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0. 300 too / "0 0. 0 32 31 0* 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 2, 4 6 8 10 12 14 16 16 20 22 24 26 28 Collector Supply Voltage: V,, (Volts) Collector Supply Voltage: Vcc (Volts) Fig. 5. iL Effect of supply voltage on. output power Fig. 5. 12. Effect of supply voltage on efficiency 1 (Computed) 25 — a. IB (Experimental) - 1 ICOL (Computed) 0 400 - -u ICOL (Expermental) -250 - -u 200 4 5 100 -100 0 4 8 12 16 20 24 28 32 36 0 4 6 12 16 20 24 2 2 3 Collector Supply Voltage: Ve (volta) Collector Supply Voltage: ~ V olt Fig. 5. 13. Effect of supply voltage on base current Fig. 5. 14. Effect of supply voltage on collco urn

160 C 0.. _02_.02 Q.01Z815 -0t1225 U. U07 CDEP CDIFF R 2V 0. 0. 0263'~L_, b-. -02245 * _ tRS I/~AvC.iv'r aR 0.6667 1 L n1QS 4.66x101-10E CCEDEP C 1EDIFF' e C A C 1. Ix7__ =-033011 CDFF 15 (J e0 2. E' U. ~.,? Z = 0.666 Rs'c'n' C-I C" = " JC " c 0.314 QFSR R. Q = 4. 66 x o" 10 - -V = C7?Tr, = 0.Oil CCDiFF = AQis e T 2.5 AA = m.4 F1C -+ c EI)EP = A) FE (A CE.-.. 1.04 VZE + CEV A 0.5 AE SuprcmumF AEiIM ZE = 0.8 C CYC CFC vY.: =C 0.314 AELiM =0.06 AC = Supremum ACLIMC 034 VC = 0.17 A VA. vFIB CLIM VA = 6.2 NA 4.0 S VSDC + VSA sin t VSDC -2 Fig. 5.15. Scaled equivalent amplifier representation with extended transistor model

state equations: s i A' X+ BN' U + BS' U (5.1) where X [EB' vCE' VE'B" VC'B" iLS LEE LL UN F' POFiF] iR' oRiR iA S =: CCC BB CS+CBE+CCB CCB O O O O O CCB CL+C +C 0 0 0 0 0 CB L CE GB o 0 CE 0 0 0 0 S = 0I O CC 0 0 0 0 0 0 0 LS 0 0 0 0 0 O LEE 0 0 0 0 0 0 0 LL

1 1 11 R R BB+RCC RBB+R R +R RBB+R S BB CC BB CC BB CC _ 1 1 1 1 RBB -1 RBB+R R RL RB+R R+R+R A=BB CC L B CC BB CC BE CC o 0 0 0 0 1 0 1 1 1 RBB 1 _ _ R +R R Rcc R +R R+R BB CCC BB CC BBBCC -1:0 0 0 0 RC R RB R _B B RB BB 0 R R +R R +R RBB 0 REE R ~RR Rcc+cBB RCC+RBB RCC+RBBBB CC 0.1 0 o 00 l ~~~~~~~~~~~~~~~~~~_

163 O O O O 0 R| 0 0 0 00 0 0 0 1 R 0 L o 0 O O 1 0 0 0 1 o o -1 -1 I I O BN' = 0 -1 1 0 0 BS' = I O O 0 0 0 0 0 0 0 -1 0 00 0 0 0 0 0 0 0 0 0 0 O -1 0 with the necessary side conditions Q v FF ( EB (5.2) QRS e C B 1) (5. 3) R 7RTR QFs 1 = FSF(E /AA-1 (5.4) 1- (VEB,/VA and E CEDIFF + CEDEP + CA (5.5) *As described in Chapter 2.

164 CC = CCDIFF + CDE (5. 6) The technique employed for finding the forced steady-state solution was the same as had been used successfully in earlier analyses of the various class C amplifier simulations. The actual algorithm used for solution of this system of equations is illustrated and discussed in Appendix C. The steps involved in the numerical solution can be summarized as: (1) Guess the initial values of the seven state variables. (2) Solve the system of equations for one period of the input forcing signal with a double precision predictor-corrector numerical integration routine. (3) Compare the final values of the state variables to the initial values. (a) If the final values are sufficiently near the initial values, the steady- state solution has been found, and the next portion of the analysis can be conducted. (b) If the final and initial values are not sufficiently near, set the initial values to be equal to the final values and repeat parts (2) and (3). (4) Integrate the steady-state waveforms to determine average base current, average collector current, collector power dissipation, etc.

165 (5) Perform a numerical Fourier analysis of the solution waveforms, and compute the power gain, output power, efficiency, etc. 5.3. 1 Effects of Signal Source Amplitude. The computed effects of input source amplitude on amplifier behavior are indicated in Figs. 5.16, 5.17 and 5.18. These calculated results show that a source amplitude of 8 volts peak produces average base and collector current values (-17. ma and 85 ma, respectively) close to the values measured experimentally (-20 ma and 110 ma). The source amplitude determined from the experimental measurements at 100 MHz with the directional coupler and a peak reading voltmeter in the input circuit was 18. 3 volts peak. However, observations with a sampling type oscilloscope (Fig. 5.2) indicated appreciable distortion was present in the incident signal from the input source and that the peak amplitude of the fundamental component was approximately 8.0 volts. The problems created by the distortion and uncertainty of input signal amplitude can be alleviated by choosing a computational source amplitude that provides agreement between the experimental and computed device terminal currents and by comparing the output load powers rather than the power gains. Such an approach was used for the Of course, the power gains can be obtained from the output load powers and the input source amplitudes, e.g., Transducer Power Gain = Load (VSA)2/8 Rs but will have limited meaning for comparisons with this 100 MHz amplifier.

500 1.0 400 0.6 0.~ ~ ~~~ ~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~. 2300 0.6 100o 20 0.4 0 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2 4 6 10 12 14 16 is 20 2 4 6 8 10 12 14 16 16 20 Driving Source Amplitude: VYS (Volts) Driving Source Amplitude: VS (Volts) Fig. 5.16. Effect of source amplitude on output power Fig. 5. 17. Effect of source amplitude on efficiency o-o —-a Average Collector Current: 1COL (mA) 0 -Average Base Current: (mA) 200 - -lo, ISO -.20 100 -- 30 so -40~r 0 2 4 6 6 10 12 14 16 1s 20 Driving Source Amplitude: VS (Volts) Fig. 5. 18 Effect of source amplitude on base and collector current

167 analyses with the extended transistor model. 5. 3.2 Computed Performance. The computed waveforms and load power spectrum of the 100 MHz amplifier operating with the reference circuit conditions of Fig. 5.15 are shown in Figs. 5. 19 and 5.20. The waveforms of collector-emitter and emitter-base voltage exhibit the same peak amplitudes and shapes, within experimental measurement accuracy, as observed with the experimental amplifier (Fig. 5.2). One advantage of the computer simulation lies in the ability to predict waveshapes such as the terminal currents and the junction voltages that cannot conveniently be measured experimentally (e. g., experimental attempts to observe the current waveshapes at VHF frequencies usually disturb the amplifier circuit to such an extent that the results are unreliable.) The complexity of the base and collector current waveforms illustrates the falacy of assuming simple analytic pulse forms to predict high frequency amplifier performance. Assumptions of sinusoidal emitter-base junction potential are also unrealistic in such large signal analyses. For comparison with the experimentally observed amplifier behavior, the computed effects of input signal frequency over a two octave bandwidth are also given in Figs. 5.3 through 5. 6. Effects of load resistance and collector supply voltage are illustrated in Figs. 5.7 Note that experimentally the base-emitter voltage was observed and computationally the emitter-base voltage is shown. This polarity reversal should be remembered when making the emitter-base waveform comparisons.

6. 00 0 0.6 36.6* 11.. 5..078 - 21.2 0.10 ~.0.40 6. s.06 2o -3.60 -29 15.5 4.02 -6.80 0.408- 5.75 1.47 - -10.0 -3. 25 -1.01 -1.90 0.2 0.4 0.6 0.6 1.0 0 0.2 0.4 0.6 0.6 1.0 0 0.2 0.4 0.6 0.6 1.0 0 0.2 0.4 0.6 0.6 1.0 Time (Seconds) Time (Second) Time (Seconds) Time (Seconds) (a) Source voltage (b) Emitter-base terminal voltage (c) Collector-emitter terminal voltage (d) Emitter-base Junction voltage 43.6 - 90.5 - 431. 210. 34.7 - 45.7 - 332.X0.6 25.0 4232. 4. 0s. 6 F -59 9 0133. -17L 6.04 -113. 3 - -30L -0. c - I -165. 5.1 -437. 0 0.2 0.4 0.6 0.8 1.0 0 0. 2 0.4 0. 6 0. 8 1.0 0 0.2 0.4 0.6 0.6 1.0 0 0.2 0.4 0.6 0.6 1.0 Time (Seconds) Time (econds) Time (Seconds) Time (Seconds) (e) Collector-base junction voltage (f) Base current (9) Collector current (h) Output inductor current 337. 5.90 269. 4.72 4 202. -3.5 - 135. -.36 67. 1.16. is.01.0 0.00 0 0.2 0.4 0.6 0.6 1.0 0 0.2 0.4 0.6 0.8 1.0 TIme (Seconds) Time (Seconds) (i) Emitter-base diode current (j) Collector-base diode current Fig. 5.19. Typical waveforms with extended model analysis

169 10 0 o -10 -20 _30 0 4 -40 _ -50 -60 - 1 2 3 4 5 6 7 8 9 10 Harmonic Number: N Fig. 5.20. Computed output power spectrum

170 through 5.14. These computed results appear to be in moderate agreement with those of the experimental amplifier except for load resistances larger than 300 ohms. In the load resistance region of 200 to 300 ohms, the computed collector current is observed to have two possible modes, with the mode of operation being determined by initial conditions. The waveshapes resulting from each of the two modes appear generally the same with the exception that operation in mode 2 causes the transistor to remain in saturation longer than it does in mode 1. The operating paths of the collector circuit for both modes are plotted in Fig. 5.21. From this plot we observe that the peak signal amplitudes are greater for mode 2, but the paths of the limit cycles for both modes are similar. The limit cycles of the junction potentials (Fig. 5.22) provide additional information about the differences between the two modes of operation. In mode 2 the transistor is driven into the inverse region for approximately 10 percent of the cycle. This does not occur in mode 1 where, as with most class C amplifiers, the collector potential does swing negative with respect to the base potential when the emitter-base junction is reverse biased. The possibility of operation in the inverse region increases with large collector voltabe amplitudes that result with very large load resistances. Mode hopping was not observed experimentally in the range of load resistance investigated. However, such behavior is not unusual for tuned power amplifiers, and mode changes with frequency, source

700 45 Notation: RL = 3000 0 0 —O,Mode 1 (Forward) (Cutoff) 0C — Mode 2 600 40 ~ I - 0.3 600 - Foyward Region ----- Cutoff Region Mode 2.....- Inverse Region 500- ^ Saturation Region 0.23 ~ 2 l l| T / lRL= 300 fl 400 t=o 30 -0.90 0.1 Model o0.81~~~~~~~~~~~~~~~~~~0.3 0 >_ 0.1 ( 100 0 25 0.62/ 200 I (Vt 20 0. I o. 2. i of io 0 5;0~, 4 0.3 0. = 01 0,,,. h0.7 4;0 ~~~~0.1 100 /0.2 15.~~~~-A ~~0.6 p ~.2 ~t 0'.0.4 0.3 -,, 1~~~~~~~~~~0 000 0.7 0 0.8 0. 0.6 (Saturation) 0. (Inverse) -10 0 10 20 30 40 -2 0 2 4 6 8 vCE (Volts) EB Fig. 5. 2L Collector circuit limit cycle Fig. 5. 22. Limit cycle of junction potentials

172 amplitude, and supply voltage have been observed in similar amplifiers utilizing the 2N3866 at VHF frequencies. For example, the class A1 amplifier circuit of Fig. 5. 23 was developed as part of a wideband amplifier study. 1 The swept frequency response of the amplifier (Fig. 5. 24) over a frequency range of 70 to 400 MHz was found to be dependent on the input signal power. The three response curves of Fig. 5.24 correspond to input powers of 4.23, 2.12, and 0. 841 milliwatts. Relatively smooth response characteristics resulted for small input powers; but the response was found to "break up" at the higher signal levels, particularly for frequencies below 200 MHz. A sampling oscilloscope was used to monitor the output voltage waveforms of the amplifier at fixed operating frequencies. The output waveforms of Fig. 5. 25 were observed at a signal frequency of 190 MHz and illustrate the jump in operating mode that can result from changes in signal amplitude. As the signal amplitude is increased, the output signal remains nearly sinusoidal up to the level shown in the top trace which is 8.8 volts peak to peak. A slight further increase of the input amplitude causes the output waveform to jump to the one shown in the lower trace. In this new operating mode, substantial harmonic content is evident in the output waveform. This same hopping of mode produced the irregularities mentioned for the swept frequency response (Fig. 5.24).'This study was conducted by A. B. Macnee and Dennis Packard at The University of Michigan Cooley Electronics Laboratory.

173 2N3866 40 1000 1000 7.96 50RFCj i + CS VL 2.2k R| vs - VBB + Vcc 470r Fig. 5.23. Experimental class A1 wideband amplifier circuit The nonlinear mode hopping behavior is representative of the effects that can be investigated conveniently with computer simulations but not with analytical techniques. Various transistor parameters (depletion capacities, charge storage time constants, static current gain, emitter lead inductance, etc.) can be altered in the simulation, and thieir effects on circuit stability and performance can be evaluated. In this manner the simulation can be used to determine which device parameters are critical in the operation of a given circuit and thereby suggest optimum devices for such application.

174 -- ~V LI S~~~I I I I 70 100 150 200 250 350 300 400 Freq. in MHz Fig, 5.24. Swept frequency response of experimental amplifiers; available input powers are 4. 23, 2. 12, and 0. 841 mW Fig. 5.25. Output waveform change associated with "mode jump" at 190 MHz. Vertical scale 3 V per division; horizontal scale 2 ns per division

175 5.4 Allll)lifili' S(iisitivities In addition to guiding selection of transistor types, we can utilize the extended model representation of a tuned power amplifier to estimate how critical each circuit and device parameter is to the overall behavior of the amplifier. If we determine that some device parameter has a strong influence on computed performance, then the value of that parameter must be determined precisely to achieve accurate simulations. Less critical values need not be measured as precisely or in some simulations may be removed from the model. The simulation circuit of the 100 MHz amplifier is representative of many power amplifier configurations. Thus, the sensitivity of this circuit behavior to the various transistor parameters should be representative of many applications. The sensitivity of a circuit behavior function to a change in a circuit parameter can be described briefly as f - af/f Af/f [f(P') - f(P)]/f(P) p ap/p Ap/p (p'- p)/p where f is a function of several parameters of which p is one p is the parameter under investigation p = P + Ap Ap is a small variation in p

176 In general, we wish to make as small a perturbation, zAp, in the parameter value, p, as possible. However, in numerical analyses, too small a perturbation may cause such small variations in the functions under consideration that the variations are lost in computational noise. For the computer-aided sensitivity analyses with the extended transistor model, parameter variations of 10 percent seem reasonable. By making such variations from the standard values (shown in Fig. 5.15) for each of the model and circuit parameters, the sensitivities of output power, efficiency, base current, and collector current have been determined (Table 5. 1). From these tabulated results we find, for example, that a 10 percent error in modeling the forward current transport factor, ~F Xcan lead to an error of 48.3 percent in the computation of the output power of the amplifier. This sensitivity to a change in transistor UF can be expressed alternatively in terms of the common emitter static current gain of the transistor, 3F, by the manipulation L PL F/F P S/3 = S =S (1- eLF) = 0.0594 F PF F F F where PF uF 1- poF Thus we find the sensitivity of output power to the directly measured

177 I_____ _____ _ Amplifier Functions Parameters PL 7 I COL VSA 3. 88 0. 321 +2. 02 3. 47 BSDC -2. 88 -0. 125 +0. 0490 -2. 72 VC I 0.874 -0.433 -0. 316 0. 370 T -2. 67 0. 135 -1.04 -2.78 Rs | -1.52 -0. 392 -0. 792 -1.17 L I 0. 600 -0. 125 -0. 00646 0. 798 CS 1 0.0739 -0. 117 -0.179 0.153 RL -0. 236 -0. 721 +0. 291 0. 440 LL 1. 50 0. 715 -0. 437 0. 670 CL 1. 91 0. 234 +0. 131 1. 52 CCB -0. 0821 -0. 0874 -0. 170 0. 0371 CBE 0.00513 0.00330 +0.0889 -0. 0137 CCE 0. 199 -0. 0346 +0. 0407 0. 155 RCC -0.455 -0. 228 -0. 495 -0. 190 RBB 2.74 0.759 +0. 899 1. 70 REE -0. 00977 0. 377 -0. 246 -0. 0844 LEE -0. 0506 0. 178 -0. 131 -0. 216 | QFS | 0.0724 -0. 164 -0.219 0. 204 Table 5.1. Sensitivities with extended transistor model analysis

178 Amplifier Functions Parameters P I IOL QRS -0.107 0.0521 -0. 330 -0. 157 TF -0. 506 -0.251 -0.230 -0. 250 TR -0.0602 0.138 -0. 335 -0.133 aF 4.83 1.09 +5.24 4.24 aR -0. 456 -0.325 -0.150 0. 224 X 1.40 -0. 181 -0. 0589 1.53 VA 1.91 -0. 131 -1.65 2.03 NA 0.0759 -0. 0595 +0. 0961 0. 0801 CJC i-0. 224 -0. 294 -0. 126 0. 114 VZC 0. 0975 -0. 0525 -0. 00972 0. 0675 YC -0. 00308 0.0464 -0. 471 0. 0495 CFC -0.0350 -0. 194 +0. 00662 0. 176 ACLIM -0. 0317 -0. 0987 -0. 150 0. 0693 CJE -0. 247 0. 167 -0. 440 -0. 400 VZE 0. 187 -0. 0444 -0. 152 0. 196 YE 0. 317 0. 199 +0. 118 0.0573 CFE 0. 118 -0.0550 +0. 0555 0. 0820 AELIM 0. 139 -0. 0526 +0. 0184 0. 108 Table 5.1. (Cont. )

179 model parameter, OF' to be much less than the sensitivity of aF' and in consideration of modeling accuracy requirements, the OF dependence has the more direct significance. As a similar application of the tabulated sensitivities, we observe that using a 2N3866 transistor with an emitter-base avalanche potential, VA, 10 percent greater than the 6.2 volts used in this simulation could lead to a 20. 3 percent increase in the average collector current of the amplifier circuit. 5. 5 Conclusions The computations utilizing the extended transistor model have demonstrated the ability of the simulation to predict the behavior of VHF power amplifiers. The simulation provides the versatility and convenience of monitoring several functions that cannot be observed readily with experimental techniques. In addition the simulation can be used to predict how changes in transistor parameters will effect the amplifier behavior. Further comparisons of the extended model analyses to analyses with other model representations will be given in the following chapter.

CHAPTER 6 COMPARISON OF AMPLIFIER REPRESENTATIONS 6.1 Introduction The ideal switch and intrinsic transistor model representations have been found to be useful for analysis and study of basic characteristics of low frequency tuned power amplifiers. In the high frequency analyses with the intrinsic transistor model, some of the behavior predictions were found to differ significantly from results obtained with a 100 MHz experimental amplifier. Consequently, the intrinsic model was augmented to include major extrinsic effects, and the resulting extended transistor model was used for calculations and comparisons with another 100 MHz experimental amplifier. In order to provide a better comparison between the various models, all of them are used in this chapter to predict the fundamental characteristics of a common amplifier. The amplifier chosen for this comparison standard is the experimental 100 MHz amplifier presented in Chapter 5 and shown again in Fig. 6.1. Small signal measurements of the passive output network of the amplifier at a frequency of 100 MHz led to the equivalent output circuit of Fig. 6.2. Observation of the collector-emitter voltage waveform of the experimental amplifier indicated that the transistor was in saturation approximately 40.4 percent of the time which implies a switching duty 180

1COL AVG Collector Voltage 1000 pF V (10' volts) ItI~ i~ii.~ ~ *.:ii Vertical: 10 v/cm ~cc 4 Horizontal 2 ns/cm RF Choke j000 pF LL 75 nO R 1000 F R 1000 pF - 0 ~~2N3866 Pbi(788 4mW) #1 C RL 50 Pbr 1-~~~~~~~I-10 pF Directional Coupler S HP 431 B LS 1-10 pF 50 i,20 dB -15.5 d Power 50 nH Attenuator Meter 1000 Incident Or Base Voltoqe Sampling Scope RF Choke Spec truutr 50 (1, 10 dB Attenuator 1000 F5 Analyzer Boonton 230 A AVG Power Amplifier I 2 v I t s GR 1208 B Oscillator (o = 100 MTz\ 1o sec Fig. 6.1. 100 MHz experimental amplifier, measurement circuit and collector voltage waveform

182 factor of 0.404 for analyses with the ideal switch representations. Scaling the amplifier center frequency by a factor of 108 and scaling the network currents by 10 leads to the computational models illustrated in Figs. 6.3, 6. 4, 6. 5, and 6. 6. The capacitance value chosen for the fixed capacitance-ideal switch model, C, represents the sum of the output tuning and stray capacitances of the amplifier and the net collector-base capacitance of the 2N3866 transistor evaluated at the average collector-base potential, Vcc - Vbb' Similarly, the capacitance parameters for the ideal switch-depletion capacitance representation were selected to match the collector-base depletion capacitance characteristics of the 2N3866. The intrinsic and extrinsic transistor model parameters were also chosen to match the 2N3866 characteristics as discussed in Chapter 2. Analyses with each of the amplifier representations were conducted numerically as discussed in preceding chapters. The amplifier's behavior characteristics chosen for investigation and comparison were circuit waveforms, fundamental output power, collector efficiency, and where applicable, average base and collector currents. The circuit parameters used as variables were source driving period, load resistance, and collector supply voltage. The computed effects of input source amplitude on the intrinsic and extrinsic transistor model representations are also included but these effects were not verified experimentally.

183 Vcc (10V) ('73 nH) i R(225 l) 2N3866 C(7.2 Pf) Fig. 6. 2. Measured equivalent output circuit Vcc (10V) L(. 0073 H) R(. 225)? VC',T"v C(1. 005 f) Fig. 6.3. Scaled equivalent output circuit for ideal switch analysis V (1OV) L R (0. 0073 h) (0. 225Q1) switch closed switch open \T v_;,vj CC(v) Cj C(v) = (A)Y + CF (A) F A = Supremurn A+ VZ LIM VZ = 0.5 ALIM = 0.0625 y = 0.474 Cj = 2,548 C = 0.17 Fig. 6. 4. Scaled output circuit for analysis with ideal switch and depletion layer capacitance

V (10V) L 007) R(.225) LL COL F FF RS(. 05) B RB(.02245)'R C(.8 C) 72) ~RR ECDIFFfCDEP'A CA VSDC (2V) (.763) -Xv 0. 9877 F (QFSAF F)'( ED1) F _?LVCB/ 1) 0. 6667'R -XVCB R ~~~ ~~10 eNv/ FS 4. 66 x10 CEDIFF FS VEB -7 AQQR e- XCB Q l. 16 x 0r CDIFF RS e RS VA 6.2 F NA 4. 1 2. 56 QA 7(QFS/aFF) (VEIByVA j 21. 3 CA FiA/(VA -V #) Fig. 6.5. Scaled equivalent amplifier representation with intrinsic transistor modl

185 C COL_ _ Rcc 0.012815 225 0.0073 C. CDEP CDIFF iR FF I2V 0224. 0'F 0. 026 11DP CEDIFF eil Q iA 0I 7 0 05 0 C E' 0. 016 REE C F QRS TR =. 0. 0001 055 C VillF 1. FE LEF A2V 0.000336=Speu|F.01 FSVE B 0.9877 (VZ C C = 01 E Supremum AE = - RR Q 4S.66x lO'1~ CEDIFF =~FS Cl CJC = 1 Z = 0.011 -Av CCDIFF ='QRS e R=. 25 CJEC A = 21.3 CDEP C FE(A )y FE VZE + V EB. A~B' CPN = p.0. E_ [ 1 1 C =017 ELIM VZE 0.8 CCE CDEP (YC + CFC YE 0.314 AELIM =0.06 A VZC AC - SupremuVmZC + vCJC BN 0 V)' * VSA s I VCSC = 0.341-2 "FZF'(VED/VA)NA C = v 0. 5 TF' vE ACUM 0.0625 VA =6.2 NA 4 4.0 VS VSC(' ~ VSA sin.t VSDC =-2 with extended transistor model

186 6.2 Waveform Comparisons The output load voltage waveforms (Fig. 6.7) all have the general shape of one period of a damped sinusoid. The most predominant differences in the voltage waveforms are their amplitudes. The peak to peak amplitudes are: Experimental... 3 5V Ideal switch-fixed capacitance --- 7 5V Ideal switch-depletion capacitance --- 65V Intrinsic... 59V Extended --- 36V In comparing the voltage waveforms for the ideal switch analyses we see that one effect of the nonlinear depletion capacitance is to narrow the waveform during the time that the capacitor voltage exceeds the supply voltage and to widen and limit the waveform when the voltage is small or negative. Such an effect is anticipated since the depletion capacitance value varies inversely with the capacitor voltage. Of the models considered the only form capable of producing a nearly linear change in output voltage with collector current during saturation is the extended transistor model. We see the need for adding series resistance to the output terminals of the other models if the saturation voltages are to be current dependent. The addition of such series resistance not only improves the "fit" of the saturation characteristics but also limits the rate of change of output inductor current

60.7 70. 3.~ 45.0 0 55. 8 ~ 29.3 3, o 0~~~~~~~~~~~~~~~~~ ~~~41. 3 0. 0 13.7 s 6 Ct~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~C,Q -1.98'12.2 -17. 6 -.2.29 (a) (b) 0 0. 2 0.4 0. 6 0.8 1. Time (seconds) Time (seconds) (a) Ideal switch, fixed capacitance (b) Ideal switch, nonlinear capacitance 00 1. 0 36.628. 9 39.44 21.2 27.8 5 s~~~~~~~~~~~~~U 16.2 13.5 5.75 4.62 -1. 96 i.-6.9% 0.2 0.4 0.6 0.8 1.0 9 0.2 0.4 0.6 0.8 Time (seconds) (M) Time (Seconds) (c) Intrinsic model (d) Extended model Fig. 6.7. Output voltage waveforms

188 during saturation. Thus adding series resistance reduces the amount of energy added to the output circuit during saturation; as a result, the output voltage amplitude is reduced. The waveforms of current in the output tuning inductors (Fig. 6. 8) are proportional to the integral of output voltage, and except for amplitude differences, these waveforms are very similar to each other in appearance. The emitter-base junction voltages resulting from analysis with the intrinsic and extended transistor models, vE,B,, are very similar (Fig. 6.9), and as noted previously, cannot justifiably be assumed sinusoidal. The emitter-base terminal voltage of the extended model analysis (Fig. 6.9c) appears more nearly sinusoidal, which is in agreement with the experimentally observed waveform (Fig. 6.1). The base current waveforms of the intrinsic and extended model analyses are of the same shape and amplitude, but their average values differ (Fig. 6.10). [The apparent phase shift between the intrinsic and extrinsic waveforms is produced by a shift in phase of the input signal (Fig. 6.10c) and not from differing delays in the models. This phase shift was added to improve convergence to a stable limit cycle of the numerical analysis with the extended model as described in Appendix C.] The collector currents also are of similar shape (Fig. 6.11); however, the peak amplitude calculated by intrinsic model analysis is almost twice that calculated with the

423. - 344. 183. - 1' 124. 5 - 4 -6 47 -o4.7 -296., -314. -536. - 533. -776. 0 0.2 0.4 0.6 0.8 1.0. 2 0. (a) Time (seconds) Time (seconds) (a) Ideal switch, fixed capacitance (b) Ideal switch, nonlinear capacitance 330 210. I 100 - 80.6 - 8. o.Leo -48. 8 -300 -178. - -500 500 -308. -640 -437. (C) 0 0.2 0.4 0.6 0.8 1.0 (d) 0 0.2 0.4 0.6 0.8 1.10 Time (scondo) Time (Seconds) (c) Intrinsic model (d) Extended model Fig. 6.8. Inductor current waveforms

6.17 11. 6 4.72 9. 10 0 3.26 6. 56 1. 81 4. 02 0. 357 1. 47 0 1. 10. 0 00 0.2 0. 4 0. 6 0. 8 1.0 1 0.2 0.4 0.6 0.8 1.07 (a) 0 0.4 06 08 1 Time (seconds) ( (a) Intrinsic Model ~~~~~~~~Time (Seconds) (a) Intrinsic mnodel (b) Extended model 10. 6 7. 83 0 >. 5. 06 2. 29.48 -3. 25 0 0. 2 0. 4 0. 6 0. 8 1. 0 Time (Seconds) (c) Extended model Fig. 6.9. Emitter-base voltage waveforms

108.0 98. 5 6.00 56.2 45.7. 80 I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~. 80 *1 4, 4 4. 24 - -7.10 l -0.40 -47.7 -. -59.9 3 -3.60 -99. 6 -113. -6.80 -152. 0 -165. -0 0.80-10.0 (a) 0.2 0.4 0.6 0.8 ~1.0 (- 0 0. 0.4 0.6 0.8 1.0 0 0.2 0..0.6 0. 2 0. 4 0. 6(eod Time (seconds) )' (~) ~Time (seconds) Time (Seconds) Time (Seconds) (a) Intrinsic model, base current (b) Extended model, base current (c) Extended model, source phase reference Fig. 6. 10. Base waveforms CD 681.0 431. 431, - 514.0 - * 332. 347.0E' 232. 0 179. - O [p 133. 12. 2 33. 7 -1550. 2 0. 4 0. 6 0. 8.0 -65. 6 Time (seconds) (b) 0 0.2 0.4 0.6 0.8 1.0 Time (Seconds) (a) Intrinsic model, collector current (b) Extended model, collector current Fig. 6. 11. Collector current waveforms

192 extrinsic model. Since the base and collector currents were not observed experimentally there is no direct verification of their waveform, but comparison of more easily verified characteristics (Sections 6.3, 6.4, and 6.5) will lead us to accept the extrinsic model predictions as the more accurate of the two. 6.3 Frequency Response Comparisons Comparing the computed and measured effects of signal frequency, load resistance, and collector supply voltage on amplifier performance will allow us to evaluate the ability of the models to predict behavior over a range of operating conditions. The effects of signal frequency, or period, over a two octave bandwidth are presented in Figs. 6.12, 6.13, 6.14, and 6.15. The output powers predicted from computations with the ideal switch and intrinsic transistor models (Figs. 6.12a, b, and c) are about four times larger than the measured power. One noticeable difference in the two power responses computed with the ideal switch using (1) fixed and (2) nonlinear output capacitances (Figs. 6.12a and b) is that the nonlinear simulation predicts a slightly wider bandwidth with an abrupt roll-off for large switching periods and a more gradual roll-off for small switching periods. With the extended model the maximum computed output power (Fig. 6.12d) is much closer to the measured power (about 40 percent greater), but the computed power peaks at a frequency of 125 MHz

Fundamental Output Power- P (roW) Fundamental Output Power: PL (mW) ndamentalOutputPwer: L (W) oo p o oo ) hi ~ ~ o ~' o ol o oo 0~~~~ 0'-' o ~ ~~~~~~~~~~L o~~~~~~~~~~~~~~~~~~~~~~~~~o 0 ~~~~~~~~~~~~~~~~~~~~~~~ D 0 0 0m CD. (,~~~~, l C aCOA ='1 -'; CD~~~~~~~~~~~~~~~~~~~~~~~~~~C -r~~~~~~ CA - s *19 o~ Fundamental Output Power: ~L(i)Fundamental Output Power: PL (miW) CD I, I I C I I 0~~~~~~~~~~~~~~~~~~~ o~~~~ ~~~~3 ~ 8'P od o~ o 3C N CD oc3, ca El rl a o~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 0 o_ o_~f S~~~~~~~~~ CD aD p 0 ~~~~b o -, f~f (P~~~ 0 6TI ~~~~~~~~~~ Cd o 31 er_ o~~~~~~~ ~~~~~~~u o C! cr f' 2;~ ~~~6

194 instead of the 100 MHz center frequency of the experimental amplifier. Although the results using the extended model are not in as close agreement to the measured amplifier performance as one would wish, the extended model does provide a significant improvement relative to the other simulations. Also, experimental measurement errors of the absolute power levels can be appreciable (about 20 percent) with the measurement techniques employed, and stray parameters in the passive tuning elements add to the measurement difficulties in the VHF range. The efficiencies computed with the ideal switch and intrinsic model simulations (Figs. 6. 13a and b) all exceed the efficiencies measured with the experimental amplifier For the extended model, the computed and measured efficiencies (Fig. 6.13d) agree quite well up to a frequency of 110 MHz (T/TO 0 9). Above 110 MHz the experimental efficiency leveled off and then peaked slightly at 165 MHz (T/T 0. 6). Computations with the extended model produced a peak at 165 MHz but did not exhibit the relatively flat efficiency curve between 110 and 165 MHz. As with the output power frequency response, we conclude that the extended model provides marked improvement in computations of the amplifier efficiency response. The variations in the average base and collector currents due to changes in excitation frequency are shown in Figs. 6.1 4 and 6. 15. Similarly to the output power and efficiency comparisons, the extended model is found to provide a better fit to the experimental amplifier than

1.2 -1.2 - 1.0 ^ ic (Computed), 1.0 - c (Computed) |- x x c (Experimetal) 0.8- l (Experimental) 0.8-;9 u Fundamental Output Power. Fundamental Output Power c = Collector Supply Power'c Coll0ector Supply Power 0.6 -- 0.6 0.4 - 0.4 0.2 - 0.2 / Fl P 0 fx 0 I I I I I E 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (a) Scaled Driving Period: T/T o (b) Scaled Driving Period: T/To (a) Ideal switch, fixed capacitance (b) Ideal switch, nonlinear capacitance 1.2 Fundamental Output Power 1.2 Fundamental /cI = Collector Supply Power c ollector Sup Power __ —* 7{c (Computed) 1.0- - c (Computed) l- -x c (Experimental) 0. r/c (Experimental) 080.6 M 0.6 0.6 0.4 - 0.4 0.2 40 0 0 o I I I I I i I 0 0' 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (c) Scaled Driving Period: T/T0 (d) Scaled Driving Period: T/To (c) Intrinsic model (d) Extended model Fig. 6.13. Frequency response of efficiency

196 the intrinsic model. 6.4 Comparisons of Load Resistance Effects The influence of load resistance value on the amplifier output power is illustrated in Fig. 6.16. The lack of model resistance in the ideal switch and intrinsic transistor models results in predictions of increases in output power with load resistances less than 50 ohms. This deficiency is overcome with the extended model, and with the exception of the double mode predictions (Section 5.3.2), its behavior predictions very closely resemble the results obtained with the experimental amplifier (Fig. 6.16d). The dependence of efficiency on load resistance is also found to be well simulated with the extended transistor model (Fig. 6.17d). The base current predictions obtained with the intrinsic transistor model agree with the experimental amplifier for load resistances less than 150 ohms but are unsatisfactory for larger load resistances (Fig. 6.18a). The extended model provides good simulation over the 30 to 550 ohm load resistance range (Fig. 6.18b). Average collector current computations stemming from the intrinsic model display greater fluctuation with load resistance than measured experimentally, and the computed current increases excessively with small load resistances (Fig. 6.19a). The extended model reduces the fluctuations and also provides good simulation for the entire load resistance range (Fig. 6.19b).

10 - 10 e — (Computead) 2 0 - ( —x l x(Experimental)..W 0 -l -o -too 16 N~~~~~~~~~~~~~~~~~~~~~~~~ -10 -20 S. I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~I 1 -30 -! -30 4' -40 -40 I I I I I I I t I (a) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0.(b 0.4 0. 6 0.6 1.0 1.2 1.4 1.6 1.8 20 Scaled Driving Period: T/To Scaled Driving Period: T/T0 (a) Intrinsic model (b) Extended model Fig. 6. 14. Frequency response of base current 33 0 -0'COL (Computed) 30 -3'COL (Iim l) 250- x- - — ~'COL (Experimental). 2 (C1COL' d 250- O 250 -O cJ.) V ~ ~ 0 200 200 150s. 15150 40 r~100K' 3-K-K-KX-K 100 50 3r\50' I I I (a) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 (b) 0.4 0.6 0.6 1.0 1.2 1.4 1.6 1.8 2.0 Scaled Driving Period: T/T0 Scaled Drivn Period: T/TT (a) Intrinsic model (b) Extended model Fig. 6. 15. Frequency response of collector current

600 - PL/ (Computed) 600- PL/4 (Computed) 39- 0 PL (Experimental) "L (Experimentl 500 1' 500-L $ 400 - Nu 400 - X'~~~~~~~~~~~~ o300 I300 0 0 200 i 200 "~100 5%,100;= oi I. 1II I 1 I 0 I..1 I i i 0 20 50 100 200 500 1000 0 20 50 100 200 500 1000 (a) Load Resistance: RL (ohms) (b) Load Resistance: R. (ohms) (a) Ideal switch, fixed capacitance (b) Ideal switch, nonlinear capacitance 60 X- -3 Ps (Experimental) Co L ~~~~~~~~600- -'L/4 (Computed) C 0,C1 500 -P (Experimental) 400~ 400 -X 0, 0, ro K.- xL (Computed, Mode 2) 0300 2 20 0L (Computed, Mode 1) ~ 200 N, 00~~~~~~~~~~~~~~~ 100 0 20 50 100 200 50.0 1000 00 0 20 50 100 200 500 10 (c) Load Resistance: RL (ohms) (d) Load Resistance: RL (ohms) (c) Intrinsic model (d) Extended model Fig. 6.16. Effect of load resistance on output power

0.6- 0.6 0.5 0.5~ O~lC~-~ h _~ ~IC(Exprimend) P il (Experimental)ntal XIX/~~~~~~~~~~~~~~~~~~~~~~~~~~~X 0.3 - C/2/ ~~yutu u OS l/ (Computed) 03'c2(o u0 U 0.2 - (p e 0.4 - U KU 0.1 0.1 0.11 1 I I,,1,t I, I,, I 0 I i,,I IJ (a) 20 50 100 200 500 1000 (b) 20 50 100 200 500 1000 Load Resistance: RL (ohms) Load Resistance: RL (ohms) (a) Ideal switch, fixed capacitance (b) Ideal switch, nonlinear capacitance CD 0.5 0. ( " 0.4 -.-o r (Computed).K U.K'' X- -X 17 (Experimental) N. 3 0.3 (Computed, 0.3 0 ~~~~~Mode 1) 7Cm U u Mode 1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~l (Computed, Mode 2)' 0.2 o 0.2 - 0. 1 0.1 0 0 I I p 0 I I I I, I 20 50 100 200 500 1000 20 50 100 200 500 1000 (C) om) (d) Load Resistance: RL (ohms)Load Resistance: R (ohms) (c) Intrinsic model (d) Extended model Fig. 6. 17. Effect of load resistance on efficiency

10 - 1B (Computed) to I0 (Computed) 0- -x~ I' (Experimental) 0 -10 -10 -30 0 -30-40 -40 11 1. (a) 20 50 100 200 500 1000 (b) 20 50 100 200 500 1000 Load Resistance: RL (ohms) Load Resistance: R (ohms) (a) Intrinsic model (b) Extended model Fig. 6. 1 Effect of load resistance on base current G. (Computed) 0 250 - COL 250 0 -K r- coL (Experimental)' 200'1 200 o 0 UO 1CO ro(Computed, Mode 2) 150 150 0 100 K~-K.-..K..... -K- ~ -~ 1COL (Experimental) 7 r, 100 XYI-X~Xs, ~~I-~,~~ -1I~1~ ~'.CX~C ~XI5 100 - -K 0 L 50 o 50'COL (Computed Mode1) > 0U ~~~~~~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~~~~0 200 500 100 200 500 1000 200 500 100 200 500 1000 (a) (b) LoadResistance: RL (ohms) Load Resistance: RL (ohms) (c) Intrinsic model (d) Extended model Fig. 6.19. Effect of load resistance on collector current

201 6. 5 Comparisons of Supply Voltage Effects When the transistor is modelled as an ideal switch with fixed output capacitance, the collector supply voltage has no effect on the computed efficiency, and the output power increases as Vcc2 (Section 3.2.5). If the output capacitance is given a voltage dependency such as in Fig. 6.4, the output power no longer varies directly with Vcc2 (Section 3.3). When modeling the 100 MHz amplifier as an ideal switch with nonlinear capacitance, the output power variations of Figs. 6.20a and b are predicted. For supply voltages less than 5 volts, the output power increase at a greater rate than V 2. For supply voltages greater than 20 volts, the output power increases more slowly than Vc2; and in the range 5 < V < 20V a dependency proportional to cc cc V 2 is observed (Fig. 6.20a). In Figs. 6.20b, c, and d, the comcc puted dependencies of output power on supply voltage are compared to experimentally measured amplifier performance. Computations involving the intrinsic model predicted output powers greater than observed experimentally as well as predicting output power proportional to Vcc up to 24 volts. For supply voltages greater than 24 cc volts, the output power computed with the intrinsic model is relatively constant corresponding to the limiting of output power by input signal power instead of supply voltage (Section 4.4.1). The extended model simulation predicts the experimentally observed results with reasonable accuracy over the large supply

10. 000 Pot~ V cc 1.000 F_-1 - R o0. 225.2 L 0. 0073 CF. 0. 17 c~~vcc. 1.005 i 0.100 IiQVCC ho0. V 2 a 500 04 100 V.-0.5 0. ~~~~~~Z p.. / t ~ y 0. 474 * 400 ALIM =0. 0625 L/A (Computed) ~~~ / ~~~~T =l.0 300T = 0. 404 L (Experimental).~200 X.'. 6 C 100 III__ AIIIaI_ 0 4 8 12 16 20 24 28 32 36 1 10o. - 100 Collector Supply Voltage: Vc (Volts) Collector Supply Voltage: Vc (Volts) (a) Ideal switch, nonlinear capacitance, log-log scale (b) Ideal switch, nonlinear capacitance soo5 L/4 (Computed) 500 I / k~~~~~~~~~~~~~~~~~0 400 - 400 o 0 0. 10 (Computed) 300 - PL (Experimental) 300 L/10 p (Computed) 0 0~~~~~~~ 0 a 200 200 200/ L (Experimental) 100 100 0 1 0 1 _ I I I 0 4 8 12 16 20 24 28 32 36 0 4 8 12 16 20 24 28 32 36 Collector Supply Voltage: Vcc (Volts) Collector Supply Voltage: V (Volts) (c) Instrinsic model (d Extended model Fig. 6. 20. Effect of supply voltage on output power

203 voltage range of 2 to 28 volts. The fact that the computed output power did not reduce for supply voltages above 12 volts as observed with the experimental amplifier, may be attributed to the fact that the computation was not performed at the frequency for maximum output power with Vcc = 10 volts. That is, the experimental amplifier was tuned for maximum output power with a signal frequency of 100 MHz and a supply voltage of 10 volts. Supply voltages greater than 10 volts apparently detuned the experimental amplifier slightly causing the observed decrease in output power. The simulation circuit was found to be tuned to 125 MHz for maximum power (Fig. 6.12d), and thus the detuning effect is not as noticeable when operating the simulation circuit at 100 MHz. The dependencies of collector efficiency on supply voltage are illustrated in Fig. 6.21. The efficiencies predicted with the ideal switch and the intrinsic transistor model are twice as large as the measured efficiencies. Due to coupling of input circuit to output circuit through the transistor, it is possible to develop load power with zero collector supply voltage. Thus under conditions of small collector supply voltage it is possible for the efficiency PL(1) PV cc to exceed unity as predicted by the analysis with the intrinsic transistor model in Fig. 6.21b.

I~~ -\ q~~-vc r (Computed) ~~~1. ~~0 F 1 ~~~0 F \ -X 3 c (Experimental) 0.8 0.8 1. 0 8 0.6. o 0 3 o.4 - ~ 0.4 - O 2 4- ~x~..X c (Experimenital) 0.2) __ __ __ _ __ __ __ _ __ ___O.2 _ __ (Computed)_ o. l I I'' I' I I', 0 1 6 0 24 2 3 60 4 8 12 16 20 24 28 32 36 Coector Supply Voltage: V (Volts) Collector Supply Voltage: Vcc (vo)Volts) ~0~( ended model S.2 ~c (Experiment (xe nal) 0 4 8 12 16 20 24 28 32 36 283236 CoCoector Supply Voltage: Vcc (Volts) (c) Extended model

205 As with the load resistance variations, the base current variations with supply voltage (Fig. 6.22) are slight and are fairly well simulated by the intrinsic model for supply voltages in the range of 12 to 24 volts. The extended model offers improved simulation over the entire range of 2 to 28 volts. With the intrinsic model the calculated collector current increases linearly for Vcc up to 28 volts, but with the extended model and the experimental amplifier, the collector current remains relatively constant for Vcc greater than 10 volts (Fig. 6.23). 6.6 Computed Effects of Signal Amplitude The effect of input signal amplitude on base and collector current, output power, and efficiency was not measured with the experimental amplifier. This behavior was computed with the intrinsic and extended transistor model simulations and the results are presented in Figs. 6.24 through 6.26 for comparison. As illustrated, the general behaviors are the same for both simulations. 6.7 Conclusions Modeling a VHF power amplifier with the ideal switch, intrinsic, and extended transistor representations has demonstrated the necessity of the more complex extended model for achieving accurate simulations over wide ranges of operating conditions. A major deficiency of the ideal switch and intrinsic transistor models is their

* l 1B (Computed) 25 _I1 *- (Computed) (Cmp ) 25 - - (ECpomeutal) 25 ---- IB (Ectperimental) x — — x IB (Experimental) ~~~~~~~~-25-n -- - 5- - - - - & -75 _ -7_ too -100,I, I,,,, I, I., 1,1,, I I,I I, I,,.' 0 4 8 12 16 20 24 28 32 36 0 4 8 12 16.20 24 3 (a) Collector Supply Voltage: Vec (Volts) (b) Collector Supply Voltage: Vc (Volts) (a) Intrinsic model (b) Extended model Fig. 6.22. Effect of supply voltage on base current 0 ICOL (Computed) 1COL (Computed) 400 -f " U )i~ S — ICOL (Experimental) _ 400- ICOL (Experimental) 30 300300 200-0 2o00 5c 200 0 1 100 r~ - o 0 4 8 12 16 20 24 28 32 36 0 4 8 12 16 20 24 28 32 36 (a) Collector Supply Voltage: Vcc (Volts) (b) Collector Supply Voltage: Vcc t(olts) (a) Intrinsic model (b) Extended model Fig. 6. 23. Effect of supply voltage on collector current

1200 -20 1000 oo &300' 200 20C - ~~~~~~~~~~~~~~~~~~~~~~~~~~too 06 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00 2 4 6 8 10 12 14 16 18 20 2 4 6 6 10 12 14 16 18 20 (0) Driving Source Amplitude: VSA (Volts) Driving Source Amplitude, VM (VOlS) (a) Intrinsic model (b) Extended model Fig. 6. 24. Effect of source amplitude on output power 1.0 1.0 0. 8 0. O 0 S0.6 0.4 -.4 0. 20.2 0 0 2 4 6 8 10 12 14 16 18 20 2 4 6 0 to 1 14 Cu) DDriving Source Amplitude: VSA (Volts) 18) Driving Source Amplitude: VSA (Volts) (a) Intrinsic model (b) Extended model Fig. 6.25. Effect of source amplitude on collector efficiency

208 0 —- O Average Collector Current: ICOL(mA) O -~ Average Base Current: IB(mA) -5 200 -10 150 - -15 100 50 02 4 6 8 10 12 14 16 18 20 (a) Driving Source Amplitude: VSA (Volts) (a) Intrinsic model co c;..o Average Collector Current: ICOL (mA) 0,. - Average Base Current: IB (mA) 200 - -10 150I -20 100 - -30 50 -40 4 6 8 10 12 14 16 18 20 (b) Driving Source Amplitude: VSA (Volts) (b) Extended model Fig. 6.26. Effect of source amplitude on base and collector current

209 failure to account for resistive potential drops that occur when a transistor is in saturation for short time durations (Section 2. 5.3. 5). Due to insufficient output resistance, the ideal switch and intrinsic transistor simulations predict output powers and efficiencies that are larger than those measured with the corresponding experimental amplifier. In lower frequency simulations (Sections 3.5 and 4.3) and in applications with small peak collector currents, the need for a collector saturation resistance is not so strong. The base current simulation afforded by the intrinsic transistor model is adequate for many engineering applications. However, for large load resistances, the base currents predicted with the intrinsic model do not agree with those measured experimentally (Fig. 6.18a). It has also been noted (Sections 4.4.1 and 4.6) that the internal gain of the intrinsic transistor model is unrealistically large, predicting output circuit saturation even with large supply voltages. This difficulty cannot be corrected by adding collector resistance alone. The emitter circuit elements of the extended model, LEE and REE, do reduce the transistor gain, and their inclusion in the transistor model improves the simulations of supply voltage effects. Thus we may conclude that the effort required to determine values for the additional parameters of the extended transistor model is necessary to insure proper simulation of VHF power amplifiers.

CHAPTER 7 REVIEW, SUGGESTIONS, AND CONCLUSIONS 7.1 Introduction We have used several transistor models to simulate class C/D amplifiers at low and high frequencies over wide ranges of operating conditions. The modeling procedures introduced in Chapter 2 were successfully coupled with numerical analysis techniques to investigate the essential characteristics of the transistor models as well as the characteristics of tuned power amplifiers. Effects of nonlinear capacities, avalanche breakdown, saturation resistances, and emitter inductance require complex transistor models for proper characterization. Digital computations are required for analyses when such complexities are included in amplifier simulations. The results of computational studies of several amplifiers with the various models are summarized in this chapter. The importance of the elements of the extended transistor model were investigated in Chapter 6, and the results are reviewed in this chapter. The costs of computation with each of the models are also compared. Improvements are suggested for future use of the models, and the conclusions of the study are then summarized. 210

7.2 Summary of Models 7.2.1 Ideal Switch Models. The ideal switch models of Chapter 3 were found to be useful for studying class D amplifiers at low frequencies. They provided the basic transistor output characteristics in studies relating output power and efficiency to frequency (Section 3. 2.1), load resistance (Section 3. 2.2), conduction angle (Section 3. 2. 3), supply voltage (Section 3. 2.5), tuning configuration (Section 3.4), nonlinear output capacitance (Section 3. 3), and harmonic tuning (Section 3.5). These investigations have allowed us to examine many fundamental characteristics of tuned power amplifiers. We have observed that circuit conditions for obtaining maximum outout power are generally different than those for obtaining maximum conversion efficiency (Section 3. 2. 3). In some circumstances where output power is limited by transistor power dissipation or breakdown voltage, it is possible to obtain greater output power by tuning to a condition for maximum efficiency rather than direct tuning for maximum output power (Section 3.2.3). The calculated effects of making the output capacitance of the ideal switch model nonlinear, with a moderate output circuit Q (-'10), were not as pronounced as originally suspected. Even with 5: 1 capacitance variations, over the operating period, T, the output waveforms were found to be very similar to those calculated for the fixed capacitance case. The major differences between the results

212 with fixed and nonlinear output capacitances were that with the nonlinear capacitance, the signal amplitudes were slightly less and the harmonic content was slightly greater. With fixed output capacitance the ideal switch models yield output power computations predicting power that is proportional to the square of the supply voltage. However, with the nonlinear output capacitance simulations, the output power dependency does not adhere to the square law relationship (Sections 3.3 and 6.5). This variation from square law is due to the voltage dependent tuning effect of the nonlinear output capacitance. The configurations of the input and output tuning circuits of a large signal transistor amplifier influence the way in which the harmonic voltage and current components interact. If equivalent input and output admittances for the transistor are determined by laboratory measurements on an operating amplifier (Section 1. 2), the admittance values obtained will be dependent on the tuning circuit utilized. A brief look at the effect of output tuning circuit on amplifier operating characteristics such as optimum load resistance, harmonic content, and bandwidth was conducted with the ideal switch model. For moderate Q output circuits (5 < Q < 20), the change from parallel RLC tuning to a series RL load tuning resulted in slight increases in output power, efficiency, and bandwidth with an attendant reduction in harmonic content of the load power.

213 Another modification to the parallel RLC output tuning circuit that was investigates was the addition of a series LC branch that could be adjusted to short-circuit harmonic voltage components. With both the computations and an equivalent low frequency (500 kHz) laboratory experiment, the harmonic tuning network was found to increase output power at some frequencies but greatly increased the frequency sensitivity of the amplifier. It was also determined that the observed increases in output power could not be attributed to the harmonic pumping of the nonlinear output capacitance; similar increases in output power were calculated and measured when the capacitance was constant. In general, the ideal switch simulations are adequate for class D amplifiers in which dynamic effects and saturation impedances of the transistor are negligible. Neither of these effects should be neglected in typical VHF power amplifiers, and complete characterization of such amplifiers requires more detailed transistor models. 7. 2.2 Intrinsic Voltage Controlled Transistor Model. The use of an intrinsic voltage controlled transistor model allowed both input and output properties of tuned power amplifiers to be investigated (Chapter 4). Initial studies conducted with this model illustrated the need for altering the numerical computation of device terminal currents depending on the operating region of the device (Section 4.2. 1). It was found to be advantageous to determine the currents from external

214 circuit constraints when the transistor is in saturation and from the transistor equations when the transistor is cutoff. In the active region one should determine the base current from the external circuit and the collector current from the device equations. For the inverse region, both base and collector currents should again be determined from the external circuit elements. Preliminary computations utilizing the intrinsic transistor model showed an unexpected double-peaked collector current waveshape. An experimental amplifier was constructed for operation at 5 kHz and provided verification of the predicted waveshape. This experiment confirmed that this model was satisfactory for low frequency amplifiers* with output circuitry of moderate to high Q (Q > 5). The intrinsic voltage controlled model of a 2N3866 transistor was used to simulate a 100 MHz amplifier without input tuning. At the nominal operating condition, the computed gain was approximately 30 percent greater than that measured experimentally, and the computed efficiency exceeded the experimental efficiency by 8 percent. The frequency response predictions were similar in shape to those By "low frequency amplifier" we imply that the time constants associated with the transistor are much smaller than those associated with the passive tuning circuitry so that the dynamic response is essentially determined by the passive tuning elements. For convenience, we may use f < fT/10 as a definition of "low frequency" where f is the operating frequency of the amplifier and fT is the current- gain- bandwidth product of the transistor.

215 measured; the computed frequency for nlaximunl power was 8 percent lower than that measured, and the computed frequency for maximum efficiency was 40 percent higher than measured. The computed and measured effects of supply voltage were in agreement for voltages less than 15 volts. For higher voltages the experimental amplifier was not driven into saturation, but the simulation erroneously predicted that saturation continued over the computational supply voltage range of 2 to 24 volts. Over the range of load resistances considered (20 - 550 iQ), the output power behavior was predicted correctly only for resistances greater than 100S2. For the smaller resistances the model did not properly simulate the device losses. The general conclusion reached with the intrinsic model studies was that the model is suitable for simulation of low and high frequency tuned power amplifiers (f < fT/4) in which computational accuracies of 30 percent are acceptable. In addition, the accuracy can be severely degraded (see Fig. 4.9) if the output circuit Q is low (Q < 2) or if the range of external circuit parameters is large. -The model should be modified if such conditions are not satisfied. 7.2.3 Extended Voltage Controlled Transistor Model. An extended voltage controlled transistor model was used in Chapter 5 to investigate its ability to provide improved characterization of VHF power amplifiers. It has been demonstrated that the extended model is capable of simulating a high frequency (50 - 200 MHz) class C

216 amplifier adequately for wide ranges of operating conditions and was found to be superior to the other models for this simulation (Chapter 6). In addition to using the extended model to predict the behavior of a VHF amplifier, it was used to study the sensitivities of several of the amplifier performance characteristics (output power, efficiency, base current, and collector current) to changes in external circuit and model parameters (Table 5.1). We can use the information from this study to estimate the importance of each model parameter and the accuracy to which each parameter should be determined for future simulations. For example, averaging the magnitudes of the sensitivities of the output power, efficiency, average base current, and average collector current given in Table 5.1 leads to a simplified tabulation (Table 7.1). In Table 7.1 the parameters are listed in order of decreasing sensitivity and are arbitrarily separated into four groups for comparison. We observe that the first group is largely composed of the external circuit parameters. Of the transistor parameters in that group (aF' RBB' VA' X), the base resistance, RBB' should be considered the most significant since caF is actually determined from a OF measurement and OF is in a less sensitive Group 4. Values for VA and X can be determined with reasonable precision by simple static measurements leaving RBB as the most amplifier representation (RBB = 22.45 a ) was established in Section

217 Averaged Sensitivity Parameter Sensitivity Group U F 3.85 VSA 2.42 T 1.66 RBB 1.52 VSDC 1.44 VA 1.43 1 RS 0.968 CL 0.949 LL 0.831 0.792 VCC 0.498 RL 0.422 LS 0.382 2 RCC 0.342 CJE 0.314 TF 0.309 CJC 0.190:AR 0.186 REE 0.179'YE 0.173 0.166 QFS 0.165 3 QRS 0.161 VZE 0.145 LEE 0.144 Yc' 0.142 CS 0.131 CCE 0.107 CFC 0.103 CCB 0. 0942 ACLIM 0.0874 AELIM 0.0795 NA 0. 0779 4 CFE 0.0776 VZC 0.0568 R ~0.0508 OF ~ ~ 0.0462 CBE 0.0278 Table 7.1. Averaged sensitivities

218 2.5.3.7 but was estimated very closely (RBB = 20. 0 ) in Section 2.5.3.1. Assuming that 22.45 Q is the better value for RBB, the 20.0 ~ estimate is 10.9 percent too low; and from Table 7.1 we find* that utilization of the estimated value could lead to "average" computational errors of 16.7 percent. Thus, determination of R value BB requires close attention for accurate simulations. The elements in Group 2 are equally split between external circuit and transistor parameters. The amplifier sensitivities to these transistor parameters (RCc, CJE, TF) imply that amplifier simulation accuracies of 5 percent can be provided by determining the Group 2 element values to a 15 percent accuracy. The measurement techniques suggested for evaluating RCC (Section 2.5.3.7), CJE (Section 2.5.1. 4), and 7F (Section 2.3.2) are satisfactory for providing this level of accuracy. The relatively small sensitivities to the parameters in Groups 3 and 4 suggest that these values can be estimated from a knowledge of device size and geometry without the necessity of laboratory measurements. Consideration of the intended transistor application is of course required to assess the true importance of each model parameter. For example, in many applications, input drive and collector tuning conditions will preclude the possibility of emitter-base avalanche. In such *From Section 5.4, %r error in f = sf x % error in p

219 applications, the computed performance is clearly insensitive to the avalanche parameters, and those elements need not be included in the model. The low sensitivity to the depletion capacitance parameters with both the extended model studies and the ideal switch studies with output Q's on the order of 10 suggests that their nonlinear behavior need not be simulated closely and that they may be replaced with fixed capacities representing the total depletion capacitance occurring at the average junction potential. 7. 3 Computational Costs The decision to make digital simulations of a power amplifier is influenced by the availability and computational costs of suitable transistor models. Our experience with the models investigated suggests that a large model such as the extended voltage controlled model is capable of predicting amplifier behavior more accurately than the smaller models, although the smaller models are satisfactory in many situations. Accuracy considerations alone may not be enough for deciding which model to choose for an analysis. Analysis with the larger models is computationally more expensive than with the smaller models. Also, for example, the difficulty of determining the extrinsic elements values of the extended transistor model makes this model undesirable for low frequency, high Q applications in which the extrinsic elements will have little effect on the predicted amplifier behavior.

220 The computational analysis technique of this study (Section 3.2, Appendix C) employs numerical iteration to establish the limit cycles of the various amplifier circuits. The number of iterations required is dependent on the proximity of the estimated initial conditions to the correct limit cycle values, the time constants of the passive circuits, and the operating conditions; however for the particular VHF amplifier simulated, there were no observable differences in the convergence rates of the various simulations. Figures 7.1 and 7.2 illustrate convergence behaviors that are typical of all the simulations with the various models. These figures show the number of iterations required in the analysis with the extended model as the driving period and load resistance were varied in discrete steps. Interpretation of the plots is explained by the following example: In moving from a driving period of 1.4 to 1.5 (Fig. 7.1), the final limit cycle conditions for the T = 1.4 solution were used as the estimate for the initial conditions in the T 1.5 analysis. With this estimate, 5 iterations were required to achieve convergence* to the *The convergence criteria for this analysis was defined as: 7 (XF - xI2 < 0.007 j=1 ki where x = The value of the jth state variable at the beginning ] of the period. XF = The value of the jth state variable at the end of the j period.

221 15O 10 0" ~,5 -- 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Source Driving Period: T (sec) Fig. 7.1. Convergence behavior with changing excitation period 0 15 DS O... 0 I I....I... I 20 40 100 200 500 Load Resistance: RL (ohms) Fig. 7.2. Convergence behavior with changing resistance

222 T = 1. 5 limit cycle. It is not practical to compare total computation times of the different simulations because the total number of iterations vary in the unpredictable manner illustrated in Figs. 7.1 and 7.2. From the analyses performed, all of the simulations exhibited similar nondeterministic convergence characteristics. However, as an overall average, each of the simulations was found to require about the same number of iterations for convergence. Thus, in comparing computational costs, it is reasonable to compare the time per iteration of each simulation instead of the total times. The computation time required for each iteration is dependent on the operating conditions of the amplifier, T but over the ranges of this study (e.g., 20 < R < 550, 2< T < L 2 2 TO 2 < VCC < 30), the machine time required per iteration can be estimated for each model as: Transistor Model CPU Time, Cost/Iteration* Ideal Switch, Fixed Capacitance 0.5 Sec, 4 Ideal Switch, Nonlinear Capacitance 0.5 Sec, 4~ Intrinsic Voltage Controlled 2.0 - 3. 0 Sec, 17 ~- 25 Extended Voltage Controlled 4. 0 - 5.0 Sec, 33 - 42 These figures are based on speed and present costs of the IBM 360/67 system used in this study at The University of Michigan.

223 The ideal switch representations were described by a second order system of differential equations; whereas the intrinsic and extended model representations required third and seventh order systems respectively. The computation time appears to be roughly proportional to the order of the system of equations with some dependence on the complexity of the differential equations. We can estimate that an analysis with the extended transistor model will be about ten times as expensive as a corresponding analysis with the ideal switch representations and twice as expensive as with the intrinsic model. Thus it is desirable to use the smaller models whenever such models provide sufficient accuracy. The decision of model size to be selected for adequate accuracy is often difficult. If several models are available, an effective way to check accuracy is to compare computed results with all the models using operating conditions at the extremes of the desired ranges of investigation. Given that several of the models predict the same amplifier behavior within desired tolerance limits, then the appropriate model for the investigation is taken as the simplest of those predicting the same behavior. Table 7.2 is provided as a guide to the choice of transistor model, however, the circuit designer/analyst is still faced with the task of selecting the appropriate model for each application.

224 Type Circuit To Be Analyzed Suggested Transistor Model Output Tuning and Ideal Switch Matching Networks Q > 5, f < fT/10 Class C Amplifier Intrinsic Model f < fT/4 Q> 2 Accuracy - 30% l Class C Amplifier Extended Model With Fixed f < f /4 Depletion Capacities and - T/ Without Case Capacities.5< Q < 20 Accuracy - 20%0/c Class C Amplifier Extended Model f < fT/2.5< Q < 20 Accuracy - 10% Table 7.2. Guide to model selection 7 4 Improvement to Ideal Switch Models The ideal switch models of transistor output characteristics do not provide for device power loss during saturation. As a result, output power and efficiency predicted by computations utilizing the ideal switch models were larger than those observed with experimental

225 amplifiers. The departure of computed results from experimental results was particularly evident in situations yielding high switch currents. In these situations the addition of a series output resistance to the switch model would be helpful to account for device losses during saturation. Although not tried in this study, such an addition does not increase the order of the corresponding system of equations and thus should improve the modeling capability with only a slight increase in computational effort. 7.5 Improvements to Intrinsic Model As with the ideal switch models, the addition of a series collector resistance to the intrinsic voltage controlled transistor model would improve the simulations of the saturation characteristics. This collector resistance should be added to amplifier simulations in which the transistor is expected to be driven into saturation during portions of the operating cycle. 7.6 Improvements to Extended Model The extended voltage controlled transistor model was capable of simulating the behavior of a VHF amplifier with reasonable accuracy (Chapter 5). Of course, this model could be enlarged to include higher order effects for improved accuracy. For example, a one-lump approximation to the diffusion equation has been used as the basis for the transistor models of this study. Higher order approximations, as

226 suggested in Ref. K1, could be utilized. The parameters of such multi-lump models can be estimated by physical principals with a knowledge of device geometry, doping profiles, and construction techniques. Such information is seldom available and techniques for extracting the model parameters from experimental measurements are desirable. The extended voltage controlled model can be improved without much additional effort. A base lead inductance value was established in Section 2.5.4, and this element can easily be added to the model. The nonlinear depletion capacitances are distributed along the junctions. Instead of representing these capacities as single elements across each junction, they can be conveniently split into two capacities —one across the active junction and one outside the extrinsic base resistance (Fig. 7.3). The ratio of the two portions of the depletion capacities is suggested by device geometry. A photomicrograph of a 2N3866 transistor is illustrated in Fig. 7.4a. Recalling the high frequency current distribution in the 2N3866 (Fig. 2.26b), we can associate a portion of the depletion capacitance with the active part of a junction and the remainder with an inactive part. For a 2N3866, the ratio of the inactive to active areas of the collector-base junction is approximately the same as the ratio of the base area to the emitter areta; as viewed frotm the sulface of the planar device (Fig. 7.4b). Fol a 2N3866 we estimate

C'COL Rcc C, CB CDEP c Inactive CCDEP CDIFF'R F F Active ig RBR B' fF'B BBF C A EDEP kC Inactive EDEP EDIFF A R CE Active A CEB REE LEE if E Fig. 7.3. Model with split of depletion capacities

228 Base Areas Emitter Areas Visible at Surface n (a) Collector Base ea AE [ Emitter B1 C Inactive CEDE, Active EDEP, EDEP Inactive / Active |.. _... =1 C CDEP AB Inactive CCDEP AE CDEP CCDEP Active Inactive Active CEDEP Inactive << 1 EDEP (b) Active Fig. 7.4. (a) Photomicrograph of 2N3866 before metallization (from Ref. C4) (b) Example for estimating capacitance split by surface areas of planar device

229 C AB CDEP B INAC TIVE C A 3-4 CCDE P E ACTIVE and we can split the collector depletion capacitance (Section 2.5. 1) accordingly. For the emitter-base junction, the area outside the active portion depends on the diffusion depth of the emitter and is much smaller than the active area. Therefore, EDEP INACTIVE << EDEP ACTIVE and the emitter depletion capacitance need not be separated into two parts. A capacity from collector to emitter may also be added to the model. This capacitance is expected to be independent of the junction potentials. Its value can be determined from small- signal, lowfrequency measurements in a manner analogous to the method used for determining the three terminal inductances (Section 2.5. 4). The dependence of caF and ~'R on junction potentials and terminal current is measured routinely (Section 2.3. ). Instead of approximating -aF and ~R as constants, their behaviors may be representedby polynomial expressions determined from the

230 experimental data or may be stored in tabular form for the numerical calculations. Another alternative is to employ an expandable representation as suggested by Ref. G5. Many extensions to the electrical model of the transistor in its package are possible (Ref. H4). The necessity of each model element depends on operating frequency, signal amplitudes, and methods of operation. 7.7 Amplifier and Device Optimization The ability to analyze tuned power amplifiers numerically provides a potential for applying numerical optimization methods to improve operating characteristics. Constrained optimization of external circuit elements and bias conditions is a desirable extension of the analysis methods developed in this study. We can also consider optimizing device characteristics. Since many device parameters are interrelated, transistor design involves many compromises in these parameters. For those device relationships that can be approximated mathematically, an optimum device can be designed for desired power levels and frequency ranges. Such optimizations are indeed desirable; however, the actual optimization technique requires careful consideration. Suppose, for example, that the numerical optimization procedure (e. g. Fletcher-Powell, Ref. Fl) requires gradient computations in order to minimize some chosen amplifier performance function. The number of directional components of the gradient is equal to

231 the number of parameters to be adjusted. Each gradient component can be determined by independent perturbation of each of the parameters. For each perturbation one or more analysis iterations will be required to establish the perturbed limit cycle. After the gradient is established, the performance function must be repeatedly evaluated as the parameters are varied to achieve a minimum. A total computation time for such a procedure can be estimated roughly as: Number Time Number 1 SmFor of One x ]literations PUTime > Optimizer Amplifier Establish LIterations Analysis Limit \ Limit / Iteration Cycle Number Number of.,r of Function Parameters Paaees + Evaluations Gradient During Gradient Parameter C omponents Variation [20] x [(5 sec x (2) 3000sec 5 in $250.00 3000 sec = 50 mm id $250.00

232 Such computation time requirements are large, and alternative techniques are desirable. The ability to determine network sensitivities to all adjustable parameters with only two analyses, one for the original network and one for an adjoint network, plus a back substitution may provide an alternative optimization method (Ref. D1). However, such methods become quite complex for nonlinear dynamic circuits and may not be practical for this application. In any case, numerical optimization of tuned power amplifiers is desirable, but implementation of optimization methods will require a large effort. 7.8 Conclusions This study of tuned power amplifiers required the development of suitable transistor models and experimental techniques for determining the model parameters. These models have been successfully coupled with numerical analysis methods to study many characteristics of tuned power amplifiers. The use of digital computations has removed the need for many assumptions (low frequency, high Q, sinusoidal potentials, no saturation, no extrinsic model parameters, zero or constant depletion capacitance, no avalanche breakdown, etc.) which have limited previous analyses. These assumptions are generally not valid for VHF power amplifiers. Although the costs of the modeling process and the digital computations can be appreciable, they are necessary for typical problems involving design, analysis, and optimization of VHF power amplifiers.

APPENDIX A EXPERIMENTAL MEASUREMENT OF CHARGE PARAMETERS The method used for determining the forward and reverse charge time constants of a transistor, T7F and TR, was outlined in Section 2.3.2. The technique for determining TF requires measurement of transient base and collector currents resulting from an emitter excitation. The base current is measured by monitoring the potential developed across a small resistor, Rb, inserted in the base circuit (Fig. A. 1). For accurate measurements the collector-base potential must be held relatively constant; therefore, Rb should be small enough for the developed base potential to remain much less than the collector potential. For collector potentials on the order of a few volts, the base potential must be limited to a few millivolts. In the experimental procedure used, Rb is provided by the 50 input impedance of a sampling oscilloscope. The capabilities of the sampling scope provide the key to the charge measurement. The scope is required to monitor base potentials of a few millivolts in amplitude and a few nanoseconds in duration (Fig. A. 2); such performance is well within the capabilities of most sampling scopes. However, the greatest advantage in using a sampling oscilloscope to monitor the base voltage is its ability to provide an output voltage that is a time and amplitude scaled replica of the base voltage. Because of the 233

Pulse iE CCOL Generator -LTI i~~~i~ YV~ to B ~~~~cc t C lear C Sampling R II~ + Scope+ e mplitude e B & Time f Scaling' Fig. A -I Basic circuit for charge storage measurement

235 Emitter Current - " 20- 50 ns Collector Current \ mA'COL Base Current O.1 mA B 5 ns -_ 5 mv Base Voltage eB 0 1 Real Time Scope Horizontal Sweep 1 ms 2v Sampling Scope Output - __ -S Integrator Output e0 Kt0 Ktl Scaled Time t2 Fig. A. 2. Typical waveshapes for charge storage measurement

236 sampling nature of the scope, the reconstructed waveform displayed and provided as an output assumes the time period of the horizontal sweep and can be independent of the time period of the original signal. The amplitude of the displayed signal is dependent on the gain setting of the vertical amplifier of the scope. The oscilloscope delay and triggering circuits (Fig. A.3) can be adjusted such that the scope will display only the negative transient of the base potential (Fig. A. 2). This waveform is thus available as an output signal from the oscilloscope. An integral of this negative transient can then be performed and used to determine the amount of stored base charge: E.g., referring to Figs. A. 1 and A. 2, G = gain of vertical channel of oscilloscope amplitude of scope output signal, leSI amplitude of scope input signal, leBI 1.0 (volt/cm) vertical sensitivity (volt/cm) (for the scope used) K = time scaling factor t2- kt0 tl- t Thus, es(Kt) = GeB(t)

2000 Pf Te4 200 V HP 215A PuAser CurrentBan Transformer Trig 40 ns. Pulse r 1;00 out I MHz nut 50 Op Variable Atgtenuator 470g 1' _________ 6 O.02 Pf 02aVc b +55v +12v -6v COLT A B Channel 0 5015 A RG U -- Input output rgnu Ext Sweep Sweep Signal Sweep 0-Delay & Input output Trigger 15' RG 58U Tek 561 A Scope Sweep Generation 3S76 Sampling Dual Trace Pulse Integration Circuitry 3T77 Sampling Sweep Fig. A. 3. System for TF charge storage measurements

238 and the stored charge, QB, can be related to the output of the stored integrator, e0, as follows; Let tO = 0 tl QB J iB(t) dt stored t=O t 1 eB(t) GfRb t- Sdt t=O Rb t 1 1. es(Kt) dt G Rb t=0 Let T = Kt Kt QB G R eS(T) K stored b T=0 t2 - KGRb ft2 S Now with e (0) setO t 1-2 e=(t2) RC e S() dT Hence oQB= KGRb e0(t2) stored b

239 The control and measurement circuitry used for the charge measurements is shown in Figs. A.3, A. 4, A. 5 and A. 6. For the 2N3866 transistor, a much wider excitation pulse is required for the TR measurement than for the TF measurement. For that reason, the pulse driver and delay circuits of Figs. A. 5 and A. 6 differ slightly from those of the TF measurement (Fig. A.4). The actual details are not as important as might be implied by the circuits given. Many circuit variations and measurement automation are possible. The circuits shown were largely determined by the performance characteristics of the available measurement equipment and components.

+55 +12 +12 +12 +55v 4.7K I 10K /'jSW ~, VStop 100K' 22K +12 10K TOff 15K 6. O5.K TOff C~tr IOK 47K QI 5a 100K ~ ~ 47 47 v~~~Stop 1 IN2928A -6 -6.2 -6 Hoffman 330 + 55 47K +12 Q3 10K Start 100. -6 20 Pf Q6 2N43 60 R I 02 0 50KI Input 20 Pf N751 75 PfN 9! - SP'72 7 L1 2;Jq64 I 8 output 47K +12o 47K lO 3 4 ~ 1 25 Pf 6a WV Balance +12 -6 1 75 K151 510 Pf f..f.. ~ ~~~~~~~~~~+12 -6 Fig. A 4. Sweep generation and pulse integration circuitry for charge storage measur(mn

-2 -~30v GR 1217-A Pulser Sync 2 7 lis Pulse Pulse out 20 ktHz out 0 ~~~Driver Circuit 56 r% Ti T3.5 iCOL +55 +12 -6 Sync +12 Delay Circuit i -6 A B 03 Av =P A Ort s e u q mesmn HP 215A Ext + 100 ns Ext Sweep Trig Input ~~~Sweep Sig Sw~eep Output Hi Z Trigge La Tek 561, 3S76., 3T77 Swfleep Generation and Pulse Integration Krohn- HiteCictr 330 M Filter 01 HNz 20 k~z 3.5 Av Fig. A. 5. System for TR charge storage measurement

_n 272 Output to Input' - -Transistor From.02 Being Measured GR Pulse Output 2.2K 22K (-2)- (-30v) Sets Pulse Amplitude +12 +12 +12v +12 9 120K 10K 250K'4.7K 120 1 OK.006,4. 7K JOutput To Ext Trigger 47K 1 0OK 1000 Pf -6 220K 76 Input From GR Sync Output 1 OK Fig. A. 6. Pulse driver and sync delay circuits used for TR charge storage measurement

APPENDIX B TRANSFORMATION FROM CHARGE CONTROL TO VOLTAGE CONTROL The voltage controlled intrinsic transistor model (Fig. 2.12) is mathematically identical to the charge controlled model (Fig. 2.1). If we take the differential equation description of the charge control model (Eqs. 2.1 - 2.2) qF ~ qR ~ B FF + + TRR + CEDEP VE'B' CCDEP vC'B' qF R R ~i + CC - - +C COL F TR qR TRR CDEP C'B' F qR ~ TF ""-TR - qR + CCDEP vC'B' and remove the charge variables by utilizing the nonlinear charge constraints (Eqs. 2.3- 2.4) qF = QFS (e EB - ) qR = QRS(eX vC'B' 1) where 243

244 ~F 7F IEBO QFS 1- YFaR QO RTC BO QRS 1- C FRF we get a system of voltage controlled equations. QFS (- ca) - vEtB \ QRS(1- aR) / C B' B TFF (Xvl R R - QFS(e F )VE'B' - CEDEP VE-'B - X QRS(e CB ) V,B, - CCDEP VEB, =T 1 RS e C IB_! -Q v FC E- RS C'B''COL TF ( VB 7R7 + ( QRS-e VC'B') + CCDEP VCB, We can associate the current terms dependent on the time derivatives of voltage with capacitances and separate the nonlinear capacitive and resistive effects. With the definitions

245 iF A QFS E'B EB' r (e) = Ar QRS Ac'B' 1C f A -X VEB CEDIFF AQFSe ~A - t~VC'B' CDIFF = QRS e the voltage control equations can be expressed conveniently as B' = (1- F) iF + (1- R) iR - (CEDIFF + CEDEP) E'B, (CCDIFF + CCDEP) VC'B' COL = F - iR + (CCDIFF CDEP) VCB? This system of equations has the circuit representation used for the voltage controlled transistor model.

APPENDIX C ALGORITHM FOR CLASS C AMPLIFIER ANALYSIS A flow chart describing the computer algorithm used for analyzing the 100 MHz amplifier simulated with the extended transistor model (Section 5.3) is shown in Fig. C. 1. The numbers presented beside the blocks of the chart refer to the line numbers in the related Fortran IV program listing (Table C. 1). A typical data set for use with the program is illustrated in Table C. 2. In this example the external circuit parameters are contained in data Lines 2 through 12. The parameter PHI is the phase angle of the sinusoidal input excitation. Experience has indicated that convergence to the limit cycle is facilitated by selecting PHI such that the system state variables are relatively smooth at the endpoints of the period. Such selection normally requires one solution to be found from an arbitrary choice of PHI in order to aid the selection for successive runs. The transistor parameters for the example are entered in Lines 13 through 38. Estimates of the initial conditions for the seven state variables are contained in Lines 39 through 45, and again, experience gained from preceding runs guides the selection of these values. Maximum step size in the independent variable (time) in the integration subroutine and the allowable cumulative integration error 246

247 are specified by Lines 46 and 47. The maximum number of total iterations allowable for each solution is declared by JMAX (Line 48), and the squared error convergence criterion is given by SLOP (Line 49). Lines 50 through 59 are used to determine which of the computed waveforms are to be plotted. Data for successive runs will be the same as for the preceding run unless specifically altered in the data set. For example, in the second run of Table C. 2 (Lines 61 through 71) the value of the excitation period T is changed from 1.05 to 1.15, and some of the waveform plot requests are negated. The initial conditions for this second analysis will be the final values determined for the state variables in the first analysis. This retention of final values reduces the input data required and provides a reasonable estimate of initial conditions when small parameter increments are made between analyses.

248 Time Clock Read and Print Starting Values or Value Changes for External Circuit Parameters, Model H Data Set Parameters, Initial Exusted, Stop Conditions, Numerical \ Constraints Compute Fixed Entrles of 8ystem Matrices S, A', IS', BNN' (Eq. S.i) { Invert Fixed Entries of.and Formulate 4,, IS, N &et Iteration Courter, J= O Set Up Starting Values and Constraints ior Numerical Integratlon Pr\ nt CPU Tlme Subroutine FCT Update Time Dependent and Nonllnear Terms In System. subroutine Compute Hamming Predlctor Corrector Integration Routine Subroutine OTp If Step in Independent Variable t Is Sufficient, \ ~Prl~nt CPU Tt~ Store x and Compute IB and ICOL... bnterpolate x and tFina tFloal r T Compute SquRred Error,', | etween XInitlial and XFlnal Err Set XInitial =!Flnal,.. *... Euler Integration to ind BAVG' COLAVG: Base Power, Collector Power, Load Power Print VS, IB, ICOL, X IF, m, PCT, PLITR, CPUTIM Compute PB PC PLS, PLI T, r", ]M, PVCC, PVCCIC \ Requelsted Plot VS, Xt, X2, X9, X4, IB, ICOL, X7, IF, IR \ Prnt CPU Tme / Compute Fourler Coefficents and Power Spectra for X2 r Compute PR PRDB PL2 ni' n2, n3, nc, n3T, ncT PSA, GPBASE,GAVA1L, GPTPAV, OPTPB Print Spectra, Cmins, \ Efficlency, Average Currents, etc. t~ Establish Initial Values for Succeeding Aralysis *ig. I.. lo car fr las aplfir nayss Fig. C..1. Flow chart for class C amplifier analysis algorithm

Table C 1. Program listing for class C amplifier analysis I C*.'~C1A~ T:;CIC; r ii7AvLIFT FR ANALV'ZTS WITH F XTFIFD T-rNLTO -VOr~fTTL Lf A J ".'~ a~ S~Yf = APAX + BP* U N + S SP1I*.s r P N= A*>* 4 IN:*1 J + I SNIJS 4 X* I = FF,? X?= VC 17- X?=V F" R X4= VO' X =T I I, x6= T I., 7 X7= T LL. C- r~ ~cq~e~r~t fJ\J II= I F tJM-'?=ALPHAF*IF, t.uN3= IP UJN4=ALPHAR, JN5= I A 7 i = V1 T VS S =VJ? =VCC, 01S 3 =V S AV G nTMFNSIJ3l S(7,7),SrN IIVf7,7),tA(',7),A(7,7)1 III 1 H.I~P I 7 2Xl(30C),) (2pN,X 3 (3), X4(P f 7, 3 ),X(3 ),XX(37 i. 1 2 X I 1 3 n~l),X2 I?t?/i), X 3 I ~") ~ 1(4 1 3 ~i~crL (1 TYM[. ) "I (7 t C P 1j'r T -4 3 3, C i 3 ~~~~~~V r) T ( 3' " ) EKf v I R I.. ))Ty- 5 3C ),CPI1i I1 3~C 13? 4 Y ( 7 ),f) EWY('7),DEPY(7)tPPRM$U) AJX(16,r7),IMAGF(9q9O) 14 5CRF( 1 ), CTV ( It ),tCMA ( 1i.),Cf'/V>r,-( 11) P( 11),PR(11),PP93(1 I 15 6 Tt F r!3r T P ( 3 ~ " l 56 C 1 7 11 v- NA, 111Y VI P H 1 9V r", r' V S A T t A ~Ar A f4 10f~~IOFS-v L PAF v Trr t RS vAL P11APv P. 7" ~~~~C3C, C CqV C1Ab,, G O I k C FC 1-A4.L T M.) 21 4LSI, CS 9L.Lt CL. fjCC8 C, vCC tF t LF.~ 2'I 6 T t X I I X?, Q r X 4 v X, 5 p Y6 v X7 v V S T q I R3 t I C n7 L.1 I F, I R v C E I C Ct R L 2 4 To T YM F v 7 S,, VrS (-'P (.. M v VA t NIA? 5 P, 9S (isS 1. 2 1 BS u T,?,3 OS Bs S 3 It B S 2,t AP 1 4 t, P~ h 46 2 7 FAL L AMRDP~ROA 9 I L S I V I LLC I V v TRE t COL. v I C 7 f,nIRTF 1EEK ERO S p LS I 9 t (TF r 1 P 2' I~~I TLFPTTt T~v M 3D 3FP O rF A PM I~~~~~~0 IOFSAL~PHAF,TQPSALOHA P7E v, l t P, RM~

Table C.1. (Cont.) 31. C:3? N A EI.. T S T / D A T VS, PHI t VS C VCC T,RS,LS, CS, L, L, L CL, 1 CCF,3 CC F,,CC.F QCC,.F,,RR tE RF,LE.4 2 OFS,ORS TF, T aPt AL -PHAF, AI_ D0 1 AP, L A.MB t V VA, NAt 35. 3C JC, V7C, GAMMAC, CFC,,A4LI M, 36 4CJ F,VZE GflMMAF,C FF,A 3LT m, 37 r!VFP IVVCF TV, VFPD3PI tVCPD. I, S T, I STV, F I LL IV, 3P 6Pr STFP, PCEPR, JMA.X, SLP. 30 7DLTVF, PLTVCF,FPV F PPVCP P L TT, tLT TC, 40t OPLT, T L.L Pt TVS, Pt T F, PLT T.. 41 1/ P I V E/T 1 T,r)UTY C Y 42 2 /.)T / PS,P t P - PV CC t L P L 2, I. t 3, 43 3 CF.1, EC F2,EFF3 EFFC, EFF3 T,FFCT, 44 4GAVATL, GPBAS E,PTPAV GP TPR. AVG VC1 C 4 -5 3, DVCC C NC 401 46 C O C7 FTEYTE NAL FrfT t..JTDP 4P C CLL T 1] ".:F An,=AAT A, t=CCo, F RP=1e IS)} 52?P f I T Ff ( 6,?C 2 )! Er? W P RIT F(6, DATA ) 5 t1'4 C" T, I 7 515 1 5 WRP ITlF 6, 16 ) FI' ]FO.:::-T(F IFPP.n tN INOUT OP ATA —- ATA SFT I. T TITTED ) 57 " f',: TP. lOC'q 13? Fs=lI./T 59 WS=6. 283 1 0.PF S AF- Gi. =V s nc/vsRA t T1 = ARS f. r71 ) /,',,S T T? IT/2. - T1 T AU=T 2-T 1. A4 ) L.t T YC Y = T A../ T. C; tFWR TF( 6,DR T Vf)

Table C.1. (Cont.) A~6 i~) ).172 IPO W=1,,7 f7 nm 112 ICfLLMN=1,7 69 S{ IPDWr, ICr LUNI) =,n. (;9.' INV( IOOW,.ICt.N) =C. 7? C TP N( IR WT I C ]LMN)=o. 7r a P ( T P 1Dd I C1 rFlt) L =. 71 112 A( IRpW,1 CnLNM)=O. 72'. n.14 T IC LY~N=I,5 7: H P! P (I P. ~w, IC C) YL:} =e7?4 1 4 H N{ T P _i:W, IC:t L.,N ) _ 1. 7? Dn 116 TICLMN-1,3 73 II 6 TwICOLMN)=113 76 F.SD I nSIP(RfW,1CnLMN }=n. 77 16 BS( IRfOW, I CrL. N) =0. 7R9 12CN CflnNTIIJ F 70 AP( D,4)I=t./(I B+R tC),. ~AP.( 1,1! =-1./RS-AP(1 4) ""nl1 APf 1,2)=-A'( 1,4) P2 AP(2,1)=AP(I,?) 8.3 AP(D 2, 2) =iP( 1 2) -1. /RL 84 AP(2,4)=AP( 1,4) 8,A. &Pl AP(4,1)=AP(1,4) Rt~t q ~AP ( v.?)=AP ( 1, 4),7 A (.,4,)=AP(1,2) r A $.A P(5,1)=-1.. A P ) = - 6 C J ( f c:' +P B.) c'r~ AP(6,?)=.+AP(61t ) 91 AP( 6,3 =1. di2 AP(6,4 )=-AP{ 6,2) 03 APt(7,2) =1. 94 A. (6,6)=-REF-(RR *PPC)/( R.R_+PCC) )6 AP (1 6) =RPCC/ (PR.B+RCC) 07 AP( 26)=-PRB / RR+PCC ) 98 AP(2,7)=-I. o A(3f>.)=-1.

Table C.1. (C ont.) Sr 3 nP ('4CAP( 46)=-AP(?,6) f3NP(3,1)1)1 1 f7 2 RNP(93,4)=-1. PYP(3,5)=-1. 1C4 SNP(4p?)=-1I. r a f l,,JP 4 1 I 1 R' SP(11 )=-I.IPS IC7 P (2,') =1 fL PSP(5,3)=-1. -P (7,2)=-I. 111 ___)= S~RF+CI 112 S(21ihC.CR 1I3 S ( 2, 2 )=(CL+CCEs +C C R 1'. c(3v3h)=CF Sf4,4h)=Cr.117 S (f-,96)=L F S(7,7)=LL 110 F)D= S(U I ),)* ( 2,2)-S(1,2)S 2 ( 1) 1 3 C: S~~~ T N, v I r1 )=S ( 2 rf) f 1 2 S INV( I 2)=-S( 2 t I / ST NV (2, 1 ) =-S( 1I, 2)f T TNV( 2,2) =S 1~, 1)fF) 124 S4IV( 3) =c* 125 TINV(4,t 4) =(I. I 2~ 6s I iV (, 1 )=I *S f( 5,5) 1 27 T rvV(t!~ ~)= S f 6, f~ 12" SIV I7,7)=1. S( 7,7)!2 ~ ~ ~ l~~~t\!=l p7t 1 2 f ~WI 2C'~ NC=I,97 132 R T2C? A=1,7

Table C.1. (Cont. ) 1 34 nn?4 NC= 1,5 135 N f R,N )= =Q. 136 on?4n4:,I=]t7 1. 3 7?2 NC R, (NNC )= BNI ( -,NC ) + TNv NP N ) T I, ( NC) 1~a;'01 2.so NC=.,3 1 3 9 83( N P., C )=O. 140: ri 2.2 NIl=- 7 141? RI S (N R,,C )n N Nr ) + S I N.',N l9IT i S I NC) 14? 34< C NTN tJE 143 C 144. St.S1 2=SI 21, 2?)VCC 145 3SU S??2 S 12,p 2 )*VCC 146 1 SU S5 3=-8R S ( 5, 3 ) *VSDC 147.SUJS7?=BS(7, ) VCC 41 AP14 =AP(, 4) -r. lI. AP46=^AP(4,6) 150 TYME(9)=-I, 1. 5 1 TYM.F 1) =0o 152 Xl ( 11 =VFEB TV,!53 X2(1[lI=VCETV 1 54 X 3( O)=VE PB P 155 X4( 1n)=VCPBPI 1 56 X5(10 )=TLSTV 157 X6( 1V)=ILEFIV lt 5.'.~. X7 ( 1 ) =IT L TV 1t 59 VST( 9-V) - - S+ VS A*SN(PHI ) 1. 6 T BFr=(TFA.ALPHAF ) / ( 1.-AL PHtAF) 161 TBR= ( T *AL PHAR ) ( 1. - At. PHAP ) 162 ICEZF(ERO(QRS* 1. (.-AL.PP.AF*AL PHAR ) ) I ( T3R t( 1.-ALPHARP) ) 163 IEZERO= ( OFS* ( 1.-ALiHAF*AtLH4R ) / ( Tf *( I.-ALPHA F) 164 ICfOL () =I C ZEP F 16[. 6 B(9 =-ICZEO-I F 7 F 1 66 DT=PCSTEP*T tF 7 J=

Table C. 1. (Cont. ) 168 3c;C~ Y(12=X] (1C! ec; Y ( 2)- =Y2 1 O ) 1 7'' Y ( 3 ) = X'3 10) 171 Y(4)=X4(1C) 17? Y(5)=X5(1.) I - Y (7) X7( 1 ) 17: PRP 1P)-=. 1 7 p,2 _ T)= r' 77 PM(3)=DT 178 PRM( 4 }C F=:CF PVtC Cr 179 PRM ( I ) =. 1. Pr, NDI) M=7 181 THLF=5 i]' "):pyz- ( 1 ) =Y ( 15 1 nE PFRY (2.)=.5 184 F)pY f -.)=. l PF5 DEP.RY(4) = 2'A EP~()=E 1lP7 ODFRY6)=.1 1 DP Y( 7)=. 1 1]c It=10 1 91iFW ITFI 6 444) I]09 2 444 FOArM T(T'rrry F ANr)Y Tl T-T TF, J=', 2 i) V}3 (:AL l. T T F 1,1 ) *!rcz ~ i,,1"r. " C, LL T,,'TFG( PP,9 Y, F OY YNOt I -', HL Fi Fi C rT tnT AU ) *! or,. {hL CL TBF( 1,. ) l. c( TNIA X= T.- I la7 " mt X=1 MAX- l p r From IBM Scientific Subroutine Package (Subroutine DHPCG).

Table C.1. (Cont.) 0 f* *~C4**A!:)JUST FNfIPntINTS nr CfMPUTATION ( T Ym f A T) T AX) ( I MX Y T)-TADJ*( ( TMAX)-1f I I. IX ) 2' 2 X I2. X)X ( M AX ) =X v ( I A )-T &. A * AD ( X 2 f MAX ( I M AT m )-( ))..'...'. Xzf PIM.X)=xY4( T'AX-) -TAr)J" Y(X4( TIAX) -X I MT.Y X)I 7 r: 4. x 5 r I A A X ) = X 4 5 T h- A X )T A J 4^-{ X 4 1 I MA A X )-X 4 l T Xif T ):?r' 5 - X5 ( I','A ) ='X5 t k,AX)-'T An.J (x (M A...X ) -X5 f I.~ I ) ) 270 X,~,( ]8 M X) =,X (!.",.'X) - T A.rJ:~ ( X ( T. A X) -fY f t A XX ) ) 2..7 X7( [MAZX=Y7( -.Ax)-TAn-TJ*(X7 Y7 M4X)-.7(.It'MI X)) 2.r" TYMF(]TMA.Y) =T c?1 r wR I TF (, 6 1 T I tHL F,TY. Y. E I{,, I"IAI AX ), X I2.',A X ), X3[ IT XA, X I.'X X 4), 2 11. ]. X5 I M A X), ( I X " A X, ).X? 7[I.X TX!Y!?2 A7I FF f.DAT(' I')LFT,~' F,T,R AICT T ) ) 21 3 E s T SO= 213 214 1 ( l( iTAX)-XI ( I 1)) /fYl MAY) )*2 ) + 01 215 2( z (( X2( IMbX)-?( lO ))/X2( AIIAX) )*t2A + 216 31 ((XX3(TN IAX.)-XI Y I)) Y3( TIM AX )**2)+ 7I7 4( ( (,.(I11AX)-X4( 10) )/X4(I TPAX)*t), 7 1 15 ( ( Xf 5 ( TI (AX)-y5U 1 1) ) /X5( IMAX) ) **? )+ 219 6( ( (X6( i.Af ) Y6 Ir X( ]. iA Y ) XF TAt) ):~ ) + 7220 7 C ({ X 7 (T I MAX ) - X 7 T(1 i) ) / ~Y 7( IA X ) ) 2) 221 T F (FPS T SO-StLP) POr (,Oc,7-C 222 7" 7 j=J+1 22' IF( J-JM AX ) 71,7 tC',720 224 71 n X1(l.n})=X' l (l4AA) 722 X?( l7 )=XI?( I2)M.AY) 22 ti X3 1 1Q ) =X3 T IAX) 227 X4( n)=X4(T AX) 228 X ( 1n)=X 5(IMAY) 229 X6(f,)=Y6(IMAX) 230 X7( 1 )=Y7( IMAt ) 231,r Tf'"?32 7e WFP TF ( W. 721 ) )IMAX

Table C.1. (Cont. ) 2?3 721. cRiPMAT(' N: Cr.NVFRGfNCF WITH',I 2,' ITERATIONS' ) 73r C -***EUtLEU INTFCTGPATOCN?36 n AVGTLT=-. 237 AVGICT=O. 2'~. AVGI RT=3. 23Q P.BT=O 2 4r PC T=C. 241 PL1TP='O. 2'? tNTL TI= MAX- 1.O.2N II-1'~!LTLT= A.... 92.. 4 1:.',.,T.M'144 JJ=TT+1 245 PRT-PT- 8.T T ) X1 "X 1 )-IB(JJ ),i(J 1 JI ) 2446 PC T=PCT+* CIOL (I I )*X2 ( I )+ I COL (JJ )*X2 ( JJ )?47 PLI TP=PPL1TR + f X2( I I )-VCC)2 ) + ( ( X2JJ -VCC) **2 248 AVG L T=AVGLT+X7( I )+X7 JJ J J /24n AVnIr T=t V'ICT*+IAC- L( II )+T. CfL(JJ) 2 f. AhVGI T=VG AGRI TT + I B( T T g + ) R( J+J) 2522 sr2 (7R T' r5 f1W811. ) T T TYME( T T r),VST(11,t B 3( T I) t ICrL( I), 53 I 1,XX1 2(,BX I ( ) I X )X? (I ),X3 T I ),)4 ( II) X CT I) X6 I ) Y7( II) 254 2,P T' t,PLITP, CPUTT M I I), IF( II), T1 1 I) 92sQ I fl?MArA t T=, T3? T TI M F = ( 1^ 7 VS= I 9I O' 3 T R',.7 "-7;7' V..P..= ~....,'. I ILS= I 3, ILF=',LI. -' T Il.='''re tI O ~' r =,r. J;, P - ) t f7 l.r t rD I 1' f, t=, 1 2,5/ 2,^O LW IF=,IC1.3I, TP=v, JC.3) ~'r'QW ITf( L= 8.11),ITTA TYM (T AX), VSVT( I. A X), I,T MAX),I,I MAX) 3 2 1XI (TMAX ),X2 ( IT AX ) 3 1Y ), X4 ITM AX), X5 ( IAX) X. IMY )t X7( IM4 X)?2'- PF=Pf=T ( fIMAX-" 1O)*2) ) 264 PC=PCTT ((I MMAX-lO)?.). -,5 PL =P l_ = T / I - L* l r t A.X- l ) ) 266 Pl. I= PL 3+ PC

Table C.. (Cont. )?67 AVGICt=AVGTLT/( IMAX-1 )*?. ) A.4 V, I C= A V C T / r MA x-. 2.) 7. _AVfr, I7 =AVCIBT! f ( I(f.A'/X- 1' )*2. )?7 r PVC>=-A VG VCL*VCC 271 PVCC. IC=AVGTC*VCC 272?"r At- 1-' 27? r 274? " Fr A T 1 F( 1, 7~ I F ( Pt. TVc ) ltq lP' "" 1 7r,", 27 I 7rr, W R ITE(6, 20? 277 rCALl S T PiT PTIAGE,TYMC l),VSt( fI),Nh'.)AT.,tT, 2 A,11,'VS T VS TI1E') 279,1 C ON TT N!lJF 2709 F ( PL TVER ) 219 210,222 C^, 2 1 rn 2l~ 71'i IR ITF (,2'0 ) 72 q1 C lAlt S T P L T2 ( IG F,T MF (I( ) t X 1 ( 1 ), NDAT A,4, t, 1,V F VS T IME).P 2 12r'.' F(PL TFlF)?4.0,?4 P,23"V,4 3?9 3 2_3:3 WD TF {(. 20' F) 284 L nAt L STP LT?( 2( MA GE t TVMf ) r X2 ( ) N AT 4' 4l,VC F VS T E'?8ci?4.:' I F ( PV F P BP ) 2A, 22rr,?5 0 2;. 6 -... — tI 5...........?P7 CAl I STPLT2( ITMAG-E TYC ( 1 r) 1x3( ),'I ATAt,,e, 1' 3, t VEPBP VS TVIMF' ) 288? " 1F ( PVCPR })?c.O,2R. -, 27-nm?2, 2 7r', ^ W TwTF ( 6?v ) 29...AI.L STPLT7( ItAMAGE tTYMF( 1 ) X4 I) t OA.TA,4, 13 VCpP VS T TF )?91 299 5 "!~ TF ( PLTIR 310 131rNIt 900?92 2 ) C' WPRITF(6,?000) 2>07 CAl L STnLtT( 2(IMAGF',TYMF( 1r ), T lr( ),X,DATA, 4,O' m,1, I R VS TME' ) 2( 3.. C I' F ( FPLTI C) 3 2 0 3 2 t 3 1 rn 29 3t"00 W I TFI 6,?tT ).? CALAL L ST T? (MAE,TYMF( Ic ), I. rL( I )ATA,4,' T A, 1 2, CnL VS TIME' ) 2q7 ~3 3 ^ 3 F ( PLT I L), 3't f, 3 fl 798 W3ln tNR I TF( 69?Cr )

Table C.l. (Cont.) CALL STPLT2(1MAGETTY iF(1 C)XX(1.)),NflATA,4,er,11,uILL VS T IE') 3r. n - 4 T FI: I ( P L T TJ F 1 3 C!' L ) j ~354r 3 I 34C) W I TFE(PLTT 1f)3 % c, r 3'M 39"'1 4PITE(r,?cn' ALL STPLT(IMT A G F TY Mc(I)IF(1q N AT A 4,9O I,,I F VS TIMEI) 3C P4 3 7 3 WPTTF:(( r,?r>n) 3 05 CALL STPLT2(I,4 M AGETYME(IC), I R( IN'AT A,4 0,11I VS TTPF') r" 3VY' CrNTINUF?, 7 C -4P WITTF ( 6v 2rC'O) CALL TIMF1,91) IMAXEV=IMAXXf 311 IM 3AXFV=PfAAVFV*2 312 N=(W IAXFV-10 /2 313 M=10 314 CALL FnP0IT (X2(lf0),N,,M,,r FRC, IcfvP) 315 IF ( - q C i, 6 JEP) 3 1 6 WI WI 6TE(,r6C 5 )ITP R 17 hnsi Fn AT( I FP=r TI 314 CA*,*CrMAS(I)=nC C=fMPc nNFNT, CMAG(?)=PJNflAMFNTAL, COAl( 3)=2\1D HAPRMDIC, ET. 31 9 61 0 < 2=M+l 3 20 Or 700 1?=1,tK2 321 CMA S( S 04 1 I2)(C (R C)*?)(M(T2 2 322 CMAG((2)=SOO T CMAAf%4~n(2 323,C 324 P0 ( T 2) =C MAGS Q I( 1 2.2 *PL) 325 P 1) = (CMA( 1 ) -VCC )A*2) /P L 32 6 PL. 2= PC 3 27 DO 72C'0 1 3 =l F B PRS Sub3)rTine Pa tFrom IBM Scientific Subroutine Package.

Table C. 1. (Cont.) 33,, 7?.,', PtL 2= PL2+P( I ).31 FF I=P 2)/Pl 332 FF2=P (2 )/PL? 333 EF'3=( 2) /( PDR+PVCC) 234 EFFC= P( 2 )/ PVCC 331 F'F3T=(PL I -PC)/ (PB+PVCC) 336 F FC T= ( Pl 1- IPCr /PVCC'37 PSA= (VS A**? ) / ( R.*P S ) GPBRASF =P f? ) /PP, 339 fGAVt IL=P( 2)/PSA 4 rP T DA V= PL 3 / P's A 341 GPTPR=(PL1-Pr) /PR 342 WR ITF( 6,750F, ) 343 7 c;' FM')P AT( 4 Nt', X tC,CA r r',IQ,, oI )(N) WATTS' SX, 344 1' OR ATI ( N/(l)' 4X, PRATIo.( r,) 345 in 76h0 1 4=1, K? 346 T5=I4-1 347 761.n WRITE(6,77n0) 15,CAG( I4 ),P( I4),PR 4), PRDB( 14) 34...77r.0 FOPRMAT( i? HO, 1 2 4( 3X, 1PE 12. 5) ) 3 49 C q S n WP ITFE(6,7850) 3S1 7R5, FCRtAT ( 1H- ) 32 WP I TF (6,UT ) 353 VFBITV=X (IrAX) 3' VCEIV=X?(IUMAX) 35,'> VFPRPIX=X3( I MAX):356 VGCP BPI=X4( TMA X) 357 IS IV=X5 ( IMAX) 35P IT EE V=X6 ( MAX) q35 9 I LL TV=X7 ( TMAX ) 360C) O TO 100 6 1 1 T STp ENO

Table C.1. (Cont.) 364 C 7665 C 366 C 6 7 St)BR3T JTINF FCT(I TYDEPY) 368 C?-Sqt DIMENS ION A(7,7),f N(7,5),S( 7,3}, 3 70 2 X I ( 3 O)n, X 2 ( 3rr ), 3n),x )(4 (3 O) X5 3n 0), X 6( 30 ) X 1 ), 371 3V ST ( 30 ), I B( 30 r ), I Cnt (rnO), yF( 3'1"),CP T1F' CP JT. ), 372 4Y(7),D:Y(7),F F(3 c),IR(3CO) 373 C 374 COMMON WS,PHT,VSDC,VSA, T LAM.BDA, 375 1 OFSAL.HAF, TtF ORPS, AL PHA, TP t 76 2 C J EV ZE, GA.CMME, CFE, A3L I:, 3 77 3C JC, VZC, GAM MACC FCC, A4 L I M 379 4LS, CStLILt Cl,CCRB,,CCELFECtC E, 7o 5 A,.RN,'BP, 3PO 6T.t X I X, X X4, X4, X X6 t X7,VST, f8, I Cft L, F Pt I!-I, CE, CC., L 3P 7, TYM E, S,VCc,CCP trT T VA,NA 9 82 8tS.;tS t2, BSSUSSS2,? i S 5 3, 53, S Itt72,A P14, A 46 393 C.84 RFAL (. BDA, F, TP, t LALS yF. - L, T B, I Cr, I A 1,NA 38~ii5:C ~9,6 - OnDqt!,L:: PRECI STON YfrEPY, ZT 397 C, C WST=WS*ZT'-',o l VST( f ) =-VSOC +VSAA S IN ('.ST+ PHI ) 3e2 A ~l'=- LAt, A A r)OA*V( 3 ) 13 A2=-LtAMn.f.A*Y ( 4) 304 TF(A1-I00. 2 1212,? 05S 22 h!= 11)-* 3s06? 1 I F f( A2-10n: )' Xt,:l t..n 307 3 21 2qO I

Table C.1. (C ont.) I l P 31 C fINTrJ I.E 4C(0 ~ R( I()=(V S*(FX-(P(tA2l)-1. ) )f(ALPHAF*TF) 4 A3=V7c+Y(3) 402 A4=VZC*Y(4) 403 IF(A3-A3tIM)4 4'.40, 404 4C6 A3=A LIM It 5 4 1 IF(44-A4L1P)42, 42,v43 406 4? A4=A4LU' 407 43 C TF = C F F + C CrI RA3 3**AnMMAF) E 40P CTC=C FC+CJC/A4 **CAMMAC) 4r~o ~3IF(Y(3)*_.G7T.(q*VA4)) GO Tr 49 4lr' TA=O. 411. CA~i. 412 GO TO 52 4 I'3 49) IF(Y Vt,33)-VPb -( L * - ) )5-1 951'1.95 r r 414( 5t I: A= (QFS;* 1E-6)/(AI'HAF*TF) 416 GO IT) 52 417 51i TA=(QFS/(AL PHAF*TF) )* (1./(1-(Y(3)fVA) )**NA)-1o 419 CA=(TPl*A)/(VA-VY3)) 41 9 5? CE=L.AMBn*0FS*FXP(A1 )+CTF+CA 420 C, C=I-AMfk3A*QRS*PEXP(A2)+CTC 4?1 IDFRrY ( 1 ) =A 1 9 1 ) *Y( I ) +A 1. -P 2) *Y(2) + 1 v4) *Y(( 4) +A 1 I 5r) *Y 5) + 2,~~~~ A ( It, 6) * Y (6G) +Ad (I1 7 * EY (77) +B S ( 1, i ) *vs r ( i ) + F3SUJS 12 K.3 f 9EY(2)=A( 2,1 )*Y( 1 )+A (?, 2)*Y( 2) +A (4)*(4)+A(2,5)*Y(5)+ 424.A (,6) * 6) +A (?'r 7 ) *Y ( 7 ) +P S( 2v, 1) *VST( I ) +SUS22 425 DFtPP(3)= (TI IA-ALPHAR*IR(I)1A-Y(6)IC F 426 DFR V ( 4) = ( AP 14*( Y( 1, )+Y( 2) -Y(4) ) +AP 46Y(6) + I P ( I) -4 PAFIF(I)/CC 427 fPPY (5) =A (5,1) *Y (I ) +8 US 53 428 DER V(6)=A(6,1) *Y( I) +A (6,2) *Y(2)+A(6,3)*Y 3) 4?9.A(6,4) *(4) +A (6 )*Y(6) 430 DFPY(7)=A(7,,?)*Y(2)+BSUS7 -431 RETURNI 432 ENSI

Table C.1. (Cont. ) 433 C 434 f 435 C 43 6 C 437 StRP O..IT TNE Ot..TP (ZT, Y, )ER Y, IHLF,N DIM,P RM) 438 C 473 D)IMFNSIJN a.7 7),E,Nf7,5), 449 l ( I7 t S ) 3 440 155(7,3), 41?X 1 3 ), X? X f3( n ). X3 3C- ), t X41 30',) v X 5( 3,00) v X -( 30$), X7( 3C0)}, 442 3V ST 3( 0 ),t C (, rO, TYMF (3'" 1 CPlT [ MT. ( 30 }, 443 4Y(7), OE'Y(f 7 i, PRM 5 I IF F. 3 r. I, 3) 444 C 445 C flMON W S,PH f V SfC t VS AI L A tMBD A, 446 1Q FS ALP HAF T F R S ALPHAPR., TP., 447 2CJE VZE,G AMMAF, CFEA 3LIMt, t 3CJC,V 7C, GAM M-"CIC,CFC, A4L tI T,'- 4L.S, CSLL, Ct.. CCB,.-CE,L EE,C, 45.r 5.ABNvRSt 451 6L T, XI, t Y? X3,X X4, X 5, X6, X7 t V Tt I R I CflF FC RL t CCC L 45 C-7, TYMF, F S i, VCCPUT M VA tNA' 453 P8 BS'JS I BSt.S 2 2, BSt'S 53t, PStJ 57?, A P 14, A P 46 454 C 4~5 9 Ftt, FAL a L L' A. tS E,L,I 3Ct CO,! t,I T I, AN.A _56 C 4R7 1Pft.!lF PRFCfSTnN YyDFPY,PPrD,7T 4t9P IF{ Z'T-TV,'- T- t -1 )-.'c.co* T) 7,th63,v63 TYF( )= 7T 46 XIT T )=Y 461 X?(T)=Y(2) 46? X3( I ) =Y (3) 463 X4(I )=Y(4) 464 X64()=Y(5) 466 X( I )=v() 466 X7( I)=Y(7)

Table C.1. (Concluded) t67 I F( )=(VST( I )+Y ( 1 ))/IQ s- x ( I)+CS*r.F Py ( 1 468 CALL TIMF(rP I,,ITMF) 46S C PIJTT',( ) =T- F*. E-3 47 T F (Y(3)+Y(4) ).t T.l. )r. Tr 12C 471 ICOL I T ) =At.. HAF F ( I )-TP ( T )+CC* Y ( ERY(1 ) +fERY( 2 ) +_ E Y 4E ) 472 1 =+1 473 7.) PR E TlJU.N 4' 120 I COL ( I ) =-( 7 ) +( VC C-Y (? ) / RL-CL*tERY ( 2 ) 4':, GO Tn 110 476 END C3

264 Table C.2. Sample data set for class C amplifier analysis 1 t DA 3lA 2 V sA -., 3 pH -=2.51324,'4 V SC(= 2., 5) VCC(= 1 0. 6 T = 1. r, r 7 RS=.05, 8 L5. S 07, 9 ( 1CS-. 1, 1(); L 22.', 1 CI. = I. 0073, 13 C C t3 6, 1'4 C B1 — 016, 115 CC Tr =:. fC- 6 16 pcRCC-C 012801T, 17 RBBB=.02245, 1 ) R EE=. 0004 55, 1'9 LEE= 3. i",- 4, 20 QS=4. 6E- 10o, 21 1 6-7 2 2 T F. ( 1, 23 TR B -2. f, 2 4 A IP tl A P' 1 87, 25 A P Ii A -. 66667' ~26 sLnADA — A21. 3, 2 7 V A,. ) 2g N- A= 4., 29 C C,:-=. 341, 30 V Z. C — C. 5, 3'1 v, M MAC= 474 f 32 CtC-. 17 3 3 A 1.I:M- =. 062 5, 34 CE=1.0'4, 3 V Z E Z=. 8, 36 G4MMAE. 114, -- 7 C E-.! 0 1, 3 8 A 3LII T10 6, 39 VEBIV=. 211, 4 0 VCr EIV4.tS 6, 41 V EPBPI=- 1. 058,'42 CPBP=-. 3 2, 4 3 ILS I] V-l 11. l4 r I L,; V —i 29 8 147 C!',[: — 1. E-;,48 JMAX- 1!.,

265 Table C. 2. (C ont. ) C #; [( jJ' * 0Q,1 375, r', 2 ~' It I i= 1., I r)? LTTLI.= 1s, P TrIC - 1. 1 Se?['.il. =- 1c., c~',svL' L. [.r= 31., A IA t6 1- 1T1. 15, f P l t. — 1, f /1 p. - -1.', P V C i.['-[ - 1., C 7 tPL TI'=-1., 6:: PI... T1P =T, 7" p [LT I!=- 1 I 7 1; - 7 2Z A, l A 7 3 r1.2, 7 14. 7 3 A T A 7- T=1. 4, 2'F 1.. 5,:.. ) q, N ~:5'=I- *j1.h,. t, F. r N Z, 7.; t.: A T A:. 1 I' -' 1. 7,'t'7).- 1' A TAD A 1T 9 2 a }:ND L't.'-,)A T I

266 Table C.2. (C oncluded) V1"' 1V - i IV --. 21 1 1)32 VC EPIV — 1. 56, 1 ) 3- C E' [I- 1 54 1( 4 VC I?PPI. 362, 1(1 ]. I. SI -V —119. 1('6 I't;?'.- b'X- 27 3, 100 s I I -=2 11') 11!3 T- 9, 11I'2?;I,'' lATA I1 iC 1 ] E&,.I ) 11; $; A N1) I i; 0 j. I, i. 117 /87 1: 1.~ 5, i"A T A 1 1. 1 2 T f. 1',l 12-, T.... % 12'.~~ ~~~~~ ~I','12:)f, l; Pl[

BIBLIOGRAPHY B1. Beaufoy, R., and J. J. Sparkes, "The Junction Transistor as a Charge Controlled Device, " Automatic Telephone and Electric Journal, Vol. 13, No. 4, 1957, pp. 310-327. B2. Brubaker, Richard, (Motorola), "ICs Pick Frequencies for Untuned Power Amplifier, " EDN, October 1, 1970, pp. 50-52. C1. Calahan, D. A., Computer-Aided Network Design, (Preliminary Edition), McGraw-Hill, New York, 1968. C2., "Numerical Considerations for Implementation of a Nonlinear Transient Circuit Analysis Program,'.IEEE Transactions on Circuit Theory, January 1971. C3., and N. E. Abbott, "Stability Analysis of Numerical Integration, " Proc. of Tenth Midwest Symposium on Circuit Theory, May 1967, pp. 1-2-1 - 1-2-20. C4. Carley, Donald R., Partrick L. McGeorgh, and Joseph F. O'Brian, "The Overlay Transistor," Electronics, August 23, 1965, pp. 71-84. C5. Caulton, Martin, and W. E. Poole, (RCA Electronic Components Division, Sommerville, N. J.), "Designing Lumped Elements into Microwave Amplifiers, " Electronics, April 14, 1969, pp. 100-110. C6. Characteristics and Limitations of Transistors, SEEC, Vol. 4, John Wiley and Sons, New York, 1966. C7. Chudobiak, Walter J., and D. F. Page, "Frequency and Power Limitations of Class-D Transistor Amplifiers," IEEE Journal of Solid-State Circuits, Vol. SC-4, No. 1, February 1969, pp. 25- 37. D1. Director, S. W., and R. A. Rohrer, "The Generalized Adjoint Network and Network Sensitivities, " IEEE Trans. Circuit Theory, Vol. CT-16, August 1969, pp. 318-323. El. Ebers, J., and J. L. Moll, "Large Signal Behavior of Junction Transistors," Proc. IRE, Vol. 42, December 1954, pp. 17611772. 267

268 BIBLIOGRAPHY (Cont.) E2. Elementary Circuit Properties of Transistors, SEEC, Vol. 3, John Wiley and Sons, New York, 1964. E3. El-Said, M. A. H., "Analysis of Tuned Junction-Transistor Circuits Under Large Sinusoidal Voltages in the Normal Domain - Part I: The Effective Hybrid-vr Equivalent Circuit, " IEEE Trans. on Circuit Theory, Vol. CT-17, No. 1, February 1970, pp. 8-12. Fl. Fletcher, R., and M. J. D. Powell, "A Rapidly Convergent Descent Method for Minimization, " The British Computer Journal, Vol. 6, 1963, pp. 163-168. F2. Fowler, M. E., and R. M. Wharten, "A Numerical Integration Technique for Ordinary Differential Equations with Widely Separated Eigenvalues, " IBM Journal, September 1967. GI. Gear, C. W., Numerical Integration of Stiff Ordinary Differential Equations, Report No. 221, University of Illinois, Urbana, Department of Computer Science, January 20, 1967. G2., "Simultaneous Numerical Solution of DifferentialAlgebraic Equations " IEEE Transactions on Circuit Theory, January 1971. G3. Giacoletto, Lawrence J., Dynatron Oscillator Operation with Particular Emphasis to a New Saw-Tooth Current Oscillator, University of Michigan Ph.D. Dissertation, 1951. G4. Grover, F. W., Inductance Calculations, Dovers Publications, Inc., New York, 1962. G5. Gummel, H. K., and H. C. Poon, "An Integral Charge Control Model of Bipolar Transistors, " B.S.T.J., May-June 1970. H1. Hamilton, D. J., F. A. Lindholm, and J. A. Narud, "Comparison of Large Signal Models for Junction Transistors," Proc. IEEE, March 1964, pp. 239-248. H2. Handbook of Chemistry and Physics, 27th Edition, Chemical Rubber Publishing Co., Cleveland, 1943, pp. 2379-2381.

269 BIBLIOGRAPHY (Cont.) H3. Handbook of Basic Transistor Circuits and Measurements, SEEC, Vol. 7, John Wiley and Sons, New York, 1967, Chapter 7. H4. Harrison, R. G., "Modeling a Microwave Power Transistor," 1971 IEEE International Solid-State Circuits Conference, February 1971, pp. 36, 37, 195. H5., "A Nonlinear Theory of Class C Transistor Amplifiers and Frequency Multipliers, " IEEE Journal of Solid-State Circuits, Vol. SC-2, No. 3, September 1967, pp. 93-102. H6. Hegedus, Cornel L., "Charge Model of Fast Transistors and the Measurement of Charge Parameters by High Resolution Electronic Integrator," Solid State Design, August 1964, pp. 23-36. H7. Hejhall, Roy, "Systemizing RF Power Amplifier Design," Motorola Application Note, AN-282, January 1967. H8. Hester, Donald L., "The Nonlinear Theory of a Class of Transistor Oscillators, " IEEE Transactions on Circuit Theory, Vol. 15, No. 2, June 1968, pp. 111-118. H9. Houselander, L. W., H. Y. Chow, and R. Spence, "Transistor Characterization by Effective Large-Signal Two-Port Parameters, " IEEE Journal of Solid State Circuits, April 1970, Vol. SC-5, No. 2, pp. 77-79. H10. Hyde, F. J., "Parametric Action in Transistors: Theory," Proc. IEE, Vol. 113, No. 2, February 1966 (Institution of Electrical Engineers), pp. 209-213. Hit. Gok, I., and F. J. Hyde, "Parametric Action in Transistors: Experiment," Proc. IEE, Vol. 113, No. 2, February 1966 (Institution of Electrical Engineers), pp. 209-213. J1. Jensen, Randall W., "Charge Control Transistor Model for the IBM Electronic Circuit Analysis Program," IEEE Transactions on Circuit Theory, December 1966.

270 BIBLIOGRAPHY (Cont.) K1. Koehler, Dankwart, "The Charge-Control Concept in the Form of Equivalent Circuits, Representing a Link between the Classic Large Signal Diode and Transistor Models, " B.S.T.-J., Vol. XLVI, No. 3, March 1967, pp. 523-576. L1I. Leadon, R. E., and M. L. Vaughn, "Short-Pulsed Radiation Effects on Dynamic Electronic Components," Final Report, Gulf General Atomic, Inc., June 5, 1969. L2. Leuthauser, C., and B. Maximow, "16- and 25-Watt Broadband Power Amplifiers Using RCA-2N5918, 2N5919, and TA7706 UHF/Microwave Power Transistors," RCA Application Note AN- 4421, October 1970. L3. Linvill, John G., Models of Transistors and Diodes, McGrawHill, 1963. M1. Macnee, Alan B., "Computational Utility of Nonlinear Transistor Models, " Technical Report ECOM- 01870-17, Technical Memorandum No. 98, November 1967, Cooley Electronics Laboratory, University of Michigan. M2. Macnee, Alan B. (Chairman), "Semiconductor Circuits, " An Intensive Short Course, The University of Michigan Engineering Summer Conferences, June 1970. M3. Malmberg, A. F., F. L. Cornwell, and R. N. Hofer, NET-i, Network Analysis Program, 7090194 Version (LA3119), Los Alamos Scientific Laboratory, Los Alamos, New Mexico, 1964. M4. Mathers, H. W., S. R. Sedore, and J. R. Sents, "Automated Digital Computer Program for Determining Responses of Electronic Circuits to Transient Nuclear Radiation, " (SCEPTRE), Vol. 1, February 1967, IBM Corp. Electronics Systems Center, Technical Report No. AFWL-TR-66-126, Owego, New York. M5. Milliman, L. D., W. A. Niassena, and R. H. Dickhawt, "Circus —A Digital Computer Program for Transient Analysis of Electronic Circuits — User's Guide, " January 1967.

271 BIBLIOGRAPHY (Cont.) M6. Misawa, T., "Negative Resistance in P-N Junctions under Avalanche Breakdown Conditions, Part I (pp. 137-142), Part II (pp. 143-151), IEEE Trans. on Electron Devices, Vol. ED-13, No. 1, January 1966. M7. Moll, John L., "Large- signal Transient Response of Junction Transistors, " Proc. of the IRE, December 1954, Vol. 42, pp. 1773-1784. O1. Okrent, Howard, and L. P. McNamee, "NASAP-70 User's and Programmer's Manual," UCLA-ENG-7044, October 1970. P1. Peden, Robert D., "Charge-Driven HF Transistor-Tuned Power Amplifier," IEEE Journal of Solid-State Circuits, Vol. SC-5, No. 2, April 1970, pp. 55-63. P2. Physical Electronics and Circuit Models of Transistors, SEEC, Vol. 2, John Wiley and Sons, New York, 1964 P3. Pritchard, R. L., Electrical Characteristics of Transistors, McGraw-Hill, New York, 1967. R1. RCA Silicon Power Circuits Manual, Technical Series SP-51, Radio Corporation of America, Electronic Components and Devices, Harrison, New Jersey, January 1969, pp. 262-378. R2. Rose, B. E., "Notes on Class-D Transistor Amplifiers," IEEE Journal of Solid-State Circuits, June 1969, pp. 178-179. R3. Russo, P. M., "On the Time-Domain Analysis of Linear TimeInvariant Networks with Large Time-Constant Spreads by Digital Computer, " IEEE Transactions on Circuit Theory, January 1971. $1. The Semiconductor Data Book, Motorola Semiconductor Products, Inc., 1970. S2. Scott, T. M., "Tuned Power Amplifiers, " IEEE Transactions on Circuit Theory, Vol. CT-11, No. 3, September 1964, pp. 385-389.

272 BIBLIOGRAPHY (Cont.) S3. Slatter, J. A. G., "An Approach to the Design of Transistor Tuned Power Amplifiers," IEEE Transactions on Circuit Theory, Vol. CT-12, June 1965, pp. 206-211. S4. Snider, D. M., "A Theoretical Analysis and Experimental Confirmation of the Optimally Loaded and Overdriven RF Power Amplifier, " Lincoln Laboratory (MIT) Technical Report No. 428. S5. Sparkes, J. J., "A Study of the Charge Control Parameters of Transistors," Proc. of the IRE, October 1960. S6. Spirito, P., "Static and Dynamic Behavior of Transistors in the Avalanche Region, " IEEE Journal of Solid-State Circuits, Vol. SC-6, No. 2, April 1971, pp. 83-87. T1. Tatum, John, "RF Large-Signal Transistor Power Amplifiers, " Electrical Design News, May, June, and July, 1965. T2. Terman, F. E. and W. C. Roake, "Calculation and Design of Class C Amplifiers, " Proc. IRE, Vol. 24, April 1936, pp. 620-632. W1. Ward, R. B., "A Study of Class-C Applications of Power Transistors at High and Very High Frequencies, " Report 713-1, Stanford Electronics Lab, February 1963.

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278 DISTRIBUTION LIST (Cont.) No. of Copies 1 Office, AC of S for Intelligence Department of the Army Attn: ACSI- DSRS Washington, D. C. 20310 1 Chief, Mountain View Office EW Lab USAECOM Attn: AMSEL-WL-RU P. O. Box 205 Mountain View, California 94042 1 Chief, Intelligence Materiel Dev Office Electronic Warfare Lab, USAECOM Fort Holabird; Maryland 21219 1 Chief Missile Electronic Warfare Tech Area EW Lab, USA Electronics Command White Sands Missile Range, N. M. 88002 Headquarters U. S. Army Combat Developments Command Attn: CDCLN-EL Fort Belvoir, Virginia 22060 USAECOM Liaison Officer MIT, Bldg. 26, Rm. 131 77 Massachusetts Avenue Cambridge, Mass. 02139

279 DISTRIBUTION LIST (Cont.) No. of Copies 18 Commanding General U. S. Army Electronics Command Fort Monmouth, New Jersey 07703 Attn: 1 AMSEL- EW 1 AMSEL-PP 1 AMSEL- IO-T 1 AMSEL-GG-DD 1 AMSEL- RD- LNJ 1 AMSEL-XL-D 1 AMSEL-NL-D 1 AMSEL- VL-D 1 AMSEL- KL-D 3 AMSEL- HL- CT-D 1 AMSEL-BL-D 3 AMSEL-WL-S 1 AMSEL-WL-S (office of record) 1 AMSEL-SC Dr. T. W. Butler, Jr., Director Cooley Electronics Laboratory The University of Michigan Ann Arbor, Michigan 48105 16 Cooley Electronics Laboratory The University of Michigan Ann Arbor, Michigan 48105

DOCUMENT CONTROL DATA. R & D (siterlfi rilnelhtfstirmn fi title, body of ab rhri aue d * ln"ctnen1 nnnol0t0in " ll i ho ehtered when MlO arall re rr(ul clss8 tied I. ORI N A TI N ACTIVITY (Corpore#e elrthor) 2a. REPORT SECURITY CLASSIFICATION Cooley Electronics Laboratory Unclassified University of Michigan 2b aGouP Ann Arbor, Michigan 48105 3. PrPOPrT TITLK MODELING AND ANALYSIS OF TUNED POWER AMPLIFIERS 4. OtSCR PTIVe' 140.tt (Type of repo#t 8nd tnctlsve dae.) C.E.L. Technical Report No. 218. D. AU tH4c'n) (rlP l-t nme, mwddle tniots, eant name" ) Ned E. Abbott 6. REPORT OATSt 7 a. TOTAL NO. OF PAGES t7b. NO. OF REFS November 1971 302 59 |a. CAnNTRACT OR1 GRANT NO. Oa. ORIGINATOR S REPORT NUMBER(IS DAAB07- 68-C-0138 TR218 014820- 29 b. PROJECT NO. 1H021101 A042.01.02 IC. Ig-b. OTHER REPORT NO(S) (Any other numbers Ihat may be assigned Ihis report) d. ECOM-0138-29 10. CISTRIUTON STATEMENT Distribution limited to U.S. Government agencies only; Test and Evaluation; 30 Aug 71. Other requests for this document must be referred to Commanding General, U.S. Army Electronics Command, ATTN: AMSEL-WL-S, Fort Monmouth, N. J. 07703 i'. SUPPLtM04tAE& NOTes 12. SPONSORING MILITARY ACTIVITY U.S. Army Electronics Command Fort Monmouth, New Jersey 07703 Attn: AMSEL-WL-S'3. A'TR"CThe desire to understand and describe the characteristics of tuned power amplifiers has stimulated the research summarized in this report. The principal objective of the research is to provide analytical methods for use in the design of transistorized class C VHF amplifiers. The analysis methods employed are numerical in nature allowing the removal of simplifying assumptions required by purely analytical methods. Several transistor models compatible with digital computations are introduced to facilitate the study. Experimental techniques for establishing the parameter values for the models are also presented. Each of the model forms is used to study various aspects of class C/D amplifiers. Basic amplifier characteristics such as output power and efficiency dependencies on frequency, load resistance, supply voltage, nonlinear capacitance, and tuning configuration are investigated with a simple ideal switch representation of a transistor. An intrinsic voltage controlled transistor model and an extended voltage controlled model are used to study several large signal amplifiers. For purposes of comparison these amplifiers are also constructed and investigated experimentally. The intrinsic transistor model is found to provide moderate simulation accuracy for class C amplifiers in which the ranges of signal swing, load impedance, and supply voltages are limited. For accurate simulations of high frequency, large signal amplifiers over wide ranges of operating conditions a more complete device description such as the extended model is required DD D,'..14 73 Security Cl~slflication

Security Classification 1 4. LINK A LINK B LINK C K EY WORDS.. ROLE WT ROLE WT ROLE WT Amplifier VHF Transistor Computer Analysis Class C Amplifiers DD, 1OAov 7 (_1473 ( BACK ) */ NO V 6l., __*_07_- _6_R 9,

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