AFCRL-70- 0514 1363-7-T Circuit Realizations of Impedance Loading for Cross Section Reduction by E. Lawrence McMahon The University of Michigan Radiation Laboratory 201 Catherine Street Ann Arbor, Michigan 48108 September 1970 Scientific Report No. 8 Contract F19628-68-C-0071 Project 5635, Task 563502 Work Unit 56350201 Contract Monitor: John K. Schindler Microwave Physics Laboratory Prepared For Air Force Cambridge Research\ Laboratories Laurence G. Hanscom Field Bedford, Massachusetts 01730 This document has been approved for public release and sale; its distribution is unlimited.

1363-7-T ABSTRACT Techniques for realizing a reactance which is a decreasing function of frequency are discussed. A Negative Impedance Converter (NIC) circuit is analyzed and techniques given for compensating for imperfections and frequency dependence. An RC realization of the desired impedance is given, and it is demonstrated that this realization can be modified to compensate for phase shift in the NIC. An analytical and numerical analysis of a NIC based on amplifiers with 50 Q input and output impedances is presented.

1363-7-T TABLE OF CONTENTS ABSTRACT ii ACKNOWLEDGEMENTS iv I INTRODUCTION 1 ~ II THE NEGATIVE IMPEDANCE CONVERTER 2 III OTHER REALIZATIONS 21 IV CONCLUSIONS 26 REFERENCES 28 iii

1363-7-T ACKNOWLEDGEMENTS The author is grateful to Professor Thomas B. A. Senior and Dr. Valdis V. Liepa for their technical advice, and to Mr. Charles B. Loftis for carrying out the experimental work. iv

1363-7-T TABLE OF CONTENTS ABSTRACT ii ACKNOWLEDGEMENTS iv I INTRODUCTION 1 II THE NEGATIVE IMPEDANCE CONVERTER 2 III OTHER REALIZATIONS 21 IV CONCLUSIONS 26 REFERENCES 28 iii

1363-7-T ACKNOWLEDGEMENTS The author is grateful to Professor Thomas B. A. Senior and Dr. Valdis V. Liepa for their technical advice, and to Mr. Charles B. Loftis for carrying out the experimental work.

1363-7-T I INTRODUCTION The reduction of the radar cross section of conducting bodies by impedance loading has been studied for a number of geometries. The frequency range for which this technique is particularly attractive is that for which the dimensions of the conducting body are comparable to a wavelength. In this range, the load required generally has a real part whose frequency dependence is not easily characterized, but which is generally small compared to the imaginary part. In the particular case which has been the object of investigation under this contract - that of a sphere loaded by a slot in the plane of incidence - the real part is essentially zero over the frequency range of interest, while the imaginary part is quite well approximated by the negative of a series LC reactance. Such a reactance, which decreases as the frequency increases, will be referred to hereafter as a negative reactance; there should be no occasion for confusion between this term and the negative, but increasing with frequency, reactance of a capacitor. Since it is well known that the reactance at any lossless, passive network is an increasing function of frequency, the negative reactance required for loading obviously cannot be realized by a passive network. Of the active elements available for synthesis the most obvious choice is the Negative Impedance Converter, or NIC; the properties and some realizations of the NIC are discussed in the following.

1363-7-T II THE NEGATIVE IMPEDANCE CONVERTER I1 12 Zin- V1 NIC V2 Zin V5 I FIG. 1: NIC with load. Figure 1 shows the referencing conventions used throughout this report. The NIC is characterized by the relation Z -Z In order to determine how in L the NIC must behave in order to satisfy this relation, it is convenient to use the h-parameters. These parameters have the general form V11 hl 1 h12 I1 11 121 I (1) I2 h21 h22J V2 The addition of the load impedance, ZL, imposes the additional constraint V2 =-I ZL (2)

1363-7-T where the minus sign is a consequence of the reference direction chosen for I2. Combining (1) and (2), and solving for Zin, we obtain h12h21 Z. =h....(3) in 11 h22+ YL The requirement that Zi = - Z then imposes the conditions h=h2h =0 (4a) 11 22 h12 21 -= (4b) Although (4b) can be satisfied in an infinite number of ways, only two cases are encountered in practice. The first is the current inversion NIC, or INIC, where h12 =h21 =1 (5) and the other is the voltage inversion NIC, or VNIC, where h12 =h21 =-1. (6) The INIC has the property that V = V (7a) 1 2 11=12; (7b) the voltages are thus the same as they would be with the NIC replaced by a direct connection, while 12 is equal and opposite to the value it would have in a direct connection. For a VNIC, V =-V, (8a) I =-I; (8b) 1 2' here the voltages are reversed and the currents have the values normal in a direct connection. Of the numerous circuit realizations of the NIC available in the literature, one originally given by Yanagisawa (1957) was chosen for investigation. A simplified diagram of the circuit, with bias circuitry omitted, is shown in Fig. 2a. Figure 2b shows a model of the circuit suitable for first-order analysis; the

1363-7-T 12 i z12 + + o V1 V2 I I R- R R R a a Rb (a) Simplified Circuit (b) Simplified Model FIG. 2: Yanagisawa NIC. transistors have been replaced by simple, controlled current-source models, with base resistance and base-emitter drop neglected. Assuming further that a = 1 for both transistors, Kirchhoff's Current Law gives I =IZ (9) 3 2 and I4=11. (10) We also have the constraint I4R a=I3Rb. (11) Combining these three relations, we have R I a (12) Since V1 and V2 are obviously equal, the circuit function as an INIC; the conversion factor is unity when R =Rb. A more accurate analysis takes into account the collector capacitances of the two transistors, which can be expected to be significant in the frequency range of interest. Since the two collector-base junctions are in parallel, the circuit model is that of Fig. 3, where C = 2 Cb,the sum of the two collector-base capacitances.

136 3-7-T 3 vI3 1 V2 + 3 _3 - Ra V3 Rb FIG. 3: High-frequency model of NIC. Again assuming that al = a2 = 1, we may write V V 2 (13) as before; from Kirchhoff's Current Law at the upper node we have 1+13 -11-aI-I3=I2-I3I= SC(V2-V3)' (14) and summing currents at the lower node gives I1+I2=V3 (Ga+Gb). (15) Combining these equations with the relationshi p I3=V3Gb (16) and eliminating 13 and V3 in Eqs. (14) - (16), we obtain Gb-sC G +Gb 2= G +sC I1+ SC G +sC 2(17) a a When C = 0, this equation reduces to Eq. (12), as expected. With C ~ 0, there are two departures from ideal behavior: the frequency dependence of h21 and the non-zero h22. The first of these effects can be eliminated by adding a capacitance 2C in parallel with Gb; mathematically, this is equivalent to replacing Gb in (17) by Gb+2C. Making this substitution, and letting G =Gb, we obtain I2=I1+2sCV2. (18)

1363-7-T There remains the non-zero h22 term, which is equivalent to a capacitance 2C across the output terminals of the circuit. Since the NIC is otherwise ideal, this appears as a negative capacitance, -2C, across the input terminals and can be cancelled by an equal positive capacitance. In practice, this was found unnecessary, the capacitance added by the input circuitry being sufficient for compensation. The complete NIC circuit is illustrated in Fig. 4. The functions of R1, R2 and C2 have already been explained. R3 and R4 are biasing resistors; since for signals they are across the input and output, respectively, they cancel one another by NIC action. The remaining resistors, with their associated bypass capacitors, are needed to maintain the transistors in their active regions. If they were omitted, the circuit would have a stable state in which both transistors were cut off, with zero base-emitter voltages. If either transistor were to turn on even momentarily when power is first applied both transistors would be forced into the active region. It was found, however, that this mechanism could not be depended upon, necessitating the additional bias circuitry. + 20 V DC 3 0 Cg 100 RqS 1500 V V -0 Out 27K R6 5.1500 6'-[Q2 2 R1 820 2 820 60 FIG. 4: Complete NIC circuit. Values in ohms pF; Q12N711B, Q2= MPS 6521

1363-7-T In the analysis above, both base resistance and the frequency dependence of a have been neglected for the sake of simplicity. Inclusion of the base resistance complicates the analysis to the point where algebraic analysis is no longer fruitful. Computer analysis, using the CIRAN circuit analysis program available of the University of Michigan IBM 360 system, was therefore initiated. These studies led to the conclusion that non-zero base resistance does not seriously degrade the performance of the circuit as long as it is small compared to the external resistances; experimental results have borne out this conclusion. The frequency dependence of transistor a is a much more serious problem, and proved to be a serious obstacle in the early stages of this investigation. Making the usual first-order assumption that a is given by a =+1 (19) where s is the complex frequency variable and to is the alpha-cutoff frequency, leads, after considerable algebraic manipulation, to an approximate h-parameter description of the NIC having the form V1I 0 1 I1 vi] ~~~~~~~~~~~= II ~~(20) 1-3s/oo 2sC l+s/o V 2 1 1+s /~) 1+3s/too /L as compared with the ideal (to which Eq. (20) reduces for s = O ) of the form V 1 1 I1 (21) I2 11 0 V2 The non-zero h22 in Eq. (20) represents a parasitic RC admittance across the output terminals of the NIC. This is not a serious problem in an otherwise ideal device, since a parasitic admittance across one part of the NIC can be cancelled out by an equal admittance across the other port.

1363-7-T The forward current gain, h21, in (20) has the form of an all-pass phase shift function, with a phase angle which departs significantly from 00 at frequencies as low as wo/30, which is in or below the frequency range of interest. After extensive analysis, it was concluded that this phase shift could not be compensated for by modification of the NIC itself. This immediately led to the further conclusion that the desired input impedance could not be realized (in the frequency range of interest) by means of an NIC and an LC load. This is illustrated in Fig. 5, where for clarity, it has been assumed that the NIC exhibits a constant phase shift, 0; that is Z Z L (7-e) in L Wi z-plane W3 z-plane z-plane t 3 \ 7 ir-0 W2 W2 ill I (3 sl (l a) Desired input impedance. b) Load impedance required c) Load impedance rew/o phase shift. quired w/phase shift. FIG. 5: Effect of phase shift in NIC. The desired input impedance shown in Fig. 5a, is a pure reactance decreasing as frequency increases. Without phase shift, that is, with a conversion factor E']r=-1, the required load impedance is a pure reactance increasing as frequency increases, as shown in Fig. 5b. As is well known, such a reactance is easily realized with passive elements. The situation resulting when the conversion factor is ej(7r-) is 8o

1363-7-T shown in Fig. 5c; here, in order to obtain the desired input impedance, the load impedance must be shifted by an angle 0 from the ideal load impedance. Since this impedance has a negative real part for w2 < W < W3 it obviously cannot be realized with passive elements. Fortunately, this difficulty can be circumvented, at the cost of a few extra passive elements, by means of an RC realization (Kinariwala, 1959). The desired input impedance, frequency and magnitude-normalized, is given by 2 s +1 Z(s) =. (22) s If a positive constant of appropriate value is subtracted from Z(s), we obtain 2 11 s +(a+ -) s+l (s+a)(s+ 1) a a Z (s)=Z(s)-(a +)=- _ (23) 1 a s s where it is assumed, without loss of generality, that a < 1. Now Yl(s), the reciprocal of Z1(s), has all its poles on the negative-real axis of the s-plane. Y1(s) can therefore be expanded in the same manner as an RC admittance, although it is not actually an RC admittance, since its poles and zeros do not alternate on the negative-real axis. The result of this expansion is a_ s a s 1-a 1-a2 Y (s)- 1__ ___ (24) s+- s +a a which is the difference of two RC admittances. Y (s) can therefore be realized with two passive RC networks and a single NIC. The realization of Z(s) is then achieved by the trivial operation of adding in series the constant originally subtracted in (23). The final realization is shown in Fig. 6. Subject to the constraint that it be less than unity, the parameter a is'free', and its value may be chosen to attain objectives such as convenient element size or reduced sensitivity. The effect of phase shift in the NIC is shown in Fig. 7, which should be compared with Fig. 5. As before, the NIC is assumed to exhibit a constant phase

1363-7-T (l1+a a (l-a2 Ideal (i-aa z (sZ- NIC a2o a2) -'a FIG. 6: RC realization of desired load. z plane z plane z plane wL 2I~~~I I W2 I a) Impedance desired at NIC b)Load impedance required c) Load impedance required input. w/o phase shift. w/phase shift. FIG. 7: Effect of NIC phase shift on RC realization. shift, 0, giving a conversion factor ej(7r ). In order to obtain the desired impedance at the NIC input in the presence of phase shift, the load impedance must be rotated in the z-plane through an angle 0, as before, The crucial difference between the RC realization and the LC realization is that in the RC case, the rotated load impedance remains in the right half of the z plane and is therefore at least potentially realizable. 10

1363-7-T This realizability was checked by attempting to match the load impedance required, using measured values of the NIC conversion factor, Zin/ZL. The form of the modified load impedance is shown in Fig. 8. The element values were chosen L 9o R R C1 R SCo a) Load impedance w/o phase shift. b) Load impedance w/phase shift. FIG. 8: Load compensation for NIC phase shift. for an exact match at ka = 0.7 and 1.2. C1 and R were chosen to match the real part of these two points, and C2 and L were then chosen to give the correct imaginary part; the procedure thus required simultaneous solution of two pairs of nonlinear equations. The two values of ka used for matching points were picked by trial and error; obviously, bandwidth can be traded for better accuracy by choosing frequencies closer together, and vice versa. The calculated results are given in Table I. As might be expected, since the desired load impedance is a well-behaved function of normalized frequency, an excellent, broadband match was obtained at the load. Some deterioriation is observed when this load is transferred to the NIC input. Although this is almost entirely due to numerical error (the calculations were carried out on a desk calculator, not a digital computer), it is felt that the values obtained are reasonable. An actual circuit could not be expected to operate in as smooth and consistent a manner as a smoothed set of measurements. There would thus be a similar deterioration in practice, although arising from a different mechanism. The correspondence between the impedance desired and that actually achieved is markedly poorer at the circuit input. This is due to the fact that operation of the

TABLE I Zl~~~ Z~~in Load Impedance Impedance at NIC Input Impedance at Circuit Input ka Desired Obtained Desired Obtained Desired Obtained.5 10.17 - j11.37'10.45 - J10. 70 -2.35 + j3.18 -2.44 + j3.01 0 + J5.80 0.65 + J4.14.6 10. 13 -j8. 84 10.25 - j8.55 -2.35 + j2.65 -2.38 + j2.58 0 + J3.71 0.36 + j3.02.7 10.02 - J6.91 10.02 - j6.92 -2.35 + j2.27 -2.35 + j2.27 0 + j2.03 -0.02 + j2.03 *8 9.83 - 5.44 9.76 -J5.61 -2.35 + 1.99 -2.32 +j2.04 0+jO.62 -0.54+J1.15.9 9.58 - J4.22 9.49 - j4.50 -2.35 + 1. 77 -2.31 + j1. 84 0 j0.64 -0.92+0.14 1.0 9.28 - j3.21 9.21 - j3.52 -2.35 + j1.59 -2.31 + J1.67 0 - j1.78 -1.28 - J087 1.1 8.95 - 2.44 8.91 - J2.63 -2.35 + J1.45 -2.33 + 31.50 0 - 2.84 -1.05 ]2.61 1.2 8.61 - 1.79 8.61- J1.79 -2.35+ J1.33 -2.35+ J1.33 0- J3.86 -0.13- 3.83 1.3 8.25 - 1.23 8.30- j1.00 -2.35+ j1.22 -2.39 + j1.15 0 - j4.84 1.46 - 4.96 1.4 7.88 - 0.85 7.99- j0.22 -2.35+ j1.14 -2.45 + j0.97 0- J5.81 3.11 - 6.01 1.5 7.51 - 0.53 7.69+ 30.53 -2.35 +jl.06 -2.41 + 0.74 0 - j6.79 4.79 - 5.29

1363-7-T circuit depends on the subtraction of two impedances of the same order of magnitude; this is an error-magnifying process in both numerical calculation and physical operation. The RC combination connected across the NIC input combines in parallel with the negative RC impedance seen across the input terminals of the NIC to yield sC= SC s (C -C )+s 2CC (R -R ) __1 2 1 2 1 2 2 1 Y=sCR1+sCR (25) l+sC R li+sC1R1R )l+SC R)(+sC2R2) 1+C 1+sCR2 11 2 2 The correct operation of the circuit depends on the exact equality of R1 and R2 and the resultant cancellation of the second term in the numerator of (25). In practice, this condition cannot be achieved exactly; as will be seen from Table I, the input impedance of the NIC has a real part which varies about ~ 5 percent around its mean value and thus cannot be exactly cancelled by the constant R1. However, by careful adjustment, it should be possible to move the spurious pole introduced by incomplete cancellation far enough from the origin that its effect will be negligible. The impedances given in the last column of Table I were checked by a computer program which calculates the change in cross section produced by a given load. For purposes of comparison, the input impedance of the idealized circuit, with no phase shift, was also calculated by the same numerical procedure and the corresponding cross section reduction calculated. The two circuits are shown in Fig. 9, and the calculated changes in cross section are given in Table II. The calculations discussed above were carried out primarily to check the feasibility of adjusting the load to compensate for phase shift, and no attempt at optimization was made. The results given in Table II should therefore not be viewed as the best attainable. In practice, it should be possible to approach fairly closely the cross section reductions obtained using the idealized circuit. 13

1363-7-T 10.71 10.71 6.26 2.35 2Ideal 35 2.35 Nonide.0396 10.94 ~NIC NIC 1/2.48 }/1.59 1/2.48:5.7 ZiA IzL zin zL FIG. 9: Load realization with ideal and non-ideal NIC's. TABLE II ka Change in Cross Section (dB) Change in Cross Section (dB) Idealized Circuit Actual Circuit.5 -11.01 2.30,.6 -12.83 3.39.7 -28.43 -27.66.8 -22.35 - 3.45.9 -19.16 - 1.58 1.0 -12.56 - 0.57 1.1 - 4.43 1.27 1.2 - 5.51 - 5.48 1.3 - 7.18 - 2.07 1.4 + 2.24 - 1.02 1.5 - 6.36 -

1363-7-T Experimental results obtained in the 1 - 10 MHz band have substantiated the calculations quite well. Figure 10 shows the measured input impedance of the NIC with a series RC load; the measured reactance has been multiplied by frequency for convenience in presenting the data. Since the nominal values of real part and imaginary part times frequency are respectively -120 O and + 160 fQ for perfect operation, it can be seen that the data of Fig. 10 represents nearly ideal behavior. Figure 11 shows the measured input impedance of the "idealized" circuit shown; a number of points merit comment. First, since no load compensation was used, the results shown represent that which is relatively easy to achieve; variation of the load should produce further improvement. The short lengths of coaxial cable shown in the diagram were for the attachment of monitoring equipment which was not being used when these measurements were made; it is probable that they contributed to capacitive compensation at the input, as discussed above. It should be noted that the real part of the measured impedance is not zero but rather is equal to the 100 Q2 contributed by the resistance in series with the input. Since the RC realization theoretically requires a series resistance to achieve a purely reactive input impedance, this result is somewhat surprising. It is felt that resistances unaccounted for in the original analysis (particularly base resistances) are producing this result. In any case, removal of the 100 Q resistor (or replacing it by a much smaller resistor) would obviously yield the desired, purely reactive, input impedance. The operation of this circuit in the 1 - 10 MHz band, and the degree of success achieved without using the more elaborate load-compensation techniques discussed above, warrant some optimism for achievement of the desired input impedance at higher frequencies.

Real I (-ohms)' II jcco $ c \ I I i, i- I(gUINo) I zl ~.~ulx~q~m 16

28 100~ 1/2 w 24 NIC 1.5ft -- 2.l 2-.l_ 20 200era m7ic 16 - 12 Jacks Li'~ - 110. _ 4 105- L 8 N N -4 95 Imagery — 12 -16 -20 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 I I. I I II. I l I Frequency (MHz) FIG. 11: Measured impedance of RC realization.

1363-7-T A variation on this circuit, carrying out the same realization in a different manner, has also proved successful. Referring back to Eq. (24), the admittance is expanded in the form a a ~s 2s 1-a 1-a Y1(s) = - s +a 1 1 s+a In the circuit discussed above, this was realized by a series RC network in parallel with a negative, series RC network consisting of a NIC loaded by a series RC combination. An alternative realization is obtained by expanding the second term on the right side in partial fractions, yielding 2 a a 2 2 1-a a 1-a2 s+a (26) s+a 1-a2 s+a which is a negative resistance in parallel with a postive, series RL combination. This leads to the realization of Z(s) shown in Fig. 12. The complete circuit is shown in Fig. 13, and measured results are displayed in Fig. 14. Although the frequency (l+a2) a (1-aa 4 1-a2 la)a-2 Ideal a2 /C_.-a2)..+@ A a i NIC FIG. 12: Alternate realization of Z(s)

51 10 43 6 R 3 R2. z-.-* - 1. 1 R51 R4 -51R 51 II.1 Ir~- I R FIG. 13: RL realization. I —'C5 L -_3 R ~51 R4 51 FIG. 13: RL realization.

40 30 20 X 10j~~~~~ tO~ \ ~D ~ riv e = 3.0 V r ive = 6.0 V N -10 Real Imaginary -20 O Imag. Drive = 3.0 V into Bridge o Imag. Drive = 1.0 V Into Bridge 0 I.5 2 1 Frequency (MHz) 3 FIG. 14: Measured impedance of RL realization. 20

1363-7-T range is somewhat lower, the results are as good or better than those from' the previous realization, and the circuit appears somewhat more stable. The principal limitation at this point seems to be the passive components rather than the NIC; the stray capacitance of the resistances is particularly troublesome. Ways of alleviating these difficulties are being studied, and development of the circuit is being actively pursued. III OTHER REALIZATIONS Although the Yanagisawa NIC has been investigated to the greatest extent, others have been considered to some degree. One circuit which was briefly considered was given by Larky (1957); it is shown in Fig. 15. The operation of I1 Ra Rb 12 V1 V2 Q2 FIG. 15: Larky NIC circuit. this circuit is in many respects quite similar to that of the Yanagisawa circuit. Since V1 and V2 differ only by the base-emitter drop of Q1, they are essentially equal. Neglecting base current, all of I1 flows through Ra; since the equality of 21

1363-7-T V1 and V2 produces equal voltages across Ra and Rb, we have I1Ra=I2Rb, thus achieving NIC action. This circuit was investigated in the hope that it might have some theoretical advantage over the Yanagisawa circuit in terms of phase shift, stability, etc. No such advantage was in fact found, and since biasing of this circuit is more difficult, the investigation was carried no further. Since there is a strong tendency among designers of active networks toward the adoption of the differential-input operational amplifier as a "universal" active element, a NIC realization using such an amplifier received considerable attention. The fact that development of this circuit is not being actively pursued at the present time is the result of limited manpower rather than unsatisfactory results. The diagram of this circuit is given in Fig. 16. Although based on completely I1 12 V R R V2 FIG. 16: Operational amplifier NIC. different physical mechanisms, the operation of the circuit is very similar to that of the Larky circuit. The virtual short at the amplifier input forces the approximate equality of V1 and V2, and thus of the voltages across R1 and R2. Since the amplifier draws no input current, I and 12 flow in R1 and R2, respectively. It therefore follows that IRI=I2R2. More exact analysis yields essentially the same result provided r << R1, R2 << ri and >> 1, where 22

1363-7-T r. and r are respectively, the input and output impedances of the amplifier, and 1 0,u is the open circuit voltage gain. A conventional differential amplifier was constructed using 2 N 4959 transistors. A number of feedback compensation schemes were tried before settling on a series RL feedback element. Reasonably flat gain to 100 MHz was thereby achieved; this was accompanied, however, by phase shift of almost 30~ at 100 MHz. The gain was also disappointing low, on the order of 5 - 10 dB in all cases giving otherwise reasonable results. Despite these difficulties, the circuit of Fig. 16 operated successfully as a NIC, although the conversion factor was frequency dependent both in magnitude and phase. It is felt that the real usefulness of this approach is dependent on the development of an integrated or hybrid, high-frequency differential amplifier. With the rapid advances being made in the solid state and integrated-circuit areas of technology, the development of the necessary amplifier should not lie too far in the future. VHF amplifiers which are commercially available at the present time most commonly have 50 Q input and output impedances and linear phase shift in the gain characteristic. An investigation into the usability of such amplifiers as the active element in a NIC has been undertaken. The investigation was aimed at obtaining a practical realization of the ideal NIC illustrated in Fig. 17, in which Ii r I L + + V +V VL - 2V V 1 FIG. 17: Amplifier NIC 23

1363-7-T an ideal, voltage-controlled voltage source is used to make VL= -V1, thus giving 1= -V1/ZL and Zin = - ZL. An extremely straightforward approach to this realization uses two stages, each consisting of an inverting amplifier with large negative feedback. Each stage is assumed to have input and output impedance Ro; the model assumed for the amplifier and the diagram of the NIC circuit are shown in Fig. 18. This circuit, as expected, does not behave as an ideal NIC due to the non-zero input admittance and output impedance of the amplifier stages. Ro v -V2R 2 C a) Amplifier model. b NIC configuration. FIG. 18: Realization of NIC with amplifiers (Rf= 2 Ro ). Analysis has shown that the input admittance of the circuit of Fig. 18 b is given by y. =a-bY (27) in c+dY' where a, b, c and d are appropriately dimensioned constants. Letting Y =+YL, which is equivalent physically to connecting a resistance R = b/a in parallel with p the desired load, gives ad c + - + d Y = b L _d ad +bc in -b YL b 2 L 28) Then adding a resistance R = d/b in series at the input gives ad +bc = in b2 L L *(2 24

1363-7-T The final form of the circuit is shown in Fig. 19. The compensating resistances A, RA have values R = 0.65 R and R = 0.04 R. Cwith computer analysis of thn.is circuit, p o s o with phase shift in the amplifiers neglected, showed essentially ideal NIC operation. Phase shift was then introduced by replacing the amplifier model of Fig. 18a with the model shown in Fig. 20, with R and C chosen to give 450 phase shift (and 3 dB gain reduction) at the highest frequency investigated. R + + + oR V e VC V ~ C FIG. 20: Amplifier model with phase shift. Because of the large negative feedback in the overall circuit, this large open-loop phase shift had a surprisingly small effect. Calculated results for a series RC load, both with and without phase shift, are shown in Fig. 21. The figure also shows the load impedance required to compensate for phase shift and produce the correct input impedance. Since this is a smooth curve in the Z-plane, it should be possible to match it quite closely with a fairly simple 25

1363-7-T Without phase shift. z plane IZL compensated With phe shift It FIG. 21: Effect of phase shift on NIC performance. network similar to that shown in Fig. 8b. Due to the tediousness of the calculations, the load parameters were not determined but the process is relative straightforward. The NIC is not the only active device which could be used to realize the desired impedance, although many of the other possibilities (operational amplifiers, controlled sources, etc.) actually reduce to variations of the NIC. One approach which does not fall into this category is a realization using the negative-resistance characteristic of a tunnel diode. Although unsuccessful, this realization is presented for the sake of completeness. The tunnel diode may be modelled to the first order, by a negative resistance in parallel with a capacitance, as shown in Fig. 22a. After examining various configurations incorporating the model, the circuit of Fig. 22b was arrived at. Straightforward analysis indicates that Z. of this circuit should exhibit a negative resistance characteristic in a band around the resonant frequency of the LC combination. In practice, difficulties with biasing and stability proved insurmountable, and the investigation was not pursued further.

1363-7-T Bias Supply RFC C-R L' L Lo a) Diode model. in b) Complete circuit. FIG. 22: Tunnel-diode negative-reactance circuit. IV CONCLUSIONS To date, this investigation has produced one circuit (the Yanagisawa NIC) which operates satisfactorily in the 1 - 10 MHz range without load compensation, and which shows promise for operation at substantially higher frequencies. Another circuit, the operational amplifier NIC, has been shown to be feasible, although limited by the present state of the art. A very promising configuration using single-ended amplifiers with 50 2 input and output impedances has been investigated analytically and numerically, with excellent results. An RC realization of the desired impedance has been developed, and the technique of modifying this realization to compensate for phase shift and other imperfections in the NIC has been shown to be feasible. 27

1363-7-T RE FERENCES Kinariwala, B. K. (1959), "Synthesis of Active RC Networks," Bell System Technical Journal, 38, pp. 1269-1316. Larky, A.I. (1957), "Negative Impedance Convergers, " IRE Trans., CT-4, 124-131. Yanagisawa, T. (1957), "RC Active Networks Using Current Inversion Type Negative-Impedance Convergers," IRE Trans., CT-4, 124-131. 28

UNCLASSIFIED Security Classification DOCUMENT CONTROL DATA - R & D (Security classification of title, body of abstract rand ilsdxlnR minnotation nu.st be entered when the overall report is classified) I. ORIGINATING ACTIVITY (Corporate author)!2a. REPORT SECURITY C.LASSIFICATION The University of Michigan Radiation Laboratory, Dept. of UNCLASSIFIED Electrical Engineering, 201 Catherine Street, 2b. GROUP Ann Arbor, Michigan 48108 1 l 3. REPORT TITLE CIRCUIT REALIZATIONS OF IMPEDANCE LOADING FOR CROSS SECTION REDUCTION 4. DESCRIPTIVE NOTES (7ype of report and inclusive dates) Scientific Interim 5. AU THOR(S) (First name, middlo ieltial, last name) E. Lawrence McMahon 6. REPORT DATE 7;i, TOTAL NO. OF PAGES 7b. NO. OF REFS September 1970 33 3 8a. CONTRACT OR GRANT NO. 9a. ORIGINATOR'S REPORT NUMBER(S) F19628-68-C-0071 b. PROJECT NO., Task No and Work Unit No. 01363-7-T 5635-02-01 Scientific Report No. 8.DoD Element 61102F l.h. OTHER REPORT NO(S) (Any other nulmbers that may be asslgncod this report) d. DoD Subelement 681305 AFCRL-70-0514 10. DISTRIBUTION STATEMENT This document has been approved for public release and sale; its distribution is unlimited. II. SUPPLEMENTARY NOTES 12. SPONSORING MILITARY ACTIVITY Air Force Cambridge Research Laboratories (CRD TECH, OTHER Laurence G. Hanscom Field Bedford, Massachusetts 01730 13. ABSTRACT Techniques for realizing a reactance which is a decreasing function of frequency are discussed. A Negative Impedance Converter (NIC) circuit is analyzed and techniques given for compensating for imperfections and frequency dependence. An RC realization of the desired impedance is given, and it is demonstrated that this realization can be modified to compensate for phase shift in the NIC. An analytical and numerical analysis of a NIC based on amplifiers with 50 ohm input and output impedances is presented. DD FORM 1473, o' SUNCLASSIFIED S~r\r i, - _ - iic;.....;....:......_____

UNCLASSIFIED Securily Clssif'ication K LINK A LINK O LINK C KEY WORDS.i... ROLE WT P OL E t OLE Tj Negative Impedance Converters Impedance Loading Radar Cross Section Reduction RC Active Synthesis UNCLASSIFIED Sivcirity (- fi.l, io lil~~~~gifrr;~~~~~~lrill~~~

UNIVERSITY OF MICHIGAN 311111111111111111 11111115 03465 82 3 9015 03465 8248