THE UNIVERSITY OF MICHIGAN Memorandum 13 SYSTEM/360 INTERFACE ENGINEERING REPORT David Mills CONCOMP: Research in Conversational Use of Computers ORA Project 07449 F.H. Westervelt, Director supported by: DEPARTMENT OF DEFENSE ADVANCED RESEARCH PROJECTS AGENCY WASHINGTON, D.C. CONTRACT NO. DA-49-083 OSA-3050 ARPA ORDER NO. 716 administered through: OFFICE OF RESEARCH ADMINISTRATION ANN ARBOR November 1967

PREFACE The System/360 interface provides a connection between the PDP-8 and the multiplexor channel of System/360 models 30, 40, and 50, as well as the 2870 Multiplexor Channel attached to other models. Either byte-interleaved or burst-mode operation can be sustained at transmission rates up to 70 kilobytesper-second. Interface control operations are supervised via the PDP-8 accumulator and interrupt facilities, while data transfer operations are directed via the three-cycle data break facility. The interface is attached directly to the channelcontrol unit interface cables which interconnect the IBM equipment and occupies one control unit position on the channel. The equipment satisfies all original equipment manufacturer's (OEM) specifications as described in the following IBM publications: 1. System/360 I/O Interface: Channel to Control Unit Original Equipment Manufacturer's Information, IBM Corporation, Form A22-6843-3. 2. System/360 Power Control Interface: Original Equipment Manufacturer's Information, IBM Corporation, Form A22-6906-0. The accompanying photographs on the next two pages show the Data Concentrator, including the System/360 interface together with its test panel. The interface itself is assembled in the bays immediately above the test panel. iii

1 11.......... ~~i i~~~~~~~~~~~~~~~~~~~~~~~~i iiiii!~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~iiiiii i:i~i Figure i. The Data Concentrator. The Interface is in t heC Bay immediately above the Test Panel.

'~i~~:.=. ~.~..~ ~..~ ~,.:......~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~................??......?~....~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~............ ~~~~~~~~~~~~~~~~~~~~~.........,, ~~~~~~~~~~~~~~~~~~~~~~~~~i Mr | 00:C00 O.. Figure ii. The Test Panel of the Interface.

ACKNOWLEDGMENTS In the design of the equipment described herein, Mr. Dan Pence transcribed the logical functions to DEC Flip-Chip technology and constructed the working documentation, consisting of logic diagrams and computer-generated punched-card wiring lists. Working from these wiring lists, the GardnerDenver Company of Grand Haven, Michigan, constructed the FlipChip mounting panels using automatic wire-wrap machinery. Mr. Ken Burkhalter designed the IBM-DEC interface circuit boards and power control equipment described in Appendix D. The Test Panel, described in Appendix F, was constructed using photographic techniques by the Prin-Tek Company of Detroit, Michigan. All the special printed-circuit components were supplied by the Photo Tek Company of Ann Arbor. Mr. David Flower and Mr. Warren Kennison assembled the equipment in a most craftsmanlike fashion. The IBM company provided documentation which was invaluable in the design of this equipment. In particular, Mr. Les Bailey and Mr. Dan Murphy, both of IBM, have contributed much useful advice. vii

TABLE OF CONTENTS Page PREFACE............................. iii ACKNOWLEDGMENTS.................................... vii LIST OF FIGURES............................... xiii I INTRODUCTION.............................. 1 II CHANNEL INTERFACE LINES......................2 BUS OUT C............................... 2 BUS INO O.O O e c......................... 2 Outbound Tags........................ 4 Inbound Tags............................. 4 Selection Controls.......4............. 4 Metering Controls.................... 5 III CONTROL SEQUENCES............................. 5 3.1 Initial Selection Sequence............... 6 3.2 Service Cycle............................ 9 3.3 Special Sequences........................ 12 3.4 Polling Operations....................... 14 3.5 Equipment Failure Diagnostics............ 18 IV PROGRAMMING CONSIDERATIONS FOR IBM SYSTEM/360 INTERFACE..................................... 19 4.1 Command Interface Operations............. 22 4.2 Service Interface Operations............ 26 4.3 System/360 Control Program Operations.... 36 Start I/O............................... 37 Halt I/O...-C............................ 37 Test I/O................................. 38 Programming Notes........................ 39 V ARCHITECTURE OF SYSTEM/360 INTERFACE.......... 39 APPENDIX A....OCO.............................. 62 APPENDIX B.......................................... 73 APPENDIX C.........O...O.......................... 83 ANALYSIS OF SELECT LATCH CIRCUITRY.............. 85 APPENDIX D............................................ 88 ADDITIONAL CONSTRUCTION DETAILS................. 90 D1 System Configuration................... 90 D2 Power Control Unit.O.................. 92 D3 IBM/DEC Interface Modules.............. 94 ix

TABLE OF CONTENTS (cont'd) Page APPENDIX E......................................... 99 APPENDIX F......................................... 145 Fl The Test Panel............................ 147 F2 Diagnostic Procedures.................... 149 xi

LIST OF FIGURES Figure Page i The Data Concentrator..........i........ iv ii The Test Panel of the Interface....... v 1 Channel-Control Unit Interface Lines.... 3 2 Initial Selection....................... 7 3 Service Cycle (Burst Mode)............. 10 4 Interface Disconnect.................... 13 5 Control Unit Busy....................... 16 6 Register Bit Assignments................ 21 7 Initial Selection-HIO................. 23 8a Service Cycle-Stop..................... 27 8b Service Cycle-End....................... 28 9 Principal Interface Components.......... 40 10a AR1, BR1, AR2 Registers................ 43 10b BR2 and CTL Registers...,,.............. 44 11 PDP-8 Data Paths........................ 45 12 Bus Gating.............................. 46 13 Select Interception..................... 48 14 Channel Seizure..,..................... 49 15 Command Storage/Proceed................ 51 16 Status.................................. 52 17 Parity Check........................... 53 18 BR2 Gating.............................. 55 19 Command End,.e...,.....,,............ 56 20 Service End.......................... 58 21 Cycle Reset.......................... 59 22 Control Operation Decoder and Channel Request Flip-Flop....................... 60 Al Channel Seizure......,................ 64 A2 Command Byte Storage................. 65 A3 Command Status Presentation............ 66 A4 Special Status Presentation............. 67 xiii

LIST OF FIGURES (cont'd) Figure Page A5 Service Cycle............................ 68 A6 Service Cycle End......................... 69 A7 PDP-8 Data Break Cycle.................. 70 B1 Initial Selection....................... 73 B2 Service Cycle.......................... 73 B3 Control Unit Busy..................... 75 B4 Interface Disconnect................... 75 B5 Channel Seizure................... 77 B6 Gate Transfer........................... 77 B7 Major State-Service Cycle.............. 79 B8 Data-Break Service Cycle................ 79 B9 Test I/O Loop.,......................... 81 B10 SEL OUT/SEL IN Delays.................. 81 C1 Select Latch.,..................... 86 C2 Select Latch State Table................ 87 D1 Physical Configuration.................. 91 D2 Power Control Unit..................... 93 D3 DEC to IBM Bus Driver Module............. 95 D4 IBM to DEC Bus Receiver Module....., 97 D5 SEL OUT Bypass Module...................... 98 E1 AR.............C O..................... 101 E2 BR1..................................... 102 E3 AR1/BR1 Pulsing......................... 103 E4 AR2...C oooooo................e........ 104 E5 BR20................................... 105 E6 AR2/BR2 Pulsing....................... 106 E7 BR2 Gating........,................... 107 E8 Control Register........................ 108 E9 Clearing the Control Register........... 109 E10 Control Operation Decoder............... 110 Ell IOT DetectionO eccc.................. 111 xv

LIST OF FIGURES (cont'd) Figure Page E12 Transfer Direction......... 112 E13 Address Register Compare................. 113 E14 Address Detect......................... 114 E15 Channel Request......................... 115 E16 Select Interception...................... 116 E17 Channel Seizure.......................... 117 E18 Command Storage.......................... 118 E19 StatusC...... o o... 119 E20 Command Cycle End........................ 120 E21 Data Break....................... 121 E22 Data Break..e...................... 122 E23 Service Cycle Reset..................... 123 E24 Command Cycle Reset. System Reset........ 124 E25 BUS OUT Parity........................... 125 E26 BUS IN Parity..,........................... 126 E27 BUS OUT Parity Check. BUS IN Parity Check.....O............................ 127 E28 BUS-TAGS OUT Gating..................... 128 E29 Select Out Gating...................... 129 E30 BUS-TAGS in Gating...................... 130 E31 On-Line/Off-Line Circuitry............. 131 E32 Test Panel Push Button Gating............ 132 E33 Connectors Positions..................... 133 E34 PDP-8 Cable Connectors (Page 1 of 3)..... 134 E34 PDP-8 Cable Connectors (Page 2 of 3).... 135 E34 PDP-8 Cable Connectors (Page 3 of 3)..... 136 E35 IBM Cable Connectors (Page 1 of 2)....... 137 E35 IBM Cable Connectors (Page 2 of 2)....... 138 E36 Test Panel Connectors (Page 1 of 3)...... 139 E36 Test Panel Connectors (Page 2 of 3)..... 140 E36 Test Panel Connectors (Page 3 of 3)...... 141 xvii

LIST OF FIGURES (cont'd) Figure Page Fl Test Panel Layout........................ 148 xix

SYSTEM/360 INTERFACE ENGINEERING REPORT I. INTRODUCTION The System/360 interface appears to the resident System/360 control program as similar to the 2702 Transmission Control. This approach is felt more fruitful in the face of heavy commitments to software support provided by the manufacturer. Its pertinent features are as follows: a. The interface recognizes a class of device addresses that are assigned according to the conventions established by IBM. b. Recognition of command codes and generation of status responses are in most cases under the control of the resident PDP-8 control program. c. Several buffer registers isolate the two machines so that the exchange of control and data information does not affect the timing of other control units that may be attached to the channel. d. Data transmission between the two machines proceeds in a byte-interleaved or burst-mode fashion at an aggregate data rate which may be programmed by the PDP-8 and indirectly by the System/360. The System/360 interface consists of two principal components: the command interface, which services initial commands issued by the System/360 control program through the multiplexor channel, and the service interface, which transmits data and status information between the two machines. Both of these interfaces operate independently and in an overlapped fashion except at the channel interface circuitry itself, which is necessarily sequential in operation. At the channel interface the entire PDP-8 system appears to the System/360 as a control unit and accesses the interface transmission lines in the fashion prescribed for these devices. - 1 -

II. CHANNEL INTERFACE LINES The System/360 interface is connected to the multiplexor channel via a set of 34 lines which are common to all other control units serviced by the channel. All of these lines except one are simply looped through the interface and attached to the various bus drivers or receivers as required. Thus in off-line or power-down situations it is not necessary to physically reroute or switch these lines, but merely to gate off the bus drivers and receivers. The one exception (the SEL OUT line) is physically broken at the interface. The interface-inbound SEL OUT line is routed to a terminator and bus receiver, while the interface-outbound SEL OUT line is routed from a bus driver. During normal equipment operation, signals received on the inbound SEL OUT line are processed internally and then propagated to the next control unit via the outbound SEL OUT line. During off-line or power-down conditions the terminator, bus receiver, and driver are bypassed with a relay. The interface lines and their nomenclature used throughout this document are summarized in Figure 1. Following is a brief description of the function of each of these lines. For greater detail, the reader is referred to the pertinent IBM publications. BUS OUT. A set of nine lines, including a parity line, which propagates outbound information a byte at a time from the channel to all control units serviced by the channel. The information is conditioned by the outbound tag lines (ADR OUT, CMD OUT, SRV OUT) actuated by the channel and may represent a device address, a control unit command, or an outbound data byte. BUS IN. A set of nine lines, including a parity line, which propagates inbound information a byte at a time from a selected control unit to the channel. The information -2

-3BUS OUT CHANNEL BUS IN CONTROL UNIT ADR OUT CMD OUT OUTBOUND TAGS SRV OUT ADR IN STA IN INBOUND TAGS sRV IN SEL OUT SEL IN OP L OUT OPL IN SELECTION HLD OUT CONTROLS SUP OUT _ REQ IN MTR OUT* MTR IN* METERING CLK OUT* _ CONTROLS *NOT USED FIUGRE 1. CHANNEL-CONTROL UNIT INTERFACE LINES

-4is conditioned by the inbound tag lines (ADR IN, STA IN, SRV IN) actuated by the control unit and may represent a device address, a status byte, or an inbound data byte. Outbound Tagso Three lines: ADR OUT, CMD OUT, and SRV OUT used to condition information on BUS OUT. If ADR OUT is up, the channel is attempting to gain initial selection of a control unit in order to transmit a command byte. When selection is achieved, CMD OUT indicates that a command byte is available on BUS OUT for interpretation by the control unit, SRV OUT is used as an interlock during data and status transmission cycles. These tags are also used in combination during certain control sequences not involving the use of BUS OUT. Inbound Tags. Three lines: ADR IN, STA IN, and SRV IN used to condition information on BUS IN. If ADR IN is raised by the control unit, the information provided on BUS IN identifies the particular device requesting channel service. If STA IN is raised by the control unit, the information on BUS IN is the status byte pertaining to the device, and if SRV IN is raised, the control unit is requesting channel service for a data byte. Selection Controls. Seven lines controlling the seizure and sequencing of transmission operations between the channel and the control unit. SEL OUT and SEL IN form a loop from the channel outbound through all control units in turn and finally inbound to the channel. A signal propagated on this line is intercepted by a control unit depending upon its position along this loop, which in effect establishes its priority for channel service. OPL OUT and OPL IN are conditioned by the channel and the control unit respectively and indicate the availability and connection

-5status of each of these devices. In particular, a control unit raises OPL IN when it has achieved selection on the interface, and is held up for the duration of the particular channel-control unit sequence involved. HLD OUT/ is used in conjunction with SEL OUT to minimize propagation delays through the select circuitry of the control units. SUP OUT is raised by the channel to inhibit control unit seizure of the interface under certain conditions. REQ IN is raised by each control unit requesting channel service and conditions the channel to poll the interface for seizure. Certain combinations of these selection control lines are used to indicate special conditions such as system and selective reset, and in conjunction with the outbound tag lines to indicate special conditions such as interface disconnect. Metering Controls. Three lines used to condition usage meters on the various devices of a System/360 complex. The equipment described herein makes no use of these lines. III. CONTROL SEQUENCES A number of control sequences are possible between the channel and the interface and, of these, most have several variations. All sequences can be grouped in one of three classes, however: 1. those involving initial-command selection, 2. those involving data transmission, and 3. those involving presentation of ending status. For any one device, these sequences proceed in the order named; that is, the device is selected and logically connected to the channel, then transmits its data, and finally transmits status regarding the condition of the I/O device at the conclusion of

-6the operation. However, certain conditions can occur which are asynchronous to the progression of an operation through the states corresponding to the three principal sequences. Such acoditions include those that halt data transmission and those that test device status during the course of an operation. Some of these can be produced by the channel without intervention by the program. The operation of the interface using typical sequences is summarized below. Additional details of operation in exceptional cases are discussed in the pertinent IBM publications, 3o1 Initial Selection Sequence Figure 2* shows the sequence of interface tag line signals during an initial selection procedure. This sequence is used for all channel commands and, in addition, for the Test I/O (TIO) sequence. The sequence begins when ADR OUT is raised by the channel while a device address is on BUS OUT. If the address has odd parity and lies within the block recognized by a control unit, that control unit prepares to seize the channel when SEL OUT rises on the interface. When this occurs, the control unit a. inhibits propagation of SEL OUT to the next lowerpriority control unit on the interface, bo raises OPL IN to indicate to the channel that the control unit has in fact seized the interface, and c. internally stores the device address presented on BUS OUT. The channel then acknowledges OPL IN by dropping ADR OUT. The control unit then places the just-stored device address on BUS IN with odd parity and raises ADR IN. This returned address is checked by the channel for correct parity and for match * Wave forms shown in bottom of figures correspond to interface circuitry signals described in Section V. Timing information is given in the form of channel sequence photographs in Appendix Bo

ADR OUT SEL OUT OPL IN ADR IN CMD OUT STA IN SRV OUT OUR ADR I CU SEL r I CMD CYC I I CMD DLY L CHL SRV | I CMD END. FIGURE 2. INITIAL SELECTION

-8against the address first transmitted on BUS OUT. If these tests fail, the channel performs a malfunction reset, which affects all I/O devices attached to the channel. Depending upon the particular machine model, this operation may result in a processor check or in a bit set in the Channel Status Word (CSW) stored as the result of the channel operation. Following reception of a correct address on BUS IN, the channel next places the command byte (all zero bits for a TIO, nonzero for a valid channel command) on BUS OUT, and raises CMD OUT. The control unit stores the channel command internally and checks the byte for odd parity. Following this operation, the control unit drops ADR IN, which the channel acknowledges by dropping CMD OUT, an invitation for the control unit to present a status byte. In most IBM control units, the allowable channel commands are well prescribed and represent only a few of the possible 255 codes. Acco-rdingly, it is possible to detect immediately upon storage of the channel command byte whether the control unit can accept the particular command or not. Thus the control unit has the option of either accepting the command by presenting the channel with an all-zero status byte or rejecting the command with a status byte containing the unit check bit. In the equipment described here, the command may undergo analysis by the PDP-8 program, a process which may require a lengthy period compared to the channel selection sequence. Accordingly any channel command, other than TIO, is always accepted, even if it does not have odd parity. It is up to the PDP-8 program to interpret the particular command code and to transmit possible rejection using an ending-status presentation containing the unit check bit. Thus, following the acceptance of the channel command, the control unit places an all-zero status byte on BUS IN and raises STA IN, to which the channel responds with SRV OUT. The control unit now drops all inbound tag and bus lines and disconnects from the interface. If the channel forces burst mode at this time, SEL OUT will still be up at the control unit,

-9and a sequence of SRV IN-SRV OUT signals is expected by the channel to transmit the data associated with the operation. However, the multiplex channel will force burst mode only in connection with an Initial Program Load (IPL) operation. Therefore the equipment considered here is not normally expected to operate under channel-forced burst mode conditions. 3~2 Service Cycle Figure 3 shows the sequence of interface tag line signals during a service cycle procedure. This sequence is used for all data and status byte transmission between the channel and the control unit, In the byte-interleaved mode, one such sequence is executed for each data byte separately. In the control-unit-forced burst mode, the initial part of the service cycle sequence is followed by alternate SRV INSRV OUT pairs. The service cycle sequence differs from the initial selection sequence in that the transmission is initiated by the control unit rather than by the channel. A control unit requesting service raises the REQ IN tag line when the SUP OUT tag line is down at the control unit. (Certain sequences are expected to override the SUP OUT signal; see below.) When the channel next polls the control unit interface by raising SEL OUT, the highest priority control unit requesting service inhibits the propagation of SEL OUT, places its device address on BUS IN, and raises OPL IN and ADR IN, The channel checks the device address for odd parity, retrieves the addressed subchannel status in its active registers, and issues CMD OUT. The control unit recognizes CMD OUT as permission to proceed with the operation, and it next drops ADR IN. When the channel drops CMD OUT the control unit raises either ao STA IN and places a status byte on BUS IN,

SUP OUT REQ IN SEL OUT OPL IN ADR IN CMD OUT SRV IN SRV OUT CHL REQ CU SEL SRV CYC I I CMD DLY CHL SRV BRK REQ SRV HLT FIGURE 3. SERVICE CYCLE (BURST MODE)

-11b. SRV IN and places a data byte on BUS IN for transmission to the channel, or co raises SRV IN and waits for a SRV OUT channel acknowledgment that a data byte has been placed on BUS OUT for transmission to the control unit, If the device address does not have odd parity, the channel performs a malfunction reset, If a status byte does not have odd parity, an interface control check condition is generated. If, in the case of channel-inbound transmission, a data byte does not have odd parity, a channel data check condition is generated. Depending upon the particular machine model, these indications appear as a processor or memory check and as a bit set in the CSW stored as the result of the channel operation. The channel acknowledges the receipt of a data or status byte, as appropriate, with SRV OUT. This response is also used by the control unit to verify the presence of a data byte on BUS OUT where appropriate. The channel may alternatively respond to SRV IN with CMD OUT, indicating that the data region in its main storage is exhausted, and may respond to STA IN with CMD OUT, indicating that the status byte is to be stacked in the control unit for later presentation to the channel. In any case, the control unit responds to an outbound tag line at the end of the service cycle sequence by dropping all inbound tags and disconnecting from the interface. The channel is now free to continue polling for other control units on the interface or to issue new commands to the same or other control units. In particular, under some conditions, certain channel-generated commands may be directed to a busy control unit before device-end status has been serviced by the channel (see below).

-123.3 Special Sequences During the course of normal equipment operation and in certain abnormal situations, special control-unit interface sequences may be generated by the channel. These fall into two classes: those intended to stop device activity by request from the System/360 program, and those generated either by manual intervention or by the machine itself for the purpose of temporarily disconnecting the device from the system. The first class of sequences includes the interface disconnect sequence generated by the channel in response to a Halt I/O (HIO) instruction executed by the System/360 program. Such a sequence can occur at any time, either within an initial selection or a service cycle sequence. The sequence is signaled after the device address has been checked by the channel and when ADR OUT is up at the control unit while SEL OUT is down. The sequence usually occurs before the command byte is stored on initial selection, but may occur after CMD OUT rises during a service cycle. Figure 4 shows an interface disconnect sequence on initial selection. Following such a sequence, the control unit is expected to remove immediately all signals from the interface and to present ending status following its device operation. The ending status is to be transmitted only if the associated System/360 subchannel was working at the time of the sequence and may be cleared by a channel-generated TIO command prior to program intervention. The second class of sequences includes the selective and system reset sequences generated by the channel in response either to manual intervention or equipment malfunction. The system reset sequence is indicated when both OPL OUT and SUP OUT are down at any control unit. This sequence occurs when power is first applied to the system, or when either the SYSTEM RESET, LOAD, or PSW RESTART pushbuttons are depressed on the System/360 operator's control panel. The selective

-13ADR OUT SEL OUT OPL OUT ADR IN OUR ADR 1 CU SEL I CMD CYC CMD HLT FIGURE 4. INTERFACE DISCONNECT

-14reset sequence is indicated when OPL OUT is down while SUP OUT is up at a control unit during an operation involving that control unit. This sequence occurs when the channel has detected a malfunction of the control unit or channel circuitry. Such a malfunction may involve invalid BUS IN parity, improper signal sequencing, or excessive sequence timings. In the case of either the system or selective reset sequences, the control unit is expected to disconnect from the interface without presenting ending status for the operation. Since the control unit may be reselected immediately following a reset sequence, the control unit must appear busy to the channel while any internal time-dependent reset operations are completed. 3.4 Polling Operations Since both the channel, its attached control units, and their attached devices operate asynchronously with respect to each other, conventions for device polling and acknowledgment are required. The polling-acknowledgment conventions appear at three levels: a. during the initial selection of a control unit, b. during the channel seizure procedure by a control unit, and c. during the selection and deletion procedures of a device attached to a control unit. Additional conflicts for both channel and subchannel access by the System/360 program are resolved by the channel and in some systems by the channel controller. The channel selects an attached control unit with the initial selection sequence. If the control unit is free to accept a command (without respect to the status of its attached devices), it responds with the sequence shown in Figure 1. If not, then the control unit responds with the

-15control unit busy sequence shown in Figure 5. This sequence begins in the same fashion as the initial selection sequence; that isthe channel places a device address on BUS OUT and raises ADR OUT. When SEL OUT rises at the control unit servicing the device, and if the control unit is busy servicing some other device, the control unit responds by placing a status byte on BUS IN and raising STA IN. The channel responds with SRV OUT unconditionally, following which the control unit disconnects from the interface. Note that this sequence does not require the control unit to store the device address presented on BUS OUT or to present stored status for the device, even if it is available somewhere in the control unit. The status byte presented to the channel during the control unit busy sequence may take two forms. One form includes both the status modifier and busy bits, which by convention inform the System/360 program that the control unit is busy and will present a status byte containing the control unit end bit at some future time. The other form includes all three of these bits, which by convention inform the System/ 360 program that the control unit is temporarily busy and that the operation which was rejected by the control unit should be immediately retried. The second form of status byte is used when the control unit busy condition is expected to last somewhat less than a millisecond, the interrupt processing time of typical System/360 programs, and the first form is used in all other cases. When the channel is not busy with some internal operation and is not in the process of issuing an initial selection sequence directed to some attached control unit, the channel normally reverts to the polling mode. In this mode the channel interprets REQ IN as a request to poll the interface with SEL OUT, an operation that presumably will result in some control unit raising OPL IN. In some models of the System/360 product line, the polling mode may be entered at interesting times, for instance while the channel is retrieving the Channel

- 16ADR OUT SEL OUT STA IN OUR ADR CU SEL I CU BUSY I L FIGURE 5. CONTROL UNIT BUSY

-17Address Word (CAW) or a channel command from main storage. Since the System/360 CPU is interlocked between the time that an I/O instruction is decoded and the time that the channel or the addressed device responds, it is important that the control unit sequence following REQ IN be as short as possible. In extreme cases of control unit delay during a Start I/O (SIO) operation (either addressed to the control unit or not), a processor check may occur when the System/360 CPU microprogram attempts to update its interval timer. Data byte transmission operations for any particular device take precedence over all other channel operations, and are guaranteed to proceed without interference to the subchannels connected to other devices serviced by the channel. Status byte transmission operations, on the other hand, are considerably more involved and may take one of two alternate forms depending upon whether the subchannel in question is busy or not. An ending status presentation to a busy subchannel must contain the channel end bit, but may contain others as well. Such a status presentation will always be accepted by the channel with a SRV OUT response to a STA IN during the service cycle. Once this status has been stored in local subchannel storage, the channel requests a System/360 CPU interrupt which causes a channel status word (CSW) containing the subchannel status to be stored in main storage. An ending status presentation to a subchannel not in the busy state will be automatically stacked in the control unit with a CMD OUT response to a STA IN tag during the service cycle. Before stacking the status at the control unit, however, the channel stores the device address of the requesting control unit in a special register called the Interrupt Buffer (IB) (or Interrupt Queue). At this time the channel requests a System/360 CPU interrupt, and, when granted, causes a channel-generated pseudo-Test I/O command to be issued to the device whose address is stored in the IBo The control unit in question now furnishes this status as the result of an initial selection sequence rather than the service

-18cycle sequence originally requested. Not all IBM control units can tolerate this interesting procedure; and, in fact, wellknown machine hang-ups revealed in IBM documentation in connection with the 2702 Transmission Control are due to the failure of that device to process the pseudo-Test I/O. 3~5 Equipment Failure Diagnostics Most control unit component malfunctions can be diagnosed by the channel; and, in many cases, the System/360 control program can recover from the malfunction condition, record the failure, and continue system operation. In the case of the programmable control unit equipment considered here, certain invalid programming sequences can also produce such malfunction indications to the channel. Six malfunction conditions are recognized by channel circuitry as probably originating in an attached control unito These may or may not be detected separately or as distinct from a processor check, depending upon the machine model: 1. Channel timeout. The System/360 CPU had not been released a pre-set interval (typically 150 microseconds) following issuance of an I/O instruction. 2, Address-in check. The channel detected a parity error on the address received from the control unit during a service cycle. 3. Status-in check. The channel detected a parity error on the status byte received from the control unit. 4. Incorrect selection. The address received from the control unit during an initial selection sequence does not match that transmitted by the channel. 5, No response. The control unit did not respond to re-selection on a chain-command operation. 60 Incorrect tag sequence. The control unit disconnected from the channel before the channel dropped the SEL OUT tag lineo

-19Any of these malfunctions cause the channel to assume an interface control check condition, which may be indicated as a bit set in the CSW stored as the result of the operation and further detailed in the log-out area peculiar to the model. Condition 6 can occur on the multiplex channel only as the result of an Initial Program Load (IPL) operation and will always be produced when such an operation is directed to a control unit such as the 2702 Transmission Control or the interface equipment described herein. IV. PROGRAMMING CONSIDERATIONS FOR IBM SYSTEM/360 INTERFACE The System/360 interface is composed logically of two subinterfaces: the command interface and the service interfaceo The command interface stores the channel command and device address developed during the multiplex channel initial selection sequence and presents the appropriate status byte to the channel to terminate the sequence. At the conclusion of the sequence, appropriate bits are set in a control register to indicate the particular type of sequence to the PDP-8 interrupt processoro The service interface supervises data break operations between the PDP-8 and the multiplexer channel. This interface is started by the PDP-8 program by loading a three-bit command code in the control register, following which three-cycle data break operations occur for data transmission between a block of PDP-8 memory and the channel. Both data and ending-status bytes are transmitted in this fashion. At the conclusion of the operation, either at channel-stop or word-count-equal-zero times, bits are set in the control register to indicate the termination condition to the PDP-8 interrupt processor; Five registers in the interface are available to the PDP-8 program. Two of these, AR1 and BR1, are used in connection with the command interface, while another two, AR2 and BR2, are used in connection with the service interface.

-20The fifth register, CTL, is common to both interfaces, and serves as the controlling element for the various operations. The AR1, BR1, and AR2 registers can be read, cleared, and loaded (one's-transfer) from the AC of the PDP-8. The BR2 register is connected only to the data break facility. The CTL register can be read, inverted, and tested bit-by-bit with appropriate microinstructions(see below). Some of these registers need not be read or loaded during the common interface operations; the general read/load facility is included primarily for diagnostic utilitieso Figure 6 illustrates the coding of the various register bit assignments and establishes the IOT microinstruction codes for their access. The operation of the control register invert-undermask (CTL INV) and test-under-mask (CTL TST) microinstruction is as follows: Both of these instructions address the twelve control register bits in one-to-one correspondence with the bits of the ACo The operation of the CTL INV microinstruction results in a bit-wise inversion of each bit in the control register for which the corresponding bit in the AC is a one. The operation of the CTL TST microinstruction results in a single-instruction program skip if each control register bit which is in correspondence with a one bit in the AC is a one. If any control register bit in correspondence with a one bit in the AC is a zero, no program skip is generated. An unconditional skip is generated if the AC contains all zeros. The RD, CLR, and WR modifiers may be applied to the registers designated AR1, BR1, and AR2. The sequence of the IOP pulses is such that the micro-operations are performed in the order listed. The RD, TST, and INV modifiers may be applied to the register designated CTL. The micro-operations are performed in that order. Appendix F illustrates segments of code that are applicable in common programming situations.

CHANNEL DEVICE ADDRESS ADR PREFIX- -\/ — - ADR OFFSET - AR1(630X) PDP-8 0 1 2 3 4 5 6 7 8 9 10 11 AR2(632X) YS///g//// ///I I I I I 10P1 RD 2 CLR 360 0 1 2 3 4 5 6 7 4 WR,f —--'-~ —--- CHANNEL COMMAND PDP-8 0 1 2 3 4 5 6 7 8 9 10 11 BR1(631X) - READI 10P1 RD KW/V4AMMIMI ~ 1-WRITE 2 CLR 36 0 0 1 2 3 4 5 6 7 4 WR f —----- " DATA BYTE PDP-8 0 1 2 3 4 5 6 7 8 9 10 11 BI R2(DATA BREAK) |____________________________////1Y///'_____________ I___I__I__I_ I I I | DATA TRANSMISSION 360 0 1 2 3 4 5 6 7 f —--— ~ —--— r STATUS BYTE PDP-8 0 1 2 3 4 5 6 7 8 9 10 11 A STA CU ISCHAN DEV UNIT UNIT BR2(DATA BREAK) MOD END I END I END |CHECK IXCPT STATUS PRESENTATION 360 0 1 2 3 4 5 6 7 c- ~ORDER- ) ADVISORY - COMMAND INT. -- SRV. INT. PDP-b 0 1 2 3 4 5,6 7 8 9 10 11 CTL (633X) -1 2 CMD CMD SRV ICMD CMD CMD S RV SRV 1OP1 RD CHN PCK PCK I RST I STK HLT END HLT END 2 TST V_ —- CAUSE PROG. INTERRUPT J 4 INV FIGURE 6. REGISTER BIT ASSIGNMENTS

-224.1 Command Interface Operations (Figure 7) Three of the four System/360 I/O instructions will result in a channel sequence in the command interface, and two of these will normally end by interrupting the PDP-8 program. An SIO instruction executed by the System/360 will result in one or more channel commands being fetched from System/360 core storage and transmitted to a control unit. If the device address specified in the SIO instruction lies within the block recognized by the command interface and if the interface is not busy (i.e., holding a previously issued command), then the interface will seize the channel and store the device address in AR1 and the command byte in BR1. If the channel sequence is generated as a result of a valid channel command,the command byte stored in BR1 must be nonzero, and will be an odd number if channel-outbound service is indicated and an even number if channel-inbound service is indicated. Note that in order for the selection sequence to be initiated, the parity of the device address must be odd. If this parity is odd and yet the parity of the command byte is not odd,then the CMD PCK bit of the control register is set. This situation, interpreted as a BUS OUT parity check, does not affect the progress of the selection sequence or the status byte subsequently transmitted to the channel. At the conclusion of the initial selection operation, the CMD END bit of the control register is set if the channel accepted the interface-generated all-zero status byte and;the CMD STK bit if the channel rejected the byte. If the channel sequence is generated as the result of a valid channel command, an occurrence of the later situation must be interpreted as a System/360 machine check.* When either the CMD END or CMD STK bits are set,the PDP-8 is interrupted. * Note that in current System/360 channel equipment, stack on initial selection iC-MD STK) never occurs on an all-zero status byte. In the case of a nonzero status byte, stack on initial selection will be generated only in certain cases

-23ADR OUT CMD OUT IBO$O | STA IN BI=O SRV OUT CMD END INITIAL SELECTION-STATUS ACCEPTED ADR OUT CMD OUT! BO-O = STA IN r BI=10 CMD OUT CMD STK INITIAL SELECTION-TIO STATUS STACKED ADR OUT SEL OUT CMD HLT INITIAL SELECTION-HIO FIGURE 7.

-24A Halt I/O (HIO) instruction executed by the System/360 causes a special channel sequence to be transmitted to a control unit. If the device address specified in the HIO instruction lies within the block recognized by the command interface and if the interface is not busy, then the interface will seize the channel and store the device address in AR1. BR1 will be forced to an all-zero byte. This sequence ends by setting the CMD HLT bit of the control register. A selective reset sequence generated by the channel during the progress of any command interface operation will also set this bit.** When the CMD HLT bit is set, the PDP-8 is interrupted. A Test I/O (TIO) instruction executed by the System/360 causes a special channel sequence which is identical to the SIO sequence except that the command byte contains only zero bits. If the device address specified in the TIO instruction lies within the block recognized by the interface and if the interface is not busy, then the sequence ends by the transmission to the channel of a status byte containing only the status-modifier bit. If the channel accepts this byte, the interface is released and the PDP-8 is not disturbed. If the channel rejects the status byte, then the CMD STK bit is set in the control register and the PDP-8 program is interrupted. It is the responsibility involving command chaining. Since the command interface generates a nonzero status byte only in response to a Test I/O instruction, and since this "instruction" may not occur as an element of a channel-command sequence, it is not at all clear from extant documentation whether the CMD STK bit can ever be set in any likely programming situation. ** A selective reset sequence is generated by channel equipment, at least in some models, in response to a status presentation of bad parity and possibly in response to an invalid tag-line sequence. A presentation of a device address of bad parity in conjunction with ADR IN will usually result in a channel-generated system reset sequence. A presentation of a data byte of bad parity is not always detected by the channel itself, but may be detected by the CPU or memory bus register circuitry and cannot be differentiated from parity errors due to other causes.

-25of the PDP-8 program to retransmit a status byte containing the status modifier bit via the service interface when allowed by the channel (however, see preceding footnote). Note that this behavior in connection with the TIO instruction is consistent with that of the IBM 2702 Transmission Control and implies, in particular, that the command interface cannot provide status in response to a program-generated TIO instruction. Note further that pseudo-TIO instructions can be generated by the channel without intervention by the program, and in these cases the command and service interfaces must cooperate in the successful transmission of a status byte to the channel. Such situations arise in connection with ending-status transmissions to subchannels not in the busy state (see below). If a system reset sequence is generated by the channel, either as the result of power-up, initial program load, or manual operator intervention, the CMD RST bit of the control register is turned on. This operation clears all other bits of the control register and results in a PDP-8 program interrupt. All System/360 registers and subchannels are reset and placed in the available state. Pending data and status transmissions on the part of the PDP-8 should be suspended. If any System/360 channel operation is directed to the command interface when either the CMD STK,CMD RST,CMD HLT, or CMD END control register bits are set, the command interface will immediately reject the operation with the control unit busy sequence, which involves the transmission to the channel of a status byte containing the status modifier, busy, and control unit end bits. This sequence is by convention interpreted by both the channel and the System/360 program as an indication to immediately retry the operation. For this reason, the resident PDP-8 program should give high priority to command interface interrupts, since the System/360 program may be hung up during the response interval. The PDP-8 interrupt processor clears such interrupts by inverting the

-26appropriate bit of the control register to a zero. Previous to this operation, meaningful contents of both the AR1 and BR1 register must of course be preserved in core storage by the interrupt processor. It is possible in some System/360 programming systems that tight TIO or HIO loops may be executed under certain conditions. In the case of the HIO instruction, the resultant load on the command interface will most certainly lock up the PDP-8 interrupt processor, which then must clear the System/360 condition, presumably by the transmission of ending status to the channel. In any case, the PDP-8 program must be aware of situations inherent in the particular parent System/360 supervisory programming system in which TIO or HIO loops are involved or in which the multiplex channel is masked against interrupts, and must give high priority to channel service under those conditions.* 4.2 Service Interface Operations (Figure 8) In all service-interface operations, a block of data is transferred either channel-inbound or channel-outbound. The three-cycle data break facility of the PDP-8 is used for this block transfer operation, which once initialized by the PDP-8 program, continues until the PDP-8 residual word count decrements to zero, until the channel detects that a System/360 core memory storage area is exhausted, or until the System/360 program issues an HIO instruction. All transmission operations make use of only the low-order eight * A typical instance of a tight TIO loop occurs after presentation of a unit check to certain present System/360 programming systems. Programming constraints imposed by other control units, in particular the 2841, require that a TIO be directed to the control unit immediately following a unit check. In such a case, the selector channel must be disabled before issuance of the TIO. In such cases, the same behavior may exist on the multiplexror channel, a behavior which is strongly disadvised, since not only the command interface but other IBM control units as well will hang up the system for some time.

- 2 7 - -27CHL REQ SEL OUT I, im~~~~~~~~~~~~~~~~~, SRV IN I SRV OUT BRK REQ. SERVICE CYCLE (BYTE-INTERLEAVED MODE) CHL REQ SEL OUT SRV IN CMD OUT CMD HLT SERVICE CYCLE-STOP Figure 8a.

CHAN REQ SRV IN BO REQ SR II SRV OUT SRV END WC=O BRK REQ PRP END WC=O CHAN REQ SEL OUT BI REQ SRV IN SRV OUTI SRV END SERVICE CYCLE-END FIGURE 8b.

-29bits of a PDP-8 core memory locationo The four high-order bits are ignored in channel-inbound operations, and are replaced by zeros in channel-outbound operations, Either data bytes or status bytes may be transferred using the appropriate interface order codes (see below). In the case of status byte transmission, the service interface will automatically represent status to the channel following a stack-status channel sequence, All data and most status operations involving the service interface take place only when the associated System/ 360 subchannel is busy, that is when a valid channel command has been stored by the command interface. If the low-order bit of the channel command is a zero, then channel-inbound service is requested and the PDP-8 program must select the interface-outbound data operation. If the low-order bit of the channel command is a one, then channel-outbound service is requested and the PDP-8 program must select the interfaceinbound data operation. Violation of these constraints will usually result in either a channel check, processor check, or storage check, depending upon the particular System/360 model. Status presentation to the channel when the subchannel is busy will not usually be stacked by the channel; and, if a status presentation happens to be stacked, it can eventually be cleared by re-presentation to the channel. If the subchannel is available to the System/360 program, then any status presentation will be automatically stacked and must be cleared by a channel-generated pseudo-TIO command. Such considerations dictate a careful organization of the PDP-8 program to avoid System/360 hangups due to conflicts at the command and service interfaces, All service interface operations involve a programmed procedure which

-30a. presets the word count and current address locations accessed by the three-cycle data break facility, b. loads AR2 with the specified device address, and finally c. loads a three-bit order code into the control register. The service interface then proceeds with alternate channel sequences and three-cycle data break operations until either the PDP-8 word count is decremented to zero, or until a stop sequence is generated by the channel. The appropriate bits are then set in the control register and the PDP-8 program is interrupted. The interrupt is cleared by inverting the appropriate control register bits to zeros. In the case of data operations, operation can be selected in either the byte-interleaved or burst mode. The byte-interleaved mode is appropriate for either low-speed operations with all models or both low- and high-speed operations with the higher-numbered models. Depending upon the width of the data paths to core memory and the degree of CPU involvement in the multiplexor channel operations, the burst mode may be appropriate for high-speed operations with the lower-numbered models. A channel-outbound byte-interleaved data operation is started by loading an octal 2 into the high-order three bits of the control register. An octal 3 starts the same operation in burst mode. These orders initiate a data operation from the channel to the PDP-8 core memory. When the PDP-8 word count decrements to zero, the SRV END bit is set in the control register. When a stop sequence is transmitted by the channel in response to a service request by the interface,the SRV HLT bit is set in the control register. No data byte is transmitted to the PDP-8 core memory on a SRV HLT cycle.

-31This operation is suppressible, That is, if the channel is undergoing some critical sequence which should not be interrupted for lower priority operations, the service interface will suspend data transmission. Such is the case when another control unit on the channel is operating in burst mode or when certain status operations are pending at the channel. If an operation is not outstanding in the System/360 subchannel addressed by AR2, then, depending upon the model, the channel will either respond unconditionally with a stop sequence or an interface disconnect sequence, either of which sets the SRV HLT bit of the control register, or hang up the channel. If a data byte presented by the channel does not have odd parity, then the SRV PCK bit is set in the control register. This condition does not affect the further progress of the operation and in particular does not cause a PDP-8 program interrupt. A channel-inbound byte-interleaved data operation is started by loading an octal 4 into the high-order three bits of the control register. An octal 5 starts the same operation in burst mode. This order initiates a data operation from the PDP-8 core memory to the channel. When the PDP-8 word count decrements to zero, the SRV END bit is set in the control register, The last byte fetched from PDP-8 memory on the SRV END cycle is transmitted to the channel. When a stop sequence is transmitted by the channel in response to a service request by the interface, the SRV HLT bit is set in the control register. The last byte obtained from PDP-8 memory on a SRV HLT cycle is then lost whether or not the SRV END bit is set during the same cycle. The comments above under channel-outbound diata transmission concerning data suppression and operation with an available subchannel apply also to channel-inbound data transmission~ Odd parity is automatically generated on all channelinbound operations whatever their nature, and the SRV PCK control-register bit is never affected by such operations.

-32When either the SRV END or the SRV HLT control register bits become set as a result of a service interface operation, the PDP-8 program is interrupted. The interrupt processor can determine how many data bytes have been successfully transmitted by inspecting the residual word count stored by the three-cycle data break facility and applying the modifying factors shown in Table 1. If the SRV HLT bit is not on at the conclusion of an operation, the opportunity exists to transmit additional data blocks. If both the SRV HLT and SRV END bits are set in the control register following a channel-outbound data operation, an interface failure is evident. At the conclusion of the transmission of all data blocks, and in any case following any operation terminated by the SRV HLT bit, a status presentation is expected by the channel. Such a presentation must include the channel end bit and may include others as well. Following the presentation of channel end, the subchannel involved reverts to the interruption-pending state and may allow certain I/O instructions addressing the subchannel to proceed directly to the command interface. The subchannel reverts to the available state upon receipt of an interrupt response from the System/ 360 CPU, following which any I/O instruction may be directed to the command interface. The channel end and device end bits may be combined in a single status byte. A standard status operation is one in which a status byte containing the channel-end bit is to be transmitted to a working subchannel. Such an operation is started by loading an octal 7 into the high-order three bits of the control register. This order initiates a status operation involving status byte transmission from the PDP-8 core memory to the channel. Usually only one byte will be transmitted to the channel on any one operation; but, regardless of the number of bytes actually transferred, the operation can legitimately terminate only when the PDP-8 word count decrements to zero,

TABLE I Order SRV HLT SRV END Sequence *Bytes Transmitted Data Outbound CTL 2] 0 1 PDP-8 stop N-W CTL 1 0 channel stop N-W 1 1 not possible (see text) Data Inbound CTL 4l 0 1 PDP-8 stop N-W CTL 4Ig 0 channel stop N-W-1 1 1 channel stop on last byte N-W-1 Status Inbound CTL 61 0 1 PDP-8 stop N-W CTL 7e 1 0 not possible (see text) N-W-1 1 1 not possible (see text) N-W-1 N = initial word count W = residual word count

-34a condition that sets the SRV END bit in the control register and interrupts the PDP-8 program. If an interface disconnect or selective reset sequence is transmitted by the channel in response to a status presentation, then the interface will immediately disconnect from the channel and cause the SRV HLT bit to be set in the control register. The standard status operation is not suppressible by the channel. That is, status presentations cannot be locked out of the system if the channel is disabled but has an interrupt pending for another device. Under these conditions, a TIO instruction issued by the System/360 program can clear pending status at the service interface. Such a procedure is called for following presentation of unit check in a status byte to certain System/360 programming systems (see preceding footnote). Such systems regularly follow presentation of unit check by a Sense channel command while the channel is disabled, and rely on clearing device status using a TIO loop. Note that in such cases a busy indication is returned to the System/360 program as long as the subchannel is working; and, in particular, the TIO is not propagated to the device itself. Thus, if the subchannel is working, a standard status operation will always terminate with the channel accepting the presentation by the service interface, and in particular without the generation of pseudo-TIO commands on the part of the channel. If a standard status presentation is once stacked by the channel for any purpose, then the interface itself automatically "demotes" the priority to that of a special status presentation. A special status operation is one in which a status byte is to be transmitted to a subchannel not in the working state. That is, a subchannel in either the available or interruption-pending states. Such an operation is started by loading an octal 6 into the high-order three bits of the control register. This order initiates a status byte transmission in the same manner as the standard operation, with

-35the exception that the presentation is suppressible by the channel. Such behavior is necessary to avoid the lockout of a channel-end status presentation of a lower-priority control unit on the channel interface cable by an unsolicited status presentation by the service interface. As in the standard operation, the special operation ends by setting the SRV END bit in the control register. To summarize the application of the two kinds of status operations, the standard operation is used to transmit a status byte, which must contain the channel-end bit, to a working subchannel; and the special operation is used to transmit a status byte to a non-working subchannel. A failure to make this distinction will result in a machine hangup in the lower-numbered models of the System/360 product line and in an interface control check (channel timeout) in the highernumbered models. Such situations may result in a diagnostic Channel Status Word (CSW) to be stored by the System/360. If SUP OUT is up when SRV OUT is raised by the channel in response to an ending status presentation, the CMD CHN bit of the control register is set. Such an action is interpreted as an indication that the channel is command-chaining the previous operation and is about to reselect the interface for issuance of a new channel command. The indication of the CMD CHN bit is only advisory to the PDP-8 program and does not affect the progress of any channel or interface sequence. Depending upon the circumstances involved, the PDP-8 program may process this indication as a request to save such status presentations as the attention bit until the end of the System/360 channel program, or to assign high priority to command interface operations so that the immediately following reselection procedure will not delay the channel.

-364.3 System/360 Control Program Operations Interface programming considerations for the System/ 360 resident control programs are similar to those for the 2702 Transmission Control. However, due to the somewhat richer architecture of the interface, the behavior of the two machines will be slightly different. The main differences are: 1. channel-end and device-end status presentation do not necessarily have to occur in the same byte, 2. burst-mode operation can be sustained, 3. no immediate channel command operations are possible, 4. unsolicited status presentations are possible. Considerations 1 and 2 imply that it is possible to use the interface on a shared subchannel, effecting a cost reduction in channel equipment on some models. However, since it is not possible to determine at initial selection time whether a particular device attached to the PDP-8 and logically connected to a particular System/360 subchannel can or cannot accept a channel command (consideration 3), use of this capability would be rather awkward. Consideration 2 implies that system performance at moderate data rates can be materially improved in the lower-numbered models by programming the PDP-8 to operate in short multi-byte bursts. The System/360 programming problems in connection with burstmode operations are similar to those arising in connection with tape control unit operations on the multiplexor channel. Consideration 3 is another implication of the general interface characteristic that all commands are accepted if the interface is not busy. Consideration 4 is an implication of the capability of the interface to clear asynchronous unsolicited status presentations as the result of a pseudoTest I/O instruction.

-37Following is a short summary of the operation of System/360 I/O instructions when directed to a device address recognized by the interface. Only those features of operation dependent upon the peculiar characteristics of the interface are emphasized. Start I/O Issued to a nonworking channel and subchannel, this instruction will always result in a command interface operation involving the transmission of a channel command to the interface. If both the command and service interface are idle before transmission of the channel command, then condition code 0 is set at the conclusion of the Start I/O operation. I/O activity is begun and the subchannel is placed in the working state. If the command interface is busyg then condition code 1 (CSW stored) is set at the conclusion of the operation. The device status field of the CSW contains the busy, control unit end, and status modifier bits. No I/O activity is started and the command interface is undisturbed following this operation. Normally the indicated busy condition may be expected to last in the order of a few hundred microseconds, representing the interrupt processing time of typical PDP-8 programs. If the command interface is idle and the service interface is holding pending status for the device addressed by the Start I/O instruction, then condition code 1 is set at the conclusion of the operation. The device status field of the CSW contains the status presented by the service interface and in addition the busy bit. No I/O activity is started and both the command and service interfaces are idle following the operation. Halt I/O, Issued to a nonworking channel, this instruction will always result in a command interface operation without regard to the state of the subchannelo In addition, the

-38subchannel will be set up to signal the service interface to stop data transmission the next time a service cycle is requested. If the command interface is idle prior to the issuance of a Halt I/O instruction, then condition code 1 is set at the conclusion of the Halt I/O operation and the status field of the CSW is replaced with zeros. I/O activity is stopped by the addressed device, which will then provide ending status under control of the resident PDP-8 program. If the command interface is busy, then condition code 1 is also set following the operation, but the status field of the CSW contains the busy, control unit end, and status modifier bits. The Halt I/O indication has not been stored by the command interface, although the subchannel is set up to signal this condition when the service interface next requests a service cycle. Test I/O Issued to a nonworking channel and subchannel, this instruction will always result in a command interface operation but will not affect the PDP-8 program unless status presented is stacked by the channel. (And whether this can ever happen. is highly dubious-see comments elsewhere in this documents) Condition Code 1 will always be stored at the conclusion of the Test I/O operation. If the command interface is busy prior to the issuance of this instruction, then the status field of the CSW will contain the busy, control unit end, and status modifier bits. If the command interface is idle and status for the addressed device is available at the service interface, then that status replaces the status field of the CSWo If neither of these conditions hold, then the single status modifier bit is placed in the status field of the CSWo

-39Programming Notes Contrary to published doctrine, it is evidently possible to cause I/O interrupts from devices whose subchannels are working, but without including the channel end bit and without affecting the status of the subchannelh It is not at all clear whether this is possible on all models or whether unknown machine incompatibilities can occur. Use of this feature (for instance as an attention interrupt) in real-time control environments is obvious. In some programming systems, an automatic Sense channel command is issued (with channels disabled) when a unit check bit is set in a status byte. These systems rely on a Test I/O loop to clear ending status from the Sense command. If the Test I/O loop is looking for device end, then the cooperating PDP-8 program must present channel end and device end together on the status byte which ends the Sense command. Alternatively, the PDP-8 program must arrange that a channel end status presentation for a particular device address be followed only by status pertaining to the same device. Otherwise conflicts between the channel and the interface can occur in which the channel is asking for status (via a programmed or pseudo-Test I/O) for a device that the service interface is just not prepared to surrender. V. ARCHITECTURE OF SYSTEM/360 INTERFACE* The System/360 interface contains the registers and control circuitry to provide a bidirectional asynchronous transmission of both command, status, and data bytes between the System/360 multiplexor channel and the PDP-8. The interface consists of four data registers, their transfer gates, a control register, and various sequencing circuitry. The organization of these components is shown in Figure 9. * Logic symbology in this section corresponds to IBM standard usage~ See Preface.

BUS IN BI C1AR1-B I AR2+BI BR2+BI PARITY AR1i BR AR2 BR2 BO [ SEQUENCE CONTROLS BOAR1 BOBRBOBR PARITY FIGR 9. RI1=OA I LII9 PSEQUENCE CONTROLS _ MB OUT AC OUT MA OUT MB IN AC IN OUTBOUND TAGS INBOUND TAGS (PDP-8) (PDP-8) PDP-8 FIGURE 9. PRINCIPAL INTERFACE COMPONENTS

-41Referring to Figure 9, the four data registers are designated Address Register 1 (AR1), Buffer Register 1 (BR1), Address Register 2 (AR2), and Buffer Register 2 (BR2). All four registers are provided with jam-transfer direct-coupled diode-capacitor-diode (DCD) gates from the test switches, and, in addition, all except BR2 are provided with onestransfer DCD gates from the PDP-8 AC. ARl is used to hold the device address presented by the channel during the initial selection sequence and is provided with jam-transfer directcoupled (DC) gates from BUS OUT. BR1 is used to hold the command byte presented by the channel during the initial selection sequence and is provided with ones-transfer DC gates from BUS OUT. AR2 is used to hold the device address presented to the channel during a service cycle. No inbound transfer gating is provided except for the DCD gates mentioned above. BR2 is used to hold a status or data byte during a service cycle and is provided with ones-transfer DCD gates from the PDP-8 MB and with ones-transfer DC gates from BUS OUT. BUS IN is provided with ones-transfer DC gates from AR1, AR2, and BR2 as well as constant generators 10, 40, and 70 (hex), which are used to synthesize certain status bytes. The PDP-8 AC is provided with a special set of ones-transfer DC gates called the EAC bus, which is in turn provided with ones-transfer DC gates from AR1, BR1, and AR2. The EAC bus is used both to isolate the PDP-8 AC bus from the loading of the transfer gates and to provide a uniform interface for additional equipment, other than the interface, which may be connected to the PDP-8. The PDP-8 MB is provided with onestransfer gates from BR2o These gates are used in connection with a special data multiplexor described elsewhere. A nine-bit parity detector connected to BUS OUT indicates that odd parity is present on these lines and is used in conjunction with AR1, BR1, and BR2 when these registers are loaded from BUS OUT. A parity error during the

-42BR1 or BR2 loading operation will set the CMD PCK or SRV PCK bits of the control register respectively. An eight-bit parity generator connected to the BUS IN transfer gates provides odd parity for the BUS IN (P) line and is used in conjunction with all BUS IN operations. An eight-bit zero detector connected to BR1 is used during the initial selection sequence to detect the occurrance of a Test I/O channel command and to condition the following BUS IN status accordingly. An eight-bit compare circuit is connected to ARl and AR2 to detect when these two registers contain identical bits and is used during the pseudo-TIO status sequence. A three-bit decoder connected to BUS OUT is used during the initial selection sequence to determine whether the device address present on BUS OUT falls within the block serviced by the interface. Eight blocks of addresses, each consisting of a contiguous block of 32 addresses, may be selected by a jumper card. The twelve-bit Control Register (CTL) is composed of a three-bit Order Register (OR) and a nine-bit Status Register (SR). The OR is used to hold the order code during a service cycle and is automatically reset following the conclusion of a block transfer operation. The SR is used to hold the various bits that indicate termination conditions of the interface sequences, However, the SR has no direct connection with any status byte that may be presented to the channel. The logical details of these registers and their transfer gates are shown in Figure 10. Figure 11 shows the logical details of the PDP-8 data paths, and Figure 12 shows those of the BUS IN data paths. Circuit names, which appear only in this simplified description, are indicated on these diagrams. In some cases the actual circuit names and logical details differ from those recorded here. The logical details of the circuitry for all of these components are straightforward and are recorded in Appendix E, The logical organization of the control and sequencing circuitry, however, is

-43BAC(4-11) AR1 SW(O-7) REG BO(0>-7)AR1(0-7) BO(0-7) FF AC+AR1 SW-+AR1 BO-AR1 0-+AR1 Comp. AR1=AR2 (8) BAC(4-11) AR2 SW(0-7) R REG A 0 SWF (AR2(0-7) FF AC->AR2 SW+AR2 (8) 0-+AR2 ZERO BR1=O BAC(4-11) BR1 DET (8) SW90-7) REG (BR1(0-7) AC-BR1 SW-+BR1 o (8) NOTE: PWR CLR CLEARS ALL REGISTERS. BO-*BR1 0-B R 1 FIGURE 10a. AR1, BR1, AR2 REGISTERS.

-44 - MB(4-11) 1 BR2 SW(0-7) REG BR2(0-7) BR2 MB(4-11) BO ( 0- 7 ) FF BR 2MB (NAND) MB-+BR2 SW+BR2 ( BO+BR2 0+BR2 OR INT BAC(4-11) CTL(6-11) SW(0-2) FF CTL(3-5) INV-+CTL OCTL(3-5) SW(0-2)+CTL(O-2) OP 0CTL(02TL(O-2) O->CTL(6) CTL OP: 0 IDLE CTL=0O 1 IDLE 1? OP 2 BO REQ 2) 3 BO REQ(BURST) 3 CMD CHN 4 BI REQ 4 CMD PCK 5 BI REQ(BURST) 5 SRV PCK 6 STA REQ 6 SYS RST 7 STA REQ(PRI) 7 CMD STK 8 CMD HLT CMD INTF 9 CMD ENDJ 11 SRV ENDHLT SRV INTF 11FGURE b. BR2 AND CTL REGISTERS FIGURE 10b. BR2 AND CTL REGISTERS

-45-4 5 - )~' R1 AR1(0-7) GATES' (NAND) AR1 SEL - -(NAND) (8) +EAC(O-1) BRI EAC EAC BR1(0-7) GATES AC(O-11) BR1 SEL (NAND8)l (12) 1 NAND) (8) (12) EAC-AC AR2 AR2 (0-117) I )GIATES (NAND) (12) l~ ~~~~~~(2 IOT- AR1 SEL EAC{0-11) M B ( 3 - 8E) A R2 SE L I 11 -8CTL PT CTL(0-11)i D /]GATESI CTL SEL v I{NAND)i VA [ I/I' ~~~~EAC->SKIP I~ S l(12) EAC(O-11) -~~~~A BAC(0-11) N — ~_ ~~A BAC(O=11) I N j, ~~AR1 SEL I OT[ MB(3-8) i- m ~~~R2 SEE DET,CTL SEL FIGURE 11. PDP-8 DATA PATHS

-46o O -tB I OO*BI 0 01 + I BI(P) AR1+BIB AR2-BIBI BR2BBR2-*BI 10+-BI BPAR -BO +BI) GATES(0-7) AR2+BI V(HAND) -BI(0-7) 70BI FISET 1 BI (I2,3) +B0(0-2) ADR... "[ ET i 0*B I SET BI(3) SET -B0(O-7) BO PAR +BO(0-7) 1 " INV I ~ PAR FIGURE 12. BUS GATING

-47central to the operation of the interface and is discussed below. Figures 13 and 14 show respectively the logical organization of the circuitry used to intercept polling signals from the channel and that used to seize the control unit interface for the various kinds of sequences. During an initial selection sequence, the OUR ADR gate (Figure 13) detects the conditions for channel-requested service (initial selection) and the REQ IN gate detects the condition for control-unit requested service (service cycle). These gates may not respond simultaneously. The remaining circuitry shown in Figure 13 is used in conjunction with the channel polling signal to detect the conditions under which the interface may seize the channel. The principal functional block in this circuitry is the select latch, shown in simplified form in Figure 13 but actually consisting of two interconnected flip-flops. This rather interesting circuit is a high-speed two-input switch with inputs derived from SEL OUT and from the two servicerequest gates OUR ADR and REQ IN. An analysis of this circuit is given in Appendix C When SEL OUT rises at the interface while either of the two service-request gates OUR ADR and REQ IN have truevalued outputs, the interface will fall into one of three states: CMD CYC, SRV CYC, or CU BUSY (see Figure 14). If OUR ADR is true and if the command interface is not busy (i.eo, contains no previously stored command), then CMD INT is false and CMD CYC state is entered; if OUR ADR is true and if the interface is busy, then CMD INT is true and the CU BUSY state is entered. If OUR ADR is false and if REQ IN is true, then the SRV CYC state is entered. Entrance into either the CMD CYC or the SRV CYC state causes OPL IN to be raised after a short delay to allow the circuitry to stabilize, and entrance into the CMD CYC state causes the address presented by the channel on BUS OUT to be jam-transferred to

-48OPL OUT OUR ADR AND ADR OUT ___ BO ODD PAR ADR DET OPL IN REQ IN SUP OUT CHL REQ OUR ADR CU SEL REQ IN CU SEL HLD OUT SEL PROP SEL OUT OPL IN FIGURE 13. SELECT INTERCEPTION

-49OUR ADR AND CMD INT _ CU BUSY CU SEL FL CU BUSY BO-AR1 AND CMD CYC CMD CYC RST CMD CMD CYC OPL IN AND OR AR1=AR2 CHL REQ STA REQ ADR IN DLY CMD OUT SRV CYC REQ IN CU SEL SRV CYC FL.. RST SRV FIGURE 14. CHANNEL SEIZURE.

-50AR1. Entrance into the CU BUSY state causes the control-unitbusy byte to be placed on BUS IN, and STA IN to be raised without disturbing any of the active interface registers. The CMD CYC and SRV CYC flip-flops each have their own reset line, which is connected to gates described below. The CU BUSY flipflop is reset when SEL OUT drops. Figure 15 shows the logical organization for the circuitry used during the command-storage/proceed phases of the sequences initiated by entrance into either the CMD CYC and SRV CYC states. Both of these sequences begin by placing on BUS IN the contents of AR1 or AR2 as appropriate and proceeding through the channel sequence until CMD OUT is dropped. During the CMD CYC sequence the byte on BUS OUT is transferred to BR1 when CMD OUT is raised by the channel. The short delays indicated on Figure 15 allow time for the parity circuitry to stabilize before bus transfers are executed. Following the command-storage/proceed phase of either the CMD CYC or SRV CYC sequence, both the CMD DLY and CHL SRV flip-flops are set. These flip-flops are reset when OPL IN drops. When the CHL SRV flip-flop becomes set, a byte of data or status information may be transferred between the channel and the interface. If the CMD CYC flip-flop is set, then the sequence ends by presenting to the channel either an all-zero status byte or a status byte containing the status modifier bit, depending upon whether BR1 has been stored as a nonzero byte or a zero byte respectively. If the SRV CYC flipflop is set, then the sequence ends by transferring a byte from BUS OUT to BR2 (channel-outbound service requested) or from BR2 to BUS IN (channel-inbound data or status service requested) with the appropriate tag line. If the CU BUSY flip-flop is set, then a status byte containing the status modifier, control unit end, and busy bits is placed on BUS IN. Appropriate delays are included to allow time for the parity circuitry to stabilize and for skew distortion to stabilize. Outbound parity-checking circuitry is shown in Figure 17.

-S1CMD CYC AR1+BI ADR OUT CMD DLY ADR IN OR DLY SRV CYC AR2+BI AND - CMD OUT __- - 4 > AND ADR IN CMD DLY | T h FL CMD CYC DLY OPL IN AND BO+BR1 CMD CYC SRV INT AND BRK STA (DCD MPX SEL SRV CYC BT2A OR CHAN SRV CMD DLY CMD OUT* CHAN SRV RST CHN *DROP TRANSITION FIGURE 15. COMMAND STORAGE/PROCEED

-52CMD CYC AN CMD STA 00+BI (ACCEPT) SRV CYC CHL SRV BR1=O 40+BI(STA MOD) SRV STA REQ STA IN AND SPC CU BUSY 70+BI (CU BUSY) 10F+BI (BUSY AND FIGURE 16. STATUS

-53BO+BR1 CMD PCK AND BO ODD PAR CMD PCK FL BO+BR2 AND SRV PCK _ WX- FL ~~~SRV PCK FIGURE 17 PARITY CHECK FIGURE 17. PARITY CHECK

-54If a status request is pending at the time an initial selection procedure is signalled by the channel, then, if the contents of AR1 match those of AR2, the SRV CYC flip-flop will be set when the channel command is stored in BR2. (See gate next to SRV CYC flip-flop in Figure 14.) This special condition is detected when the status byte is transmitted to the channel. If both CMD CYC and SRV CYC flip-flops are set following the command-storage/proceed phase of the sequence, then BR2 is transferred to BUS IN and STA IN is raised. If, furthermore, the command byte stored in BR1 during the sequence eontains nonzero bits, then the busy bit is logically OR'ed into the status byte. Figure 18 shows the details of the BR2 gating. The terminating conditions for the CMD CYC sequence are shown in Figure 19. If a nonzero command byte has been stored in BR1 during a CMD CYC sequence, and if the channel has responded to presentation of the all-zero status byte with SRV OUT (any other response is an equipment check), then the CMD END bit is set in the control register. If an all-zero command byte has been stored in BR1 during the sequence and if the channel has responded to the presentation of the status byte containing the status modifier bit with CMD OUT (stack status on initial selection), then the CMD STK bit is set in the control register. These are the only two bits that can be set following a complete CMD CYC sequence, and they are mutually exclusive. If at any time, either during an interface operation or not, both SUP OUT and OPL OUT are down at the interface, the CMD RST bit is set in the control register. This operation clears all control register bits except the CMD RST bit, which is forced to the set condition, and in addition clears all flip-flops in the interface to the channel-disconnect condition. If during a CMD CYC sequence ADR OUT is up at the interface while SEL OUT is down (interface disconnect) or SUP OUT is up while OPL OUT is down (selective reset), then the CMD HLT

-5SSRV IN BO+BR2 AND SRV OUT BO REQ SRV CYC CHL SRV CTL(O) OR BR2+BI SRV STA SPC STA SRV IN AND OLY OR 0-OBR2 ORH (PULSE) DCD) MPX SEL BT2(PDP-8) BRK STA(PDP-8) CTL (O) 0002-DA(PDP-8) MPX SEL BR2+MB(PDP-8) ~~~~AND ~MB+BR2 BT1 (PDP-8) (PULSE) BRK STA(PDP-8) CTL(O) FIGURE 18. BR2 GATING

-56CMD STA AND CMD END BRl=O SRV OUT CMD END - <FL AND CMD STK CMD STK CMD STK FL CMD CYC AND OR CMD HLT ADR OUT SEL OUT CMD HLT FL AND OPL OUT SUP OUT SYS RST (DCD) (PULSE) CMD RST FIGURE 19. COMMAND END

-57bit of the control register is set. This operation clears all flip-flops in the interface to the channel-disconnect condition. The terminating conditions for the SRV CYC sequence are shown in Figure 20. This sequence may end in three ways: a. in a request for a data break operation to fetch a data or status byte from PDP-8 core memory (BRK REQ), b. in an ending condition which stops data transmission and interrupts the PDP-8 program (SRV END and SRV HLT), or c. in a stack-status condition which disconnects the interface from the channel and immediately re-requests channel service. The PREP END flip-flop is set on a data or status operation in which the PDP-8 block transfer word count decrements to zero. In the channel-inbound case the channel must either accept or reject the byte before an ending-condition bit (SRV END or SRV HLT) is set in the control register. Following the ending operation in the case either of a CMD CYC or SRV CYC sequence, the interface is disconnected from the channel with the circuit shown in Figure 21. Here the various terminating conditions are detected and the reset signals for the CMD CYC and SRV CYC flip-flops are generated. In addition, signals are derived that condition the PDP-8 interrupt bus (INT REQ) and that indicate that the command interface is busy (CMD INT). The channel-request circuitry is shown in Figure 22. Note that when a channel-outbound request is initiated a special pulse is generated which sets the CHL REQ flip-flop and starts the operation. Conversely, when a channel-inbound data or status request is initiated a special pulse is generated which sets the BRK REQ flip-flop (see Figure 20) and starts the operation.

-58WC=O AND PRED END MPX SEL 0+CTL(0-2) SRV OUT AND OR SRV CYC,,, SRV HLT AND AND (DCD BOREQ ] SRV END BT1 __ BRKSTA SRV END FL! ANDX OR SRINT BRK REQ CTL(O) l -DCD BRK REQ AND ADR ACCP SRV HLT OR FL ~SRV HLT SRV IN A CMD OUT OPL OUT AND ADR OUT FIGURE 20. SERVICE END

-59CMD RST CMD INT OR CMD END CMD HLT INTEQ OR CMD STK (PDP-8) SRV END OR SRV INT SRV HLT 0 —CTL (0-2) DLY RST SRV BRK REQ DLY CMD INT RST CMD OR CMD CYC CMD BUSY AND SRV OUT DLY AND CHL SRV CMD OUT FIGURE 21. CYCLE RESET

-60CTL(0) FL 0 BO REQ CTL(1) 2 OR BO REQ FL O (DCD) HABI REQ CTL(2)o 5' AND OR (DCOD)T BT2A(PDP-8)(PULSE): SRV INT CHAN REQ BRK STA(PDP-8) PX SEL 22. CONTROL OPERATION DECODER AND CHAN RE Q FLIP-FLOP SRV CYC SRV OUT SRV HLT FIGURE 22. CONTROL OPERATION DECODER AND CHANNEL REQUEST FLIP-FLOP.

-61Additional details of interface operation are summarized in flow chart form in Appendix A. Circuit details are shown in Appendix E.

APPENDIX A CHANNEL SEQUENCE FLOW CHARTS

-64 - NO YES START r SEL OUT NO CDYES ORYES DRO ~~E S CMD INT OUR ADR ADR OUT YES NO lNO RAISENONO STA INSPC S (70+BI) ES PROPAGATE SRV SEL OUT SEQ SEL OUT YES END RESET CU BUSY LATCH DROP ALL TAGS FIGURE A1. CHANNEL SEIZURE

-65SEQ BO+AR1 BCMD OUT o +BR1 SET CMD CYC B0+BR1 LATCH RAISEESPC | SRV CYC OPL IN AR1=AR LATCH STA SRAISE RA ISE ADR IN (AR1-+BI) FIGURS A2. COMMAND BYTE STORAGE

- 66CMD STA YES CMD OU BR1=0 3 S NO NO SET RAISE RAISE CHL SRV I STA IN STA IN LATCH (00+BI) (40-+B I).NO NO SRV OUT ~ CMD OUT YES YES i SET NO SET CMD END BR1=O CMD STK LATCH LATCH YES RESET CMD CYC LATCH RESET DROP CMD DLY AND ENAD ALL TAGS \ CHL SRV LATCHES FIGURE A3. COMMAND STATUS PRESENTATION

-67SPC STA CMD OUT YES BR1= NO NO SET I I RAISE RAISE CHL SRV STA IN STA IN LATCH 0 (BR2+1O-+BI) (BR22+BI) N YESNO CHL REQ SRV OUT CMD OUT LATCH PREP END SRV END NO SET t BRK REQ LATCH RESET RESET |CMD CYC AND _ DROP CMD DLY AND SRV CYC _ ALL TAGS CHL SRV LACE LATCHES LATCHES NO YES END sc- BRK REQ BRK FIGURE A4. SPECIAL STATUS PRESENTATION

-68SET AND ADR IN RACHL SRV SET NO NO SRV CYC BO REQ BI REQ LATCH AISE OPL IN RAISE AND ADR IN RAISE SRV IN (AR2+BI) SRV IN (BR2~BI) CMD OUT NED RAISE S YES I F STA IN (BR2-+BI) YES CMD OUT END N OO YES 0+B R 2 FIGURE A5. SERVICE CYCLE

-69tSEND SRV CYC S YES SET SRV HLT PREP END FIU SET 6 SER T SRV END BRK REQ RESET CHL REQ LATCH RESET SRV CYC LATCH RESET DROP CMD DLY AND YES ALL TABS CHL SRV NO FIGURE A6. SERVICE CYCLE END

-70BRK RESET BRK REQ LATCH YES SET WC=O PREP END LATCH NO MB'+BR2 REQ IN BR2'+MB N 0 PREP END YES SET CHL REQ LATCH, RESET PREP END SET SRV HLT LATCH END END FIGURE A7. PDP-8 DATA BREAK CYCLE

APPENDIX B CHANNEL SEQUENCE PHOTOGRAPHS

-73ADR OUT OPL IN ADR IN CMD OUT STA IN SRV OUT 1iS/CM Fig. B1 INITIAL SELECTION REQ IN OPL IN ADR IN CMD OUT SRV IN SRV OUT FIg S/CM Fig. B2 SERVICE CYCLE

-74FIGURE B1 INITIAL SELECTION (lis/cm) Line Name Signal Name Pin Polarity 1 ADR OUT ADO 1B01S IBM 2 OPL IN OPI lB01D IBM 3 ADR IN ADI 1B01H IBM 4 CMD OUT CMO 1B01T IBM 5 STA IN STI 1B01E IBM 6 SRV OUT SRO 1B31D IBM FIGURE B2 SERVICE CYCLE (lis/cm) Line Name Signal Name Pin Polarity 1 REQ IN REI 1B31M IBM 2 OPL IN OPI lB01P IBM 3 ADR IN ADI 1B01H IBM 4 CMD OUT CMO lB01T IBM 5 SRV IN SRI lB01K IBM 6 SRV OUT SRO 1B31D IBM

-75ADR OUT SEL OUT STA IN SUP OUT I,.S/CM Fig. B3 CONTROL UNIT BUSY ADR OUT SEL OUT OPL IN ADR IN SUP OUT Fig. B4 INTERFACE DISCONNECT

-76FIGURE B3 CONTROL UNIT BUSY (lPs/cm) Line Name Signal Name Pin Polarity 1 ADR OUT ADO 1B01S IBM 2 SEL OUT SEL OUT 1B01P IBM 3 STA IN STI 1B01E IBM 4 SUP OUT SUO lB01V IBM FIGURE B4 INTERFACE DISCONNECT(0.5Ss/cm) Line Name Signal Name Pin Polarity 1 ADR OUT ADO 1B01S IBM 2 SEL OUT SEL OUT 1B01P IBM 3 OPL IN OPI 1B01D IBM 4 ADR IN ADI 1B01H IBM 5 SUP OUT SUO 1B01V IBM

-77ADR OUT OUR ADR SEL OUT CU SEL CMoD CYC OPL IN O.5$ S/CM Fig. B5 CHANNEL SEIZURE OUR ADR ADR IN(DLY) ______________ ARI —BI CMD OUT BO-BRI 1.0 S CM Fig. B6 GATE TRANSFERS

-78FIGURE B5 CHANNEL SEIZURE (0.5ps/cm) Line Name Signal Name Pin Polarity 1 ADR OUT ADO+ 1B18P DEC + 2 OUR ADR OURAD+ 3B10P DEC + 3 SEL OUT SEO+ 1A22N DEC + 4 CU SEL SEL+ 3B10F DEC + 5 CMD CYC CMDCY+ 3B12L DEC + 6 OPL IN 1B01D IBM FIGURE B6 BUS TRANSFERS (l.Ois/cm) Line Name Signal Name Pin Polarity 1 OUR ADR OURAD+ 3B10D DEC + 2 BO+AR1 BOAR1+ 3B13P DEC + 3 ADR IN BADI+ 3A09D DEC + 4 AR1+BI AR1BI+ 3A13D DEC + 5 CMD OUT CMO+ 1A25U DEC + 6 BO+BR1 BOBR1+ 3A13J DEC

-79CHL REQ CU SEL SRV CYC CMD DLY CHL SRV BRK REQ 1.O/.LS/CM Fig. B7 MAJOR STATE-SERVICE CYCLE MPX REQ __________ MPX SEL BRK STA CHL REQ BT1 BT2A 1.OuS/CM Fig. B8 DATA BREAK-SERVICE CYCLE

-80FIGURE B7 MAJOR STATES-SERVICE CYCLE (lps/cm) Line Name Signal Name Pin Polarity 1 CHL REQ CHNRQ+ 3B18P DEC+ 2 CU SEL SEL+ 3B10F DEC+ 3 SRV CYC SRVCY+ 3B13N DEC+ 4 CMD DLY CMDLY+ 3A07J DEC+ 5 CHL SRV CHSRV+ 3A07P DEC+ 6 BRK REQ BRKRQ+ 3B17P DEC+ FIGURE B8 DATA BREAK-SERVICE CYCLE(lis/cm) Line Name Signal Name Pin Polarity 1 MPX REQ REQ1 3A17D DEC2 MPX SEL SELl- 2B30E DEC3 BRK STA BRKSTA 1B03P DEC+ 4 CHLREQ CHNRQ+ 3B18P DEC+ 5 BT1 BT1 3B29S DEC(P) 6 BT2 BT2A 3B29T DEC(P)

-81ADR OUT OPL IN CMD OUT STA IN SRV OUT SUP OUT 2FuS/CM Fig. B9 TEST /O LOOP 1.. S/CM SEL OUT SEL OUT PROP SEL IN O.11S/CM SEL OUT SEL OUT PROP Fig. B10 SEL OUT/SEL IN DELAYS

-82FIGURE B9 TEXT I/O LOOP (2,s/cm) Line Name Signal Name Pin Polarity 1 ADR OUT ADO 1B01S IBM 2 OPL IN OPI 1B01D IBM 3 CMD OUT CMO 1B01T IBM 4 STA IN STI lB0lE IBM 5 SRV OUT SRO lB01D IBM 6 SUP OUT SUO 1B01V IBM FIGURE B10 SEL OUT/SEL IN DELAYS Line Name Signal Name Pin Polarity (lis/cm) 1 SEL OUT SEL OUT 1B01P IBM 2 SEL OUT PROP SEL PRP 1B02P IBM 3 SEL IN SEI 1B01M IBM (O.lis/cm) 1 SEL OUT SEL OUT 1B01P IBM 2 SEL OUT PROP SEL PRP 1B01P IBM

APPENDIX C ANALYSIS OF SELECT LATCH CIRCUITRY

ANALYSIS OF SELECT LATCH CIRCUITRY The select latch consists of two interlocking flipflops interconnected as shown in Figure C1. The outputs of one flip-flop are designated 0 and 1 in the diagram and those of the other flip-flop as 2 and. 3. The latchback lines connect from 1 to 1' and 3 to 3' respectively. The request signal is designated -REQ and the select signal as SEL. By straightforward analysis, the state table of Figure C1 is derived, which gives the outputs of the circuit as a function of the inputs. Four states may be recognized; and these are called Q, R, S, and T. (T does not appear for any output and is an unstable state.) A transition diagram for this circuit is shown in Figure C2. The stable states are designated idle (no activity), select (this control unit selected),and bypass (some other control unit selected). Gates connected to the circuit detect the select and bypass states and inhibit propagation of SEL OUT in the bypass case. These states and the output decoding are so arranged that races between states cannot occur and so that no noise appears on any output during transitions. The circuitry is implemented using standard modular components of about 35 nS propagation delay. Decisions and state transitions must be completed in times comparable to this. Two of these circuits are used in the System/360 interface. One is connected to the CU SEL line and used in the channel seizure operation; and the other is connected to the CU BUSY line and used in the control unit busy operation. -85

-86indino zz~U ATA~~~~~~~~~~~ k;~~-4 CY sindNI Z I;1 I sn I

-87TABLE I INPUTS OUTPUTS -REQ SEL 1' 3' O 1 2 3 STATE O O O O 1 1 1 1 Q O O O 1 1 1 0 1 Q O O 1 0 1 1 1 1 Q O O 1 1 1 1 0 1 Q O 1 0 0 1 1 1 0 R o 1 0 1 1 0 0 1 S O 1 1 0 1 1 1 0 R o 0 1 1 1 0 0 1 S 1 0 0 0 1 1 1 1 Q 1 0 0 1 1 1 0 1 Q 1 0 1 0 0 1 1 1 Q 1 0 1 1 0 1 1 1 Q 1 1 0 0 1 1 1 0 R 1 1 0 1 1 0 0 1 S 1 1 1 0 0 1 1 0 R 1 1 1 1 0 1 1 0 R 00,10 OT 00,10 1 T>____ IDLE 01,11 FG EC11 S E 0 0,10 L BYPASS O SELECT FIGURE C2. SELECT LATCH STATE TABLE

APPENDIX D ADDITIONAL CONSTRUCTION DETAILS

ADDITIONAL CONSTRUCTION DETAILS D1. System Configuration The System/360 Interface as a component of the Data Concentrator is assembled in two equipment racks which also house a high-speed paper tape reader/punch and the various power supplies and connectors which service the system. The euqipment layout in these racks is shown in Figure D1. The PDP-8 occupies one of these racks in which space is available for further expansion of extended memory, from the now present 12K. The other rack contain.s interface circuitry, the reader/punch, and the power supplies. The top three bays contain the interface circuitry itself. These bays are connected to the Test Panel immediately below, to the PDP-8, and to the Channel Interface connectors (bottom bay) with DEC module connectors. The tape transport for both the reader and the punch are mounted on slides immediately above the operating table as shown. The two logic bays which service this equipment are installed immediately below the table. Except for the attached PDP-8 cables, which are routed through the interface, this equipment is entirely independent of the interface. At the bottom of the rack is a panel which carries the four channel interface connectors. The eight cables which connect to the Data Concentrator side of these connectors are routed to DEC module connectors on Bays 1 and 2 above. The four cables which connect to the IBM side of these connectors enter through the fan hole in the bottom of the cabinet. The fan itself has been relocated to a panel on the rear plenum door immediately below the power supplies. The power supplies and AC distribution system are mounted on the rear plenum door. A resonant-transformerregulated supply provides +10 volts and -15 volts to the interface equipment and Test Panel. A separate supply provides various voltages to the reader/punch equipment. Power for -90

-91RACK 1 RACK2 SPARE SPARE BAY 1 BAY 2 PDP-8 BAY 3 INDICATOR PANEL PCO1 TAPE READER/PUNCH TABLE PCO1 BAY 1 PCO1 BAY 2 MEMORY EXTENSION SPARE CHANNEL CONNECTORS FIGURE D1. PHYSICAL CONFIGURATION

-92margin-check operation is obtained from an internal supply of the PDP-8. Switches mounted on each mounting bay allow power for that bay to be obtained either from the regular supply or the margin-check supply. The Power Control Unit provides AC power to the Data Concentrator in response to control signals issued by the parent IBM system. Power requirements for the Data Concentrator, including the PDP-8, total about two kilowatts at 115 VAC. A single 30-ampere circuit is used to power the equipment. D2. Power Control Unit All line power to both the PDP-8 and the interface circuitry is controlled by the Power Control Unit. This equipment sequences power on and off in response to standardized signals furnished by the System/360. The operation of the equipment in response to these signals is summarized in System/360 Power Control Interface-Original Equipment Manufacturers' Information, IBM Corporation, Form A22-6906-0. The Power Control Unit (Figure D2) includes a 24V DC power supply, which is connected to the line power at all times, and two relays. One of the relays is actuated by the power sequence control of the channel and turns on the line power to the PDP-8 and interface circuitry. The other relay is actuated by a DC power supply in the interface circuitry and enables the power sequence control of the channel to step to the next control unit on the interface. Two switches are used to control the operation of the equipment. One of these, the LOCAL/REMOTE switch, is used to transfer control of the equipment between the channel (REMOTE) and the local controls (LOCAL) for maintenance purposes. This switch should not be actuated while the equipment is in the on-line state. The other switch (POWER ON/OFF) actuates a relay which turns on line power to the PDP-8 and interface circuitry. It is effective only when the LOCAL/ REMOTE switch is in the LOCAL state.

NUMBERS REFER TO EPO CONNECTOR TERMINA'LS \ UNIT _______________________________ I SOURCE EPO DEC +10 0 H701 POWER SUPPLY GND 2 EPO CTRL -15 OFF OFF FUSE LOCAL/REMOTE _ON SWITCH 55 I LCL POWER RMT _ _PWR HOLD LC L I I I I PWR 6 PICK STEP eRMT 0IC cu ~~~~~~~~~LCL EBERT C - 0 OSYS SOURCE CDIN4002 1 3 RELAY 0 10.0 RMT RELAY z:F~~ I I i ~~(r~ LOCAL L 0 R F. r~~~~-0 WRCOP P&IB KRP llDG-24VDC -0 0 PWR C(MP 11OVAC PDP-8 A 30AMP33/ BREAKER 15V DEC POWEI "OUTSIDE' "INSIDE" PRSENSE POWER I 1 I POWER ~~~P & B KRP11DG-12VDC POWER POWER STRIP STRIP -CINCH BARRIER STRIP FIGURE D2. POWER CONTROL UNIT tt\ CN

-94D3. IBM/DEC Interface Modules The accompanying circuits have been designed to provide IBM/DEC compatibility in a package appropriate for installation in DEC 1943 Mounting Panels. Characteristics have been chosen to satisfy the requirements outlined in System/360 I/O Interface-Channel-to-Control Unit Original Equipment Manufacturers' Information, Form A22-6843. None of the available DEC modules satisfy these requirements, notably that which specifies that the components not disturb the interface bus lines in the event of power failure or offline operation. BUS DRIVER (Figure D3) Input DEC standard levels of -3v and ground. The circuit acts as an AND for negative true-valued inputs and as an OR for positive inputs. Other input characteristics are identical to those of the Rlll Diode Gate. Output IBM Standard SLT bus levels of ground and +3v. SLT conventions assign a logical a to ground level and a logical 1 to +3v. The leakage in the 0 state is less than lnA at +3v and the output voltage in the 1 state is 3.85V at 59.3 mA and 4.5 at 30 pA. In a power-off condition the leakage in either state is less than lnA. Performance Propagation delay is 45ns for output rise (0 to +3V) and 25ns for output fall (+3v to 0). Transition time is 20ns for output rise and 10ns for output fall. Characteristics are not significantly affected for power supply variation of +5V on either the +10V or the -15V supply.

2N3009 2N2894 2N3009 D (2)1N3605(2) 1N457A O H F~ ~ ~ ~ ~ ~ ~ ~ ~ H r' —-'qL E O —---— ~ 4 2 2N30-09 2-0 T. FIGURE m I:~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~. o o —.c: C) LO~~~~~~~~~~V LOf a~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ u, I-r~~~~~~~~~~~~~~~~~~~~~~~0Io (ri O,,1 i s V~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.' 2N2894 D EC OIMBSDIVEMOULE2N3009 2N2894 2N3009 (2) 1N3605 (2) 1N457A io CUM 0,O~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0" -15V FIGURE D3. DEC TO IBM BUS DRIVER MODULE.

-96BUS RECEIVER (Figure D4) Input IBM standard SLT bus levels of ground and +3V. SLT conventions assign a logical 0 to ground level and a logical 1 td +3v. The circuit is non-inverting. Input bus loading is +25OpA at +3V and-90pA at ground. (+equals conventional current into the receiver input.) The input impedance (at lkc/s) is 10K ohms. In a power-off condition the input bus is loaded at 285pA for an input voltage level of +3v, and linearly decreases to zero as the input voltage falls to zero. Output DEC standard levels of -3v and ground. Output characteristics are identical with those of the Rll Diode Gate. Performance Propagation delays and transition times are all 20ns for both output rise and output fall. Characteristics are not significantly affected for power supply variations of +5V on either the +10V or -15V supply. SELECT-OUT BYPASS (Figure D5) This module contains an encapsulated DPDT relay, together with its driving circuitry, and in addition an electronic switch which provides termination for the SEL OUT signal on the channel-control unit interface cables. The terminator is a 92-ohm resistor. Bus voltage levels are expected to be in the range zero to +5V. Inputs DEC standard levels of -3v and ground. Relay driver: ground level activates relay armature. Terminator switch: ground level causes terminator to be disconnected.

-97L -O * o +1oV a! - 3 ziO CN peq -i FIGURE D4. IBM TO DEC BUS RECEIVER MODULE 1.SK LO FIGURE D4. IBM TO DEC BUS RECEIVER MODULE

-98U S o -o I N 0-_I 47 B -0 -1SV 2N3638!N4001 2N3638 V 2.7K RELAY -DRIVER A +10V 92/2W F TERM lN.605 2N2894 2N3009 TERM j o 2N3009 TERMINATOR (2)1N457A -A DRIVERo FIGURE D5. SEL OUT BYPASS MODULE

APPENDIX E LOGIC DIAGRAMS

-101P~~sWAR1 (DCD)~- I 0 1BOAR1+ m2BOA PDCAR1 AND PSWAR1 (DC D) FL~ L ~AR1(0 -7)R205 2A09 F2A1 G AR1(0-7 PACAR1 AND DCD BAC(4-11)- i B(0-7)- l B AR+ 2B 12 ~NAKNANDD R123 EAC94-11)AR1AC+ I 2B08 4 ~2B11 K NAND 1' >R123 BBI(R17) AR1BI+ v 12B8 2B11l FIGURE El. AR1

-102[BO(O-7)+ ___J\| AND BR1=0 INV TSTIOR123 >R002 F V R107 T BOBR1+ 2B13 2B17 K 2B18 2B15- N PDCBR1 JNV TSTIO+ BR121 D SW(O-7)+ |||||3A12 PSWBR1 (DCD) L 1 I FL | BR1(0-7)|2A16 BR1(0-7)+ -AND (DCD) [SW(0-7)PACBR1 AND BAC(4-11)- BRACR123 EAC(4-11 BR1AC+ V2B13 FIGURE E2. BR1

-103PWCLR- OR PDCAR1 J P.A. F IOP2- R603 D AND 2A08 AR1AC- (DCD) PSWAR1 P.A. s PBO SWAR1R TIOP~ ~2A08 S.T. DIF K AND WA50A(DCD) 2~~~AOD L OFTSTPACAR1 P. A. IOP4 R R- ~~2AO88 R AND AR1AC- DCD) S PWCLR- -OR PDCBR1 LP.A. M BQARl- R602 H AND 2B20 CPJ(DCD) IOP2E AND BR1AC- (DCD) F PSWBR1 P.A. ~FIPB1 SWBR1 ER6b03 S.T. ~~~2B16 s D0' D1 AND 2AP, (DCD) OFTSTPACBR1 -P.A. M R603!.OP4-!^~1 i2B16] BRAC= 1~~i) FIGURE E3. AR1/BR1 PULSING

-104PDCAR2 SW(0-7) +..AND / PI AR2S'-7' 2A23 2A23AR2.(0- 7) + (DCD) PACAR2 AND (DCD) BAC(4-11)NAND R123 EAC(4-11)AR2AC+ I 12B21 NAND 2B23 FIGURE E4. AR2

-105Isa(O-7)+ NAND BBR2+ 2B25 PDCBR2 SW(f-7)+ PSWBR2 I(DCD) T 1 I ~FL I ~BR2 (0-7) - R205 2A25 2A28R BR25-7)+ AND _ (DCD) PMBBR2 AND (DCD) BMB(4-11)KNAND,R123 MB(4-11) SEL1+ 2B25 2B28 [ I NAND R123 BBI I2-7)BR2B-I+ v12B2S -BIR2 B 2 8+ FIGURE E5. BR2

-106PWCLR- OR PDCAR2 J P.A. F IOP2- R603 D AND 2A24 AND AR2AC- (DCD) E PSWAR2 P. A. R6B3 PB2 SWAR2 R6I3 S.T.2A KS DF KI AND OFTSTBRKST- (DCD) PACAR2 P.A. IOP4- R AND AR2AC- (DCD) PWCLR- OPDCBR2 V P.A. u ZBR2 R602 S AND 22B2 BR1K AND BRKST- (DCD) PSWBR2 PA PB3 [ [ SWBR2 i2A24 S ST1 D,F D AND 2(DCD) OFTSTPMBBR2 P.A. M BT2A- R6I K AND

-107BSRI+ M BOBR- INV BOBR2+ SONNAND "EINV. _ R1 2 1 RI BOREQ+ pB26 1B25 SRVCY+ M SCCSBI CHSRV+ N NAND L R121 BIREQ+ P 1B24 S R BR2BI+ NANGTDN SRSTA- T +2 R121 SPSTA- U 1B24 J H BSRI+ NAND SRVCY ] m R121 SRVCY+ M SCCSBO 1B25 CHSRV+ N L K BOREQ+ P 1B25 S ZBR2 ZBR2 T NAND R CHSRV+ u 1B25 CTL00+ S BRKSTBRKSTA T R121 R SEL1+ U 1B26 FIGURE E7. BR2 GATING

-108ZCTL0 SWCTL L [EAC(-l-2)AND R ~~AND (DCD) (DCD) TT FL CII~ LTL(F-2)~~ICTLAC- IcJP.A. IR205 s1R~ I R0 3B196 SWCTL (DCD) NAND LTL(0- 1 + R1 2 3 CTLAC+ 3A25 EAC(0-l)ZCTL3 BAC(3-5,7-11)AND (DCD) FL T CTL(3-5,7-Al3B221 CTL(3-5,7-l+ AND BAC06DCD)I CTL)6R205 3B18 CTLO, 6+ PBAC ( SYSRST FIGURE E8. CONTROL REGISTER

SYSRST S DCO ZCTLO PWCLR- T p INV. N CTLOZ- U R121 3 B1 CTL02+ ZIPCTL V 3A17 T DIODE s R0 01 3B15 SYSRST m DC3 ZCTL3 PWCLR- N L N R ZIPCTL p 3A17 3B10 PWCLR- J DC6 ZCTL6 ZIPCTL K NANDH UrINVl T R121 R107 3A17 3CAI FIGURE E9. CLEARING THE CONTROL REGISTER

-110DECODER R151 3A22 CTL (0- 2)+ C 2 P BOR1 D F BOREQ+ NANDr 3 R BOR2 E 3A23 E INV D BOREQL 1R107 3A24 4 S BIR1 H K BIREQ+ NAND R 13 5 T BIR2 3A23 H INV CTL(0 2)- R 7 3A24 6 U STR1 L N STREQ+ NAND 7 V STR2 M 1 13 P S DISABL NAND SUO+ R3 FIGURE E10: CONTROL OPERATION DECODER BOR2 T V BURST+ NAND R113 ~BIR2 U 3A23 K INV J BURST3A24

- 1 1 1 - -ili3pl ~~~~~AR1ACDECODER 30 ARACR151 M K 3B2 3 31 BR1ACBMB(6-8)+ N 32 AR2ACp 3 3 CTLACR' 34 S I I I I AR1AC+ 35 M I M INV. L 3A24 T ~~~~R1071 BMB ( 6-8) - M.36 3A2 >~~~~~ 37 I BRAC+ B PI INV. IN _ ~IN~V. BRAC R107 3A24 BMBF3- M[ BMB3T BMB04+ N NANDL AR2AC+ R121 BMBOS+ p S INV R - -3A21 R121 3A24 CTLAC+ U INV. T R107 3A24 FIGURE Ell: IOT DETECTION

-112AR1AC- S NAND EACENB BR1AC- T R121 R AR2AC- U 3B06 CTLAC- V H K U T EACAC+ NAND INV. lop'.R113 R107 IOP1 I 3AO6 3A13 3 3B24 L__ NL EACACNAND l R113 RDENB INV. RDENB+ 3A06 U S R17 R M 3A13 READ ENABLE IOP2 R U SKIP NDNAND ACTEST _ N S11 R111 3B24 T 3B08 SKPENB J U NAN!H T I E CTLSK1 v IR121 R00n CTLAC- K 3BO6 3iS7 CTLSKP J H M L SKIP+ NAND INV. R121 SKIP- R107 1B28 1A30 BOREQ- D F XFER NAND ~SELl1~+ R113 SEL1+ E 3A06 TRANSFER DIRECTION FIGURE E12.

-1133B24 3B24 D-S ACTEST EAC(0-11)- * D T INV. KN3A26 BAC (0-11)- R17 BAC (0-11)+ 3B26 123A27 3 B 2 7 MASK TEST EAC(0-11)+ NANDAC-11 3A05 JACAC+ 3B05 GATE EAC AC INV. EAC (0-11) - R107 EAC(O-11)+ 2 12B18 ASW(0-7)+ ~R107 ISW(0-7)2A29 AR1(0- 7)+ AR2(0-7)- N ORI D J. R 141 AR1(0-7) = 2A17 AND 2A19 ADD. REG. COMPARE IAR2(0-7)+', FIGURE E 13.

-1144 0BI+ E D INV. R 1 0 7 1 B 2 7 CUBSY+ H F BBI 1R 1 0 7 1 B2 7 K B BBI2INV. R 1 0 7 1 B 2 7 IRIS7 1B27 M L BBI3INV. R 1 0 7 1 B 2 7 IOBI+ P N STATUS INV. R 1 0 7 1 B 2 7I 12 M ~iF ADRDT- ADRDT+ DECOD0 2 ) 3 EO E R| INV [ R IBO(~ e2) + DECODE R, 2e)3F E JUMPER n SR17 R151 P 405F F W990 1B27[ BO(0-2)- I lB29 R 607F H 1B30| S 809F J T APABF K U CO DF L V E FF M N ADDRESS DETECT FIGURE E14.

-115SRVCY+ E F D NAND R1211 SRO+ F PWCLR- J LRCR4 L NAND INV. CTL10- K 1 SYSRST F R CHNRQFL R205 BOREQ- N 18 P CHNRQ+ AND (DCD) BT2A- V AND SRINT- S SBM S (DCD) BRKSTA T NAND R SELl+ U R121 SRVCY- v 3A21 CHANNEL REQUEST FIGURE E15.

-116BOPAR- D EXTADD ADRDT+ F AD E,H,K BOPI- r 3BI1 3B8 F OURAD- J E OURAD+ OPO+ D NAND H INV. D H ADQ+ I R 10 I3B 4 I B3B1 E lABL DL EXTREQ OURADANDD CHNRQ+,N MPP SEO+! r I I I ~~~~~~~~SELI T |MT - IPROP' M! IHI 17' SEL+ R001 SEL- tP 7 3B [ OPEI LXIROP2 J PROP1 BREINAND R111 AD- 3BOP8 SEF E SELmI ( ROOP M(M H SEL+ NAND L NAND INV.SR p R121 R121 L R n'7 SEL- 40 3BO6 3 B o 3B~9 1A27 ROP3 j R P PROP1 INAND D NANDIHTRP R121 Dq KR121 PROP2 F 3B~91 I I 13Bl 3 L T NND K~ SP~ROP+ U R121 INV. B 0P I- V 3BO9 R1 SPROPFIGURE E16. SELECT INTERCEPTION

-117CMINT+ I OURCM1 OURCM2 E CUBSY+ OURAD+ t N I 1 3 CUBSYOURCM4 INV. OURCM3 NAND- NAND R121 R1R1 21 3B+ V 3B12 BOPI INVT USVEBB1INV. KLT R17 N A A0R121 3NV R12 SEL+ R N3B12 PWCLR- PWCLR+2 q INV. ~RSTCM DR CMD CYADO+ I g C 9 _ FIURE E2B23 CHN S AR=AR -|3R11 T | R121 - BADI+ J 0 3B12 RSTCMO+ CMDCYK = BOPI J SRVENB R D BOPI+ FIGURE E17. CHANNE L SEIZURE121

-118CMDCY+ M AR1BI- E INV. D AR1BI+ NANDADO- N R1 L R17 CMDLY-, 3A,9 3A13!iE D BADI+:NAND R121 I-3AO9 H HJINV. IF AR2BI+ NAND R0 iR2BI- R~7 R121 A2I SRVCY+ K 3A13 3AP)9~Im~ BADI+ T DY1 CDY2 CDY3 CMDLY+ NAND V M INV. INV. AND FL J R113 R107 1 R107 (DCD) R205 CMO+ 1A25 1A27 1A7I 3HA7 CMO+ BOPI+ D CMDLYANDE (DCD) (INACTIVE GATE) N NQAND |LBOB R1M L BOBR1- K~iNV. I BOBRi+ NAND CMDCY+ J1A13 3A08 CMDLY+ E CHSRS N CMDL NAND AND FR121 DD CMO- F3A8 BT2A- V P CHSRV+ AND SRINT- S SBMA (DCD) FL R21aS BRKSTA T NANDR S 3AR7 SEL1+ U R121 F R CHSRVSRVCY+ V3A8.......~~~~~~~,,. I~~8 RSTCHN J INV. R121| 3AO8 BOPI+ FIGURE E18. COMMAND STORAGE

-119CMDCY+ M L K 00BI+ 40BI- 40BI+ SRVCY- NT NAND JNV. NAND U INV. T SRVCY- N NANDJ H U T CHSRV+R121 R7 R121 R107 CHSRV + 3A15 ~ 3A14 3A15 1A27 E- K UC>~ _ 00BI+ TSTIO+ SRSTACMDCY- S AND I S NAND R BSTI+ SRVCY+ T R121 T R121 U 3A15 1 U 3A16 STREQ+ V V CUBSYL1LIT;;;; 1L SPSTANAND N R121 P 3A16 H F SPSTA+ INV. J 10BI- 10BI+ NAND H S INV. R R121 R107 TSTIO- K 3A16 1A27 FIGURE E19. STATUS

-120TSTIO- p L CTL09SRO+ N NAND 00BI+ M 3A12 CMD.END K H CTL07NAND R121 CMO+ J 3A12 CMD.STACK CMDCY+ S R CTL08NAND ADO+ T NAND R121 SEO- U 3A12 INTF.DISC. SRSTA- E CMDCHN L CTL03F ER1E21CMDC R121N SPSTA- F B2 CMD.CHAIN SUO+ SRO+ FIGURE E20. COMMAND CYCLE END.

-121INTF.DISC. ADO+ E CTL10SRVCY+ F NAND D OPO- K NAND H SEL.RST. R121 CMO+ P3Al11 SERVICE END SEL1+ P N CYCSEL INV. R107 3A14 1B05 JUMPER LOADRS W990 E DADR09 INV, K IV D F DADR10 1A22 H DADK11 HIADRS K ADREXT M V J L ADREX2 1A22 F ADRES3 FIGURE E21. DATIA BREAK

-122~~~R P INV. N -~PREND+ E D PRENDI NAND -......R121 ZCTL0 F O UI~~~3A11. M L CTL11~NANDiO SRO+ NNAND R121 SRVCY+ 3A10 SRV.END BTBRKJ H BT1 T R S INV. R'R P, NAND NAND ~~~~~~~R121 R2 CTL10+ R2 BRKSTA S 1B28 1A30 (SRV HLT) iBTBRK+ S R BOREQ+ T R121 SEL1+ U 3A10 VBURST+ E D SROBUR E D REQ1 NAND NAND R121 R121 SRO+ tF F SRO+ 3A16 3A17 S R PREND- TNAND R121 SRVCY+ U3A9 SRINT- V CTLO0- V AND (DCD) F P _ BRKRQ+ R205 3B17 SEL1- U _ _ BRKRQAND R ADDACP ADDAC- (DCD) INV. L N 3A13 PWCLRFIGURE E22. DATA BREAK.

-123CTL06- S NANDR CMINT+ CTL07- T R121 CTL08- U 3A20 CMINTCTL09- V E INV. [ R107 3A14 E INTR8+ INTRPT NAND INVP PDP-8 INTERRUPT D K N IR121 Rill 3A15 3B14 CTL10- E D SRINT+ NAND.SRINT' INV I " P N R1711 ~B14 3A19 SRINT-.RI! RSTSRV BURST- J H BURBRK S INV.u v NAND Rill2 BRKRQ+ K RVCY+ MICLE RESETYC CHSRV+ NN L N

-124SWRST V OR T SYSRST _-~ _ ~~P.A. SUO- J SUOPO R603 NAND H R AND!B24 I R121 C S](DCD) SYSTEM RESET BOPI+ U V RSTCHN _[ ~NAND BURST+ P BURBK- 3A06 BRKRQ+ R 3ACHANNEL SERVICE RESET CMINT- E D RSTCMD NAND SRO+ SCCC I NAN H F CMDCY+R121 STACK ON INIT. SEL CHSRV+ A COMMAND CYCLE RESET R121 CMO+ P SELECTIVE RESET S I ADR OPO _ T- FIGURE E24

-125BOO+ I 1 PARBA P AR-[ PARGI PARQJ PARE N A N D INV. NAND INV. 1,NAND N R113 R107 D LR113 N PR17 NR113 B~i+1A2SPAROD ARll$ Bol+ IA23 1A26 PAO A24 IA26 PR 1A25 E ] 1 HNAND K NAND S P NAD H NAND S N B9+R113 R107R11 BO11A2351A26 J B02+ PAROCIiN NAND INV BO. L i~!N HIR iF B03-R113 Ra B83_ i A2 3I RI B94+ PARQ~~E PARF N PAROK NAND V R113' K J D F S R113 R113 -- 2 1A25 IV 6+ PPARHA2 1A23 ~ ~~~ ~ ~~~~ ~ ~~~~~~~~~~, [A61A51A26/ NAND I P I INV' T NAND K B0-R113 RB85- ~ l1 1XA24) l2 Nm I?A' B8.F E!25! BSO PAI po6[1A24 FIGURE E 2S5. BUS OUT 1P ARaITY

-126BBI0+ PARIA PARIB PARII- PARIJ PA" NAND K INV. D NAND INV. NA BBI1+ 1A07 1A09 PARID 1A08 1A09 ll BBI4BBI6R113 R113 R113 BBI1- lA07 1A18 EI I BUS I P T BBI2+ PARIC NAND I NV BBI3+ A07 A9 R BBI2-. L N M BBI4+ PARIE PARIF PARIK NAND F t K INV. D NAND F INV. R BBI6+ r 1 PARIH l 1A BBI,7+A09 | l Bl I I B I I4 BBI6- r 0 1 1.,I7- |iA0| ul I BBI6+ I 1 PARIG

-127PARO U PAROINV. T 1A26 E BOPAR R BOPARNAND INV. R1 D S BOP+ F R13R J NAND__ BUS OUT PARITY CHECK R113 BOP- KR12 3 E D CTL04NAND~ t(CMD PCK) BOBR1+ 1B J H CTL05R1A13 (SRV PCK) BOBR2+ 1B26 AR1BI+ E F ANDI D BBIP BBIP+ AR2BI+ H V INV. J AND 1B24 BR2BI+ K 2B29 L AND 00BI+ M 10BI+ P R AND 40B1I+ S BUS IN PARITY CHECK T AND CUBSY+ U V AND PARI U T 1A039 FIGURE E27.

-128-1 2 8 - 72B, ~~~~~~.RCV NAND l SBO(0-P) BBO(o-P) R123 BO(O-P) 1B14 V12 ONLIN+ NANDI INV. SBO(er-p) R 1 23 R107 ]~~~~~~~ OFLIN+ 1A12 1A17 1A15 1A18 1A22 (BSRO IS DELAYED) TAGS = ADO, CMO) l l 93~~~~~~~~~~~~~~~~~~~., SROP OPOl SUO ONLIN+ NAND I TS TAGS >R123 TAGS3 lB18 O FL I N+ V1 A15 I A1 1 A14 STAGS = ADO, SCMO, SSRO.. SOSRO, OPO, SUO ONLIN+ NOTE: BSRO NEEDS A DELAY (0.001 pfd TO GROUND) *- IBM LOG IC LEVE LS SFIGURE TAGS OUT GATING OFLIN+ 11 STAGS = SADO, SCMO, SSRO, SOPO, SSUO NOTE' BSRO NEEDS A DELAY (0.001 Hfd TO GROUND) -IMLOGIC LEVELS FIGURE E28. BUS-TAGS OUT GATING

-129SELOUT * E BSEO M SEO- N SEO+ F i ** BHLO N NA L P OFLINHLO E BRCE02(DOWN) HLO F 1NAB21 1 (UP) R UR SEONAND INV R S R R1 07 * I BM LOG I C LEVE LS 1A22 SSE2(DOWN)FIGURE E29. SELECT OUT GATING NAND NAND ~ IBM LOGIC LEVELS ~ REMOVE AT EC 29 DEC 67 FIGURE E29. SELECT OUT GATING

-130NAND BBI(0-P)+ >BDRV BI(0-P) BADI+ OP ADI ONLIN+ SPROP+ F SELPRP BDRV 1B13 OFLIN- H *IBM LOGIC LEVELS SELPRP (from relay) FIGURE E30. BUS-TAGS IN GATING

-131BREI- M RGATE- RGATE+ ADO- N NAND L H V R121 Ri7A BOPI- P OLSW1 j OLR- OLR+ (-R1213v for TO RELAY DRIVER on-line) K 0 A21 RGATE+ (3v for 1A19 ONLIN- E D ONLIN+ INV. FROM RELAY 1A22 CONTACTS ONLIN1A19 OFLIN- H F OFLIN+ INV.R107 1A22 OFLINFIGURE E31. ON-LINE/OFF-LINE CIRCUITRY

-132TEST E D OFTST+ NAND R 1 2 1 RR21 OFLIN- F 1A20 lE L m D OFTSTINV. PB4 S SWCTL R 1 2 1D,F F RI 23 12B4 INV. 2B03 PB75 | S NA SND WRST S. T. D, F R1 2 B 0 INV. 2B03 PB6 S PAN PWCLR-O S. T. D, F R I 2 3E 2 2. I

01-02 03-04 05-06 31-32 A IBM PDP-8 PDP-8 IBM A BUS PE03 ME30 BUS 01-02 03-04 31-32 B IBM PDP-8 IBM B TAG PF03 TAG 02 03 30 31 32 A TEST TEST TEST TEST TEST A PANEL PANEL PANEL PANEL PANEL 01 1 02 0 31 32 B TEST TEST TEST TEST B PANEL PANEL MPX PANEL PANEL 01-02 03-04 28 29-30 31-32 A PDP-8 PDP-8 EAC PDP-8 PDP-8 A PE02 PE04 ME34 ME35 3 01-02 03-04 28 29-30 31-32 B PDP-8 PDP-8 PDP-8 PDP-8 PF02 PF04 MF34 MF35 FIGURE E33. CONNECTOR POSITIONS

-134D AC00 E AC01 CABLE NE CABLE TO H AC02 DEVICES PDP-8 M AC04 W021 P AC05.3AO2 S AC06 T AC07 [AC(O-8) V AC08 V ACJ2 V D D CABLE CABLE FROM H H TO DEVICES K K PDP-8 W021 M M W021 3B02 P TACCLRP 3B01 S RUN S T ACJ1 AC09 AC10 AC11 SKIP M CABLE TO INTRPT K MULTIPLEX REQ1 D W021 E 2B30 3B08 SEL1S R SEL1+ INV. D DADROO CABLE CABLE R107 H DADR02 W021 W021 K DADR03 1A04 1A0314 M DADR04 P DADR05 V DAJ V S DADR06 T DADRP07 CABLE D CABLE V DADR08 FROM E E TO DEVICES H H PDP-8 W021 K BRKREQ K W021 1Bt04 M M 1B03 P P S T S T M MINCR T DADR09 DADR10 DADR11 ADDACP XFER FGRXFER I4PP B ONT g 1 3BRKSTA FIGURE E34. PDP-8 CABLE CONNECTORS (Page 1 of 3)

-135D MB00 E MB01 CABLE CABLE H MB0 DEVICES MB(0-8) TOPDP-8 MB0 M MB04 1A22 W021 W021 P MB05 T MB07 MB(4-8) I V MB08 D D CABLE E CABLE FROM H TO DEVICES PDP-8 W021 w021 3B033 -' 3B04 MB99 - MB09 A _ N _ MB10 N_ MB11 P WC=0_ CYCSEL D EAC00 3A28 E EAC01 CABLE H EAC02 DEVICES EAC(_-8)K EAC03 W21C(0-8)M EAC04 P EAC05 S EAC06 CABLE T EAC07 FROM EAC(9.-11)V EAC08 DEVICES W021 K RDENB D EAC09 3B28 3B28 M SKPENB E EAC10 H EACll D BAC00 3B30-29 E BAC01 H BAC02 CABLE CABLE K BAC03 DEVICES TOPDP-8 W021 W921 M BAC04 W W P BAC05 3B30 3B29 S BAC06 T BAC07 BAC(0-8)V BAC08 PDP-8 CABLES FIGURE E34. PDP-8 CABLE CONNECTORS (Page 2 of 3)

-136BBIP+ D BBI0+ E W021MJ BBI1+ F. CABLE (ISOLATORS ON ALL LINES) BBI2+ H TO BBI3+ J TEST BBI4+ K PANEL PANEL BBI4+ L 2B31 2B31 BBI5+ L BBI6+ M BBI7+ N CTL00+ P CTL01+ R CTL02+ S CTL03+ T CTL04+ U CTL05+ V BOP+ D BO+ E W021MJ BO1+ F CABLE (ISOLATORS ON ALL LINES) B02+ H TO B03+ J TEST PANEL B04+ K PANEL 2B32 B05+ L B06+ M B07+ N CTL06+ P CTL07+ R CTL08+ S CTL09+ T CTL10+ U CTL1ll+ V SBOP (SWITCH FILTERS W021MJ SBO0 ON ALL LINES) CABLE SBO1 TO SB02 TEST SBO3 PANEL SBO 2A3B SB05 SB06 SB07 FIGURE E36. TEST PANEL CONNECTORS (Page 3 of 3)

-137W021 BI (0-P) IBM CABLE 1A01 D BI0 E BI1 W021 H BI2 I-M K BI3 CABLE M BI4 1A02 P BI5 S BI6 T BI7 V BIP D BOO E B01 H B02 K B03 M B04 T B07 V BOP CAB LE lA31 FIGURE E35. IBM CABLE CONNECTORS (Page 1 of 2) D W021 E IBM H CABLE K 1B01 M SEI P SELOUT S ADO T CMO V SUO OPI D STI E W021 ADI_ H IBM SRI K CABLE M 1B02 SELPRP P NOTE IN CLTs V NOTE: ALL LINES CARRY IBM LOGIC LEVELS.

D SRO W021 E HCLO IBM H MTRO CABLE K MTRI lB31 M S PWRINT T HLO V OPO D E W021 H IBM o K CABLE REI 1 B 3 2 V IBMJ P NOTE: ALL LINES CARRY IBM LOGIC LEVELS FIGURE E35. IBM CABLE CONNECTORS(Page 2 of 2)

-139ARi~+ D AR11+ E W021MJ AR12+ F CABLE (ISOLATORS ON ALL LINES) AR13+ H TO AR14+ J TEST AR15+ K PANEL AR16+ L AR17+ M BR10+ N BR11+ P BR12+ R BR13+ S BR14+ T BR15+ U BR16+ V (UNASSIGNED) D BADI+ E BSTI+ F CABLE (ISOLATORS ON ALL LINES) BSRI+ H TO SPROP+ j TEST BOPI+ K PAN BREI+ L BR17+ M OFTST+ N ADO+ P CMO+ R STO+ S SEO+ T OPO+ U SUO+ V PBO w021MJ PB1 CABLE PB2 (ISOLATORS ONLY ON*) TO PB3 (SWITCH FILTERS ON $) TEST PB4 PANEL PB ~~2BO~2 ~PB6 PB7 OLSW1 OFLIN+ OLSW2 OFLIN+ * ONLIN+ SSEO1 FIGURE E36. TEST PANEL CONNECTORS (Page 1 of 3)

-140D TEST W021MJ E SADO CABLE F SCMO CAB LE TO H SSRO (SWITCH FILTERS TEST J SSE02 ON ALL LINES) PANEL K SOPO 2B01 L SSUO M SW0+ N SW1+ P SW2+ R SW3+ S SW4+ T SW5+ U SW6+ V SW7+ AR20+ D AR21+ E W021MJ AR22+ F CABLE (ISOLATORS ON ALL LINES) AR23+ H TO AR24+ J TEST AR25+ K PANEL AR26+ L AR27+ M SEL+ N CMDCY+ P SRVCY+ R CUBSY+ S CMDLY+ T CHSRV+ U BR20+ D BR21+ E W021MJ BR22+ F CABLE (ISOLATORS ON ALL LINES) BR23+ H TO BR24+ J TEST BR25+ K PANEL 2A32 BR26+ L BR27+ M CHNRQ+ N PREND+ P BRKRQ+ R INTR8+ S SKIP+ T EACENB U FIGURE E36. TEST PANEL CONNECTORS (Page 2 of 3)

K1 INV. PWCLRD D 3 B 1 C 3LE E AL FROM T 0 P DP -8 H HLDEVICES E INV. BT2AW 0 2 K K W0)21 R107 DD 3 B 29 M Mi 3B30 3A19 Pi p S S Ha INV. BTIT T R107 F V V 3B PWRCLR BT2A BT1 IOP4 IOP2 BAC11 — D BMBOO iaI aca E BMB01- igIBGS H BMB02-IP4 K BMB03- i _4INV. O" M BMB03+ P A197% P BMB04 — S BMB04+ CABLE CABLE T BMB05- g PDP-8 ~ _ DEVICES " INV. IOP2V BMB05+ W021 II Wp121 R1S0l7 L 3A31 3A32 a3A191 BMB(3-5)+ BMB(O-5 - D BMBPI6E ]BMB06++ H BM B07K BMB07+ 81CABLE B hICABLE M BMB08- PDP-8 B DEVICES P BMBe)8+ We)21 W I WP21 3B31 3B32 S BMB0~9T BMB10- J BMB( 6-8)+ BMB(6-11) CABLE D ADREX1 -D- CABLE PDP-8 E ADREX2 E DEVICES W021CR- H ADREX3 Hl W021CR 1A5 K DFO K-1 1~ M DF1 M D )U? T

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APPENDIX P MAINTENANCE AND DIAGNOSTIC FACILITIES

MAINTENANCE AND DIAGNOSTIC FACILITIES Fl. The Test Panel The System/360 interface contains facilities for self-checking during its operation and for diagnosing circuit faults. Maintenance operations can be carried out both onand off-line using built-in test controls and indicators. Precipitous fault conditions can be detected with conventional perturbation methods using the margin-check power supply of the PDP-8. The principal test component is the Test Panel, shown in Figure Fl. The top two rows of indicators on the left on this panel monitor the contents of the four principal data registers of the interface: AR1, AR2, BR1, and BR2. The next two rows of indicators monitor the status of the channel interface tag lines and bus lines. The upper row of these monitors information placed by the interface on the inbound lines to the channel; the lower row monitors information placed by the channel on the outbound lines to the interface. Beneath these indicators is a row of switches used to simulate the outbound lines in off-line operation. The large pushbutton at the extreme lower right controls the on/offline status of the interface. None of the test controls are operable when this switch in the on-line position, although the various indicators continue to monitor the state of the circuitry. When the equipment is in the off-line or test condition the signals to the channel lines are deactivated in such a way that servicing operations and power up/down sequencing can be conducted without in any way affecting the operations by the channel with other control units. To the right of the block of indicators just described is a block of 24 indicators which monitor the status of most of the control flip-flops of the interface. These can be roughly grouped as follows: If one of the top row of indicators is lit, then the interface is actively communicating with the -147

..ADR REG 1, — Y..... ADR REG 2-. UCDSVC 0 i ~2 3 4 5 6 7 0 1 2 3 4 5 6 7 S EL CYC CYC BZY IL R 0 0 0 0 00 00 0 00 00O0 00 000 0 0 BUF REG 1-. U REG 2 A L-R R N f- 0 1 2 3 4 5 6 7 0 2 3 4 6 7RE EN RQRQ TAGS IN y~~~~~~~~~~~R BUSS IN CT LSKP CM GOD ADR STA SRV SEL OPL REQ P 0 1 2 3 4 5 6 7'0 1 H LN 0 0 0 00 00 00 00 00 0 00 0O0 000 f.......TAGS INO....USN.....-'TL OPUT CM DCCMD SRV GOD ADR STA SRV SEL OPL SUQp01 2 3 4 5 6 7 0S 1T 2L EHND PCC 00 0 00 00 00 00 00 00 00 00000 I TAGS OUT... \~BUSS OUT....., Y M M M R R TST ARCDSRV SEL OPL SUP P 0 1 2 3 4 5 6 7 RTSKHTEDHTE D c 9.......REG DATA......V REG LOAD TL ICTL PWR SYSONLE 0 1 2 3 4 5 6 7 AR1 BRI AR2 BR2 OP CLR CLR RST FIGURE Fl. TEST PANEL LAYOUT.

-149channel. During various parts of a channel-interface operation, the next row of indicators may be lit. A service cycle (data or status) will result in alternate operation of the CHL REQ and BRK REQ indicators. The last two rows of indicators represent the contents of the CTL register exactly as indicated to the resident PDP-8 program. F2. Diagnostic Procedures In normal system operations the interface is online to the System/360 as indicated by the illuminated pushbutton switch at the lower right of the test panel. Alternate depressions of this pushbutton switch the interface from the on-line, to the off-line state and vice versa. In the off-line state the interface is logically disconnected from the System/360 channel-control unit lines and may be tested independently of the System/360 using the manual controls on the test panel and certain PDP-8 test programs constructed for this purpose and described below. In some situations it is desirable to activate the manual controls on the test panel when the interface is on-line to the System/360. A special override switch (TEST) is provided for this purpose. The lamp above this switch indicates, when lit, that the manual controls are operative. The interface contains special circuitry which prevents transitions to and from the on-line state when channel operations are pending at the interface. Therefore servicing operations involving such transitions can proceed without disturbing the System/360. Following is a description of diagnostic utilities intended to ferret out most component failures.

360 INTERFACE REGISTER TEST Purpose Program tests AR1, BR1, AR2, and CTL gating with the AC, and in addition tests BR2 gating with the MB. Read, Clear, and Write operations are tested with AR1, BR1, and AR2. Read, test-under-mask and invert under-mask operations are tested with CTL. The interrupt facility is tested in conjunction with CTL; and the 3-cycle data break facility is tested in conjunction with BR2. DIRECTIONS FOR USE a. Switch interface off-line. b. START program at 200. Program will stop at 214. c. Using manual controls, load all ones (377 octal) into AR1, BR1, and AR2. Press CONTINUE. d. Program will loop through all tests in about 3 seconds Error stops are documented in program listing. 360 INTERFACE ECHO TEST Purpose Program tests all channel interface circuitry except bus drivers, receivers and on-line/off-line circuitry. Channel interface sequences are simulated with the manual controls. DIRECTIONS FOR USE a. Switch interface off-line. Raise OPL OUT and BUS OUT (P) switches. b. Load program. START at 0200. Lower SR switches. Program will loop. c. System Reset. Lower OPL OUT switch. Program will stop at 221. AC will contain 0040 and SYS RST lamp will be on in CTL. Raise OPL OUT; press CONTINUE. -150

-151/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 1 /* /* SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES * / /INTERFACE REGISTER DEFINITIONS / RD=1 /IOP READ CLR=2 /IOP CLEAR TST=2 /IOP TEST WR=4 /IOP WRITE INV=4 /IOP INVERT AR1=6300 /ADDRESS REGISTER 1 BR1=6310 /BUFFER REGISTER 1 AR2=6320 /ADDRESS REGISTER 2 CTL=6330 /CONTROL REGISTER / /INTERFACE CONTROL REGISTER BIT DEFINITIONS / STREQ=7000 /STATUS REQUEST BIREQ=4000 /BUS-INBOUND SERVICE REQUEST BOREO=2000 /BUS-OUTBOUND SERVICE REQUEST CMDCHN=0400 /COMMAND CHAIN CMDPCK=0200 /BUS-OUT PARITY CHECK ON COMMAND BYT SRVPCK=0100 /BUS-OUT PARITY CHECK ON DATA BYTE CMDRST=0040 /SYSTEM OR SELECTIVE RESET CMDSTK=0020 /STACK STATUS ON INITIAL SELECTION CMDHLT=0010 /HALT I/O CMDEND=0004 /COMMAND ACCEPT SRVHLT=0002 /SERVICE STOP SRVEND=0001 /PDP-8 WC=O / /SYSTEM/360 STATUS BYTE DEFINITIONS / UNCHCK=002 /02 UNIT CHECK DEVEND=004 /04 DEVICE END CHNEND=010 /08 CHANNEL END / / 0001 5420 JMP I INTRPT BR2BLK,*.+2 / *10 AXR1, *.+1 / *20 0020 0100 INTRPT,INTX 0021 0001 BR2DBP,BR2BLK-1 0022 0035 BR2CA, TMP3-1 0023 0002 XSRHLT,SRVHLT 0024 2000 XBOREQBOREQ 0025 4000 XBIREQ,BIREQ 0026 0377 K0377, 0377 0027 0777 K0777, 0777 0030 7000 K7000, 7000 0031 7400 K7400, 7400

-152/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 2 / 0032 7767 K7767, 7767 0033 7772 K7772, 7772 TMP1, *.+1 TMP2, *.+1 TMP3, *.+1 AC, *.+1 / *100 / /INTERRUPT ROUTINE / 0100 3037 INTX, DCA AC 0101 6042 TCF 0102 6032 KCC 0103 6331 CTL RD 0104 0027 AND K0777 0105 7640 SZA CLA 0106 2000 ISZ 0 0107 1037 TAD AC 011Q 5400 JMP I 0 / /START USING START KEY / *200 / /TEST AR1, BR1, AR2 REGISTERS / 0200 6301 START, AR1 RD 0201 7440 SZA 0202 7402 HLT /AR1-AC GATES PICKED UP A BIT (AC) 0203 7200 CLA 0204 6311 BR1 RD 0205 7440 SZA 0206 7402 HLT /BR1-AC GATES PICKED UP A BIT (AC) 0207 7200 CLA 0210 6321 AR2 RD 0211 7440 SZA 0212 7402 HLT /BR2-AC GATES FAILED A BIT (AC) 0213 7200 CLA 0214 7402 HLT /OPERATOR ACTION PAUSE / /LOAD ONES INTO AR1, BRi, AND BR2 USING MANUAL /CONTROLS. RESTART USING CONTINUE KEY / 0215 1031 ARITi, TAD K7400 0216 6301 ARI RD 0217 7040 CMA 0220 7440 SZA 0221 7402 HLT /ARI-AC GATES DROPPED A BIT (AC) 0222 7200 CLA 0223 6302 AR1 CLR 0224 6301 AR1 RD 0225 7440 SZA 0226 7402 HLT /CLEAR AR1 GATES FAILED A BIT (AC) 0227 7240 STA 0230 6304 AR1 WR 0231 0031 AND K7400

-153/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 3 / 0232 6301 ARi RD 0233 7040 CMA 0234 7440 SZA 0235 7402 HLT /AC-ARI GATES DROPPED A BIT (AC) 0236 7200 CLA 0237 6304 AR1 WR 0240 1031 TAD K7400 0241 6301 AR1 RD 0242 7040 CMA 0243 7440 SZA 0244 7402 HLT /AC-ARL1 GATES INVERTED A BIT (AC) 0245 7200 CLA / 0246 1031 BRiTl, TAD K7400 0247 6311 BRi RD 0250 7040 CMA 0251 7440 SZA 0252 7402 HLT /BR1-AC GATES DROPPED A BIT (AC) 0253 7200 CLA 0254 6312 BRI CLR 0255 6311 BRI RD 0256 7440 SZA 0257 7402 HLT /CLEAR BR1 GATES FAILED A BIT (AC) 0260 7240 STA 0261 6314 BR1 WR 0262 0031 AND K7400 0263 6311 BR1 RD 0264 7040 CMA 0265 7440 SZA 0266 7402 HLT /AC-BR1 GATES DROPPED A BIT (AC) 0267 7200 CLA 0270 6314 BR1 WR 0271 1031 TAD K7400 0272 6311 BRI RD 0273 7040 CMA 0274 7440 SZA 0275 7402 HLT /AC-BR1 GATES INVERTED A BIT (AC) 0276 7200 CLA / 0277 1031 AR2TL, TAD K7400 0300 6321 AR2 RD 0301 7040 CMA 0302 7440 SZA 0303 7402 HLT /AR2-AC GATES DROPPED A BIT (AC) 0304 7200 CLA 0305 6322 AR2 CLR 0306 6321 AR2 RD 0307 7440 SZA 0310 7402 HLT /CLEAR AR2 GATES FAILED A BIT (AC) 0311 7240 STA 0312 6324 AR2 WR 0313 0031 AND K7400 0314 6321 AR2 RD 0315 7040 CMA 0316 7440 SZA 0317 7402 HLT /AC-AR2 GATES DROPPED A BIT (AC) 0320 7200 CLA 0321 6324 AR2 WR

-154/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 4 / 0322 1031 TAD K7400 0323 6321 AR2 RD 0324 7040 CMA 0325 7440 SZA 0326 7402 HLT /AC-AR2 GATES INVERTED A BIT (AC) 0327 7200 CLA 0330 5731 JMP I.+1 0331 0400 AR1T2 / *400 / /TEST ARl, BRl, AR2 REGISTERS / 0400 3034 ARiT2, DCA TMP1 0401 1034 TAD TMP1 0402 6306 AR1 CLR+WR 0403 0031 AND K7400 0404 6301 AR1 RD 0405 3035 DCA TMP2 0406 1035 TAD TMP2 0407 7040 CMA 0410 0034 AND TMP1 0411 7440 SZA 0412 7402 HLT /AR1 ECHO DROPPED A BIT (AC) 0413 7200 CLA 0414 1034 TAD TMP1 0415 7040 CMA 0416 0035 AND TMP2 0417 7440 SZA 0420 7402 HLT /AR1 ECHO PICKED UP A BIT (AC) 0421 7200 CLA 0422 2034 ISZ TMP1 0423 5201 JMP ARIT2+1 / 0424 3034 BRlT2, DCA TMP1 0425 1034 TAD TMP1 0426 6316 BR1 CLR+WR 0427 0031 AND K7400 0430 6311 BR1 RD 0431 3035 DCA TMP2 0432 1035 TAD TMP2 0433 7040 CMA 0434 0034 AND TMP1 0435 7440 SZA 0436 7402 HLT /BR1 ECHO DROPPED A BIT (AC) 0437 7200 CLA 0440 1034 TAD TMP1 0441 7040 CMA 0442 0035 AND TMP2 0443 7440 SZA 0444 7402 HLT /BR1 ECHO PICKED UP A BIT (AC) 0445 7200 CLA 0446 2034 ISZ TMP1 0447 5225 JMP BRlT2+1 / 0450 3034 AR2T2, DCA TMP1 0451 1034 TAD TMP1

-155/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 5 / 0452 6326 AR2 CLR+WR 0453 0031 AND K7400 0454 6321 AR2 RD 0455 3035 DCA TMP2 0456 1035 TAD TMP2 0457 7040 CMA 0460 0034 AND TMP1 0461 7440 SZA 0462 7402 HLT /AR2 ECHO DROPPED A BIT (AC) 0463 7200 CLA 0464 1034 TAD TMP1 0465 7040 CMA 0466 0035 AND TMP2 0467 7440 SZA 0470 7402 HLT /AR2 ECHO PICKED UP A BIT (AC) 0471 7200 CLA 0472 2034 ISZ TMP1 0473 5251 JMP AR2T2+1 0474 5675 JMP I.+l 0475 0600 CTLTI / *600 / /TEST CONTROL REGISTER GATING / 0600 6331 CTLT1, CTL RD 0601 7440 SZA 0602 7402 HLT /CTL-AC GATES PICKED UP A BIT (AC) 0603 7200 CLA 0604 1027 TAD K0777 0605 6334 CTL INV 0606 7200 CLA 0607 1030 TAD K7000 0610 6331 CTL RD 0611 7040 CMA 0612 7440 SZA 0613 7402 HLT /CTL-AC GATES DROPPED A BIT (AC) 0614 7200 CLA 0615 1027 TAD K0777 0616 6334 CTL INV 0617 7200 CLA 0620 6331 CTL RD 0621 7440 SZA 0622 7402 HLT /CTL FAILED TO INVERT A BIT (AC) 0623 7200 CLA / 0624 3034 CTLT2, DCA TMP1 0625 1034 TAD TMP1 0626 6334 CTL INV 0627 7200 CLA 0630 6331 CTL RD 0631 3035 DCA TMP2 0632 1035 TAD TMP2 0633 7040 CMA 0634 0034 AND TMP1 0635 7440 SZA 0636 7402 HLT /CTL ECHO DROPPED A BIT (AC)

-156/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 6 / 0637 7200 CLA 0640 1034 TAD TMP1 0641 7040 CMA 0642 0035 AND TMP2 0643 7440 SZA 0644 7402 HLT /CTL ECHO PICKED UP A BIT (AC) 0645 7200 CLA 0646 1034 TAD TMP1 0647 6334 CTL INV 0650 7200 CLA 0651 6331 CTL RD 0652 7440 SZA 0653 7402 HLT /CTL FAILED TO INVERT A BIT (AC) 0654 7200 CLA 0655 1034 TAD TMP1 0656 7001 IAC 0657 0027 AND K0777 0660 7440 SZA 0661 5224 JMP CTLT2 / 0662 1032 CTLT3, TAD K7767 0663 3034 DCA TMP1 0664 7120 STL 0665 6334 CTLT3A,CTL INV 0666 6332 CTL TST 0667 7402 HLT /CTL TST FAILED TO SKIP 0670 7040 CMA 0671 6332 CTL TST 0672 7410 SKP 0673 7402 HLT /CTL TST SKIPPED IN ERROR 0674 7040 CMA 0675 6334 CTL INV 0676 7004 RAL 0677 2034 ISZ TMP1 0700 5265 JMP CTLT3A 0701 7200 CLA / 0702 3034 CTLT4, DCA TMP1 0703 1034 TAD TMP1 0704 6334 CTL INV 0705 7200 CLA 0706 3035 CTL4C, DCA TMP2 0707 1035 TAD TMP2 0710 0034 AND TMP1 0711 7041 CIA 0712 1035 TAD TMP2 0713 7640 SZA CLA 0714 5321 JMP CTL4A 0715 1035 TAD TMP2 0716 6332 CTL TST 0717 7402 HLT /CTL TST FAILED TO SKIP 0720 5325 JMP CTL4B / 0721 1035 CTL4A, TAD TMP2 0722 6332 CTL TST 0723 7410 SKP 0724 7402 HLT /CTL TST SKIPPED IN ERROR 0725 7001 CTL4B, IAC

-157/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 7 0726 7440 SZA 0727 5306 JMP CTL4C 0730 6335 CTL RD+INV 0731 7104 CLL RAL 0732 0027 AND K0777 0733 7440 SZA 0734 5302 JMP CTLT4 / 0735 1033 CTLT5, TAD K7772 0736 3035 DCA TMP2 0737 7120 STL 0740 7004 CTLT5A,RAL 0741 6334 CTL INV 0742 6001 ION 0743 7000 NOP 0744 7402 HLT /CTL FAILED TO INTERRUPT 0745 6334 CTL INV 0746 6001 ION 0747 7000 NOP 0750 7410 SKP 0751 7402 HLT /CTL INTERRUPTED IN ERROR 0752 6002 IOF 0753 2035 ISZ TMP2 0754 5340 JMP CTLT5A 0755 7200 CLA 0756 5757 JMP I.+1 0757 1000 BR2TI / *1000 / /TEST BR2 AND DATA BREAK / 1000 3034 BR2T1, DCA TMP1 1001 1034 TAD TMP1 1002 3036 DCA TMP3 1003 1021 TAD BR2DBP 1004 3010 DCA AXR1 1005 7240 STA 1006 3410 DCA I AXR1 1007 1022 TAD BR2CA 1010 3410 DCA I AXRi 1011 1025 TAD. XBIREO 1012 6334 CTL INV 1013 7200 CLA 1014 3035 DCA TMP2 1015 1021 BR2T1E,TAD BR2DBP 1016 3010 DCA AXR1 1017 1410 TAD I AXR1 1020 7650 SNA CLA 1021 5225 JMP BR2T1A 1022 2035 ISZ TMP2 1023 5215 JMP BR2T1E 1024 7402 HLT /DB WORD COUNT FAILED TO DECREMENT 1025 1022 BR2T1A,TAD BR2CA 1026 7040 CMA 1027 1410 TAD I AXR1 1030 7440 SZA

-158/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 8 / 1031 7402 HLT /DB CURRENT ADDRESS FAILED TO INCREM 1032 7200 CLA 1033 1034 TAD TMP1 1034 7041 CIA 1035 1036 TAD TMP3 1036 7440 SZA 1037 7402 HLT /DB TRANSFER DIRECTION SENSE WRONG 1040 7200 CLA 1041 1023 TAD XSRHLT 1042 6335 CTL RD+INV 1043 7200 CLA 1044 6335 CTL RD+INV 1045 7200 CLA 1046 3036 DCA TMP3 1047 1021 TAD BR2DBP 1050 3010 DCA AXR1 1051 7240 STA 1052 3410 DCA I AXR1 1053 1022 TAD BR2CA 1054 3410 DCA I AXR1 1055 1024 TAD XBOREQ /(RATHER UNORTHODOX SEQUENCE) 1056 6334 CTL INV 1057 1025 TAD XBIREQ 1060 6334 CTL INV 1061 6334 CTL INV 1062 7200 CLA 1063 3035 DCA TMP2 1064 1021 BR2T1D,TAD BR2DBP 1065 3010 DCA AXR1 1066 1410 TAD I AXR1 1067 7650 SNA CLA 1070 5274 JMP BR2T1C 1071 2035 ISZ TMP2 1072 5264 JMP BR2T1D 1073 7402 HLT /DB WORD COUNT FAILED TO DECREMENT 1074 1022 BR2TLC,TAD BR2CA 1075 7040 CMA 1076 1410 TAD I AXR1 1077 7440 SZA 1100 7402 HLT /DB CURRENT ADDRESS FAILED TO INCREM 1101 7200 CLA 1102 1023 TAD XSRHLT 1103 6335 CTL RD+INV 1104 7200 CLA 1105 6335 CTL RD+INV 1106 7200 CLA 1107 1036 TAD TMP3 1110 0031 AND K7400 1111 7440 SZA 1112 7402 HLT /DB PICKED UP BITS IN POS 0-3 1113 7200 CLA 1114 1034 TAD TMPi 1115 0031 AND K7400 1116 1036 TAD TMP3 1117 3036 DCA TMP3 1120 1034 TAD TMP1 1121 7040 CMA 1122 0036 AND TMP3

-159/SYSTEM./360 INTERFACE DIAGNOSTIC ROUTINES PAGE 9 / 1123 7440 SZA 1124 7402 HLT /BR2 ECHO FAILED 1125 7200 CLA 1126 1036 TAO TMP3 1127 7040 CMA 1130 0034 AND TMP1 1131 7440 SZA 1132 7402 HLT /BR2 ECHO FAILED 1133 7200 CLA 1134 2034 ISZ TMP1 1135 5201 JMP BR2T1+1 / 1136 5737 JMP I.+1 1137 0215 ARITI / AC 0037 AR1 6300 ARiTi 0215 AR1T2 0400 AR2 6320 AR2T1 0277 AR2T2 0450 AXR1 0010 BIREQ 4000 BOREO 2000 BRi 6310 BRIT1 0246 BRIT2 0424 BR2BLK 0002 BR2CA 0022 BR2DBP 0021 BR2T1 1000 BR2T1A 1025 BR2T1C 1074 BR2T1D 1064 BR2T1E 1015 CHNEND 0010 CLR 0002 CMDCHN 0400 CMDEND 0004 CMDHLT 0010 CMDPCK 0200 CMDRST 0040 CMDSTK 0020 CTL 6330 CTLT1 0600 CTLT2 0624 CTLT3 0662 CTLT3A 0665 CTLT4 0702 CTLT5 0735 CTLT5A 0740 CTL4A 0721 CTL4B 0725 CTL4C 0706 DEVEND 0004 INTRPT 0020 INTX 0100

-160INV 0004 K0377 0026 K0777 0027 K7000 0030 K7400 0031 K7767 0032 K7772 0033 RD 0001 SRVEND 0001 SRVHLT 0002 SRVPCK 0100 START 0200 STREQ 7000 TMP1 0034 TMP2 0035 TMP3 0036 TST 0002 UNCHCK 0002 WR 0004 XBIREO 0025 XBOREO 0024 XSRHLT 0023

-161d. Test I/O. Perform the following sequence. 1. Place valid device address recognized by interface on BUS OUT switches. 2. Raise ADR OUT. 3. Raise SEL OUT. Interface will respond with OPL IN, store BUS OUT in AR1 and clear BR1, CU SEL and CMD CYC lamps will go on. 4. Lower ADR OUT. Interface will respond with ADR IN and place AR1 on BUS IN. CU SEL lamp will go off. 5. Raise BUS OUT (P). Lower all other BUS OUT switches. Raise CMD OUT. Interface will respond by dropping ADR IN. CMD DLY lamp will go on. 6. Drop CMD OUT. Interface will respond with STA IN and place the status modifier bit (position 2) on BUS IN. CHL SRV lamp will come on. 7. Raise SRV OUT. Interface will drop all inbound signals and disconnect. CMD CYC, CMD DLY, and CHL SRV lamps will all go off. e. Start I/O. Perform the above sequence except Step 5. At Step 5 place a valid (non zero) channel command on BUS OUT and raise CMD OUT. Interface will respond by dropping ADR IN. CMD DLY lamp will go on. At Step 6 the interface will place an all-zero status byte on BUS IN. Before Step 7 press STOP on PDP-8. After Step 7 the CMD END lamp will go on CTL. Press CONTINUE; the CMD END bit will go off and the CHN REQ lamp will go on together with one or more bits in the order field of the CTL. The PDP-8 will continue running. f. Service cycle sequences. Perform a Start I/O operation with a channel command specifying channel-inbound service (e.g., octal 2). The CHL REQ and CTL (0) lamps will go on. The REQ IN tag line lamp will also go on. Perform the following procedure. 1. Load a nonzero device address in AR2.

-1622. Raise SEL OUT. Interface will respond by placing AR2 on BUS IN and raising ADR IN and OPL IN. REQ IN will be dropped. CU SEL and SRV CYC lamps will go on. 3. Lower SEL OUT. CU SEL lamp will go out. 4. Raise CMD OUT. Interface will respond by dropping ADR IN. CMD DLY lamp will go on. 5. Drop CMD OUT. Interface will respond by raising SRV IN. CHL SRV lamp will go on. 6. Stop PDP-8. Raise SRV OUT. Interface will drop all inbound tags and disconnect. SRV CYC, CMD DLY, and CHL SRV lamps will go out. BRK REQ lamp will go on. 7. Start PDP-8. The cycle will recommence at Step 2 and may be continued until either PDP-8 word count decrements to zero or until at Step 6 CMD OUT is raised instead of SRV OUT. In these cases the appropriate bits are set in CTL. (See interface description.)

- 163/SYSTEM/360 INTERFACE ECHO TEST ROUTINES PAGE 1 / /***************** **44********444********** ******* *********** /* SYSTEM/360 INTERFACE ECHO TEST ROUTINES * /* OR - HOW TO GET ALONG WITH THE 2870 ALMOSI * /* * / /ASSEMBLY PARAMETERS / BUFSIZ=4000 /MAXIMUM SIZE OF DATA BUFFER / /INTERFACE REGISTER DEFINITIONS / RD=1 /IOP READ CLR=2 /IOP CLEAR TST=2 /IOP TEST WR=4 /IOP WRITE INV=4 /IOP INVERT AR1=6300 /ADDRESS REGISTER 1 BR1=6310 /BUFFER REGISTER 1 AR2=6320 /ADDRESS REGISTER 2 CTL=6330 /CONTROL REGISTER / /INTERFACE CONTROL REGISTER BIT DEFINITIONS / STREQ=7000 /STATUS REQUEST BIREQ=4000 /BUS-INBOUND SERVICE REQUEST BOREQ=2000 /BUS-OUTBOUND SERVICE REQUEST CMDCHN=0400 /COMMAND CHAIN CMDPCK=0200 /BUS-OUT PARITY CHECK ON COMMAND BYT SRVPCK=0100 /BUS-OUT PARITY CHECK ON DATA BYTE CMDRST=0040 /SYSTEM OR SELECTIVE RESET CMDSTK=0020 /STACK STATUS ON INITIAL SELECTION CMDHLT=0010 /HALT I/O CMDEND=0004 /COMMAND ACCEPT SRVHLT=0002 /SERVICE STOP SRVEND=0001 /PDP-8 WC=O / /SYSTEM/360 STATUS BYTE DEFINITIONS / UNCHCK=002 /02 UNIT CHECK DEVEND=004 /04 DEVICE END CHNEND=010 /08 CHANNEL END / *2 / BLKXFR,*.+2 /3-CYCLE DATA BREAK BLOCK 4200 0200 4246 TEST, JMS DELAY /WAIT FOR CHANNEL SERVICE 0201 1320 TAD ACTIVE /DID CHANNEL STORE COMMAND 0202 7450 SNA 0203 5200 JMP TEST /NO. KEEP TRYING 0204 7L10 CLL RAR /YES. IS OUTBOUND SERVICE REQUESTED 0205 7620 SNL CLA 0206 5213 JMP TST2 /NO. CONTINUE 0207 1317 TAD BUFLNG /GET BUFFER SIZE

-164/SYSTEM/360 INTERFACE ECHO TEST ROUTINES PAGE 2 / 0210 4277 JMS XMT /YES. REQUEST OUTBOUND SERVICE 0211 2000 BOREQ 0212 5216 JMP TST3 / 0213 1317 TST2, TAD BUFLNG /GET BUFFER SIZE 0214 4277 JMS XMT /REQUEST INBOUND SERVICE 0215 4000 BIREQ 0216 4232 TST3, JMS STATUS /TRANSMIT ENDING STATUS 0217 0004 DEVEND 0220 5200 JMP TEST / 0221 7402 ERROR, HLT /EQUIPMENT/PROGRAM CHECK 0222 6334 CTL INV /RESET INTERFACE 0223 7604 LAS /SR=ENDING STATUS 0224 7450 SNA 3225 5200 JMP TEST 0226 3230 DCA.+2 0227 4232 JMS STATUS /TRANSMIT ENDING STATUS 0230 0000 0 0231 5200 JMP TEST /RETURN TO WAIT LOOP / /TRANSMIT STATUS TO CHANNEL 0232 0000 STATUS,O /NORMAL ENTRY 0233 4246 JMS DELAY /WAIT FOR CHANNEL SERVICE 0234 1312 TAD ENDCHN /1ST BYTE - CHANNEL END 0235 3322 DCA BUF 0236 1632 TAD I STATUS /ARGUMENT=2ND BYIt - DEVICE-END STAT 0237 2232 ISZ STATUS 0240 3323 DCA BUF+1 0241 3320 DCA ACTIVE /RESET CHANNEL COMMAND 0242 1311 TAD K7776 0243 4277 JMS XMT /STATUS REQUEST 0244 7000 STREQ 0245 5632 JMP I STATUS /NORMAL EXIT / /DELAY FOR CHANNEL OPERATION 0246 0000 DELAY, O /NORMAL ENTRY 0247 6331 CTL RD /READ INTERFACE STATUS 0250 3321 DCA TMP 0251 1321 TAD TMP /IS INTERFACE BUSY 0252 0310 AND K7000 0253 7640 SZA CLA 0254 5247 JMP DELAY+1 /YES. CONTINUE IN WAIT LOOP 0255 1321 TAD TMP /NO. HAS DEVICE ADDRESS BEEN STORED 0256 0315 AND CMDBIT 0257 7650 SNA CLA 0260 5266 JMP DELl /NO. CONTINUE 0261 6301 AR1 RD /YES. COPY AR1 IN AR2 0262 6326 AR2 CLR+WR 0263 7200 CLA 0264 6311 BR1 RD /STORE CHANNEL COMMAND 0265 3320 DCA ACTIVE 0266 1321 DELl, TAD TMP /RESET INTERFACE 0267 0314 AND RSTBIT 0270 6334 CTL INV 0271 7200 CLA

-165/SYSTEM/360 INTERFACE ECHO TEST ROUTINES PAGE 3 / 0272 1321 TAD TMP /ARE ANY UNUSUAL-END BITS SET 0273 0313 AND BADBIT 0274 7450 SNA 0275 5646 JMP I DELAY /NO. NORMAL EXIT 0276 5221 JMP ERROR /YES. ABORT / /TRANSMIT BYTES ON MULTIPLEX CHANNEL / 0277 0000 XMT, 0 /ENTRY. AC=WC 0300 3002 DCA BLKXFR 0301 1316 TAD PTR 0302 3003 DCA BLKXFR+1 0303 1677 TAD I XMT /ARGUMENT=CTL BITS 0304 2277 ISZ XMT 0305 6334 CTL INV /START OPERATION 0306 7200 CLA 0307 5677 JMP I XMT /NORMAL EXIT / 0310 7000 K7000, 7000 0311 7776 K7776, 7776 0312 0010 ENDCHN,CHNEND 0313 0370 BADB I T CMDRST+CMDSTK+CMDHLT+CMDPCK+SRVPCK 0314 0407 RSTBIT,CMDEND+SRVEND+SRVHLT+CMDCHN 0315 0034 CMDBIT CMDSTK+CMDHLT+CMDEND 0316 0321 PTR, BUF-1 /POINTER FOR DATA BREAK 0317 4000 BUFLNG,-BUFSIZ /BUFFER SIZE 0320 0000 ACTIVE,O /CHANNEL COMMAND TMP, *.+1 /TEMPORARY BUF, *.+BUFSIZ /BUFFER ACTIVE 0320 ARi 6300 AR2 6320 BADBIT 0313 BIREQ 4000 BLKXFR 0002 BOREQ 2000 BRI 6310 BUF 0322 BUFLNG 0317 BUFSIZ 4000 CHNEND 0010 CLR 0002 CMDBIT 0315 CMDCHN 0400 CMDEND 0004 CMDHLT 0010 CMDPCK 0200 CMDRST 0040 CMDSTK 0020 CTL 6330 DELAY 0246 DELl 0266 DEVEND 0004 ENDCHN 0312 ERROR 0221 INV 0004 K7000 0310

-166K7776 0311 PTR 0316 RD 0001 RSTBIT 0314 SRVEND 0001 SRVHLT 0002 SRVPCK 0100 STATUS 0232 STREO 7000 TEST 0200 TMP 0321 TST 0002 TST2 0213 TST3 0216 UNCHCK 0002 WR 0004 XMT 0277

UNCLASSIFIED -167Security Classification DOCUMENT CONTROL DATA - R & D (Security classification of title, body of abstract and indexing annotation must,be entered when the overall report is classified) 1. ORIGINATING ACTIVITY (Corporate author) 2a. REPORT SECURITY CLASSIFICATION Unclassified THE UNIVERSITY OF MICHIGAN 2b. GROUP CONCOMP PROJECT 3. REPORT TITLE SYSTEM/360 INTERFACE ENGINEERING REPORT 4. DESCRIPTIVE NOTES (Type of report and inclusive dates) Memorandum 13 5. AU THOR(S) (First name, middle initial, last name).MILLS, DAVID 6. REPORT DATE 7a. TOTAL NO. OF PAGES 7b. NO. OF REFS |March, 1968 166 none 8a. CONTRACT OR GRANT NO. 9a. ORIGINATOR'S REPORT NUMBER(S) DA-49-083 OSA-3050 Memorandum 13 b. PROJECT NO. c. ci9b. OTHER REPORT NO(S) (Any other numbers that may be assigned this report) d. 10. DISTRIBUTION STATEMENT Qualified requesters may obtain copies of this report from DDC 11. SUPPLEMENTARY NOTES 12. SPONSORING MILITARY ACTIVITY 13. ABSTRACT An interface which connects a small special-purpose digital computer to a large general-purpose digital data processing system is described in this report. The small computer is the Digital Equipment Corporation PDP-8 which itself is a component of a data collection and distribution system called the Data Concentrator. The large data processing system is the IBM System/360 Model 67, which is the principal computing element at The University of Michigan Computing Center. The interface is designed to be attached to the multiplexor channel of the Model 67 along with other input-output components such as card readers, line printers, and communications equipment, and satisfies all IBM standards and interface conventions established for this type of attachment. The interface provides a bidirectional data transfer between the two machines of up to 80 thousand bytes (characters) per second using cycle-steal techniques in which data are transferred directly between the Model 67 multiplexor channel and the PDP-8 core memory without explicit program intervention. DD N0V651473 Unclassified Security Classification

-168Security Classification,14. LINK A LINK LINK C KEY WORDS ROLE WT ROLE WT ROLE WT interface, multiplexor channel, cycle-steal, control unit, PDP-8, System/360, Model 67, data transmission, Security Classification

UNIVERSITY OF MICHIGAN III3 9015 03483 7446 3 9015 03483 7446