TH E U N I V E R S I T Y 0 F M I C H IG A Memorandum 15 A 201A DATA COMMUNICATION ADAPTOR FOR THE PDP-8: PRELIMINARY ENGINEERING DESIGN REPORT David E. Wood CONCOMP: Research in Conversational Use of Computers F. H. Westervelt, Project Director ORA Project 07449,supported by. ADVANCED RESEARCH PROJECTS AGENCY DEPARTMENT OF DEFENSE WASHINGTON, D.C. CONTRACT NO. DA-49-083 ORA-3050 ARPA ORDER NO. 716 administered through: OFFICE OF RESEARCH ADMINISTRATION ANN ARBOR February 1968

TABLE OF CONTENTS INTRODUCTION............................... DESIGN OBJECTIVES.......................... SYSTEM DESCRIPTION......................... PROGRAMMING AND CONTROL CONSIDERATIONS..... A DATA FORMAT SCHEME....................... DETAILED LINE ADAPTOR LOGIC................ Serial-Deserializer Register.......... Clock Gating.......................... SDR Pulse Gating...................... Data Set Signals...................... SDR Serial Input/Output Gating........ Transmit/Receive State Gating......... Control Register 2.................... Frame Counter......................... State Synchronization................. Text State and Sync Detection......... Parity Gating......................... Clear- and Request-to-Send Gating..... Character Service Interrupt Flag...... Status Indicators..................... Control Word 1 EAC Gating............. Miscellaneous Pulses.................. APPENDIX I................................. APPENDIX II................................ APPENDIX III............................................................................... Page 1 2 3 7 14 16...........18...........18...........18...........22...........22...........22...........22...........27...........27...........27...........31...........31...........31...........35,.......... 35...........35.........I-i........ II-i........ III-i i

LIST OF DIAGRAMS Diagram Page 1 SDR Register............................. 19 2 Clock Gating............................. 20 3 SDR Pulse Gating......................... 21 4 Data Set/Interface Cable Assignment...... 23 5 SDR Serial I/O Gating.................... 24 6 Transmit/Receive State Gating............ 25 7 Control Register 2 (Frame Size).......... 26 8 Frame Counter.......................... 28 9 State Synchronization.................... 29 10 Text State and Sync Detection............ 30 11 Parity Gating............................ 32 12 Clear- and Request-to-Send Gating........ 33 13 Character Service Interrupt Flag.......... 34 14 Status Indicators........................ 36 15 Control Word 1 EAC Gating.............. 37 16 Miscellaneous Pulses...................... 38 iii 111~

LIST OF FIGURES Figures Page 1 201A Communication Link................. 4 2 201A Line Adaptor Control............... 5 3 Bit Assignment of Control Words......... 9 4 Graphical Presentation of a Message Exchange Viewed from the PDP-8.......... 17 v

Tables LIST OF TABLES Page Control-Character Definitions........... 14 I vii

A 201A DATA COMMUNICATION ADAPTOR FOR THE PDP-8: PRELIMINARY ENGINEERING DESIGN REPORT David E. Wood INTRODUCTION This report discusses the design and use of equipment built for data communication to and from the PDP-8 through a 201A data set. The purpose of the data communication interface is to allow a PDP-8 to send and receive digital data through a 201A data set in a half-duplex mode. The 201A data set operates serially at a rate of 2000 bits per second, with the transmit clocks supplied by the data set. In the receive mode, the data set achieves bit synchronization, and provides a receive clocking signal to the interface. The interface provides the character synchronization at the start of a message and then transfers successive characters in parallel to the PDP-8. The interface stores and retrieves characters from the PDP-8 memory through the data-break facility, while achieving control communication with the PDP-8 through the interrupt and programmed data transfer modes. This report will serve as a progress report for those interested in technical progress on the project, and as a rudimentary maintenance manual for thoseresponsible for system maintenance in the future. Basic design objectives and decisions will be described first. A brief overall system description together with a sketch of a data format scheme and programming considerations will be followed by a detailed description of the interface logic. -1 -

DESIGN OBJECTIVES In order to obtain a flexible interface the following design objectives were set forth: 1. Rigid interrupt discipline. 2. Minimal program interaction required during message transmission. 3. Variable character length and vertical parity calculation under program control. 4. Maximal interface status and control available upon request. 5. Hardware implementation of character synchronization using the ASCII SYN character. In order to minimize the amount of code in an interrupt processor for the 201A communication interface, the interface was carefully designed to give interrupts only and always when a character was received or transmitted. The desire to give the maximum time between interrupts at the minimal hardware cost led to a decision to use core buffers in the PDP-8 through the use of the data-break facility. This decision was also made in light of the fact that several of these interfaces were to be used on the Data Concentrator. A separate design using a hardware buffer without using the data-break facility is shown in Appendix III. The expected mode of operation of the interface utilizes an 8-bit character without vertical parity. Experimental evidence during the past year has indicated that vertical parity, at least on local hook-ups, is not needed. The decision to use an 8-bit character was strongly influenced by ASCII conventions and the fact that the central computing facility uses an 8-bit byte IBM/360 model 67 computer. The interface depends on the PDP-8 only to the extent that characters must be removed or placed in the core buffers, -2 -

-3 - and the interrupt processed within a character time for errorfree transmission. However, complete control and status presentation is available from the interface if desired, to the extent that the 201A data set will allow. SYSTEM DESCRIPTION The four sections of the equipment for one end of a data communication link are shown in Figure 1: the PDP-8, the PDP-8/201A line adaptor interface, the 201A line adaptor, and the 201A modem. The PDP-8 and the 201A modem will not be discussed here. This report is concerned with the design of the line adaptor and the line adaptor interface. The distinction between the line adaptor and its interface is in some instances arbitrary. In general, however, the term line adaptor refers to that portion which is common to the three variations of the 201A data communications adaptor described in this report. The three variations which will be presented are: the basic PDP-8 adaptor, the PDP-8 adaptor which does not use data break, and the 201A line adaptors on the Data Concentrator. The PDP-8/201A line adaptor interface is hence that portion particular to the 201A communication link being considered. Unless otherwise indicated, the basic PDP-8/201A line adaptor interface will be considered in the main body of the report. Detailed specifications of the 201A interfaces on the Data Concentrator and the 201A interface without data break are given in Appendices II and III respectively. The subsystem designated by "201A Line Adaptor Control" in Figure 1 is specified in more detail in Figure 2. The basic component of the 201A line adaptor is the serial-deserializer register (SDR). This is a serial-in parallel-out or parallel-in serial-out shift register. It accepts and transmits to the 201A data set a serial data stream at 2000 bits/sec.

LEGEND: - — SERIAL DATA LINE,,"> PARALLEL DATA LINES < > CONTROL SIGNALS PDP-8 a —PD-8/201A-LINE-ADAPTOR 7INTERFACE PDP-8/201A LINE ADAPTOR INTERFACE A * * ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~.% r -- - I I I111 SDR REGISTER I I I PARITY - CIRCUIT \ / -1 I I I I I 201A MODEM \ / I I ' I a 201A LINE ADAPTOR CONTROL I I ~~L _ _ _ _ _, 201A LINE ADAPTOR Figure 1. 201A COMMUNICATION LINK

-5 - r - I PDP-8/201A LINE ADAPTOR INTERFACE _ — I I SDR REGIST LCRCUT SDR REGISTER Figure 2. 201A LINE ADAPTOR CONTROL

-6 - On the other hand, it accepts from or transmits to the PDP-8 characters (usually 8 bits in length) in parallel. All clocking, with the exception of the data-break timing, is provided by the 201A data set. The PDP-8 sees the 201A line adaptor (L.A.) as two control or status registers with all interaction being mediated through the manipulation of bits in these 2 registers. A detailed description of these registers as seen by the PDP-8 software is given in the next section. It is sufficient at this point to note that these registers, along with the frame counter, specify to the interface its state and hence the appropriate action to take at any given instant. The frame counter is that counter in the line adaptor which determines when the correct number of bits have been shifted into or out of the SDR register. When the frame counter overflows, the character is data-breaked into core, in the case of a receive operation, or a new character is loaded into the SDR register from core in the case of a transmit operation. At the same time, an interrupt flag is set and the frame counter is reloaded. The L.A. then continues to assemble or dissassemble the next character while the proceeding interrupt is being processed by the PDP-8. This process is repeated over and over again for each character of the message. If, however, the interrupt flag has not been cleared when the next interrupt is generated, a Data Lost flag is set in additio as an error indication to the PDP-8. When vertical parity calculation is enabled in the L.A., the frame size is assumed to include a parity bit as the high-order bit. The parity calculation is based on odd parity, and a parity error will cause only the Parity Error flag to be set, with no other abnormal action initiated by the L.A. The remaining function of the L.A. is to achieve character synchronization. This is accomplished by scanning the received data stream for a given bit pattern designated by SYN (0268).

-7 - When this pattern is found, the interface is placed in what is called the text mode state, and the actions described above then take place. At the discretion of the PDP-8 software, the L.A. can be taken out of the text mode state, with the result that the scanning process will be resumed. The control sequences to transmit and receive data will be described below. The remainder of the L.A. consists of buffers and gates which will be described in detail in the section on logic. The PDP-8/201A line adaptor interface performs the logical and electrical function of mating the PDP-8 and the 201A line adaptor. This entails the control of the databreak operation between the 201A L.A. and the PDP-8, gating necessary for programmed data transfer, and the logic required for the interrupt control between the two devices. The details of these operations are presented in Appendices I, II, and III since they vary among the three systems. PROGRAMMING AND CONTROL CONSIDERATIONS The PDP-8/201A data communication interface in the case of a standard PDP-8 with single-cycle data-break capabilities is controlled by the resident PDP-8 program via three sets of IOT instructions. The device codes for these three sets of IOTs must be consecutive with the first one divisible by 4.* For example, 40, 41, and 42 are not used on most PDP-8 installations and satisfy the requirements. Furthermore, the hardware specifies (at the option of a given installation) two locations in core to be used as receive and transmit buffers. These locations must also be sequential with the convention that: receive 0 (mod2) and transmit _ 1 (mod2). After the 201A L.A. transfers a word between the SDR register and the core buffer, the 201A L.A. will generate an interrupt. The first set of IOTs will service the interrupt * that is, the second octal digit is either a 0 or 4.

-8 - as follows: Identify Transmit Interrupt (6xxl) This micro-instruction causes a skip if an interrupt caused by a 201A transmit operation is pending. Identify Receive Interrupt (6xx2) This micro-instruction causes a skip if an interrupt caused by a 201A receive operation is pending. Clear 201 Interrupts (6xx4) This instruction will cause the 201A transmit and receive interrupt flags and the character service flag in the 201A status word to be cleared. The 201A L.A. has two status or control words associated with it. Control Word 1 is serviced by the second set of IOTs and Control Word 2 by the third. (Figure 3 gives the bit assignment of these control words, and their interpretation is given below.) The IOTs for Control Words 1 and 2 behave identically. Read (6xxl) The contents of the specified control word is ORed into the AC. Skip Under Mask (6xx2) The PDP-8 will skip the next instruction if any position of the AC is a one and the corresponding position in the control word is a zero. Invert Under Mask (6xx4) This instruction inverts (complements) each bit of the control word for which there is a one in the AC.

CONTROL WORD 1: AC POSITION 0 1 2 3 4 5 6 7 8 9 10 11 CONTROL WORD 2: AC POSITION 8 9 10 11 Figure 3. BIT ASSIGNMENT OF CONTROL WORDS

-10 - The first status register, called Control Word 1, is the basic 12-bit control register for the 201A L.A. It contains the necessary status information to control the 201A data set and L.A., and to determine its state. The second status register, Control Word 2, is a four-bit register which contains the modulo 16 complement of the character or frame size, not including vertical parity. When vertical parity is enabled, as noted above, the frame size includes a bit position for parity even though it is only detected and used by the hardware. For example, in normal operation, the character size is 8 bits with vertical parity checking and computation disabled; thus Control Word 2 in this instance would contain 10. The 8 restrictions on the frame size from a hardware point of view are that it be greater than 2*and less than or equal to 121, including parity. The following definitions give the name of each bit in Control Word 1 and its position relative to the AC along with the prescribed effect the software should have on each status bit. The operations available to the software (read, clear, and invert) are indicated in parentheses. INT FLAG-Interrupt Flag (Clear) (ACO) When receiving, indicates that a character has just been placed in the receive buffer. When transmitting, it indicates that a character has just been taken from the transmit buffer and will be transmitted. An interrupt will occur only and always in these cases. DATA LOST-(Clear) (AC1) Indicates that an interrupt has occurred when the INT flag is set. This should indicate, if interrupts are processed correctly, that overrun has occurred and hence a character has been lost (receive) or a duplicate character sent (transmit). *Note: The SYN character is constrained to be 8 bits.

-11 - PAR ERROR-Vertical Parity Error (Clear) (AC2) Indicates a vertical parity error has occurred on the present character received. This indication will occur only if bit AC6 is set (see description below). REQ SEND-Request-to-Send (Read)(AC3) This is a data set control signal which tells the data set to produce a carrier and begin transmitting when the clear-to-send signal comes on. This signal is generated and cleared via transmit request in a manner described below. XMT REQ-Transmit Request (Invert) (AC4) By setting this bit, the request-to-send bit is set if the 201A L.A. is not in the receive state. If the 201A L.A. is actively receiving, the receive operation is terminated at the next end-of-character indication and then the request-tosend signal is given. If the 201A L.A. is actively transmitting and XMT REQ is cleared, the 201A L.A. will go into the receive idle state at the next end-of-character indication, that is, waiting for the carrier to be detected from the other end of the line. CLR SEND-Clear-to-Send (Read) (AC5) Indicates that sufficient time has elapsed since the request-to-send indication was given and the line is now in a transmit ready state. This indication is not the data set clear-to-send signal, but an indication derived from the data set signal which guarantees proper operation of the interface. CHK PAR-Check Vertical Parity (Invert) (AC6) Indicates to the 201A L.A. that in the receive state vertical parity is to be checked, and in the transmit state vertical parity is to be computed and the correct bit appended to the character and transmitted. Vertical parity is always

-12 - computed in the 201A L.A., but no action is taken unless the CHK PAR bit is set. This continual computation allows the 201A L.A. to go from non-parity operations to parity operations within one character time. TEXT-Text Mode (Invert) (AC7) In the receive state, text mode indicates that character synchronization has been found. If the TEXT bit is cleared while in the receive state, this tells the interface to look for new character synchronization. While looking for character synchronization no interrupts will occur. The first interrupt will occur on the first character received following the establishment of character synchronization. When in the transmit state, TEXT should normally not be altered. If the TEXT bit is cleared while transmitting, the interface is frozen until the TEXT bit is set again. This has the effect of transmitting continually the bit being presented to the line at the time the TEXT bit was cleared. During this time no interrupts will occur. The 201A L.A. will always place the TEXT bit in the correct state. It should be changed under program control only if the actions described above are desired. SET RDY-Set Ready (Read) (AC8) Indicates that a call has been answered and that there is a data set in the data mode at the other end of the line. This indication drops when either party hangs up. TERM RDY-Terminal Ready (Invert) (AC9) Indicates to the data set that it should automatically answer a call. RING-Ringing (Read) (AC10) Indicates that the data set is being called. The indication follows the actual bell or ring signal to the hand set.

-13 - CAR DET-Carrier Detect (Read) (AC11) Indicates that carrier is on the line. In most cases of normal operation when CLR SEND is on, it indicates that local carrier is present, and conversely when CLR SEND is off, that carrier is being received from the other end of the line. Throughout the definitions above, reference was made to the transmit and receive states. These states are defined within the 201A L.A. as the logical conjunction of certain signals. That is, the 201A L.A. is in the transmit state if and only if all the following signals are present: a. REQ SEND b. CLR SEND c. SET RDY d. TERM RDY e. CAR DET The 201A L.A. is in the receive state if and only if all the following conditions are true: a. REQ SEND is not present b. CLR SEND is not present c. SET RDY is present d. CAR DET is present The 201A L.A. is in the receive-idle state if and only if all the following conditions are true. a. REQ SEND is not present b. CLR SEND is not present c. SET RDY is present.

A DATA FORMAT SCHEME For the sake of completeness a brief sketch and discussion of a message format scheme is presented. The only portion of this scheme which is affected by the hardware is the actual SYN character. This particular scheme is presented for exposition purposes only and is not intended to represent the existing 201 software support. An inbound message has the following format: <Sync Characters><Text Characters><Terminating Character><Two Block Check Characters>. These characters are defined as follows: TABLE I CONTROL-CHARACTER DEFINITIONS ASCII NAME OCTAL HEX FUNCTION ETX 003 03 End of Text EOT 004 04 End of Transmission ENQ 005 05 Enquiry ACK 006 06 Positive Acknowledgment NAK 025 15 Negative Acknowledgment SYN 026 16 Synchronous Idle ETB 027 17 End of Text Block EOM 031 19 End of Message PAD 377 FF Pad for Line Turnaround A Sync Character is the ASCII SYN character. A minimum of four sync characters will be required to guarantee proper character synchronization by the software. In the case of long distance operation where there is echo suppression on the telephone line a sufficient number of PAD characters must precede the SYN characters to allow the line to settle down. -14 -

-15 - A Text Character may be any combination of eight bits which is not identical to a terminating character. The positive acknowledgment character, ACK, and the negative acknowledgment character, NAK, are considered message characters for transmission purposes. Likewise SYN is a message character which when received is deleted from the message. The message may be the empty string, that is, no text characters. A Terminating Character is any member of the following set of characters: {ETX,ETB,EOT,EOM,ENQ}. Each of these terminating characters will have the effect of terminating the present message along with other logical implications to the software. The Block Check Characters are longitudinal parity check characters treated as a code word in a cyclic code whose generating polynomial is 16 15 X2 X +X +X +1. Two block check characters must accompany every message. This format is used in a store and forward mode; that is, the PDP-8 receiving a message across a 201A data communication link will store the incoming message. Concurrently it will forward that message at a rate that the interrupt processing will bear, calculating the cyclic checksum as it proceeds. In general, when the terminating character is finally encountered in this forwarding operation, the two checksums (the one actually received and the one computed)are compared. If the two match, a positive acknowledgment ACK is returned to the sender. If a discrepancy exists, an NAK or negative acknowledgment is returned. The software determines what to do in these cases, and this problem will not be discussed here.

-16 - An outbound message has the same format as an inbound message with the addition of at least one PAD character appended to the end of the message to allow for proper "flushing" of the communication link. The PAD characters are always ignored in this context. A graphical presentation of a message exchange as viewed from the PDP-8 is shown in Figure 4. For exposition purposes the handshake message has the form: (SYN1)(SYN2)(TEXT CHAR)(ETX)(BCC1)(BCC2)(PAD1)(PAD2) with the acknowledgment taking the form (SYNl) (SYN2) (ACK) (ETX) (BCCl) (BCC2) (PAD1)(PAD2) In Figure 4, the control status is affected either by the program (P.S.-Program Set, P.C.-Program Clear) or by the data set or interface (D.S.-Modem Set, D.C.-Modem Clear). DETAILED LINE ADAPTOR LOGIC This section will present in detail the logical design of the 201A line adaptor. The logic diagrams follow standard Digital Equipment Corporation conventions. A working knowledge of D.E.C.'s R and W series logic is assumed throughout this section. The remainder of the logic for the 201A Interface is given in Appendices I, II, and III for each particular version of the interface. For completeness, both the module position and pin assignment for each circuit is indicated. All circuits within this section are in the same D.E.C. 1943 wire-wrap panel. The detailed module utilization is presented with the particular interface in the Appendices. In order to allow for multiple adaptors, as used on the Data Concentrator, the common signal names are prefixed with a # sign. In a single adaptor configuration the # sign is just part of the signal name. The logic will be presented as much as possible within the framework of Figure 2.

INTERFACE STATES CONTROL STATUS RECEIVE ACTIVE RECEIVE IDLE TRANSMIT I TURN I AROUND c E- - C, l - Z X X U U < H w co co m z Z V) -i Cxl cN X U U a 0 U E- U u < <t~ L C o CQ n. INT FLAG DATA LOST PAR ERROR REQ SEND XMT REQ CLR SEND CHK PAR TEXT SET RDY TRM RDY RING CAR DET 0 1 2 3 4 5 6 7 8 9 10 11 D.S. i D.C. i P.S.. P. C. D.S. iD.C. D.C. D.S. D.S.. S IP.S.,D.S. D.C. I. AA D.S. D.S. A H D.C. D.C. I -.1 LINE CONTENTS SYN1 SYN2 TEXT ETX BCC1 BCC2 PAD1 PAD2 SYN1 SYN2 ACK ETX BCC1 BCC2 PAD1 PAD2 LINE STATE I ANSWER HANDSHAKE - MSG I II ACKNOWLEDGMENT I Figur& 4. Graphical Presentation of a Message Exchange Viewed from the PDP-8.

-18 - Serial-Deserializer Register (Diagram 1) This is a 12-bit register with high-order position #SROO and low-order bit #SRll. Serial data are shifted into #SROO in the receive state from the data set on the clock signal #SHIFT. They are shifted out of #SRll in the transmit state into a line buffer #SDBF. Characters are strobed into the SDR register in a data-break operation from the buffered memory buffer on the #MBSR signal. This character transfer is simulated in the case of an interface not using data break, and those details are treated in Appendix III. The operation of character transfer to the PDP-8 is treated in the Appendices. Clock Gating (Diagram 2) The 201A data set provides two clock signals, #SCRB (receive clock) and #SCTB (transmit clock). The #SCTB clock is always available and is used within the data set for internal control timing. The #SCRB clock is derived from the received data stream and is provided to sample the received data line (#RDB). The interface selects the correct clock on the basis of its state (transmit/receive) SDR Pulse Gating (Diagram 3) The control of the SDR register is primarily achieved through the four pulse amplifiers (Diagram 3). To keep all transitions occurring synchronously with the #CLOCK signal it is necessary to separate the clearing of #SROO from the remainder of the register. By the use of the #FR3+ signal, the register is cleared at the eyid of a transmitted character before the next character is loaded. It is cleared at the end of a data-break operation in the receive state via #BRKDN; and all bit #SROO is cleared when character synchronization is found in the receive state. In this last case, while the remainder of the register is cleared the first bit is read in from the line. #MBSR loads ones into the register during a data break in the transmit state.

BH V" S ~ BT BMBO09 BMB10 BMB11 BMB06 BMB07 BMB08 Diagram 1. SDR REGISTER

F #SRCK B1 YR #XMT Diagram 2. CLOCK GATING

-21 - #START #DTSY #EXMT #CLOCK SFT B14 Diagram 3. SDR PULSE GATING

-22 - Data Set Signals (Diagram 4) Diagram 4 shows the correspondence between the 201 data set connector and signal designations of the 201A L.A. SDR Serial Input/Output Gating (Diagram 5) The serial input signal #RDB from the 201A data set is converted to standard D.E.C. levels (-3v, Ov) from E.I.A. standard levels (+6v, -6v) (Electronic Industries Association Standard R S 232: Interconnection of Data Terminal Equipment with a Communications Channel). When not in the receive state, the input to the SDR register is conditioned (#RD+) to shift a zero into the SDR register. The #LINE flip-flop determines whether the output from the SDR register buffered via #SDBF or a parity bit (#PTBF) is placed on the transmit data line (#SDB). When the L.A. is in the receive state, zeros are always placed on the #SDB line to minimize possible cross-talk. Transmit/Receive State Gating (Diagram 6) The XMT/REC status of the interface is specified by the two flip-flops #XMT and #REC. The definition of these states has been defined above, however, it is important to note that the state changes are synchronized to the clock. The #RSYN latch is used to prevent the loss of the last receive interrupt. Control Register 2 (Diagram 7) The second control word as defined above contains the modulo 16 complement of the current character length. This value is referred to throughout the interface as the frame size and is stored in the register #CFRO-#CFR3. The register is loaded via IOT commands described above from the PDP-8 AC, and read into the PDP-8 on an extension to the AC called the EAC. The details of the EAC buss are described in Appendix I.

-23 - DIAGRAM 4 DATA SET/INTERFACE CABLE ASSIGNMENT Interface Signal Name Data Set Connector (CINCH DB-25-P PLUG) Interface Connector (W021MJ*) Signal Name #SDB #RDB #RSB #CSDB #SRDB #TRDYB #RINGB #CDETB #SCTEB #SCTB #SCRB 1 7 2 3 4 5 6 20 22 8 24 15 17 AA AB BA BB CA CB CC CD CE CF DA DB DD Protective Ground Signal Ground Transmit Data Receive Data Request to Send Clear to Send Set to Ready Terminal Ready Ring Carrier Detect Terminal Transmit Clock Set Transmit Clock Set Receive Clock C C D E F H J K L M N P R * Special module with for shielding. all pins available and ground connections

#OUT1 F #FR3+ A03 E E I II I uI I B I B19 I Diagram 5. SDR SERIAL I/O GATING

S #PWCLR #PWCLR #SRSV N A08 A08 J B20 B21 2 #CDETB B02 L Diagram 6. TRANSMIT/RECEIVE STATE GATING

#ENAX+ #ENAX+ EAC10 EAC9 #ENAX+. E -— 0 EAC08 A30 N D N K [N) I bO BAC09 BAC08 #ENAX Diagram 7. CONTROL REGISTER 2 (FRAME SIZE)

-27 - Frame Counter (Diagram 8) The frame counter determines by its overflow when a character has been received or transmitted, thus making the positive transition of #FR3+ the character received/transmitted signal. It is reloaded from Control Register 2, each character time making use of the fact that the register is zero at this time. It is thus necessary only to clear the register at the beginning of an operation via the #SVC signal. The frame counter is normally incremented when in the text state and not in a transition state (#SVC+). The #IOPCS signal forces the counter to wait one bit time on character synchronization when parity checking is enabled to take account of the parity bit on the SYN character. State Synchronization (Diagram 9) The #SVC state and #SVC-positive transition are used throughout the interface to clear it on a XMT/REC state change or a change in the text state. The remainder of the logic is necessary for its synchronization to the clock signal. Text State and Sync Detection (Diagram 10) The text state is embodied in the flip-flop #IFMD. The flip-flop is one bit of Control Word 1 and is therefore accessed through the AC under program control. Two of its other input gates place #IFMD in the correct state when the XMT/REC state is entered. The remaining gate sets #IFMD in the text state when character synchronization is found in the REC state. This transition is conditioned by #DTSY+ and strobed on the clock signal. #DTSY+ is the logical-and gate used to determine whether the first 8 bits of the SDR register contain the SYN character.

E R H S #PWCLR 00! B14 #MBSR L #XTRQ+ 1B14 Diagram 8. FRAME COUNTER

-29 - #CLOCK p R #XMT+ + I#RSTRT #IFMD p S R T #XMT- #REC Diagram 9. STATE SYNCHRONIZATION

-30 - u 0 U::t$k II z 0 E-) EL;I UO z H EU) EP-i L) u 0^- \P r —4 + u w 04 #(t_

-31 - Parity Gating (Diagram 11) The check-vertical-parity-status flip-flop is designated #EBPC in the interface. It is manipulated in the same manner as described above for other bits in Control Word 1. The parity error flip-flop is #PAR and normally is set to zero when #EBPC is not set. When parity checking is enabled, the accumulated parity in #PATY is compared against the last bit of the character when receiving, and #PAR is set if they are not the same. Clear- and Request-to-Send Gating (Diagram 12) The contents of the transmit request flip-flop (#XTRQ) is jammed into the request-to-send flip-flop (#RQSD) at the end of each data-break cycle requested by the interface. Since the cleared status of #RQSD is-r(request-to-transmit) a gate is provided to set #RQSD immediately upon the transition of #XTRQ if the interface is in neither the XMT or REC state. This method of control of request-to-send guarantees that the processing of the current character will be concluded before the XMT/REC state is changed. Furthermore, if #RQSD is set, at least one character must be transmitted before a receive operation can occur. The clear-to-send indication, #CLSD, is derived from the data set signal #CSDB. In order to avoid a spurious receive state, clear-to-send must be delayed from dropping after request-to-send drops. This delay is necessary because the data set brings up carrier after first dropping it when clear-to-send drops. It appears that this is the result of the data set "flushing" itself after a transmit operation. Character Service Interrupt Flag (Diagram 13) The interace's character interrupt flag is #SRSV. This flag is set in the text state on each received character, and in the text state on each character transmitted if there

J J F #INVMKDI + BAC06 JR P #PATY A16 ASSHI FT, #PWCLR BACO 2 #RD+ U4 toai IB23 K Diagram 11. PARITY GATING

E E J H W #CS+ 12 1.8pf #CSDB A02 M E F Diagram 12. CLEAR- AND REQUEST-TO-SEND GATING

#PWCLR #CHRDN #XMT+ l I V p B15 p #REC Diagram 13. CHARACTER SERVICE INTERRUPT FLAG

-35 - is still a transmit request pending. Every time the frame counter overflows, an #ENDI pulse is generated. This pulse is normally the character service request except when a change in text mode generates a false overflow, thus the need for #BRENB. Status Indicators (Diagram 14) Diagram 14 shows the remaining status bits of Control Word 1. Terminal ready (#TMRD) and data lost (#DLST) can be manipulated under program control as described above. Set ready (#STRDY) and (#RING) are only gates since they present static status of the data set. Control Word 1 EAC Gating (Diagram 15) Diagram 15 shows the gating necessary to load Control Word 1 on the extended AC buss (EAC). Miscellaneous Pulses (Diagram 16) To prevent undue loading of the PDP-8 power clear signal and to allow for reshaping the pulse, #PWCLR is derived. #INVMK is the pulse used to invert under mask the bits in Control Word 1.

LEVEL CONV. #TRDYB N L BlB01 P p #PWCLR #TMRD D- A2 3 F + #PWCLR -1 I I #INVMK BACTY N T S BACO 1 #SRSV- (J1! #STRDY #RINGB A02 2 S E Diagram 14. STATUS INDICATORS

-37 - Diagram 15. CONTROL WORD 1 EAC GATING

BPCLR P.A. K L B09 D M #PWCLR -> Diagram 16. MISCELLANEOUS PULSES

APPENDIX I PDP-8/201A LINE ADAPTOR INTERFACE FOR USE WITH A PDP-8 WITH THE DATA-BREAK FACILITY I-i

APPENDIX I TABLE OF CONTENTS Page Data Break Control................................ I-1 Data Break Address................................ 1-3 Device Select Code................................ -3 Device Selection Gating........................... -7 Interrupt Control................................. I-7 Extended Accumulator Control..................... 1-10 Accumulator Input Gating.......................... I-10 Extended Accumulator Buffers................... 1-10 Data Bit Buffers................................. 1-10 Miscellaneous Circuits............................ 1-10 Cable Layout.................................. 1-16 Module Utilization............................... 1-16 I-iii

APPENDIX I LIST OF TABLES Tables Page I-1 Buffered Accumulator Outputs........... I-18 1-2 Buffered Memory Buffer Output Lines.... I-19 1-3 Accumulator Inputs................... I-20 1-4 Programmed Input/Output Control........ -21 1-5 Data-Break Address Lines.............. I-22 1-6 Data-Break Input Lines................. I-23 1-7 Data-Break Control Signals............. -24 1-8 Panel 1 - Common Section............... I-25 1-9 Panel 1 - Common Section............... I-26 1-10 Panel 2 - Port 0/Line Adaptor 1........ I-27 1-11 Panel 2 - Port O/Line Adaptor 1........ I-28 I-v

APPENDIX I LIST OF DIAGRAMS Diagram Page I-1 Data Break Control.................... I-2 1-2 Data Break Address Lines.............. I-4 1-3 Device Decoding........................ -6 1-4 Device Selection Gating................ I-8 1-5 Interrupt Control..................... I-9 1-6 Extended Accumulator Control........... I-11 1-7 Accumulator Input Gating............... I-12 1-8 Extended Accumulator Buffers........... I-13 1-9 Data Bit Buffers.................... I-14 1-10 Miscellaneous Circuits............... I1-15 1-11 Cable Layout.......................... I-17 I -vii

APPENDIX I LIST OF FIGURES W021MG Address Card..................... Figure Page I-1 1-5 I-ix

PDP-8/201A LINE ADAPTOR INTERFACE FOR USE WITH A PDP-8 WITH THE DATA-BREAK FACILITY The remainder of the logic and details of the 201A data communication adaptor using the data-break facility is presented in this Appendix. With reference to Figure 1, the body of the logic to be discussed here is considered to make up the PDP-8/201A line adaptor interface. The total 201A data communications adaptor is realized in two DEC 1943 wire-wrap panels. For the purpose of this report, each panel is called a bay. In this version of the adaptor, for the most part, the PDP-8/201A line adaptor interface is in Bay 1 with the 201A line adaptor in Bay 2. Throughout the remainder of this Appendix, unless noted otherwise, the logic discussed is in Bay 1. Data Break Control (Diagram I-1) The line adaptor signals the PDP-8 through the #BKRQ flip-flop that a data transfer is desired to or from PDP-8 core. The address within the PDP-8 memory is read by the PDP-8 from the data address lines. The low-order bit of this address is given by DIAD11. When the break request is given, the direction of the transfer is specified by the DICTL signal. When the PDP-8 enters the break state and the address is loaded into the memory address register, an address accepted pulse is generated by the PDP-8. At this time, the break request signal must be dropped by the interface. During the break state, as defined by the BBREAK signal, the BT1 pulse indicates the end of the break cycle, and is used to strobe the contents of the designated memory location from the buffered memory buffer register into the SDR register. The PDP-8 will also strobe the data-break input lines (DATA BIT) into memory at this time in case the transfer direction is into core. The break request signal is generated each time the frame counter overflows while I-1

# RR I n T BKSL# M "B3 BBREAK N BTIC P, V Li 1. #PWCLR #I #XMT nTAn11 3 K #RQSD+A3 BKSL# DICTL #RQSD+A3 s -. 3 -— o Diagram I-1. DATA-BREAK CONTROL

I-3 in the text state, and when the interface first enters the transmit state to fetch the first character to be transmitted. All of the logic shown in this diagram is in Bay 2 of the interface. Data Break Address (Diagram 1-2) The 201 line adaptor has assigned two sequential locations in PDP-8 core to be used as buffers for incoming (received) and outgoing (transmitted) data. These two locations are specified in the hardware on a W021MG address card. The address is a 14-bit address to allow the buffers to be in any core bank. The 15th or low-order bit is not required because a pair of locations is being specified. By convention, the even location of the pair is the receive buffer and the odd location is the transmit buffer. Using the DEC numbering convention, the address is given by the vector ADDR(O)...ADDR(14). Schematically, the W021MG module is shown in Figure I-1. These address lines are then buffered as shown in Diagram 1-2 and form the inputs for the data break address (DADR); the low-order bit (DIADll) is generated by the requestto-send signal and is shown in Diagram I-1. The j-th position (j=0,...,13) of the address is a 0 if there is a jumper to ground at that position and is a 1 otherwise. The W021MG address card is located in module position 1B09. If any of the three high-order positions (ADDR(O), ADDR(1), or ADDR(2)) is a 1, there must be extended memory capabilities on the PDP-8, and the eleventh or address extension cable must be provided. Device Select Code (Diagram 1-3) The device select code is a two octal digit number which selects an external device during an input/output operation. The device code appears in positions 3 through 8 of the memory buffer (M.B.) during an IOT instruction, alerting the external device that it is being selected.

ADREX3 ADDROO DADR05 -1F ADDR08 I- ~ B 10 H I ADDR09 DADR07 1L ADDR10 B. a, IB10 A10 B10 U DIAD11 U B18T Diagram 1-2. DATA-BREAK ADDRESS LINES

I-5 B09 D ADDR(O) E. ADDR(1) F ADDR(2) -0 0 --- * H ADDR(3) J ADDR(4) 0K ' ADDR(5) ---- ' L ADDR(6) M ADDR(7) N ADDR(8 P ADDR(9) R A ADDR(10) S ADDR(11) --— O T A ADDR(12) U ADDR(13) o -- Figure I-1. W021MG Address Card.

B12 II MB3 IA14 I A13 I B1 1 S U Diagram 1-3. DEVICE DECODING

1-7 The 201A L.A. has associated with it three separate device codes as discussed above. In order to specify the three devices it is sufficient, because of the aforementioned requirements, to define only a four-bit number, which appears in positions 3-6 of the M.B. during an IOT instruction. This number must also be realized in the hardware, and this is accomplished via an R002 diode module found in position 1A13 and pictured at the far left of Diagram 1-3. Thus to specify the desired set of device codes the appropriate diodes are removed. For example, using the set 40, 41, 42 as before, the diodes connected to pins E, H, L, and P must be removed. The remainder of Diagram I-3 shows the gating necessary to obtain the signals to identify each of the devices. Device Selection Gating(Diagram 1-4) The gates shown in Diagram 1-4 are located in Bay 2 and provide the signals to differentiate between Control Word 1 and Control Word 2 operation. Interrupt Control (Diagram 1-5) Every time a character is transferred between the 201A L.A. and the PDP-8's memory, a character service flag (#SRSV) is set as described above. This flag in turn sets the appropriate interrupt flag, Transmit (XINT) or Receive (RINT), which causes an interrupt request. If interrupts are enabled in the PDP-8, a program interrupt is generated. Via the appropriate IOT micro-instruction, the program can identify the device causing the interrupt. The SKIP signal will be generated, and a program skip forced if this IOT is executed. It is the program's responsibility to clear the interrupt after it is identified, and the remainder of the gates allow for this.

#FNAX+ CTWD2 J - _. I B24 #ENAX- B 13 NB 2 5,P e _M ^a_,,'#BLOCKKA I BKSLB -N I n #NLB13 I [ - I o00 #ENBL+ #ENBL1J M [>H-. B25 I'~ - I F I I CTWD1 I Diagram 1-4. DEVICE SELECTION GATING

INTREQ T ~IOP4~IOP BPCLR A_2 K - #SRSVDEVSL0 IOP4_. IoP4C A12 CRWDO # IOP4C + D lAll rB12K IB12 | iagram I-5. INTERRUPT CONTROL Di agram 1-5 -

1-10 Extended Accumulator Control (Diagram 1-6) In order to provide the IOT structure described in the Programming and Control Considerations section, the Extended Accumulator (EAC) buss was implemented. The full power of the EAC is not realized until multiple devices are using the buss, since it provides the mechanism for multiple inputs to the PDP-8 AC. Diagram 1-6 shows the gating necessary to generate the SKIP signal when a skip under mask IOT is executed. Accumulator Input Gating (Diagram 1-7) Diagram 1-7 shows the buffers which gate the EAC buss onto the AC buss. For other devices to use the EAC buss they need only provide the appropriate input to the ENBL gate and the gates for the EAC buss. Extended Accumulator Buffers (Diagram 1-8) Diagram 1-8 shows a set of buffers necessary to accomplish the inversion to gate the EAC onto the AC. The clamped loads for the EAC buss are also indicated. Data Bit Buffers (Diagram 1-9) Diagram 1-9 shows the buffers used to provide isolation between the SDR register outputs and the data inputs on a data break into the PDP-8. There is no gating signal provided on these buffers since this is the only device using the data bit lines. Miscellaneous Circuits (Diagram 1-10) Diagram 1-10 is best described as the left-over circuits without a logical home.

Diagram 1-6. EXTENDED ACCUMULATOR CONTROL

ACOO EAC06 - 0 - I!s B17 A17 1A12 Diagram 1-7. ACCUMULATOR INPUT GATING

I I B18 I B18 Diagram 1-8. EXTENDED ACCUMULATOR BUFFERS

DABTOO DABT08 #SRO8+ K #SR09+ L B20 DABT09 I vB20 H-0 I r4p~ DABT10 Diagram 1-9. DATA BIT BUFFERS

BKSL# A 1 BPCLR BPCLRC HAFA12 A I DICTL B18U I (J1 BT1 N IP BT1C _K —N B19 Diagram 1-10. MISCELLANEOUS CIRCUITS

1-16 Cable Layout (Diagram I-11) The input/output cables for the 201A L.A. are shown in Diagram 1-11. The correspondences between the signal names, module positions, and pin connections for the 201A L.A. and the PDP-8 are given in Tables I-1 through 1-7. Module Utilization (Tables 1-8 through I-11) Tables 1-8 through 1-11 give the module utilization for a 201A L.A. In addition to the module utilization, a complete signal name map is also shown.

0 1 0 2 0 3 04 05 0 6 0 7 0 8 0 9 D BACOO BMBOO ACOO DADROO DABTOO ADREX1 E BAC01 BMB01 ACO1 DADR01 DABT01 ADREX2 F H BAC02 BMB02 AC02 DADR02 DABT02 ADREX3 J K BAC03 BMB03- AC03 DADR03 DABT03 L M BAC04 BMB03 AC04 DADR04 DABT04 N P BAC05 BMB04- AC05 DADR05 DABT05 R S BAC06 BMB04 AC06 DADR06 DABT06 T BAC07 BMB05- AC07 DADR07 DABT07 U V BAC08 BMB05 AC08 DADR08 DABT08 'A1 'B' D BAC09 BMB06- AC09 DADR09 DABT09 E BAC10 BMB06 AC10 DADR10 DABT10 F H BAC11 BMB07- AC11 DIAD11 DABT11 J K IOP1 BMB07 SKIP BKRQ# L M IOP2 BMB08- INTREQ DICTL N P IOP4C BMB08 BBREAK R S BT1C BMB09 ADDACC T BT2A BMB10 BPCLRC BMB V BPCLRC BMB11 Diagram I-11. CABLE LAYOUT

1-18 TABLE I-1 BUFFERED ACCUMULATOR OUTPUTS 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A01D, A02D BACOO -------— <- BACO ME34D A01E, A02E BAC 01 --- — BAC1 ME34E AO1H, A02H BAC02 ---- --— BAC2 ME34H AO1K, A02K BAC03 -- --— BAC3 ME34K A01M, A02M BAC04 -- ---- BAC4 ME34M AO1P, A02P BAC05 ---- BAC5 ME34P A01S, A02S BAC06 -------- BAC6 ME34S A01T, A02T BAC07 -- --- — BAC7 ME34T AO1V, A02V BAC08 - --— BAC8 ME34V BO1D, B02D BAC09 ---- — BAC9 MF34D BO1E, B02E BAC10 ---- ---— BAC10 MF34E BO1H, B02H BACll --- ----- BACll MF34H

1-19 TABLE 1-2 BUFFERED MEMORY BUFFER OUTPUT LINES 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A03D, A03E, A03H, A03K, A03M, A03P, A03S, A03T, A03V, B03D, B03E, B03H, B03K, B03M, B03P, B03S, B03T, B03V, A04D A04E A04H A04K A04M A04P A04S A04T A04V B04D B04E B04H B04K B04M B04P B04S B04T B04V BMB00 BMB01 BMB02 BMB03 -BMB03 BMB04 -BMB04 BMB05 -BMB05 BMB06 -BMB06 BMB07 -BMB07 BMB08 -BMB08 BMB09 BMB10 BMB11, <o -— o -_____<> - O < ----— 0 —~ — C> ---— o — o — O.-- o. -— o ---- ---- BMBO(1) BMB1 (1) BMB2(1) BMB3(0) BMB3(1) BMB4(0) BMB4(1) BMB5(0) BMB5(1) BMB6(0) BMB6(1) BMB7(0) BMB7(1) BMB8(0) BMB8(1) BMB9(1) BMBl0(1) BMBll(1) ME35D ME35E ME35H ME35K ME35M ME35P ME35S ME35T ME35V MF35D MF35E MF35H MF35K MF35M MF35P MF35S MF35T MF35V

1-20 TABLE 1-3 ACCUMULATOR INPUTS 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A05D, A06D ACOO * ACO PE2D A05E, A06E ACO1 * * AC1 PE2E A05H, A06H AC02 * AC2 PE2H A05K, A06K AC03 ** AC3 PE2K A05M, A06M AC04 AC4 PE2M A05P, A06P AC05 | _*__. AC5 PE2P A05S, A06S AC06 * AC6 PE2S A05T, A06T AC07 * | * AC7 PE2T A05V, A06V AC08 * AC8 PE2V --— \> —0 --- B05D, B06D AC09 * AC9 PF2D B05E, B06E ACO 10 AC10 PF2E --— 0 ---- B05H, B06H AC11 ACll PF2H *Note: Collector of Grounded-Emitter Transistor

1-21 TABLE I-4 PROGRAMMED INPUT/OUTPUT CONTROL 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION B05M, B06M INTREQ INTERRUPT PF2M REQUEST B05K, B06K SKIP SKIP PF2K BO1K, B02K IOP1 IOP1 MF34K BO1M, B02M IOP2 P2 MF34M BO1P, B02P IOP4C i IOP4 MF34P *Note: Collector of Grounded-Emitter Transistor

TABLE I-5 DATA-BREAK ADDRESS LINES 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A09H ADREX3 ---—, > <> ADDR EXT 3 ME30H A09E ADREX2 --—; ----- ADDR EXT 2 ME30E A09D ADREX1 ---- -— ADDR EXT 1 ME30D A07D DADROO -z 7 < ' DATA ADDR 0(1) PE3D A07E DADR01 -- < ---- -DATA ADDR 1(1) PE3E A07H DADR02 - -------- DATA ADDR 2(1) PE3H A07K DADR03 | - --- DATA ADDR 3(1) PE3K A07M DADR04 ------ - -> DATA ADDR 4(1) PE3M A07P DADR05 ---- ^, -| | DATA ADDR 5(1) PE3P A07S DADR06 -; -.- DATA ADDR 6(1) PE3S A07T DADR07 ------ - DATA ADDR 7(1) PE3T A07V DADR08 --. - - -, DATA ADDR 8(1) PE3V B07D DADRO9 ---- --- DATA ADDR 9(1) PF3D B07E DADR10 ---- --- '- DATA ADDR 10(1) PF3E B07H DADR1 1.. ---- | DATA ADDR 11(1) PF3H

TABLE I-6 DATA-BREAK INPUT LINES 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A08D DABTOO ---— DATA-BIT 0 PE4D A08E DABT01 ----- DATA-BIT 1 PE4E A08H DABT02 ----- < - DATA-BIT 2 PE4H A08K DABT03 ------- DATA-BIT 3 PE4K A08M DABT04 -----. DATA-BIT 4 PE4M A08P DABT05 --— DATA-BIT 5 PE4P A08S DABT06 -— DATA-BIT 6 PE4S A08T DABT07 --- DATA-BIT 7 PE4T A08V DABT08 - \. DATA-BIT 8 PE4V B08D DABT09 ---- -— DATA-BIT 9 PF4D B08E DABT10 ------ > DATA-BIT 10 PF4E B08H DABT1l ---- -- DATA-BIT 11 PF4H

1-24 TABLE I-7 DATA-BREAK CONTROL SIGNALS 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION BREAK B07K BKRQ# --- -— RQUEST PF3K TRANSFER B07M DICTL --— R --— ON PF3M DIRECTION B07P BBREAK - ---- B BREAK PF3P B07S ADDACC - ---. ADDRE PF3S ACCEPTED BO1S, B02S BT1C - -- BT1 MF34S BO1T, B02T BR2A - ----- BT2A MF34T B01V, B02V BPCLRC -B POWER MF34V CLEAR *Note: Collector of a Grounded-Emitter Transistor.

PANEL 1 COMMCN SECTICN AOI A02 2 A03 A I4 AC5 At'6?1 2 21 W021 w21l lC21 i021 607 AH AI Al A A412 A13 A14 A15 Al6 kr21 C21 WC21 Rl7 Rill R1C7 R002 R107 R141 R107 A B C ) eAC'o KACr BMBI C B B rn ACCC E HAC31 BACO I BMBdl HBmB1 ACCI F H AC"2 B ACC2 BMB2 BNBC2 ACC2 J K BAC~3 AACI3 BMRB3- RMBC3- ACC3 L M EACr4 BACr4 BMB03 8B 03 ACC4 N P ACAC 5 bACC5 BMBr4- BBr'4- ACC5 S RtAC'O BACC B'B M84 BB304 ACC6 T 3[ACC7 HAgr7 BMB05- BM1C5- ACC7 U V BACi8 H ACc bMBCs bMCs5 A CC6 AC1l AC 2 AC04 AC T8 DACRnr CABTO' DADRC1 CABTI I)ADRC2 FAETO DADRrC3 CAFTC CADRC4 CARTC CACRC5 CABT CACPRr CAHBT DADRr7 CABTf DACRCB CABT" A B GNDA12 GNDA15 C 0 ADREX1 ADREX3 XINT+ BKSL# RB-BC3- BACOO- TSTSKP EACOO- 0 1 ADREX2 ADORnO GNDA12 BMB03 BACOO BACOO- EACOO E ADREX2 BPCLR SELNC BAC01- LACOO EACOI- F 2 ADREX3 ADDRC1 INTREQ BPCLRC BMBC4- BAC01 BAC01- EAC01 H ADREX1 IOP4 BMB04 BAC02- EACO1 EAC02- J 3 ADDPC2 RINT+ IOP4C SELNC BAC02 BAC02- EAC02 K IDADRrO LDAC- BMB')5- BAC03- EAC02 EAC03- L 4 ADDKC3 LOAC+ E0PC5 BAC03 BAC03- EAC03 M DAJR01 INTREQ CTWDO SELND BAC04- EAC03 EAC04- N 5 ADDR04 DEVSLO BeCb6- BAC04 BAC04- EAC04 P DADOR2 IOPL CTWD1 BMB06 BAC05- EAC04 EAC05- R 6 __ADDRC ENbL DEVSLI SELNO BAC05 BAC05- EAC05 S 7 DADRe3 CTWD2 SELDV EAC05 GRPSEL T ADDRn6 LOAC+ DEVSL2 GNDA15 SELDV U 8 LOAC+ SELND GNDA15 V.....3.1 h'-2.B (3.. '4.. "W21 2 321 W l q3'l - C21 BCe7 pre BS Hln 81 B12 813 B14 B15 B16 WC21,C.1 W?21G Rl'7 R111 R1I1 R107 R141 Rill R77 A B C 0 'ACU JAC.9 MB- B- HC6- ACC9C 3 BAC1 i5AC1C B LMBr 6 MB 5C6 AC 1O H 3 AC 11 BAC 1I BMD7- B M3 B7 - AC11 J K 1CFi I OP1 P ' i MBW.B '.8^ 7 SKIP L M IGP2 IOP2 BMBn, - BMBCB- IITREC( N P IGP4C IOP4C BMB3 E BMBC8 S H:[C T 3 T 1C — B M (1 B W - I p,09 T BT2A 3T2A BA B1 BMB1I U V.PCLt'C BPCLR C tMB11 BMB11 A B GNOB15 C ACe9 DADPC9 CABTC9 ADDRrC DADR04 B1B07 TSTSKP ICP2 8AC06- TSTSKP EAC06- D ACIC DADRln CABTl" ADDR)1 ADDR07 BMB08 SKIP1 ENBL BAC06 BAC06- EAC06 E AO___2 DAORC5 DEVNDO CTWDO SKIP1 BAC07- EAC06 EAC07- F ACll DIAD11 CABT11 ADDR03 ADDR08 DEVSLO SKIP2 SKIP BAC07 BAC07- EAC07 H ADDOR4 DADR06 DEVSLO CTWDO BAC08- EAC07 EAC08- J SKIP BKRC - ADDRc5 ADDRC9 BMB07 SKIP3 XINT+ BAC08 BAC08- EACO8 K ADDR06 DADR07 BMB08- GRPSEL ICP1 BACOS- EAC08 EAC09- L INTREQ DICTL ADDR07 ADDR1O DEVNO1 CEVNDO SKIP2 BAC09 BAC09- EACC9 M ADOR08 DADRO8 DEVSL1 GRPSEL SKIP BAC10- EAC09 EACIO- N BBREAK ACCRO9 ADDR11 CEVSL1 CEVN01 BAC10 BAC1O- EAC10 P ADDR1t DADR09 BMB07- GRPSEL RINT+ BACll- EAC10 EAC11- R ACCACC. ADDR11 ADDR12 BMBC8 DEVND2 ICP2 BACll -BAC11- EAC11 S ADDR12 DADRO1 CEVND2 DEVSL2 SKIP3 ENBL EAC11 BACTY T ADDR13 ADnR13 DEVSL2 ENBLND SKIP DEVSL1 GNDE15 BAC09- U DEVSL2 ENBLND GNDB15 V TABLE 1-8.

PANEL I... COMMON SECTION A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 R123 R2C2 R123 W___ 50S B B C BC O EACOn- IOP4 #SROO+ #XMT+ D E EAC-1- DEVSLC #SROL+ #REC+ E F LcAC- BPCLR #SRSV+ F H ACOOp CABTOO #DLST+ H J ACCI XINT+ CABTO1 #PAR+ J K EACh2-.SRSV- #SRC2+ #EBPC+ K L EAC03- 4XMT- #SR03+ #IFMD+ L M LDAC- #STRDY _ M N ACC2 IOP4 DABTC2 #TMRD, N P AC03 DFVSLC DABTl3 #RING P R EAC'4-.PCLR #SRC4+ #CARDT R S EACh5- #SRO5+ S T LDAC- RINT+ T U ACC4 4SRKSV- DOAT04 U V AC05 #REC- CABTO5 V 117 1H -_ 1.32C.21 0B22 6B23 24 B?25 B26 6B27 828 829 830 831 B32 P123 W1'02 R111 R12j A A C C ) EACh6- EACCO IOP4C #SRC6+ D E EAC'7- EACOl CTWDC #SRC7+ E F LCAC- EACr2 F H ACC6 EACC3 #SRSV+ CABT06 H J ACC7 EACO4 CABTn7 J K EACC8- EACC5 BT1C #SRC8+ K L EACI9- EAC06 SR.rC9+ L M LDAC- EAC'7 N N ACC8 EACC8 BT1 DAB T18 N P ACC9 EACC9 BT1 DABTC9 p R FAC10- EAC1C # SRlO+ R S EACh1- EAC11 SRI1+ T LOAC- I)IAC1....__ ______ ___ T U AC1, DICTL DABT10 V AC11l DA3Tll TABLE I-9

PANEL 2... PnRT n/IINF ADnAPTnR 1 AMl A'"2 AC3 Aq4 AC5 A06 A07 ~A8 A0 AlO All A12 A13 A14 A15 A16 2eIC ELIAP Rill W1 5 R Pill RO1 R302 Pill R201 R205 R205 R205 R2C5.R205 R_21 R205_ A B C #GNDN2 4 GN DC4 GNCC6 D #SO3B 4CGNDC2 #RD+ #SRCK ESCBF+ wREC- tRECEt,tRCiB 4RINGE #P.EC+ iLINlE+ COTND1 #RPQSC+ #SHIFT F #RSb SRCK CTND IT t #REC- #GNDC6 #RD+ H C SD[3,4ING #RC- #CLT1 T#OTNO2 REC+ J SPUdB -ING #RD- #CLll #REC- #AO6JK K,(THDY 3;GNCC'2 IPTBFE+ #RSNI) #AO6JK O#IVTE- #ZRCSR L RING l #CSDHB GN004 #L INE- S Rl)_ + l #CDCET B kDELAY /L 4 t TND2 #BFIX #SROON.CS+".. L. 4 VtCLTl #IFMD+ #XMT+ P #SCTB CCS+ HREC- hSHIFT R S CR- f GNC'i:2 #BFLIX 4/SCRB iXI'I- #RDS,SR DB PI #XTFR _ # AO 6S T #MB SR RT -RSt\ - A0n6ST BM 801 A B #GND14 C #SHIFT #SR) I1 -#ZERSR BMB01 #SKO 1+ #SR e#SR C+ tMHSR #SHI FT #SRO2+ fSRPO2 -'tMBO 2_ #SR 1 -#fSROl+ #MBSR #SHIFT #SRC3 -#ZERSR BMB03 # SR03+ # SR 2 -#.SR02+ #MBSR #SHIFT #tSR 04+ #SR04 -BMB04 #SRO3 -#SR03+ #MBSR #SHIFT #SR05 -#ZERSR BMB05 #SR05+ tSRO4 -#SR04+ #MBSR #SHIFT #SRn6+ #SR06 -BMB06 #SRn 5 -#SR05+ #MBSR #SFIFT #SR07 -#ZERSR BMB07 #SR07+ #SR06 -#SR 06+ #MBSR #SHIFT #SRC8+ #SRC8 -BMB08 T SRC7 -#SR07+ #MBSR #SHIFT #SR09- #SHIFT #ZERSR #SRlO+ BMB09 #SR09+ #SR08- #ZFRSR #SR08+ #SRl1+ #MBSR #SRll#SHIFT #SR10+ #SHIFT #SR10- #SR10 -BMd10 #MBSR #SR09- BMB11 #SRO09+ #MBSR #SHIFT #SDBF+ #GND14 #SR11+ #-SR11l#FRZE #SHIFT #PATY+ #PATY#GN014 #EP2 #EP2 #ZROSR D E F H J K L M N P/ R S T U V U ftSTRPY iDELLAY V ' I STRpDY #RSl #PS1 PPR1 II....2...... 3 P..4 ' % B06 BC7 Pe 8"0 810 Bl 1 2 813 B8 4 315 B16 W6C?.ELIAR. 5. kSnl5 R6 R202 R6C2 6 2 R602 R602 R202 R107 R107 R121 Ri-j R002 - A A B B C GN D34. #GND36 #GNC43 BKSLB C O 4OJUT1 '.GND34 #SCK #CCTDO #JMP3S #dJPP41 #JMP41 #SRSV+ #CAROT #BRENB IIOPCS #ENDI #SROO- 0 E 4 'P.D6 #CCT #FR3+ #RSYN- #CDTD #BR1 #EBPC+.BRENB #SROL- E F SD-3_ #SCK CC7ID t#PCLR #EXMT #PWCLR #DY+ BKRQ# #DTSY+ #DSYND F H irkQSUO+ 4RCBI IR ECG- #CLOCK 4BRKDN #CLOCK #RSYN- #DY- #BKRC+ #F1 #CHRDN #SR02- H J, R DPI #RFC+ #OTSY- #ENZR Z# SYNC- #STCK #ENAX+ #IFMD- #CHRDN #SR03+ J K 'R SB GIN34. #L37 t#SRCK #ZERSR #ZROSR nPWCLR ftSTART #SRSV- #SCK #ENAX- #DTSY- #IFMC- #OSYND K L #TM-q)U+ 4CDETB #GND36 #U37 #RECE- #ZROSR 4START BPCLR _ #REC- #RD+ #ENBL+ #ESFT #REC+ #SR04- L M #L36 #L37 f#JMP39 #J P4, #JMNP41 #RDBI #ENBL- #DY- #DSYND #SRC5+ M N fTTRDYY fCDCT #136 #L37 #START #DTSY+ fENDI #SVC- #DTSY- #DSYND N P V+HBl 4CI)T #STCK #GND43 #ODTSY- #END #IOPCS #OTSY- #SR06+ P R #V-B"H #SCTr3 #JM37 #PvCLR #XMT- #PWCLR /CS- #EFRO #SRO7- R S V+BSI #TCCT #XMT- #SRCK 4CLOCK #BRKDN #SYNC- #CS+ #F1 #DSYNO S T #JP37 #XMT+ #REC- _fESFT #EXMT #BLOCK #SVC- T -— u #STCK #CLOCK #SHIFT #MBSR #END #CLOCK EKSLB #IOPCS U V #V-,1 I #XMTE- #FR3+ #SVC- #ENDI V TABLE 1-10.

PANEL 2... PORT O/LINE ADAPTCR 1 A 17 A A1& AIS A2 A21 A22 A23 A24 A25 A26 A27................................ A?28 A2 A30 A31 A32 R21l R2C1 R2C1 R205 R2r5 R25 R 2'5 R123 R123 R123 A I c A B #CGC19 #GNC2C #INVIKK.I[NVtK #STCK #^RKDN #SRSV+ #EBPC+ #CFR3+ D # F F:.3 + E 4DYF H L INF- - J #L INE+ K 4C Lt CK L M N P R OL INE+ 4FRZF P F R Z F #FR3 +.rINVAK 4l[;/C #START #CLSD- #RQSOBACCI7 GCND19S GND2C 4PWCLR P^,CLR #PWCLR #PNCLR #REC- oPARp1 #RS1 #X`MT+ _FBPCf+ PAR+ 4CLSO+ #RQSD4,PwCLR 4PPCLP PPCLR H.ACL^. eAC02 #CS- #XTRC# IF( f)+ -PK+ --. B;"^E - A CC- 2 #CS+ FXTK(+ #IF tF, Fi)- SVC- 1CLCCK BTl R ST T 1 NVIK I NVK # I NVK I NVMK INV'K F3-+ 4 AREC- itTMRC4 ADLST+ 4SRSV+ #XTRQ+ hACCT7 IFPC- X MT+S #SRSV- #XTRQ*CLCCK <1AR'iT 'XMT- -SPSV- FESRSV #-)TSY-. FXfT-.REC+ -AC-TY HAC.I BAC"^ BAC)4 fXMT- 8ACTY EACP1 FAC ^" HACU4 #REC+ *CHfRt)N #CHRDN -,DLST+ #IFMU+ R #ENBL+ #ENBL+ EACOC EAC06 - EAC01 EACn7 - 4PAR+ #STRCY * TRQSD+ TfMRD+ #ENBL+ #ENBL+ ( EAC)2 EAC08 - EAC03 EAC09 - #XTRf+ #RING #CLSD+ #CARDT #CFR2+ 4ENAX+ EACO8 EAC09 #CFR1+ E F H J K #CFRO + #ENAX+ EAClO EAC 1 #RQSO+ #R SD L M N P R s S P T3F+ U hFFR3+ V P A T Y + #ENBL+ #ENBL+ EAC04 EACil EACCS EAC11 BKSL# C I AD 1 1 CICTL u v 00,b 17 7 H L 91 HP2 1 b22 9P23 824 P25 3?6 827 328 82g B3C 831 B32 PC' i 1 R P 121 R12 P1 21 R1 R i 6 l ll 6'3 R602 R205 R2C5 R2C5 R205 A C F f?: 'Ti PC'F- C SS)+, XMTNI; -?CLS)+ tiC AR I' T k X MTf I' I-! J L '1 X A TNi.) S T P Y ' X M T N I] ji F,' 2 + fL) Y N X Tc - #FR 3+ # FR 3 + LCY N) 4,nv_ 4ENZR P R FC + # I F + EXM T * IFFL+ - %, T ) C) - uE P2 #RD+ DOT SY+ _ #EP2 fAD AC;tSR11+ ACDACC tnXMT+ BKSL# #EP2 #8RKDN,tRO+ BKSL*,;,.,,.-,........-. A,,* A B #4GD59 IGND6)0 GNDE1 C C TWD1 IOP4 #JMP59 #CLOCK #FR1+ #LDAUX #LDAUX 0 A6LNL #ENL3L- #CFRO- #CFR2- E.BLCCK #BLNC #INVMK _ FRZE #F RZE #PWCLR #PhCLR F PHLNO #FNBL- #SVC- #CFRO- #CFR2- H CTwD2 #ENBL- #GND59 #FRO+ #FR2+ #CFRC+ #CFR2+ J AAXIN\ #ZROSR #FRZE #EFRO #GND61 BAC11 BAC09 K HiLCCK #XTRQ+ #PWCLR #EFRO #GND61 BACll BAC09 L 4AXNC #AXND #LDFR #JMP59 #LDFR #LDFR M.... -..:, I i. J - t. A I........................ ____-;_____ ___ _ Y- #__ T ftKLLt+ TKC PtRt- #tNlAX- ___R__ _ #F- KU+_F+ tFR+ BLUAUX #LCUAUX_ N P ^iYNCy PCY- ^ XFIT #IFlUt+ BT1C AhPARNDO ENAX- TMBSR -IFMD- D FR1+ #FR3+ #CFRI+ #CFR3+ P;.', v,-LRPC+ #AEC+ #RECE- #ESRS\V PAR1.DlY+ #RD+ IOP4 XMT- #CFR1- #CFR3- R.S aCYN C h IFPD+ ARQSID- #XMT+ A#RD- APARND #PATY- #ENAX- #IFMD+ #CFR1- #CFR3- S T hIFMf)+ #CLSC- #XTRQ+ #REC+ #PARNO #LDAUX #REC- #GND60 #GND61 BACO1 BAC08 T J DYi)YNC #ESRSV #CARLI?tIFMD+ #BY+ #PAR1 #RSTRT #GND60 #GND61 BAC10 BAC08 U V #S____________ TRCY #PA TY+ #LDFR #LOFR V TABLE I-11.

APPENDIX II 201A LINE ADAPTOR INTERFACE FOR USE ON THE DATA CONCENTRATOR II-i

APPENDIX II TABLE OF CONTENTS Page Data-Break Control................................ 11-3 Data-Break Address and Data Gating................ 11-5 Common Data Address Gating........................ 11-5 Scan Address Buffers.............................. 11-8 Address Decoding.................................. 11-8 Data-Break and Device Selection................... 11-8 Device Selection Gating........................... 11-8 Scan Interrupt Service Request.................... 11-8 Transmit Clock Gating............................. 11-14 "I'm Here" Indication............................. 11-14 Buffered Memory Buffer Buffers.................... 11-14 Accumulator Output Buffers........................ 11-14 Miscellaneous Circuits........................... 11-19 Cable Layout.................................... I-19 Module Utilizations............................ 11-19 II-iii

APPENDIX II Table LIST OF TABLES Buffered Accumulator Outputs............ Buffered Memory Buffer Output Lines..... Programmed Input/Output Control......... Page II-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 II-10 II-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 11-21 Data-Break Address Lines........ Data-Break Input Lines.......... Data-Break Control Signals...... Data-break Request and Select... Extended Accumulator Inputs..... Scan Address.................... Scanner Control Signals......... Transmit Clock................. Panel 1 - Common Section........ Panel 1 - Common Section........ Panel 2 - Port O/Line Adaptor 1 Panel 2 - Port O/Line Adaptor 1 Panel 3 - Port 1/Line Adaptor 2 Panel 3 - Port 1/Line Adaptor 2 Panel 4 - Port 2/Line Adaptor 3 Panel 4 - Port 2/Line Adaptor 3 Panel 5 - Port 3/Line Adaptor 4 Panel 5 - Port 3/Line Adaptor 4 ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ ~~~~~~~~ 11-22 11-23 11-24 11-25 11-26 11-27 11-28 11-29 11-30 11-31 11-32 11-33 11-34 11-35 11-36 11-37 11-38 11-39 11-40 11-41 11-42 II-v

APPENDIX II LIST OF DIAGRAMS Diagram II-1 II-2 II-3 II-4 II-5 II-6 II-7 II-8 II-9 II-10 II-11 II-12 II-13 II-14 Data-Break Control.................... Data-Break Address and Data Gating...... Common Data Address Gating.............. Scan Address Buffers................... Address Decoding........................ Data-Break and Device Selection......... Device Selection Gating................ Scan Interrupt Service Request.......... Transmit Clock Gating................... "I'm Here" Indication.................. Buffered Memory Buffer Buffers.......... Accumulator Output Buffers.............. Miscellaneous Circuits.................. Cable Layout............................ Page II-4 II-6 II-7 II-9 II-10 II-11 II-12 II-13 II-15 II-16 II-17 II-18 II-20 II-21 II-vii

APPENDIX II LIST OF FIGURES Figure Page II-1 Organization of the Data Concentrator... 11-2 II-ix

201A LINE ADAPTOR INTERFACE FOR USE ON THE DATA CONCENTRATOR The remainder of the logic and details of the 201A communication adaptors used on the Data Concentrator are presented in this Appendix. Figure II-1 shows in block form the general organization of the Data Concentrator, to the extent that it concerns the 201A line adaptors. The control of AC transfers and interrupts for the PDP-8 is handled by the scanner. In order to address a line adaptor (for the purposes here, a 201A line adaptor) the scan address register must be loaded with what corresponds to the line adaptor's logical address. This logical address, in reality, is the core address of its receive or transmit buffer. When the scanner is interrupted by a line adaptor, it in turn interrupts the PDP-8 with the scan address register set to the receive or transmit buffer address depending on the type of interrupt. The IOT structure is the same as described for the basic 201A line adaptor once the scan address register is pointed to the line adaptor. The normal operation for the scanner is to scan, in turn,each of the 64 full-duplex lines looking for an interrupt. When an interrupt is found, the scanner is stopped and a PDP-8 interrupt is generated. After servicing the scanner interrupt (indirectly a line adaptor interrupt), the scanner is restarted. The multiplexor is a buss-type multiplexor where the device presently selected gates its address and data information onto common busses. A device requests a data-break cycle by pulling to ground its break request line, and the data break is granted when its select line goes to -3v. In order to realize this buss concept, certain of the normal PDP-8 signals are electrically inverted at the multiplexor interface. II-1

11-2 IBM/360 INTERFACE PDP/8 WITH 16K 12-BIT WORDS 8 CHANNEL MULTIPLEXOR Co 0 P-l 0 z i Co 0 H z -4 Cl I I 0 a4,C T C(A Ez cl 4 ~Z~(M I SCAN ADDRESS REQ. DATA LINE SCANNER m I 000 Figure II-1. ORGANIZATION OF THE DATA CONCENTRATOR

11-3 There are four 201A line adaptors on the Data Concentrator. They all have a common control section which, in the context of Figure lis the PDP-8/201A line adaptor interface. The common section is Bay 1 of the complex with Bays 2-5,representing the four 201A line adaptors. The individual signal names in the 201A line adaptor contain a # sign which is replaced by a 1, 2, 3, or 4 in the particular line adaptor. The common signals are distinguished by the absence of a # sign. Unless otherwise noted, the logic shown in the diagrams in this Appendix is realized in Bay 1. Data-Break Control (Diagram II-1) By setting the #BKRQ flip-flop, the line adaptor signals the PDP-8 (through the multiplexor) that a data transfer is desired to or from PDP-8 core. The multiplexor responds with the BKAC# signal when the data-break cycle is granted. The direction of the transfer is specified by the DICTL signal. When the PDP-8 enters the break state, the address is loaded into the memory address register and an address accepted pulse is generated by the PDP-8. At this time, the break request signal must be dropped by the interface. During the break state, as indicated by the logical-and of BBREAK and BKSL#, the BT1 pulse is used to generate a #BRKDN pulse which strobes the contents of the designated memory location from the buffered memory buffer register into the SDR register. The PDP-8 will also strobe the data-break input lines (DABT) into memory at this time in the case that the transfer direction is into core. The break request signal is generated each time the frame counter overflows when in the text state, and when the interface first enters the transmit state to fetch the first character to be transmitted. All of the logic shown in Diagram II-1 is in the individual line adaptor bay.

B13 #BRKDN BKSL# M BBREAK N 1-0 BTIC P #START #" I p F DSMT # I FMD- #XMT ADDACC B23 K BKSL# DICTL A30 S Diagram II-1. DATA-BREAK CONTROL

11-5 Data-Break Address and Data Gating (Diagram 11-2) Each 201A line adaptor has assigned two sequential locations in PDP-8 core to be used as buffers for incoming (received) and outgoing (transmitted) data. The low-order four bits, except for the lowest order bit, are specified by an address card shown in Diagram 11-5. The high-order five bits (page address) are specified by the Scanner and are gated onto the data address lines when the PGENB signal is given, as derived in Diagram 11-3. The remainder of the address bits are specified in Diagram 11-3. The contents of the SDR register are gated onto the data break input lines when the BKSL# signal is present, as shown in Diagram 11-2. All of the logic shown in Diagram 11-2 is in the individual line adaptor bay. Common Data Address Gating (Diagram 11-3) There are a total of 128 scanner data lines (64 full-duplex pairs). This corresponds to one full PDP-8 page of buffers. In the twelve-bit PDP-8 address, the highorder five bits specify the page; the low-order bit specifies whether the address is a receive or transmit buffer as the bit is respectively zero or one. The remaining six bits specify, which of the 64 line pairs is being referenced. These 64 line pairs are further broken down into eight blocks of eight lines each. Positions 5, 6, and 7 in the address thus specify the block address. A separate cable connects the scanner to each block of line adaptors and in turn provides the block address for those line adaptors, and a common buss (PGENB) to tell the scanner to load the page address on to the data address lines. Diagram 11-3 indicates the gating necessary to gate the block address onto the data address lines and pull down the PGENB buss.

DABTOO l% IH #SROO+D A 1 BKSL# LI DABTO 1 #SR01+A 8 Z —~~A1 E DABT02 #SRO KK DABT03 m #SR03+A 8 DABT04 #SR04+R BKSL# DABTOS lo T #SRO A1 s~~1 DABT06 DIAD08 DABT08 K #SR08+ I_~J ml9 BKSL# O ^ DABT09 M r - _ #SR09+ A19 L DABT10 R Iu #SR1~0+ ^]- A19 B K S L # _ DABT11. T [V #SR11+, A19 S I oN DIAD11 U #RQSD+ A30 BKSL# T Diagram 11-2. DATA BREAK ADDRESS AND DATA GATING

DIAD07 PGENB B18 K B18 R S Diagram II-3. COMMON DATA ADDRESS GATING

II-8 Scan Address Buffers (Diagram 11-4) These buffers provide the required isolation and signal levels to allow each 201A line adaptor to ascertain whether the current scan address is actually its address. These signals are fed to an address card which decodes the scan address actually assigned to the line adaptor. Address Decoding (Diagram II-5) This address card, located in the individual line adaptor bay, provides the line adaptor with its data break address within a scan block and the signals to determine if the current scan address is the line adaptor address. Data-Break and Device Selection (Diagram II-6) The first set of gates in Diagram 11-6 derives the individual BKSL# signals from the multiplexor signals BKAC#. The BLKAC signal goes to -3v if any of the four 201A line adaptors is granted a data-break cycle by the multiplexor. The signals CTWD1 and CTWD2 are the assertion that the device codes corresponding to Control Word 1 or Control Word 2, respectively, have been detected during an IOT microinstruction. Device Selection Gating (Diagram 11-7) The gates shown in Diagram 11-7 are located in the individual line adaptor bays and provide the signals to differentiate between Control Word 1 and Control Word 2 operations. Scan Interrupt Service Request (Diagram 11-8) Every time a character is transferred between a 201A line adaptor and the PDP-8's memory, it's character service flag (#SRSV) is set, as described previously. The SCNSVC buss is pulled to ground the next time the scan address matches the

SCANO- SCAN2 -| D SA17 NSCAN2 A 7 ~1 A17 eA ~~~~~~~P _ SCANO+ 1A6__SCAN2+ F |R _ s _ SCA~~~~~i-~SCAN2 -A1 7 A1 7 SCAN1 -— AA SCAN3 -E I SCAN3+ SCAN1+ SCAN3+ *-N/V\ MO~k]A17 SCA 1- 1 B17 H Diagram 11-4. SCAN ADDRESS BUFFERS

SCAN1+ (1) Y SCAN1- (0) 0 Ah SCAN2+ (1) SCAN2- (0) SCAN3+(1) SCAN3-(0) ot0 lit ol 0 -* —% D E F i H J K L M N P R SA29 ADR08 ADR09 ADR10 ADR11 #SCAN3 SCAN2 SCAN1 SCANO =0 XMT/REC SCANO=1 XMT SCAN0=0 REC #SCAN1, o 0 #SCAN2 #SCAN3 4111,i r 0 * w #ADR08(1) #ADR09(1) #ADR10O(1) 'U' NOTE: JUMPERS ARE FOR LINE ADAPTOR #2, THUS '#' = '2' Diagram II-5. ADDRESS DECODING

CTWD1 BKAC1 DEVSL1 BKSL2 CTWD2 A A-AAA~i --- —-------- 4 u -I IT B KAC 2.... B16 B BKAC3 i A15 DEVSL2 R S KSL3 I B18 F E H A17 I F I I B191 Diagram 11-6. DATA-BREAK AND DEVICE SELECTION

#ENBL+ #SCAN1 3 E H M 241 I I, #ENAX #ENAX+ K K K M IB241 Diagram 11-7. DEVICE SELECTION GATING

#SRSV+ D B17 ~Mr~~~cr~I B18 Diagram 11-8. SCAN INTERRUPT SERVICE REQUEST

II-14 line adaptor's address, as specified by #BLOCK, #SCAN2, #SCAN1, #SCANO+. SCNSVC at this time causes a PDP-8 interrupt which the program can then identify. Transmit Clock Gating (Diagram 11-9) The 201A data sets for the Data Concentrator have externally supplied transmit clocks. This specification allows transmit interrupt staggering and the use of different clock rates. The actual clock selection is made via a jumper card in Bay 1 while the driver for the data set is in the individual line adaptor bay. "I'm Here" Indication (Diagram II-10) The gating in Diagram II-10, located in the individual line adaptor bays, provides to the scanner a not here'7 or "off-line" indication through the #HERE signal. Buffered Memory Buffer Buffers (Diagram II-11) This set of buffers is needed for loading reasons in each block of line adaptors. The buffers also provide the necessary inversion to give the correct signal polarity as needed in the line adaptors. Accumulator Output Buffers (Diagram 11-12) This set of buffers is needed to provide the necessary driving capabilities for the line adaptors. The buffers also provide the necessary inversion to give the correct signal polarity to the line adaptors.

CK201A CK201A CK201A CK201A I CK201B CK201B CK201B CK201B D E F H J K L M S T U V 1SCTE 2SCTE 3SCTE 4SCTE vU B13 #SCTE D, LEVEL AMP #SCTB " FB03 IF NOTE: JUMPER FROM DESIRED CLOCK TO #SCTE Diagram II-9. TRANSMIT CLOCK GATING

* B17 #SCAN3 #HEREB #HERE B16 B13 S L B18 Diagram II-10. 'I'M HERE' INDICATION

BMBOO BMB06 BMBOO+ BMB06+ BMB01 RMRB F ~BMB01H+ *A16 H - F BMB07+,>_ B16 H ) 7 BMB02 BMB08 AAA J BMB02+A1 K 1 A16 K J BMB08+ B16 I - BMB09 L BMB09+ B1B16 M I — 4 RMRnfA BMB10 L.)I-IL v N BMB04+ A16 m P-r -.. IN BMB10+ * - B16 BMBR BMB11 Bl6 S~_ —k>jB16 A16 Diagram II-11. BUFFERED MEMORY BUFFER BUFFERS

BACOO BAC07 BACOOC D E{;T]A15 F _m _. _ _r-ir BAC07C IF B 15 H A- Ht A BACO1!AC08 BACO1C IF A15 H -_ BAC08C B15 BAC02 BAC02C IJ A15 K -- BACO9C BAC09 W L _~~. B15 M - RACO4 BAC10 BAC04C I~ N - D A-l; A15 P _ B E -7!5I B15 E - u 1 u, -/ AC06 BAC06C B15 S BACTY BAC09C - B 1 -=: --- - Diagram II-12. ACCUMULATOR OUTPUT BUFFERS

II-19 Miscellaneous Circuits (Diagram 11-13) PRYREQ and SPSVC identify to the scanner that the interrupt (SCNSVC) is from a 201A line adaptor. The DTALST buss is used to indicate to the scanner that a line adaptor has a data lost condition (this gate is in the individual line adaptor). The remaining gates provide the necessary electrical signal inversion. Cable Layout (Diagram 11-14) The input/output cables for the 201A line adaptors are shown in Diagram 11-14. The correspondences between the signal names, module positions, and pin connections for the 201A line adaptor block and the multiplexor or scanner are given in Tables II-1 through 11-9. Module Utilizations (Tables II-10 through 11-21) Tables II-10 through 11-21 give the module utilization for the four 201A line adaptors comprising the block on the Data Concentrator. In addition to the module utilization, a complete signal name map is also shown.

R K. T R SCSVCB BLKSEL WN! BPCLRC -bI B17 IOP4 U _ DTALST SCNSVC #DLST+ A03 K Diagram 11-13;. MISCELLANEOUS CIRCUITS

0 1 0 2 0 3 0 4 05 06 07 08 05 10 11 12 13 14 II I I I I 'A' 'B' D BACOOC BMBOO+ DIADOO DABTOO EACOO SCANO -- E BAC01C BMB01+ DIAD01 DABT01 EAC01 SCAN1 - F H BAC02C BMB02+ DIAD02 DABT02 EAC02 SCAN2 J K BAC03C BMB03- DIAD03 DABT03 EAC03 SCAN3 L M BAC04C BMB03+ DIAD04 DABT04 EAC04 DEVSL1 N P BAC05C BMB04- DIAD05 DABT05 EAC05 DEVSL2 R S BAC06C BMB04+ DIAD06 DABT06 EAC06 __ CK201A T BAC07C BMB05- DIAD07 DABT07 EAC07 -- CK201B U V BAC08C BMBO05+ DIAD08 DABT08 EAC08 -- CKTLPA I A I I - D BAC09C BMB06- DIAD09 DABT09 EAC09 BKRQ1 PRYREQ E BAC1OC BMB06+ DIAD10 DABT10 EAC10 BKAC1 SPSVC F H BACllC BMB07- DIAD11 DABT1 EACHl BKRQ2 PGENB J K IOP1C BMB7+ -- -- -- BKAC2 BLKSEL L M IOP2C BMB08- DICTL -- -- BKRQ3 BLKBTO N P IOP4C BMB08+ BBREAK -- -- BKAC3 BLKBT1 R S BT1C BMBo9+ ADDACC -- -- BKRQ4 BLKBT2 T BT2AC BMB10+ -- -- -- BKAC4 DTALST U V BPCLRC BMB11+ -- -- -- -- HERE* - 4 I _ _ _ _ _ _ _ _ _ _ _ I I__ _ _ _ _ _ _ I I Diagram II-13. CABLE LAYOUT

11-22 TABLE II-1 BUFFERED ACCUMULATOR OUTPUTS 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL i LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION AOID, A02D BACOOC - - -CACOO- AO1D AO1E, A02E BAC01C ---- CACO1- AO1E AO1H, A02H BAC02C --- --- CAC02- AO1H AO1K, A02K BAC03C ---- CAC03- AO1K AO1M, A02M BAC04C ---- CAC04- AO1M AO1P, A02P BAC05C -- --— CAC05- AO1P AO1S, A02S BAC06C - — CAC06- AO1S A01T, A02T BAC07C ---- -CAC07- AO1T AO1V, A02V BAC08C ---- — CAC08- AO1V BO1D, B02D BAC09C ---- -- CAC09- BO1D BO1E, B02E BAC1OC ---- - CAlAC10- BO1E BO1H, B02H BAC11C -. --- CAC11- B01H

11-23 TABLE II-2 BUFFERED MEMORY BUFFER OUTPUT LINES 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A03D, A04D BMBOO+ - ---- - CMBOO- A02D A03E, A04E BMBO1+ - | CMBO1- A02E A03H, A04H BMB02+ --- CMB02- A02H A03K, A04K BMB03- - ----- A03M, A04M BMB03+ - _- CMB03- A02M A03P, A04P BMB04- --— >o A03S, A04S BMB04+ ----. --- CMB04- A02S A03T, A04T BMB05- --— > ---- A03V, A04V BMB05+ -- t -- CMBOS- A02V B03D, B04D BMB06- __ > -- B03E, B04E BMB06+ -* 1 CMB06- B02E B03H, B04H BMB07-. -- B03K, B04K BMB07+ ----- CMB07- B02K B03M, B04M BMB08- - i --- —o B03P, B04P BMB08+ ' ---- CMB08- B02P B03S, B04S BMB09+ --- t -- CMB09- B02S B03T, B04T BMB10+ - - t | CMB10- BOQ\2T BO3V, B04 B0MB11+ CMB11- B02V

11-24 TABLE 11-3 PROGRAMMED INPUT/OUTPUT CONTROL 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION BOlK, B02K IOP1C ---- i CIOP1 BO1K BO1M, B02M IOP2C - - CIOP2 BO1M BO1P, B02P IOP4C ---- -CIOP4 BO01P

11-25 TABLE II-4 DATA-BREAK ADDRESS LINES 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION * A05D, A06D DIADOO ---- ---- DADDOO A03D A05E, A06E DIADO1 ---- -— ADDO1 A03E A05H, A06H DIAD02 --— D> - > DADD02 A03H A05K, A06K DIAD03 - > - o bADD03 A03K A05M, A06M DIAD04 ---- - DADD04 A03M A05P, A06P DIAD05 D- --- -> DADD05 A03P A05S, A06S DIADO6 ---- ' --- > DADD06 A03S A05T, A06T DIAD07 ---- > -- DADD07 A03T A05V, A06V DIAD08 --- ---— ' DADD08 A03V B05D, B06D DIADO9 D --- —; --- —DADD09 B03D B05E, B06E DIAD10 ---- ----- ADD10 B03E BOSH, B06H DIAD11 - —..> DADDll B03H *Note: Collector of a Grounded-Emitter Transistor

II-26 TABLE II-5 DATA-BREAK INPUT LINES 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A07D, A08D DABTOO — <> -- DBITOO A04D A07E, A08E DABTO1 ----- DBITO1 A04E A07H, A08H DABT02 --- --- o DBIT02 A04H A07K, A08K DABT03 - - -— C DBIT03 A04K A07M, A08M DABT04 ' - --- DBIT04 A04M A07P, A08P DABT05 --- ---- DBIT05 A04P A07S, A08S DABT06 ----- DBIT06 A04S A07T, A08T DABT07 ---- --- DBIT07 A04T A07V, A08V DABT08 ---- --- DBIT08 A04V B07D, B08D DABTO9 --- > -- DBITO9 B04D B07E, B08E DABT10 ---- - DBIT10 B04E B07H, B08H DABT1l 1 ---- <> DBITll. B04H *Note: Collector of a Grounded-Emitter Transistor.

11-27 TABLE 11-6 DATA BREAK CONTROL SIGNALS 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION * I I B05M, B06M DICTL TRADI j B03M B05P, B06P BBREAK i -- CBBRK B03P BOSS, B06S ADDACC - -| CADACP B03S BO1S, B02S BTIC -- - | CBT1 BO1S BO1T, B B0T2AC --- CBT2A BOlT BO1V, B02V BPCLRC -| -- CPWCLR BO1V *Note: Collector of a Grounded-Emitter Transistor.

11-28 TABLE II-7 DATA BREAK REQUEST AND SELECT 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION BllD BKRQ1 -|> -~ - REQ2 D01D BlE BKAC1 - - --- SEL2 DO1E BllH BKRQ2 ---- > -- REQ3 DO1H BllK BKAC2 > ---- SEL3 DO1K B11M BKRQ3 --- ---— > REQ4 DO1M B11P BKAC3 i ----— C SEL4 i D01P BllS BKRQ4 - ---- REQ5 DO1S BllT BKAC4 --- --- SEL5 DO1T

11-29 TABLE 11-8 EXTENDED ACCUMULATOR INPUTS 201A LINE ADAPTOR! SCANNER INTERFACE | SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A09D, A1OD EACOO0 --. -— > EACOO+ A07D, A08D A09E, A1OE EACO1 ---------- EAC01+ A07E, A08E A09H, A10H EAC02 - - ---- - EAC02+ A07H, A08H A09K, A10K EAC03. --- — _. - EAC03+ A'07L, A08K A09M, A10M EAC04 - > --- --- EAC04+ A07M, A08M A09P, A1OP EAC05 ---- 1 ---- o EAC05+ A07P, A08P A09S, A10S EAC06 --- ---- EAC06+ A07S, A08S A09T, A1OT EAC07 - ----- EAC07+ A07T, A08T A09V, A1OV EAC08 --- - --- EAC08+ A07V, A08V B09D, B1OD EACO9 --. < -.> EACO9+ B07D, B08D B09E, B10E EAC10 - > -_-;. EAC10+ B07E, B08E B09H, B1OH EACll -.. - <' EACll+ B07H, B08H *Note: Collector of a Grounded-Emitter Transistor.

11-30 TABLE II-9 SCAN ADDRESS 201A LINE ADAPTOR SCANNER INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION ________ ____________.....___ i_________ i. AllD, A12D SCAN 0 - o -| | BXMT- C03D AllE, A12E SCAN 1 ----- BAD1- C03E A1lH, A12H SCAN 2..x, ---- - BAD2- C03H AllK, A12K SCAN 3 - ---- ~ BAD3- C03K B12M BLKBTO ---- ---- GND D01M B12P BLKBT 1 ---- ------ GND DOlP B12S BLKBT2 -- ---- GND Dl1S

11-31 TABLE II-10 SCANNER CONTROL SIGNALS 201A LINE ADAPTOR SCANNER INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION B12D PRYREQ - < ' '- PORQ+ DO1D B12E SPSVC < -'-'> SSO+ DO1E B12H PGENB - ---- - PGENB+ DO1H B12K BLKSEL - - --- BKSLO- DO1K B12T DTALST --- -0 DLOST+ DO1T B12V HERE* < --— LACHK- DO1V A11M, A12M DEVSL1 ^ ---—.. DSL+ C03M A11P, A12P DEVSL2 ---—. — ESL+ C03P *Note: Collector of a Grounded-Emitter Transistor

II-32 TABLE II-1,1 TRANSMIT CLOCK 201A LINE ADAPTOR MULTIPLEXOR INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A13S, A14S CK201A - --- CK2000 D03S A13T, A14T CK201B ---- ---- CK2400 D03T A13V, A14V CKTLPA --— |,

PANrEL 1. CALLtiL '.4 SfCT I( N A _A i '21. ' 21 'A " '< A" A t A' 7 A U A?' A 1 I) I 'AIN l h 2I "I ^21 h'2l f21 A"??1 h 21 All W^O21 A12 A13 A14 A15 A16 W'21 WC21 W021 R1G7 R1C7 A C A "' r. C......C L) HAC'iCL U.'UC E SAC' LC,-L ALC F H EAC'2C hGC '2C( J K AC"3C I AC' (C L " 3CA LuC,5UC.4C P tC 5C i ACS, C K S ^C"'AC S /CrnC 1' r'AC*7C BSAC,.;7L 7lJ U V L.A '?C 3F, F A B C JNA13D JIA13C BACCO BMBOne JMA13E JMA13E BACOOC BMBOn+ E C,;.1 i, ~..-'- + t 1 tl + [; I I + P. rl!3 5 - 1M31+) Ri~302/ +!i'!t' 3 -> iv F3 I".3 +!,? iv 94 - F: '5 54+ iL Mr- 25 - r lAL'-' IE It C 2 L I Q (~ O L C IULCCI I i CC I: I t C C c ) I [.)( 7 C I A C 0, I A C I C I A i;) 2! I A 1: ^ /: iI,lC " 5 - I A rs - t )I ii -' 7."u I4A'L" b D I)A 3 T r i A BT " 1 D A 3 1 F 2 EAIF 5r ). A H T f ( U /\ b I;' '7 i) fXR T[. P, CAL IT.nr C Ab T ', 1 [ XP. tT r C AFT -5 L A ' T '? C,\ i T '' F AC C C EACL 1 EAC"2 r A "I 4 i A C? 4 F AC " 5 F A C C A LAU '7 1: AC ( ' E- AC C EAC? 1 EAC2' 2 F AC E-C,4 A C'!. F A C'; EAC' 7 F AC ' SCAN"' SCAN 1 SCAN2 SCAN 3 CEVSLI CEVSL2 JJUAllS JI AI IS JiMA 11 T JA 1 1 V SCANn SCAN1 SCAN2 SCAN3 CEVSLI CF VS L J IA IIS JMA11T JIAl lT JlAAI IV JIA13H J7A13K JA 13M JPA1 P CK2r LA CK2 01b CKTLPA BACO1 BMBC1 JMA13H BACOIC BM801+ BAC02 UMB02 JMA13K BAC02C BMBC2+ BMBO3 JMA13M BMBC3+ BAC04 BMB04 JMA13P eACC4C BMBC4+ BMB05 CK2C1A BM805+ CK201H BKSL3 BKSL1 HKAC3 BKAC1 CKTLPA F H J K L M N P R S T U V,!! —',r' + [iNl ++ U I ACL I CA CM O, O, i'l " 1 <5 2 r. (3."(, S C 3 i ['e iCr 7 3t j H i " B1 1 ^. L ^ 4 ( l ' 1 "t i l irC h r 1 A 2"I 2 W. 2 1 " ''2 1 W 2 1 h2 ll [2 h0 21 B12 W321 b13 ccS 4 B14 B15 R11l R1C7 816 R107 Ai C,) F r I-i,J K L P 1 tJ '}AC"' c 13iAL.':.9( IACJ' C I i' 1i I it 2 C I l't'C I 'i2.AC i P12 C. IC iT A 12 I.T T2AC 6i 1 2AC MP fI' + oMYB' c + t L V., -, 6 -Bt i',t h:'; + i4', {', ' 7 -ti3,v'tj^ bLIy.;-8+ B,. L d + LI Ir) + U PLM3 1; + Hf/~i Bf+ C. I LC c U IA 1C, I / L 1 1 Ji Hr 5 IC TL t k F A A C L CC Ji83^S I A I::, I A l;l I I A [.~ 1 J,1 (" 5 U ICTL i RiK EAK A C ACC J.'11U r T D AL Tr DAbT 1. -.' /)ABTI 1 CYSEL J I 6A " 7 p J i B C 7 I J,'3"7T E a T 1 9 C A B TT 11 C[Blll CYSEL J P UBF 7P J F B ( 7 P L0v S7S JM13' 7T j IR 7 V7V EtACS 3 EACO EAC' l EACI" EAC11 EAC 1 RCENBi ROEIN SKENIB SKclNB J7 B" 9 P Jth"I9P JEbCSS JNfv C9S JMBI)S T JMBOI 9T JMi9SV JM '. 9V KRQ1 BKAC 1 EKR Q2 tKAC2 BKRC3 BKAC3 BKRC4 bKAC4 PRYREQ CK201A SCNSVC BAC06 BMB06 SPSVC CK201A BAC06C BM806+ CK201A BAC07 8MB07 PGENt CK201A SCSVCP BAC07C BMB07+ CK201B SCSVCB BAC08 BMBI8 HLKSEL CK201B SCSVCB BAC08C BMB08+ CK2nlB BAC09 BMB09 CLKBTO CK2C1B BAC09C BMB09+ PRYREQ BAC10 BMB10 3LKBT1 SCNSVC BAC10C BP810+ SCSVCB BACH BM811 ELKBT2 1SCTE BAC11C BMB11+ DTALST 2SCTE BACTY BKSL2 3SCTE SPSVC BAC09C BKAC2 A B C D E F H J K L N P R S T U V F'tC.L.F' L PC LC t;t6l 1+ 6t3rI;311+ JML.CSV JMi''lbV JMBCT7V HERE* 4SCTE V TABLE 11-12.

PANEL 1... CCMMCN SECTIC ____ A17 A18 A1S A20 A21 A22 A23 A24 A25 _ A26 A27 A28 A29 A3C A31 A32 RIr7 R111 W05C WC5C A A 6 B C ____ ____ ___. _ __ _ _ ______C_ D SCANC- BLKPTC 0 E SCAiNC BLKAL. 1SRSV+ 2SRSV+ E F SCAN++ F H SCANC- DIADC7 IDLST+ 2CLST+ H J SC4N1- K SCAN1 BLKBT1__ 1PAR+ 2PAR+ __ _ __ ____ K L SCAN1+ HLKAC L M SCN 1- 1STRDY 2STRCY M N SCAN2- D IACC6 N P SCAN2 1TMRD+ 2TMRC+ P R SCAN2+ 6LKBT2 R S SCAN2- BLKAC 1XMT4 2XMT+ _ __ ______ S T BKSL4 T U eKAC4 OIACC5 1REC+ 2REC+ U VV L1 81 B.1S B20 E21 f22 b23 B24 825 B26 827 828 829 830 831 832 RC 7 Rill RC 1 WeC5t C50 A A H B C C 0 SCAN3- BKAC1 eKAC3 0 E SC AN BKAC2 bLKND 3SRSV+ 4SRSV+ E F SCAN3+ BLKNC bKAC4_ _ _ F H SCAN3- bLKAC HLKNC 3DLST+ 4DLST+ H J EKSL BLLKAC J K.LKSEL bLKAC 3PAR+ 4PAR+ K L EPCLf. L M 8PCLRC 3STRCY 4STRCY M N CTD1 PGENB _ __ ___ ___ ___ _ _ __ __ N P DEVSL1 3TMRD- 4TMRC+ P R CTnl)2 BT1C R_.. R S CEVSL2 XMT+ 4XMT+ S T IOP4 T U I()P4C BT1 3REC+ 4PEC+ U V BT1 V (A W 4:sl TABLE II-13.

PANEl 2 PORT 0/LINE ADAPTOR I ACI AC2 AC3 A04 AC5 A06 A07 A08 A09__ AI All __A12 A13 A14 A15 A16 _ __2C1C EIAR RRill W5'1 Rill R001 R302 Rill R201 R205 R205 R205 R2C5 R205 R201 R205 A A B B C 1GNDC2 GCND014 1GNC06 ___ 1GND14 C D iSCB 1GND0O2 1RO+ 1SRCK 1LEFF+ 1REC- 1RECE- 1SHIFT 1SHIFT 1SHIFT 1SHIFT 1SHIFT 1SHIFT 0 E 1RCB 1RINGE 1REC+ ULINE+ O10TND1 1RQSC+ 1SHIFT 1SR01- 1SR03- 1SR05- ISR07- lSROS- 1SHIFT 1SDBF+ E F 1RSS3 1SRCK ICTLNCL 1REC- 1GND06 1RD+ 1ZERSR 1ZERSR IZERSR 1ZERSR 1ZERSR 1SR10+ F H 1CSCB 1RING 1Ri- ] CLI 110TN02 1REC+ BMB0O1 BPB03 8MB05 BFP.07 BMB09 1GN014 H J ISROB 1RING IR- 10LT1 1REC- 1A06JK 1SROl+ 1SR03+ 1SR05+ 1SR07+ 1SR09+ J K 1TROYB 1GND02 IDLSI+ 1P ITBF+ 1RSND 1A06JK 1XNMTE- 1ZRSR __1SROO- ISR02- 1SRO04- ISR06- I1SR08- 1ZERSR ISR11+ K L 1RINGB 1CSDB IC-NOD4 1LINE- 1SROO+ 1SROC+ 1SR02+ 1SR04+ 1SR06+ 1SR08+ 1SR11+ ISR11- L M 1CCETB 1DELAY 1_LO. lCTND2 IFIX ISROO- 1MBSR 1MBSR 1MBSR 1MBSR 1M8SR 1SR11- I1FRZE __M NICS+ DTALST 1 L CLT 1 IFMO+ IXMT+ 1SHIFT 1SHIFT 1SHIFT 1SHIFT 1SHIFT ISHIFT N P 1SCT2 1CS+ 1REC- 1SHIFT.1SR02+ 1SR04+ ISR06+ 1SR08+ ISR10+ 1SHIFT 1PATY+ P R ISCRB 1GNDC2 IBFIX 1SCRB 1XTI- IRD- lSR02- 1SR04- 1SR06- 1SR08- 1SR10- 1SR10-IPATY- R S _ ] _ 1. SRUB XTPQ+ 1 A6 ST___ 1MBSR BMB32 BMB04 BMB06 BMB08 BMBO10 1MBSR IGND14 S T IPSND 1AO6ST BMBOO 1SRm 1- 1SR03- 1SR05- 1SR07- 1SR09- BM811 1EP2 T U 1STRCY IDELAY iRS1 1SR01+ 1SR03+ 1SR05+ 1SRO07 1SR09+ IEP2 U V 1HERE 1STRCY RS1 1BR1 IMBSR 1MBSR 1MBSR 1MBSR IMBSR 1ZROSR V.b01 -B02 3B03 B04 BC5 B06?07 B08 109 B10 B1l B12 B13 14 -815 -B16 W6C2 EIAR W602 B501 k501 R202 R602 P6C2 R602 R602 R202 R107 R1C7 R121 R1l-l R002 A A B............ _ B' C 1GND34 IGND36 1GND43 C 0 ICUT I 1GND34 1SCTE!SCK ICCTD 1JP39 IJPP40 1JfP41 1SRSV+ 1CARDT 1BRENB 1IOPCS 1ENDI 1SROO- D E 1RDB 1CCT 1FR3+ 1RSYN- 1COTD 1BR1 1E8PC+ 1BRENB 1SROI- E F lSC _ ISCTE 1SCK 1CCID 1PWCLR I.__ EXMT ____- 1PWCLR 1DY+ BKRQl 1DTSY+ LODSYND F H 1RGSC+ 1RCBI IR:C- 1CLOCK 1BRKDN ICLOCK 1RSYN- 1DY- 1BKRC+ IFi 1CHRON ISR02- H J 1RUBI IREC+ IDTSY- IENZR 1SYNC- 1RSYN+ 1STCK 1ENAX+ 1IFMO- ICHRDN 1SR03+ J K 1RSB 1GND34 1137 1SRCK 1ZERSR IZROSR IPWCLR 1START 1SRSV- 1SCK 1ENAX- 1DTSY- 11IFMD- IDSYND K L ITNR34- 1CD ETB _ 1GND36 1U37 1RFC- 1ZROSR 1START BPCLR 1REC- _IRD+ 1ENBL+ IESFT 1RECt 1SR04- L_ M 1L36 1L37 IJMP39 1JMP40 1J1P41 1ROBI 1ENBL- 1DY- 10SYND 1SR05+ M N ITRDYB 1CDI 1L36 1L37 _________ 1START 1DTSY+ 1ENDI 1SVC- 1DTSY- IOSYND N P lV+B1l 1CCT 1V+tBC3 ISTCK 1GND43 10TSY- lEND 1IOPCS 1DTSY-1SR06+ P R 1V-BOl 1V-L3C3 1.SCTBI 1Jd,37I 1P:~CLR 1XMT- 1PWCLR!CS- __HEREB IEFRO _ISR?07-.R S lV+81 1V+B13 1CCE IXMT- 1SRCK 1CLOCK 1BRKDN 1SYNC- 1CS+ 1HERE 1FI IDSYND S T 1 Jt37 1XMT+ 1REC- 1ESFT 1_EXMT_ _BLOCK ISVC- I H_EREB T U ISTCK 1CLCCK 1SHIFT 1MBSR 1END 1CLOCK EKSLB IIOPCS 1BLOCK U V iV-B1i I V-B,3 i___ XMTF- 1FR3+ 1SVC- IENDI 1HERND V TABLE 11-14.

PANEL 2... PORT O/LINE ADAPTOR 1 A17 A18 AlC A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 _2C2 R123 R123 KR201 R2C1 K21 2 _1 R2C5 P 2C5 R2C5 R2'5 R123 R123 WSS4 R123, R111 A A B B C IC-CE19 1GND2C C D 1FR3+ 1SROC+ 1SR06+ 1INV'K 1INVMK 1STCK 1BRKDN 1SRSV+ 1EBPC+ SCAN1+ 1CFR3+ 1ADR08 0 E 1DY- 1SRC1+ 1SR"7+ 1INVMK lADAC 1STAKT 1CLSD- 1RQSO- 1DLST+ IIFMD+ SCAN1- 1CFR2+ BKSL1 E F 6KSL1 BKSL1 BAC07 1GnCIS 1GND20 1PWCLR 1PWCLR 1PWCLR 1PWCLR 1ENBL+ 1EN8L+ SCAN2+ 1ENAX+ F H 1LINE- DABTCC DAhTCb 1REC- 1PAR1 1RS1 EACOO EAC06 SCAN2- EAC08 OIAD08 H J 1LINE+ 0BO1 DABT0 BT17 1XMT+ 1EBPC+ 1PAR+ 1CLSD+ IRQSO+ EAC01 EAC07 SCAN3+ EAC09 J K 1CLUCK 1SR02+ 1SROE+ 1FPiCLR 1PICLR 1PWCLR BACC6 EAC02 1CS- 1XTRQ- 1PAR+ 1STRDY SCAN3- 1CFRI+ 1ADR09 K L 1LINE+ 1SR03+ 1SROS+ 1IFMO+ 1BKRQ+ BAC06 BAC02 ICS+ lXTRQ+ 1RQSD+ 1TMRD- 1SCAN1 1CFRO+ BKSL1 L M IFPZE BKSL1 BKSL1 1IFMC- lSVC- ICLOCK ET1 1ENBL+ 1ENBL+.1SCAN2 1ENAX+ M N 1FR3+ DABTC2 DABTC8 1RSTRT 1INVMK 1INVNK 1INVMK 1INVMK EAC02 EACO8 ISCAN3 EAC10 DIAD09 N P IPATY- DAbTC3 DAbT0C9 1INVMK lFFP+ IREC- 1TMRC4 1CLST+ 1SRSV+ 1XTRK+ EAC03 EAC09 1ACRC8 EACHL P R 1SR04+ 1SRC1+ BAC07 1IFFD- 1XMT+ 1SRSV- 1XTRQ- 1XTRQ+ 1RING 1ADR09 1RQSD+ lADR10 R S IPTBF+ 1SRC5+ 1SRl1+ 1CLCCK 1STAPT 1XMT- 1SRSV- 1ESRSV lCLSD+ 1CARDT 1ACR10 1RQSC+ BKSL1 S T BKSL1 BKSL1 1CTSY- 1XMT- 1REC+ BACTY BACOl BACOO BACO4 1ENBL+ 1ENBL+ BKSL1 T U 1FR3+ DABTC4 DABTlO lXMT- BACTY EACO91 BACO 8AC04 EAC04 EAC10 DIAD1 IAD10 U V 1PATY+ DABT05 DABT11 1REC+ 1CHRDN 1CHRDN EAC05 EACll DICTL V B17 ~18 BBlS B2C B21 B22 B23 E24 B25 826 B27 B28 B2S B30 B31 B32 Rill 1<'002 RoC1 Rill R121 k121 R121 RCCe Rill R603 R602 R205 R205 R205 R205 A A B... B C 1GN059 lGND60 lGND61 C D ISRSV+ lILCCK lTMROt 1RQSD+ 1EP2 CThDl lSCAN1 IOP4 lJMP59 1CLOCK IFR1+ ILDAUX lLDAUX D E 1RSYN\+ SCANO- 1XMTNO 1CLSD+ 1RD+ 1BLND 1SCAN2 1ENBL- 1CFRO- 1CFR2- E F 1SNND) 1SNIND lCARDT 1XMTND IDTSY+ I__ LOCK 1BLNOD INVMK 1___ FRZE 1FRZE 1PWCLR lPWCLR F H SCjNSVC ISCANI lXMTNI) lXMTE- 1ENZR IEP2 1ADAC 18LNO 1ENBL- lSVC- 1CFRO- 1CFR2- H J 1SCAN2 1STROY 1XMTE- 1PEC+ lSR11+ AODACC CTI02 1ENBL- 1GN059 1FRO+ 1FR2+ lCFRO+ 1CFR2+ J K 1SRSV+ ISN1NOD lXITN 1FR3+ IIFPC+ 1XMT+ BKSL1 1AXND ISCANI1 ZROSR 1FRZE lEFRO lGND61 BACll BACO9 K L lXNT+ IBL(CK 1FR2+ 1FRO+ 1EXNT lEP2 1BRKON 1BLCCK 1SCAN2 IXTRQ+ 1PWCLR 1EFRO 1GND61 BAC11 BACO9 L M lSN2NO sCANC+ DYNE ICYNOD 1IFPI+ IRD+ BKSL1 1AXNO 1AXND ILDFR 1JMP59 1LDFR 1LCFR M N SCNSVC ISN2NO 1FR1+ ICY- lXTPQ+ 1REC+ BBREAK 1REC+ LENAX- lFRO+ 1FR2+ 1LDAUX 1LDAUX N t~~~~~ C t- foANl; I i r 1nuw,-T., 1, I "I I. - r. t r*PsnnAi t 11 -.I. I -. -. rm.. I "I. P ISLANI IUYNL ILY- iXFl+ 1IFMU+ IBT1 1PARND IENAX- LMBSK 1lFMU- lFRK+ 1FR3+ ICFRI+ 1CFR3+ P R 1SCAN2 1EBPC+ 1REC+ _1PECE- 1ESRSV lPAR1 1 CY+ 1RD+ IOP4 1XMT- 1CFR1- 1CFR3- R S 1SCAN3 1SN2ND 1DYNC 1IFuD+ 1PCSC- IXMT+ 1RD- 1PARND lPATY- 1ENAX- 1IFMD+ 1CFR1- 1CFR3- S Ir HERNO iSCANl IFMC+ _ CLSC- IXTRQ+ 1RFC+ _ 1PARND ILDAUX 1REC- 1GND60 1GND61 BAC1O BACO8 _ T U HERE* 1SCAN2 1DYNE 1ESRSV iCPCL1 1IFMD+ iCY+ 1PARI 1RSTRT 1GN060 1GND61 BAC10 BAC08 U V 1 ERNC 1STRCY 1PATY+ 1LDFR 1LDFR V TABLE II-15.

PANEL 3 P... ORT 1/LINE ACAFTCR 2 ACL A02 A03 A04 AC5 A06 A07 A08 A09 A10 All A12 A13 A14 A15 A16 W201C EIAR Rll W501 R111i ROC1 R302 Rll R201 R205 R205 R205 R205 R205 R201 R205 A A 8 B C 2GND02 2CND04 ~ 2GNDC6 2GND14 C D 2SOB 2GND02 2RD+ 2SRCK 2SCEF+ 2REC- 2PECE- 2SHIFT 2SHIFT 2SHIFT 2SHIFT 2SHIFT 2SHIFT D E 2RCB 2RING8 2REC+. 2L INE+ 20TND1 2RQSD+ 2SHIFT 2SR01- 2SR03- 2SR05- 2SR07- 2SR09- 2SHIFT 2SDBF+ E F 2RS8 2SRCK 2CTNE1 2REC- 2CNDC6 2RD+ 2ZERSR 2ZERSR 2ZERSR 2ZERSR 2ZERSR 2SR1O+ F H 2CSDB 2RING 2RO- 2CLT1 20TNO2 2REC+ 8MB01 8MB03 bMB05 6MB07 BMB09 2GN014 H J 2SROB 2RING 2RO- 2CLT1 2REC- 2AO6JK 2SR01+ 2SR03+ 2SR05+ 2SR07+ 2SR09+ J K 2TRDYB 2GND02 20LST+ 2FTBF'+ 2RSND 2AO6JK 2XtTE- 2ZROSR 2SROO- 2SR02- 2SR04- 2SR06- 2SR08- 2ZERSR 2SR11+ K L 2RINGE 2CSDB 2GND04 2LIN — 2SRO0+ 2SROO+ 2SR02+ 2SR04+ 2SR06+ 2SR08, 2SR11+ 2SR11- L M 2CCETE 2DELAY 2L04 2CiNC2 28FIX 2SROO- 2MBSR 2MBSR 2MBSR 2MBSR 2MBSR 2SR11- 2FRZE M N 2CS+ DTALSI 2L04 2CLT. 2IFMD+ 2XMT+ 2SHIFT 2SHIFT 2SHIFT 2SHIFT 2SHIFT 2SHIFT N P 2SCTB 2CS+ 2REC- 2SHIFT 2SR02+ 2SR04+ 2SR06+ 2SR08+ 2SR10+ 2SHIFT 2PATY+ P R 2SCRE 2GNC02 2BFIX 2SCRB 2XPT- 2RD- 2SR02- 2SR04- 2SR06- 2SR08- 2SR10- 2SRIO- 2PATY- R S 2SRUBD 2XTFC+ 2A06ST 2MBSR BM BMB2 BM04 BM4806 BM808 BMBIO 2MBSR 2GND14 S T 2PSNC 2A 6ST BMBOO 2SR01- 2SR03- 2SR05- 2SR07- 2SR09- BMB11 2EP2 T U 2STRCY 2DELAY 2RS1 2SR31+ 2SR03+ 2SR05+ 2SR07+ 2SR09+ 2EP2 U V 2HERE 2STRDY 2PS1 2BR1 2MBSR 2MBSR 2MBSR 2MBSR 2MBSR 2ZROSR V BCl -RC2 8.f3 e.4 EC5 Br'6 B07 BC08 B09 B10 BL1 812 B13 814 B15 816 W6C2 EIAR.602 W5Cl I.C1 R202 R6C2 P6C2 R602 R602 R202 R107 R1C7 R121 R111 R002 A A B B C 2GND34 2GN036 2GND43 C 0 2CLT1 2GND34 2SCTE 2SCK 2CEC1 2JMP39 2JVP4,0 2JMP41 2SRSV+ 2CARDT 2ERENB 2IOPCS 2ENDI 2SROO- D E 2RUB 2CDT 2FR3+ 2RSYN- 2CDTD 2BR1 2EBPC+ 2BRENB 2SRO1- E F 2SCt 2SCTB 2SCK 2CCTC 2PWCLR 2EXMT 2PWCLR 20Y+ BKRC2 2DTSY+ 2DSYND F H 2RQSD+ 2RORI 2REC- 2CLOCK 2BRKON 2CLOCK 2RSYN- 20Y- 28KRQ+ 2F1 2CHRDN 2SR02- H J 2RDBI 2REC+ 2DTSY- 2ENZR 2SYNC- 2RSYN+ 2STCK 2ENAX+ 2IFMD- 2CHRDN 2SR03+ J K 2RSB 2GNU34 2U37 2SRCK 2ZERSR 2ZROSR 2PWCLR 2START 2SRSV- 2SCK 2ENAX- 2DTSY- 2IFMD- 2DSYND K L_ 2TMRD+ 2CDET8 2GND36 2U37 2RECE- 2ZRCSR 2START BPCLR 2REC- 2RD+ 2ENBL+ 2ESFT 2REC+ 2SR04- L M 2L36 2L37 2JMP39 2JtP4C 2JPP41 2RDBI 2ENBL- 20Y- 2CSYND 2SR05+ M N 2TROYE 2CCT 2L36 2L37 2START 2DTSY+ 2ENDI 2SVC- 2DTSY- 2DSYND N P 2V+BC1 2CDT 2V+B23 2STCK 2GND43 2DTSY- 2END 2IOPCS 2DTSY- 2SR06+ P R 2V-B01 2V-803 2SCTB 2JM37 2PWCLR 2XMT- 2PWCLR 2CS- 2HEREB 2EFRO 2SR07- R S 2V+BC1 2V+B03 2CCT 2XMT- 2SRCK 2CLCCK 2BRKDN 2SYNC- 2CS+ 2HERE 2F1 2-SYND S Tr 2JM37 2XMT+ 2REC- 2ESFT 2EXMT 2BLOCK 2SVC- 2HEREB T U 2STCK 2CLOCK 2SHIFT 2MBSR 2END 2CLOCK EKSLB 2IOPCS 2BLCCK U V 2V-BC1 2V-B03 2XMTE- 2FR3+ 2SVC- 2ENDI 2HERND V

PANEL 3 PORT 1/LINE ACAFTCR 2 A17 A1 A 1 A2(C A 1 A22 A23 A24 _A25 A26 A27 A28 A29 A3C A31 A32 R2C2 R123 R123 R201 R2C1 R2rl R2C5 R2C5 R205 R2r5 P123 R123 hS94 R123 RIll A 8 C A B 2.NV... V K STCK.2___ _ 2SV+.BPC+ SC_ N1+_ _ _ _.F _A. _ 2INVMK ZIKN\VK 2STCK 2BRKDN 2SRSV+ 2EBPC+ SCAN1+ 2CFR3+ 2ADR08 D 26NhC1 2GND20 D 2Fk3+ 2SKCC+ t 2DV- 2SRC1+ F HKSL2 H 2LINE- OABTCO J 2L iNE+ DAbTOi1 K 2CLOCK 2SR024 L 2LINE+ 2SR03+ M 2FRZE BKSL2 N 2F3 + CAdTC2 P 2PATY- DA3TC 3 R 2SR04+ S 2PTRF+ 2SKC5+ T BKSL2 U 2FR-3+ CAt1C4 V 2PAT1+ DABT05 2SR06+ 2SRC7+ 21NVMK BKSL2 PPCC7 UAST6b 2RECDABTC1 2XMT+ 2SR08+ 2PWCLR 2SRP+ 2 IFMD+ 6KSL2 2IFODDABT 08 DABTC9 2[NVIK 2SR 1 + 8ACO7 2SRll+ 2CLCCK BKSL2 2UTSYIOABTi13 2XMTDAPT11 2REC+ 2ALCC 2START 2GN0D1 2GND20 2PFhCL 2PWCLR 28 < R + 2S C2RSTRT 2FR3+ 2REC2IFCP- 2XMT+ 2St1<T 2XMT2XPT- 2REC+ 2P}CLR 2PICLR 2PPAR1 2EtPC+ 2PAR+ HACC6 EAC02 BACC6 eAC02 2CLCCK 2INVVK 2 INVMK 2TiRC'- 2CLST+ 2SRSVbACTY aC01 DACTY EACC1 2CHRCN 2CLSO2PLCLR 2CLSC+ 2CS2CS + 21 NVMK 2SRSV+ 2SRSV2ESRSV d ACT) 8AC C 2CHRDN 2ROSC2PWCLR 2RS1 2ROSD+ 2XTR C2XTRQ+ rT1 211NVMK 2XTRQ+ 2XT RCBAC 4 BACn4 2DLST+ 2IFMD+ SCANI- 2CFR2+ BKSL2 E 2ENBL+ 2ENBL+ SCAN2+ 2ENAX F EACOO EAC06 SCAN2- EAC08 DIAD08 H EACOL EAC07 SCAN3+ EAC09 J 2PAR+ 2STROY SCAN3- 2CFRl+ 2AURO9 K 2RQSD+ 2TMRD+ 2SCAN1 2CFRO+ BKSL2 L 2ENBL+ 2ENBL+ 2SCAN2 2ENAX+ M EAC02 EAC08 2SCAN3 EAClO DIAOO9 N EAC03 EACO9 2ADRC8 EACll P 2XTRQ+ 2RING 2AORC9 2RQSD+ 2ADR10 R 2CLSD+ 2CARDT 2ACRl 12RQSC+ BKSL2 S 2EN8L+ 2ENBL+ BKSL2 T EAC04 EAC1O CIACll DIAD10 U EAC05 EAC11 DICTL V H I 00 B17 1E B819 -b2C E21 122 823 H24 825 B26 B27 828 829 830 831 B32 Rill RCC2 K^C Rill RP11 R121 R121 FCC1 Rill R603 R602 R205 R2C5 R205 R2C5 A B C A B C 2GND59 2GND63 2GND61 D 2SRSV+ 2bLLCK 2T1ki)+ 2RQSD+ 2EP2 CTID1 2SCAN1 IOP4 E 2RSYN+ SCAN(- 2XlVTND 2CLSU+ 2RG+ 2PLNC 2SCAN2 2ENBLF 2Si\1. 2S\1,1ND 2CARET 2XMTND 2DTSY+ _ 2LCCK 2BLIC 2INVMK H SCNSVC 2SCAN1 2XM5IN 2XMTE- 2ENZk 2EP2 2ADAC 2eLNC 2ENBL3 2SCAN2 2STRDY 2XMTL- 2REC+ 2SRll+ ACDACC CTID2 2ENBLK 2SRSV+ 25_NlNC 2X'i1TND 2FR3+ 2IEFtD+ 2XPIT+ iBKSL2 2AXNC 2SC4A1 2ZROSR L 2XMT+ 28LGCK 2FR2+ 2FRC+ 2EXtT 2EP2 28RKDN 2BLOCK 2SCAN2 2XTRO+ M 2S\2NO SCANC+ 2DYNC 2LYND 2IF-D+ 2RD+ BKSL2 2AXNC 2AXND 2LDFR N SCNSVC 2SN2N1 FRL1+ 2CY- 2X IPC+ _2REC+ HBREAK 2RFC+ 2ENAXP 2SCA1I 2DYNC 2CY- 2XIT+ 2IFPD+ BTLC 2PARND 2ENAX- 2MBSR R 2SCAN2 2EbPC+ 2REC+ 2RECE- 2ESRSV 2PAR1 20Y+ 2RD+ IOP4 S 2SCAN3 2SN\21N 2G1Y1 2IFMD+ 2FQSC- 2XNMT+ 2RD- 2PARND 2PATY- 2ENAXT 2HERND 2SCAN1 2IF MDO+ 2CLSC- 2XTRQ+ 2REC+ 2PARNC 2LDAUX U HERE* 2SCAN2 2DYND 2ESRSV 2CARCT 2IFMU+ 2CY+ 2PAR1 V 2HERPND 2STRUY 2PATY+ 2JMP59 2CLOCK 2FR1+ 2LDAUX 2LDAUX D 2CFRO- 2CFR2- E 2FRZE 2FRZE 2PWCLR 2PWCLR F 2SVC- 2CFRO- 2CFR2- H 2GN059 2FRO+ 2FR2+ 2CFRC+ 2CFR2+ J 2FRZE 2EFRO 2GN061 BAChl BACO9 K 2PWCLR 2EFRO 2GND61 BAChl BACO9 L 2JMP59 2LDFR 2LCFR M 2FRO+ 2FR2+ 2LDAUX 2LDAUX_ N 2IFMD- 2FRI+ 2FR3+ 2CFRL+ 2CFR3+ P 2XMT- 2CFR1- 2CFR3- R 2IFMD+ 2CFR1- 2CFR3- S 2REC- 2GN060 2GND61 BAC10 BAC08 T 2RSTRT 2GND60 2GND61 BAC10 BAC08 U 2LDFR 2LDFR V TABLE II-17.

PANEL 4... PORT 2/LINE ACAPTCR 3 A' 1 A02 AC3 A4 AC 5 AO A A07 Ar8 A^9 A10 All A12 A13 A14 A15 A16 v2C 1C EIAR Rill 591 W ill RCI R32 RIll R201 R225 R20 R2'5 R2C5 R2055 R2C1 R205 A i 3 D 3SCBA E 3K Cli F 3R S3 H 3CSCL J 3SRLB K 3Tk) Yt L 3RINGbC A 3CCtE T3 P 3SCTB R 3S C <b S J V 3HiFt.3oNl,^U2 36NCC4 3GNC?2 3K1+ 3SRCt\ 3SCBF+ 3RlING H 3REC 3L INE+ 3SRCK 3CTNU1 3RING 3Rk- 3CLI1 3 I NG 3RD-' 3CL 1.53GNCC 3uLST+ _ 3PT F+ 3CSLC'S 3CNOD"4 3LIlE30EL AY 3L4 3CTN L2 3CS+ T'AL ST 3L4 3CLT1 3R C3CL- D1 3RFC30iTN)D2 3R C3RSND 3GNCC 6 RE-CER Q S L + 3GNC 6 3REC+ 3AC6JK 3A0hjK?XMTH3 ~F IX 3IFMI)+ 3XMT+ 3REC3Arc6ST 3A 6ST - 3CS+ 3GNl)r2 36FIX 3SCRB 3 S R1 _ _ _ 3STRLY 3DELAY 3 SR C Y 3SHIFT 3SHIFT 3SRO1 -3RL+ 3ZERSR BMB 1 3SRO 1+ 3ZRCSR 3SR"C3SR',C(+ 3SK I+ 3SRK3- 3iMBSR 3SH I -T 3SHIFT 3Si302+ 3RC- 3SR-2 -3MBSR HMB r2 3MB C 3SR. 1 -3SR 1+ 3MBSR 3SHIFT 3SR03 -3ZERSR MB 3 3SR03+ 3SR02 -3SR02+ 3MBSR 3SH IFT 3SR04+ 3SR04 -BMB04 3SR03 -3SRC 3+ 3MBSR 3SHIFT 3SR05 -3ZERSR BMBO5 3SR05+ 3S R 4 -3SR04+ 3M1BSR 3SHIFT 3SRO6+ 3SR06 -BMB06 3SR05 -3SR05+ 3MBSR 3S- IFT 3SR'n7 -3ZER SR EBM07 3SRC7+ 3SR'36 -3SR06+ 3MBSR 3SHIFT 3SRCe+ 3SR0EBMBn8 3SRC7 -3SRn7+ 3MBSP 3SHIFT 3SR09 -3ZERSR BMB09 3SRKO9+ 3SR08 -3SRO8+ 3MBSR 3SHIFT 3SR10+ 3SR10 -BMBlO 3SR09 -3SR09+ 3MBSR 3GND14 3SHIFT 3SHIFT 3SDBF+ 3SR10+ 3GND14 3ZERSR 3SR11+ 3SR11 -3SHIFT 3SR10 -3MBSR eMB 1 3SRl1+ 3SR 11 -3FRZE 3SHIFT 3PATY+ 3FATY3GNC14 3EP2 3EP2 3ZROSR A B C D E F H J K L M N P R S T U V 3XMI3X71P;+ 3 P S 1 3RS1 3RS1 I -d? M02 EC3 b 04 EC5: ' 6 BC7 t!0C8 B19 B10 311 1B12 B13 B14 815 B16 Ao'2 LIAR vw6C; ^1 hS5C 1 P2C2 R6C2 P602 R602 R6C2 R202 RPl7 R1C7 R121 Rill RO02 A B 13 C U F F J K L iN R S T U V -3UUT 1 31 S 0 t 3 rCS 'L+ 3UND34 '!GN [;:34 3SCTE 3 <Dt3 3 1SCTt3 3 i< iu b I 3 K C LI 3 'N 'i) 3I 3CLcLTe 3GN036 3CFDT 3S K 3CLTI 3PCCLR 3RFC3R C+ 3SRCK 3RECE 3JMP3$ 3JfP4r 3J3P41 FR 3+ 3 EXMT CCLCCK 3BRKDN '3T SY- 3ENZi 3ZERSR 3ZROSR 3PWCLR 3ZRGSR START 8PCLR 3JMP3S 3J[P4C 3JMP41 -TievY.t iCCC;.T 3V+1u1 3CDI 3V-'f 1 3V+BC 1 3GNC36 3L36 3 SC T3 3L3 7 3U?7 3L 7 3L3 7 3GND43 3SRSV+ 3RSYN3PWCLR 3CLOCK 3RSYN3SYNC- 3RSYN+ 3START 3SRSV3REC3START 3GND43 3PWCLR 3 SYNC3END 3CLOCK 3FR3+ 3SVC 3CARDT 3CDTI) 3DY+ 30Y3STCK 3S CK 3RD+ 3RDB I 3UTSY+ _..-.T. S Y _3DTSY3CS3CS+ 3ERENB 3IOPCS 3BR1 3EBPC+ BKRQ3 30TSY+ 3BKRI+ 3F1 3ENAX+ 3IFMD3ENAX- 3DTSY3ENBL+ 3ESFT 3ENBL- 30Y3ENDI 3SVC3END 3IOPCS 3HEREB 3EFRO 3HERE 3F1 3BLOCK 3SVCEKSLB 3IOPCS 3ENDI 3SROC3BRENB 3SR01 -3DSYND 3CHRDN 3SR02 -3CHRDN 3SR03+ 3IFMD- 30SYND 3REC+ 3SR04 -3DSYND 3SRC5+ 30TSY- 3DSYND 3DTSY- 3SR06+ 3SR07 -3DSYND 3HEREB 3BLOCK 3ENDI 3HERND A B C D E F H J K L M N P R S T U V 3V+HB^3 3V- '. 3 3 V+ HB3 32 3J 3C 3J I317 3PiCLR 3 LT 3XMT- 3 M37 3XMT+ 3J 3S1CK 3 3XMTE STCK XMTSRCK RECCLCCK 3CLCCK 3BRKDN 31SFT 3EXMT 3SHIFT 3MBSR 3V —C 1Cl TABLE II-18.

PAN LF- 4 PORT 2/LINE ADAFTCR 3 A17 A 18 AI A2C _ 21 A22 A23 A24 A25 A26 A27 428 A29 A3^ A31 A32 P202 R12? R123 R21 R2C1 k2C1 R2C5 R2C5 R2C5 R2 5 R123 R123 WS44 R123 Rlll A O FR_+ 3SRC+ 3 SR +C1 U 3FR3+ 3SKCC+ 3SR(6+ E 3DY- 3SRK1+ 3SRO7+ 3INVMK 3ACAC F BKSL3 6KSL3 CAC77 3CGhC1 H 3LINE- UAtBTC( DAtBT'o 3RECJ 3LINE+ iABTrCl CABrI7 3XMI+ K 3CLUCK 3SkC2+ 3SR"E+ 3F-WCLR 3FICLF L 3LINE+ 3R('C 3+ 3SR —I+ 3I1MD0+ 30B<Q+ M 3FPRE BKSL3 BKSL3 3IFFIDN 3F2 3+!)AbI t2 DA 3TCo P 3PATY- CABTC3 DAB3T'4 311\VK 3FR3+ R 3SRKO4 + 3SR1" + AC07 3IF D 3GND2C 3STARI 3GND2C 3PhCLR 3SVC3RSTRT 3REC3 X T + 3XMIT3K L C + 3INVPK JNV VK 3PWCLR 3PWCLR 3 PAR ] 3EBPC+ j PAR+ PACC6 EACC2 BAC."6 P.CC? 3CLCCK 3INVVMK?INVvK 3TMK['. 3CLST+ 3SRSVHACTY BACr HACTY EtACO ^CHP RN 3STCK 3CLSO3PWCLR 3CL SD+ 3CS3CS+ 3 NVMK 3SR SV+ 3SRSV3ESKSV SAC ^ C AC R n 3BRKKCN 3R(.SC3P CLR 3RS1 3ROSD+ 3 XTR Q+ DT1 3 I NV NK 3 X TR Q+ 3XT RL AC r. 4 '2ACC, 4 3SRSV+ 3CLST+ 3ENBL+ EAC O FAC 1 3PAR+ 3 RQSU+ 3ENBL+ EACe2 EACO 3 3XTRQ+ 3CLSD+ 3ENRL+ E AC 4 EAC '5 3ESPC+ SCAN 1+ 3CFR3+ 3[FMC+ SCANI- 3CFR2+ 3EiNeL+ SCAN2+ 3ENAX+ FAC06 SCAN2- EACE8 EACO7 SCAN3+ EACP9 3STRDY SCAN3- 3CFR1+ 3TMRU+ 3SCAN1 3CFRn+ 3ENbL+ 3SCAN2 3ENAX+ EAC08 3SCAN3 EACI: AC09 3AC4R8 EACl 3RING 3ADROC 3RQSOD 3CARDT 3ACR1' 3RQSD+ 3ENBL+ BKSL3 EAC1 0IADL11 EAAC11 DICTL 3ADR" 8 eKSL3 OIAD08 34DR09 BKSL3 I AD09 3ADR 1 tKSL3 DIAD1O A B C D E F H J K L M N P R S T U V S 3PTBtF+ 3SR(CT 5+ 3SR11+ T 13KSL3 BKSL3 U 3FK3+ IJAbTC4 CAIT 1C V 3PATY+ iDABTr'5 OLUAT11 3CLCCK 3START 3CTSY- 3 Xl T3XMT3 EC H1 317 b 18 Bi 1 82? 21 3 622 i23 E284 825 6b2o 2 7 0o28 2S B3 t31 832 R111 R:'2 Rk^n kill lkl1 h121 R121 11 26l Rll R63 R6?2 R20 25 5 R205 R2C5 A C n 3SRSV+ 3uLuCK 3TIVkUE 3:<SYi,+ SCAN:- 3XTNL F Si NDO 3SN 1N j CA: T H SCNSVL 3SCAN 1 3XM riN) J 3SCAN2 3STKCY K 3SRSV+ 3SS;l1ND 3XMITNi L 3XMT+ 3bLLCK 3FR2+ M 3S?2hN) SCANr+ 3CYNE _N SCNCVC_ 3SNi2NO 3FR1 + P 3SCLN1 3CYNL R 3SCAN2 3FBPC+ S 3SCAN3 3SN2NC 3UYN T 3HERNO 3SCAN1 3IFMD+ U HERE* 3SCAN2 3DYNl 3GND'59 3GN061) 3JIP59 3CLOCK 3 1, SU+ 3CLSu+ 3 X'MTNi 3X.1l - 3EN / 3 )X7E- 3REC+ 3FR3+ 3IIFC+ 3FRC+ EX I? CYN 3 1F FC 3CY- 3XTRC+ 3LY- 3 T + 3REC+ 3PECE3IFiDo+ 3RpSC3CLS L3ESRSV 3CaFL1 3EP2 3RD+ 3 TSY+ 3EP2 3SR11+ 3X I T+ 3 P2 3RL+ 3R (C+ 3 I F i ) + 3 ES S V 3 X MT+ 3Xl T'R + 31 F 0L)+ 3AD AC ACUACC BKSL3 3BRKDON HKSL3 d LR t A K BT1C 3PA R 1 3KC3REC+ 3CY+ 'CTCLN 2BLNC 3 dLCCK 3 LN; C TD2 3 XINC 3 6 L C K AXNC 3 EC+ 3 PAR N) 3CY+ 3PARND 3SCAN1 IOP4 3SCAN2 3ENHL3BLNC 3 INVYK 3 EN L3ENrdL3SCANh 31ZR()S 3SCAN? sXTRQ+ 3AXND -LUf-P 3 EN AX'ENAX- 3MESR 3RD+ IOP4 3PATY- 3ENAX3PAKNO 3LDIAUX 3PAR1 3SVC3GND 59 3FKRE 3PWCLR 3JMVP59 3 IFMC3XMT3 FMD+ 3REC3RSTRT 3FRZE 3CFRO3FR~+ 3EFRq 3EFRO 3LDFR 3FR1 + 3CFR1 -3GN06i0 3G(ND 6 3GNO e 3FR1+ 3FRZE 3CFR2 -3FR2+ 3GND61 3GND61 3LCFR 3FR2+ 3FR3+ 3CFR3 -3GND61 3GND 61 3LDAUX 3LDAUX 3CFRC- 3CFR2 -3PNCLR 3PWCLR 3CFRO+ 3CFR2+ BAC11 BAC09 BAC11 BAC09 3LDAUX 3LDAUX 3CFR1+ 3CFR3+ 3CFR1- 3CFR3 -BAC10 BAC08 BAC1E BAC08 A B C D E F H J K L M N P R S T U V V 3STRCY 3PATY+ 3LDFR 3LCFR TABLE 11-19.

PANEL 5 PCRT 3/LIKE ACAFTCR 4 AnI A?2 A03 A04 AC" A A_6 AtA7 AP AHO A 1 All A12 A13 AL4 A15 A16 W2CI.C EIAR R11l W.51 RPlll ROC1 R3C2 Rill 'R201 R2C5 R205 R205 R2C5 R205 R2Cl R205 A B A B 4GND14 C C 4GND02 4GND04 4GNOC6 D 4SO8 4GND02 4RD+ 4SRCK 4SCEF+ 4RECE 4RCB 4RINGB 4REC+ 4LIE+ 40TND1 4RQSD+ F 4RSB 4SRCK 4ClNC1 4REC- 4CNDC6 H 4CSOB 4RING 4RC- 4CLTI 1 40TND2 J 4SRCB 4RING 4RD- 4CLT1 4REC- 4AO6JK K 4TRDYB 4GN002 4DLST+ 4PTEF+ 4RSND 4AO6JK L 4RINGB 4CSDB 4GND04 4LINEM 4CCETE 4CDELAY 4L04 4CTrD2 4BFIX N 4CS+ DTALST 4L04 4CLT1 4IFMD+ P 4SCTe 4CS+ 4RECR 4SCRE 4CND02 4BFIX 4SCRB 4XPTS '4SRDB 4XTFH+ 4AO6ST T 4PRSN 4A06ST 4RE 4RE 4X P 4Xm:CE- 4SHIFT 4SHIFT 4SRO1 -4R0+ 4ZEKSR EC+ BMB01 4SR01+ iTE- 4ZROSR 4SROO4SROO+ 4SROO+ 4SROC- 4MBSR qT+ 4SHIFT 4SHIFT 4SR02+ 4RD- 4SR02 -4MBSR BM8B02 BMB.30 4SRO1 -4SR01+ 4MBSR 4SHIFT 4SHIFT 4SHIFT 4SHIFT 4SR03- 4SR05- 4SR07- 4SRO9 -4ZERSR 4ZERSR 4ZERSR 4ZERSR BM803 BMB05 BMB07 BMB09 4SR03+ 4SR05+ 4SR07+ 4SR09+ 4SR02- 4SR04- 4SR06- 4SR08 -4SR02+ 4SR04+ 4SR06+ 4SR08+ 4M8SR 4MBSR 4MBSR 4MBSR 4SHIFT 4SHIFT 4SHIFT 4SHIFT 4SR04+ 4SR06+ 4SRC8+ 4SR1O+ 4SR04- 4SR06- 4SR08- 4SR1OBMB04 BMB06 BMBC8 BMB10 4SR03- 4SR05- 4SR07- 4SR09 -4SR03+ 4SR05+ 4SR07+ 4SR09+ 4MBSR 4MBSR 4MBSR 4MBSR 4SHIFT 4SHIFT 4SDBF+ 4SR10+ 4GND14 4ZERSR 4SR11+ 4SRl1+ 4SRIl4SR11- 4FRZE 4SHIFT 4SHIFT 4PATY+ 4SR10- 4PATY4MBSR 4GN014 BMBlI 4EP2 4EP2 4ZROSR L M N P R S T U V D E F H J K U 4STRLY 4CELAY V 4HERE 4STRDY 4PRS1 4RSI 4BR1 3dC B02 B03 804 EC5 306 B07 BR8 809 B10 811 812 B13 814 815 B16 W602 EIAR w602 w501 W5C. 1 R202 R6C2 PR62 R6n2 P602 R202 Rl7 R107 R121 Rill R002 A B _ C 4GND34 4GN036 D 40UT1 4GND34 4SCTE 4SCK 4CCTO E 4RDB 4CDT F 4SCB 4SCTB 4SCK 4CCTD H 4RCSD+ 4RDBI J 4ROBI K 4RSB 4GND34 4L37 L.4TM.RD' 4CDETB 4GND36 4L37 M 4L36 4L37 N 4TRDYB 4CDT 4L36 4L37 P 4V+8C1 4CDT 4V+BC3 R 4V-BO1 4V-Bn3 4SCTB 4JM37 S 4V+BC1 4V+BC3 4CCT T 4JM37 U V 4V-B01 4V-BC3 4GND43 4JMP39 4JMP40 4JMP41 4SRSV+ 4CARDT 4BRENB 4IOPCS 4ENDI 4SROO4FR3+ 4RSYN- 4CDTD 4BR1 4EBPC+ 4BRENB 4SRO1 -4PWCLR 4EXMT 4PWCLR 40Y+ BKRQ4 40TSY+ 4DSYND 4REC- 4CLOCK 4BRKDN 4CLOCK 4RSYN- 4DY- 4BKRC+ 4F1 4CHRON 4SRC2 -4REC+ 4DTSY- 4ENZR 4SYNC- 4RSYN+ 4STCK 4ENAX+ 4IFMD- 4CHRDN 4SR03+ 4SRCK 4ZERSR 4ZROSR 4PWCLR 4START 4SRSV- 4SCK 4ENAX- 4DTSY- 4IFMD- 4CSYND 4RECE- 4ZROSR 4START BPCLR 4REC- 4RD+ 4ENBL+ 4ESFT 4REC+ 4SR04 -4JMP3S 4JMP4C 4JMP41 4ROBI 4ENBL- 4DY- 40SYND 4SR05+ 4START 4DTSY+ 4ENDI 4SVC- 4DTSY- 4DSYND 4STCK 4GN043 40TSY- 4END 4IOPCS 4DTSY- 4SR06+ 4PWCLR 4XMT- 4PWCLR 4CS- 4HEREB 4EFRO 4SR07 -4XMT- 4SRCK 4CLOCK 4BRKDN 4SYNC- 4CS+ 4HERE 4F1 4DSYND 4XMT+ 4REC- 4ESFT 4EXMT 4BLOCK 4SVC- 4HEREB 4STCK 4CLOCK 4SHIFT 4MBSR 4END 4CLOCK BKSLB 4IOPCS 4BLOCK 4XMTE- 4FR3+ 4SVC- 4ENDI 4HERND A B C D E F H J K L M N R S T U V TABLE II-20.

PANEL 5... PORT 3/LINE ACAFTCR 4__ __ A17 A18 AIS A2C A2 1 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 _R_2C2.R123 R123 R201 R2C1 R2C1 R205 P2C5 R205 R205 R123 R123 W394 R123 R1 A B C D 4FR3+ 4SROC+ 4SR06+ E 4DY- 4SkOI+ 4SRC7+ F BKSL4 BKSL4 H 4LINE- OABTOO DABTC6 J 4LINE+ )OABTO1 DATTC7 A B C D 4GNC 1 4GND2C 4INVMK 4 INVMK 4STCK 4BRKDN 4SRSV+ 4EBPC+ SCANl+ 4CFR3+ 4ADR08 K 4CLUCK 4SR0C2+ 4SRCE+ L 4LINE+ 4SR03+ 4SROS+ M 4FRZE BKSL4 BKSL4 N 4FR3+ DABT 2 DABTO8 P 4PATY- ALT03 OAeTC9 R 4SR04+ 4SR1C+ S 4PTBF+ 4SK05+ 4S11+ T BKSL4 BKSL4 U 4FR3+ OUAdT 4 DABT10 V 4PATY+ DABTC5 DABT11 4 1NVMK bACC7 4REC4XMT+ 4PWCLR 4 IF Dl)+ 4 IF0 -4INVMK eAC07 4CLCCK 4CTSY4XMI4REC+ 4PC4C 4START 46ND1S 4GND2C 4PWCLR 4E6PC+ 4PWCLR 4P CLR BACC6 4BKPC4 BAC ^ 4SVC4RSTKT 4INVMK 4FR3+ 4REC- 4TMRC4IFPEC- 4XMT+ 4Sl'PR- 4XMT4XfT- 4REC+ BACTY BACTY 4CLSD- 4RQSC- 4DLST+ 4[FMD+ SCAN1- 4CFR2+ BKSL4 E 4PWCLR 4PWCLR 4PWCLR 4ENBL+ 4ENBL+ SCAN2+ 4ENAX+ F 4PAR1 4RS1 EACOO EAC06 SCAN2- EAC08 DIAD08 H 4PAR+ 4CLSD+ 4RQSD+ LACO1 EACO7 SCAN3+ EAC09 J EAC02 4CS- 4XTKC- 4PAR+ 4STRDYSC.N3-_4CFR1_ 4AOR09 K EAC02 4CS+ 4XTRQ+ 4RQSD+ 4TMRD, 4SCANI 4CFRO+ BKSL4 L 4CLCCK ET1 4ENBL+ 4ENBL+ 4SCAN2 4ENAX+ M 4INVMK 4INVMK 4INVPK EAC02 EAC08 4SCAN3 EAC10 DIAD09 N 4CLST+ 4SRSV+ 4XTRQ+ EAC03 EAC09 4AIRC8 EACHl P 4SRSV- 4XTRQ- 4XTRQ+ 4RING 4ACRC9 4RQSD+ 4ADR10 R 4SRSV- 4ESRSV 4CLSD+ 4CARDT 4ACRIO 4RQSD+ BKSL4 __ S eACO1 BACI'0 HAC.4 4ENBL+ 4ENBL+ BKSL4 T EAC01 BAChC BAC04 EAC04 EAC10 DIAD11 DIAD10 U 4CHRDN 4CHRDN EAC05 EACI1 DICTL V B17 B18 I 19 2('. E21 B22 823 224 B25 B26 827 828 829 83C 831 B32 Rill RCC2 PCC1 Ril R R121 11 R121 R CC1 Rill R6q3 R602 R205 R2C5 R2C5 R2C5 A 8 C D 4SRSV+ 4BLCCK 4TPvRD+ 4RCSD+ E 4RSYN+ SCANC- 4XMTND 4CLSD+ F 4SNIND 4SN1ND 4CARCT 4XMTN _ H SCNSVC 4SCAN1 4XMThN 4XMIE- 4ENZR J 4SCAN2 4STROY 4XMTE- 4REC+ K 4SRSV+ 4SN1NL 4XMTNU 4FR3+ 4IFPD+ L 4XMT+ 4BLGCK 4FR2+ 4FRO+ 4EXIT M 4SN2NO SCANC+ 4DYNC 4CYND 4IFLC+ N SCNSVC 4SN2NC 4FRI+ 4CY- 4XTRC+ P 4SCANI 4DYNC 4CY- 4X714 R 4SCAN2 4EBPC+ 4REL+ 4RECES 4SCAN3 4SN2NU 4CYNC 4IFID+ 4FQSCT 4HERND 4SCAN1 4IFMC+ 4CLSLU HERE* 4SLAN2 4)YNC 4ESRSV 4CPR]T V 4HERND 4STPUY A B 4GN059 4GND60 4GND61 C 4EP2 CTMD1 4SCAN1 IOP4 4JMP59 4CLOCK 4FR1+ 4LDAUX 4LDAUX D 4RC+ 4ELNC 4SCAN2 4ENBL- 4CFRO- 4CFR2- E 4DTSY+ 4BLCCK 4BLND 4INVMK 4FRZE 4PRZE 4PWCLR 4PWCLR F 4EP2 4ADAC 4eLNC 4ENBL- 4SVC- 4CFRO- 4CFR2- H 4SR11+ ALDACC CThU2 4ENOL- 4CND59 4FRO+ 4FR2+ 4CFRC+ 4CFR2+ J 4XMT+ BKSL4 4AXND 4SCAN1 4ZROSR 4FRZE 4EFRO 4GND61 BAC11 BACO9 K 4EP2 48RKDN 4BLOCK 4SCAN2 4XTRQ+ 4PWCLR 4EFRO 4GN061 BAC11 BACC9 L 4RC+ BKSL4 4AXNC 4AXND 4LDFR 4JMP59 4LDFR 4LCFR M 4REC+ BBREAK 4RFC+ 4ENAX- __ __ 4FRO+ _4FR2+ 4LDAUX 4LDAUX ___ N 4If-rD+ BT1C 4PARND 4ENAX- 4MBSR 4IFMD- 4R 4FR+ 43+ 4CFR1+ 4CFR3+ P 4ESRSV 4PARL 4DY+ 4RD+ IOP4 4XMT- 4CFR1- 4CFR3- R 4XMT+ 4RD- 4PARND 4PATY- 4ENAX- 4IFMD+ 4CFR1- 4CFR3- S 4XTRQ+ 4REC+ 4PARNO 4LDAUX 4REC- 4GND60 4GND61 BAC1 BAC08 T 4IFMD+ 4CY+ 4PAR1 4RSTRT 4GND60 4GND61 BAClO BAC08 U 4PATY+ 4LDFR 4LDFR V TABLE 11-21.

APPENDIX III PDP-8/201A LINE ADAPTOR INTERFACE FOR USE WITH A PDP-8 WITHOUT USING THE DATA-BREAK FACILITY III-i

APPENDIX III TABLE OF CONTENTS Page Pseudo Data-Break Control........................ III-2 Control Gating................................... III-2 BUF Register................................... III-2 BUF Gating........................................ III-2 SDR Register...................................... III-7 Device Select Code................................ III-7 Device Selection Gating........................... III-7 Interrupt Control................................. III-11 Extended Accumulator Control..................... III-11 Accumulator Input Gating.......................... III-11 Extended Accumulator Buffers...................... III-11 Miscellaneous Circuits............................ III-16 Cable Layout...................................... III-16 Module Utilization................................ III-16 III-iii

APPENDIX III LIST OF DIAGRAMS Diagram III-1 III-2 III-3 III-4 111-5 III-6 III-7 III-8 III-9 III-10 III-11 III-12 III-13 Pseudo Data-Break Control............... Control Gating.......................... BUF Register........................... BUF Gating.............................. SDR Register............................ Device Select Code..................... Device Selection Gating................. Interrupt Control...................... Extended Accumulator Control............ Accumulator Input Gating................ Extended Accumulator Buffers............ Miscellaneous Circuits................. Cable Layout........................... Page 111-3 III-4 III-5 III-6 III-8 III-9 III-10 III-12 III-13 III-14 III-15 III-17 III-18 III-v

APPENDIX III LIST OF TABLES Table Page III-1 Buffered Accumulator Outputs............ III-19 III-2 Accumulator Inputs...................... III-20 III-3 Timing Control Signals.................. III-21 III-4 Programmed Input/Output Control......... III-22 III-5 Panel 1 - Common Section (without DataBreak).................................. 111-23 III-6 Panel 1 - Common Section (without DataBreak).................................. III-24 III-7 Panel 2 - Port O/Line Adaptor # (without Data-Break).................... III-25 III-8 Panel 2 - Port )/Line Adaptor # (without Data-Break).................. III-26 III-vii

PDP-8/201A LINE ADAPTOR INTERFACE FOR USE WITH A PDP-8 WITHOUT USING THE DATA-BREAK FACILITY The only difference between this version of the 201A communication adaptor and the basic 201A communication adaptor presented in Appendix I is that it uses a character buffer internal to the 201A line adaptor interface instead of using the data-break facility and PDP-8 core buffers. This necessitates the addition of control circuitry to transfer characters between the SDR register and this internal buffer (BUF) and additional micro-instructions to read, write, and clear BUF. The additional device code for the set of IOTs is taken to be the fourth in the set used by 201A communication adaptor (see Programming and Control Considerations). This'set of IOTs is defined as follows: Read Character Buffer (6XX1) This micro-instruction causes the contents of the 201A line adaptor character buffer to be logically ORed to the accumulator. Clear Character Buffer (6XX2) This micro-instruction causes the 201A line adaptor character buffer to be cleared. Write Character Buffer (6XX4) This micro-instruction causes the contents of the PDP-8 accumulator to be loaded into the 201A line adaptor character buffer (BUF). In order to use the same basic 201A line adaptor, the data break control signals were simulated, except that the transfer is to and from BUF instead of core. The remainder of the Appendix presents the detailed logic circuits with a brief description of their function. III-1

III-2 Pseudo Data-Break Control (Diagram III-1) Through the #BKRQ flip-flop, the line adaptor initiates the transfer to or from the SDR register from or to the BUF register. When #BKRQ is set, the direction of transfer is specified by the DICTL signal. The #BKRQ flip-flop is cleared by the first BT1 pulse after it is set. The next BT1 pulse is used to generate the #BRKDN signal which causes the reading or strobing of the BUF register. The #BRKQ flipflop is set each time the frame counter overflows while in the text state and when the line adaptor first enters the transmit state to fetch the first character to be transmitted. All of the logic in Diagram III-1 is in Bay 2 of the interface. Control Gating (Diagram III-2) The PDP-8's address-accepted signal is simulated by the ADRAC flip-flop, and the buffered-break signal is effected by the BBRK flip-flop. The sequencing through the states effected by BBRK and ADRAC is accomplished by the BT1, and BT2 pulses. The BUF register is cleared by a PDP-8 power clear signal, an explicit IOT, and by the interface before it loads the SDR register into it. The signal used to load the SDR register into BUF is READ, while LOAD is generated by the IOT used to write or load BUF from the PDP-8 accumulator. BUF Register (Diagram III-3) Diagram III-3 shows the internal buffer register. BUF Gating (Diagram III-4) Diagram III-4 shows the drivers and control gating necessary to load the BUF register into the PDP-8 accumulator.

#BRKDN B13 P #PWCLR #START T T #IFMD- #XMT ADRAC+ B23 DICTL o IVl #RQSD+ - 3 BKSL# T K Diagram III-1. PSEUDO DATA BREAK CONTROL

-B v v P2 BPCLRC I- 4 B22 IPP2 P - CTWD3 U B19 R S -V H19 1 4p M I B B20 READ BTIC IOP4C B22 I B20 I Diagram 111-2. CONTROL GATING

Diagram III-3. BUF REGISTER

ACOO AC06 BUFOO+ BUF06+ IB25 S B22 H B21 Diagram III-4. BUF GATING

III-7 SDR Register (Diagram III-5) Diagram III-5 is a revision of Diagram 1, described in the report, to reflect the loading of the SDR register from BUF instead from the buffered memory buffer. Device Select Code (Diagram III-6) The device select code is a two octal digit number which selects an external device during an input/output operation. The device code appears in positions 3 through 8 of the memory buffer during an IOT instruction, alerting the external device when it is being selected. This version of the 201A L.A. has associated with it four separate device codes as discussed above. In order to specify the four devices it is sufficient, because of the aforementioned requirements, to define only a four-bit number, which appears in positions 3-6 of the M.B. during an IOT instruction. This number must also be realized in the hardware, and this is accomplished via an R002 diode module. Thus to specify the desired set of devices codes the appropriate diodes are removed. For example, using the set 40,41,42,43, as before, the diodes connected to pins E, H, L, and P must be removed. The remainder of Diagram III-6 shows the gating necessary to obtain the signals to identify each of the devices. Device Selection Gating (Diagram III-7) The gates shown in Diagram III-7 are located in Bay 2 and provide the signals to differentiate between Control Word 1 and Control Word 2 operation.

M L E J R P E J R P E J h-q i-I I 00 Diagram 111-5. SDR REGISTER

NOTE: SELECT 1 DIODE FROM EACH PAIR FOR DEVICE CODE 1 A13 I ENBL B21 E U B121 Diagram III-6. DEVICE SELECT CODE

# F NT A Y B2! #fENAX- 13 5 #BLOCK T~~~~~~A B K L B 1 c') CTWD2 M IL -, M I B24 4 #ENBL+ #ENBL B13 IB25 CTWD1 F I B24 1 Diagram III-7. DEVICE SELECTION GATING

III-11 Interrupt Control (Diagram III-8) Every time a character is transferred between the 201A L.A. and the BUF register, a character service flag (#SRSV) is set, as described before. This flag in turn sets the appropriate flag, transmit (XINT) or receive (RINT), which causes an interrupt request. If interrupts are enabled in the PDP-8, a program interrupt is generated. Via the appropriate IOT micro-instruction, the program can identify the device causing the interrupt. The SKIP signal will be generated and a program skip forced if this IOT is executed. It is the program's responsibility to clear the interrupt after it is identified, and the remainder of the gates allow for this. Extended Accumulator Control (Diagram III-9) In order to provide the IOT structure described under Programming and Control Considerations, the extended accumulation (EAC) buss was implemented. The full power of the EAC is not realized until there are multiple devices using the buss, since it provides the mechansim for multiple inputs to the PDP-8 AC. Diagram III-9 shows the gating necessary to generate the SKIP signal on a skip under mask IOT. Accumulator Input Gating (Diagram III-10) Diagram III-10 shows the buffers which gate the EAC buss onto the AC buss. For other devices to use the EAC buss, they need provide only the appropriate input to the ENBL gate and the gates for the EAC buss. Extended Accumulator Buffers (Diagra.m III-11) Diagram III-11 shows a set of buffers necessary to accomplish the inversion to gate the EAC onto the AC. The clamped loads for the EAC buss are also indicated.

RINT+ All K IOP2 I _,- S IOP4 RINT+B13 Jw I IOP4C A12 AK 1, CTWDO KII CTWDO E AI*% /I H I IOP4C 2 D i i4- B 1 9 D Diagram 111-8. INTERRUPT CONTROL

B15 E ELVT PAC 09 n- HHSJ ( B1 4 ^ EXEDDABAC1T P CT M BAC l_ BAC lL R ~ B14 BAC10 B1 _B14 TB BAC1O r EXTNDED ACCUMULATOR cONTROL Diagram 1119.

AC06 S Diagram III-10. ACCUMULATOR INPUT GATING

I I I II I D IEACC II -I )0 - I M I F Ac 7 ' *mA^ro I I-.q -.... I EAC07 ' B16 N EACC I EAC08 B1 K - i )8 - I VI on I R' I I EAC10 I EAC10 - B I EACOS |A16 I S -- A16 B18 1 I I s 'I EAC1. — I R | EAC11 1I B|B16 B18 - 1 - Diagram III-11. EXTENDED ACCUMULATOR BUFFERS

III-16 Miscellaneous Circuits (Diagram 111-12) Diagram III-12 is best described as the left-over circuits without a logical home. Cable Layout (Diagram III-13) The input/output cables for this version of the 201A line adaptor are shown in Diagram 111-13. The correspondence between signal names, module positions, and pin connections for the 201A line adaptor and the PDP-8 are given in Tables III-1 through 111-4. Module Utilization (Tables III-5 through III-8) Tables III-5 through III-8 give the module utilization for this version of the 201A line adaptor. In addition to the module utilization, a complete signal name map is also shown (Tables III-5 through III-8).

BKSL# i BPCLR 'DICTL D 12 _ _m l2 F BPCLRC A12 H B18U Diagram 111-12. MISCELLANEOUS CIRCUITS

01 02 03 04 05 06 'A' 'B' D E F H J K L M N P R S T U V BAC00 BAC01 BAC02 BAC03 BAC04 BAC05 BAC06 BAC07 BAC08 BMBOO BMB01 BMB02 BMB03 -BMB03 BMB04 -BMB04 BMB05 -BMBOS AC00 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 01 02 03 04 05 06 D BAC09 BMB06- AC09 E BAC10 BMB06 AC10 F H BACll BMB07- AC11 J K IOP1 BMB07 SKIP L M IOP2 BMB08- INTREQ N P IOP4C BMB08 R S BT1C BMB09 T BT2A BMB10 BPCLRC BMB V BPCLRC BMB11 H. I oo Diagram III-13. CABLE LAYOUT

III-19 TABLE III-1 BUFFERED ACCUMULATOR OUTPUTS 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A01D, A02D BACOO ----- ---- BACO ME34D AO1E, A02E BACO1 ---- -— BAC1 ME34E A01H, A02H BAC02 - --- ---- BAC2 ME34H AO1K, A02K BAC03 ---- ---- BAC3 ME34K A01M, A02M BAC04 O --- --- BAC4 ME34M AO1P, A02P BAC05 ---- -— BAC5 ME34P AO1S, A02S BAC06 ---- - BAC6 ME34S AO1T, A02T BAC07 --- - BAC7 ME34T A01V, A02V BAC08 -------- BAC8 ME34V BO1D, B02D BACO9 - o BAC9 MF34D BO1E, B02E BAC10 ---- ----- BAC10 MF34E BO1H, B02H BAC11 ----------- BACll MF34H

III-20 TABLE III-2 ACCUMULATOR INPUTS 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION A05D, A06D ACOO - --- -- - ACO PE2D A05E, A06E AC01 -- --— AC1 PE2E A05H, A06H AC02 ---- > ---- AC2 PE2H A05K, A06K AC03 ---- ---— AC3 PE2K A05M, A06M AC04 - ------ AC4 PE2M A05P, A06P AC05 ----- --— AC5 PE2P A05S, A06S AC06 -------— < AC6 PE2S A05T, A06T AC07 ---- ---- AC7 PE2T A05V, A06V AC08 ---- ---- AC8 PE2V B05D, B06D AC09 ---- ---- AC9 PF2D B05E, B06E AC10 ---- ---- AC10 PF2E B05H, B06H ACll --- ---- AC11 PF2H ______________________________,_____________________________^~~~~~~~L *Note: Collector of Grounded-Emitter Transistor

III-21 TABLE III-3 TIMING CONTROL SIGNALS 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION BO1S, B02S BTIC ---- -- BBT1 MF34S B01T, B02T BT2A - — BT2A MF34T B POWER BO1V, B02V BPCLRC --— CLEAR MF34V CLEAR

III-22 TABLE III-4 PROGRAMMED INPUT/OUTPUT CONTROL 201A LINE ADAPTOR PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION *1 *1 INTERRUPT B05M, B06M INTREQ PF2M REQUEST B05K, B06K SKIP *1 SKIP PF2K BO1K, B02K IOP1 -- IOP1 MF34K BO1M, B02M IOP2 ---- -IOP2 MF34M BO1P, B02P IOP4C --- IOP4 MF34P 1._________________ _______________ ____._________ ______._______ _______,______ *Note: Collector of Grounded-Emitter Transistor.

PANEL 1.. COMMON SECTION (WITHOUT DATA BREAK) AO1 A02 A03 A04 A05 A06 A07 W)21 i4021 W_021 WOZ0 WO21 W021 A B C -O BACOO BAC03 B833 BBMB0O — C Od E BACOI BAC01 BMB01 BMBOI AC01 F H BAC02 BAC02 BMB32 BMB02 AC02 K BAC03 BAC03 BMB03- BMB03- AC03 M BAC04 BAC04 BMB03 BMB03 AC04 N P BAC05 BAC05 BMB04- BMB04- AC05 R S BAC06 BAC06 BMB04 BMB04 AC06 -T:' ---O —7 BAC 07 — BB -B05'- ACO7 U V BAC38 -BAC08 BMB05 BMB05 AC08 AC30 AC 31 AC02 AC 03 AC04 ACO5 AC06 AC07 AC38 A08 A09 A10 All A12 A13 A14 A15- A16 Rill R107 R002 a107 R141 R 107 A GNDA12 GNDA15 C -- XINT-'B-BK-SL-# B'B33- BACO)- TSTSKP EACOO- D GNDA12 BMB03 BACOO BACOO- EACOO E BPCLR SELND 3A:01- EACOO EACOI- F INTREQ BPCLRC BMB34- BACO1 BAC01- EAC01 H IOP4 B8B34 BA*02- EAC01 EAC02- J RINT+ IOP4C SEL4D BAC'02 BAC02- EAC02 K LDAC- B-MBB5- BAC EA --- EA02 AC03- L LDAC+ BMB05 BACO BAC03- EAC03 M INTREQ CTWDO SELND BAC046- EAC03 EAC04- N DEVSLO BMB36- 34-04 BAC04- EAC04 P IOP1 CTWD1 BB)35 3A405- EAC04 EAC05- R ENBL DEVSL1 SELND BAC05 BAC05- EAC05 S CTWD2 - SELDV -EAC- 5-GRPSE L T LDAC+ DEVSL2 GNDA15 SELDV U LDAC+ SELND GNOA15 V B01 B02 803 B04 B05 B36 W321 -W021 W021 W021 W021 W021 A B C D BAC39 BAC09 BMBO6- BMB06- AC09 AC39 E BAC10 BAC10 BMB06 BMB06 AC10 ACLO F F _ _._ _ _._.___. H BACi1 BAC11 BMB07- BB 07- AC1 AC11 J K IOP1 IOP1 BMB07 BMB07 SKIP SKIP L M I3P2 IOP2 BMB08- BMB08- INTREQ INTREQ N_ P 13P4C IOP4C BMB08 BM808 R S BT1C BT C BMBO09 -BMB09 T BT2A BT2A BMB10 BMB10 V BPCLRC BPCLRC BMBll BMB11 B07 B08 B09 B19 Bll B12 B13 B14 B15 B16 RIll ROO1 Rill R107 R141 R107 A B GNDB 15 C BMB07 TSTSKP IOP2 BAC06- TSTSKP EAC06- D BMB08 SKIPI ENBL BAC06 BAC06- EAC06- E DEVND3 CTWDO SKIP1 3A:07- EAC06 EAC07- F DEVSLO SKIP2 SKIP 3A:07 BAC07- EAC07 H DEVSLO CTWDO BAC08- EAC07 EAC08- J BMB07 SKIP3 XINT+ BAC08 BAC08- EAC8 K BMB08- GRPSEL IOPI BAC09- EACO8 EAC09- L DEVND1 DEVNDO SKIP2 BAC09 BAC09- EACO9 M DEVSL1 GRPSEL SKIP BAC10- EAC09 EAC13- N DEVSLI DEVND1 BACIO BAC10- EAC10 P BMB07- GRPSEL RINT+ _3411- EACO1 EAChl- R BMB08 DEVND2 IOP2 BAClH BAC1l- EACl S DEVND2 DEVSL2 SKIP3 ENBL _EAC11 BACTY T DEVSL2 ENBLND SKIP DEVSL1 GNDB15 BAC09- U DEVSL2 ENBLND GNDB15 V TABLE III-5.

PANEL I.. * COMMON SECTION (WIT4OUT DATA BREAK) A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 R123 R202 R205 R205 R205 R235 R205 R205 A 8 B C D EACOo- OP4 LOAD LOAD LOAD LOAD LOAD LOAD E EAC01- DEVSLO BUFOO- BUF02- BUF04- BUFn6- BUF08- BUF10 -F LDAC- BPCLQ CLEA: CLLEAR CLEAR CLEAR CLEAR CLEAR H ACOO #SROO- #SR02- #SR04- #SR06- #SR08- #SR1OJ AC01 XINT+ BUF03+ BUF02+'BUF04+ BUFO6+ BUF08+ BUFIO+ K EAC02- ISRSV- BACOO BAC02 BAC04 BAC06 BAC08 BACIO L EAC03- #XT- BACO- BAC0-BO2- BAC04- BAC06- BACO8- BAC03 -M LDAC- READ READ READ READ READ READ N AC02 1 OP4 LAD LOAD LOAD LOAD LOAD LOAD P AC03 OEVSLO BUF01- BUF03+ BUF05+ BUF07+ 8UF09+ BUF11+ R EAC04- BPCLR BUFD1- BUF33- BUF05- BUF07- BUF39- BUF11 -S EAC05- #SRO1- #SR03- #SR05- #SR07- #SR09- #SRI1 -T..LDAC- R I-T+ BACO1 BACO3 BAC05 BAC07 BAC09 BACll U A:04 #SRSV- BACOl- BACO3- BAC05- BAO07- BAC09- BAC11 -V AC05 #REC- READ READ READ READ READ READ WO5OS W050S # XM T+ #REC+ #SRSV+ ODLST+ #PAR+ #EBPC+ # I FM D+ #STRDY #TMRD+ #RING #CARDT A B C E F H J K L N P R S T_ U V I 4:a, B17 818 819 B20 821 B22 823 B24 B25 B26 B27 B28 329 B30 831 832 R123 W092 R11l R331 RIll R107 R202 R123 R123 A B C D EAC06- EACOO IOlP4 GRPSEL BMB07- CTWD3 BT1 BUFOO+ BUFO6 E EAC07- EAC31 CTWD3 DEVND3 BMB08- DEVSL3 A)RAC- BUF31+ B'JF3 F LDAC- EACO? #REC+ DEVND3 WRITE+ BPCLR WRITE+ WRITf H AC06 EAC03 #SRSV+ CLRND DEVSL3 WRITE- ADRAC- ACOO ACOS J AC07 EAC04 BBRK+ DEVSL3 BT1 ADRAC+ AC01 AC07 K EAC08- EAC35 BT28 REDND IOP1 BT1C BT1 BUF32+ BUFOt L EAC09- EACOS ADRAC+ #REC+ CTWD3 RT2 BKRQ# BUF03+ 8UFO< M LOAC- EAC07 CLR 4D RFDND BT2A WRITE+ WRITE N AC08 EAC08 CLEAR WRITE- CLEAR 8T2 AC02 ACOB P AC09 EAC09 WRITE- BPCLRC BBRK- AC03 - AC09 R EAC10- EAC13 IOP2 IOP4C BPCLR BUF04+ BUFI( S EACIl- EACH CTW33 CTWD3 BBRK- BUF05+ BUF11 T LOAC- DIAD11 READ BBRK+ WRITE+ WRITf U AC10 DICTL CLEAR LOAD BT1C BT2 ACO4 AC13 V AC11 _ LOAD RE3ND ADRAC- AC05 AC11 A 8 C E F H J K L N N P 1+ R L.~~~~~~~~. _ _S F= + _ _ _, _ -- - -- - - - -- ---- - - -- T U V TABLE III-6.

PANEL 2... PORT O/LINE ADAPTOR # (WITHOUT DATA BREAK) AOI A02 A03 _A04_ A5 A06 A07 A08 W201C EIAR Rill W501 Rill R001 R302 R111 A09 R201 A10 All A12 A13 R205 R205 R205 R235 A14 A15 A16 R295 R201 R205 A B C #GND02 #GND04 D SDB G DO 2 # D+ #-SCK E #RDB #R[IN8 #REC+ F #RSB #SRCK H #CSDB #RING #RDJ #SRDB #RING #RDK #TRDYB #GND 2 L #RINGB #.CSDB f. #GND04 M #CDETB #DELAY #L04 N #CS+ #L04 P #SCTB #CS+ R #SCRB IGND02 #BFIX #SCRB S #SRD3 T U #STRDY #DELAY V #STRDY #SDBF+ #L INE+ #OTND1 #OUT1 #OUT 1 P TB F+ #L I NE#0 TN 02 #OUT1 #XMT - X TRQ+ #RSND #RSI #RS1 #REC#OTND1 #REC#OTN02 #REC#RSND #GND06 #RECE#ROSD+ #GND06 #REC+ #AO6JK #A06JK #XMTE#BFIX #IFMD+ #XMT+ #REC#A06ST #A06ST #BR1 #SHIFT #SHIFT #SRO1 -#RD+ #ZERSR BUFOl#SR01+ #ZRDSR #SROO#SR33+ #SROO+ #SROO- #MBSR #SHIFT #SHIFT NSR02+ #RD- NSR02 -#MBSR BUF02 -BUF33- #SR01 -#SR1 + #MBSR #SHIFT #SHIFT #SHIFT #SHIIFT NSR03- #SR05- #SR07- #SR09 -NZERSR #ZERSR #ZERSR fZERSR BUF03- BUFO5- BJF)7- BUF09 -#SR03+ #SR05+ #SR37+ #SRO9+ #SR02- #SR04- #SR)6- #SR08 -#SR02+ -SR04+ #SR36+ OS+0B+ #MBSR #MBSR #MBSR #MBSR SHSHIFT SHIFT #SHIFT #SHIFT #SR04+ #SR06+ #SR08+ #SR10+ #SP04- #SR06- #SR38- #SR13 -BUF04- BUF06- BUF)8- BJF10 -#SR03- #SR05- #SR07- #S109 -NSR03+ #SR05+ #SRO7+ #SR09+ #MBSR #MBSR #MBSR #MBSR nGND14 #SHIFT #SHIFT #SDBF+ #SR 10+ # GND14 #ZERSR #SR11+ #SR11+ #SR11 -#SR11- #FRZE #SHIFT #SHIFT #PATY+ #SR10- #PATY#MBSR #GNDI4 BUF11- #EP2 #EP2 #ZROSR A B C D E F H J K L M N P R4 S T U V 3 1 B02 803 W602 EIAR A B C #GM034 D #3UT1 #GND34 F #RDR F #SOB H #RQSD4 #RDBI J #ROBI K #RSB #GND34 L #TMRD+ #CDETB M N #TRDYB #CDT P #V+BOL #CnT R #V-BO1 S #V+BOL T U V #V-B01 B04 B05 806 807 B08 B09 B10 B11 B12 B13 B14 B15 B16 W501 W501 R232 R602 R602 R602 R602 R202 R107 R107 R121 RIll RO02 A _-_ _ --- —------------ — A....................... A_ B #GND36 #GND43 BKSLB C #SCK #COTD #JMP39 #JMP4 1 MSRSV+ #CARDT #BRENB #IOPCS #ENDI *SROD- D #CDT #FR3+ #RSYN- #CDTD #BR1 #EBPC+ #BRENB #SR01- E #SCK #CDTD #PWCLR #EXMT #PWCLR #DY+ BKRQ# #DTSY+ #DSYND F #REC- #CLOCY #BRKDN #CLOCK #RSYN- #DY- BKRQO+ #Fi #CHRDN #SR02- H #REC+ #OTSY- #ENZR #SYNC- #STCK #ENAX+ #IFMD- #CHRDN #SR03+ J #U37 #SRCK #ZERSR #ZROSR #PWCLR #START #SRSV- #SCK NENAX- #DTSY- #IFMD- #DSYND K #GND36 #U37 #RFCE- #ZROSI #START BPLR #REC- #RD+ #ENBL+ #ESFT #REC+ #SR04- L #L36 #L37 #JMP39 #JMP40 #JMP41 #RDBI #ENBL- #DY- #DSYNO #SR05+ M #L36 #L37 #START #DTSY+ #EN3)I SVC- #DTSY- #DSYND N #STCK #GND43 #DTSY- -END #I3PCS NDTSY- #SR06+ P #SCTB #JM37 #PWCLR #XMT- #PWCLR #CS- #EFRO #SR07- R #CDT #XMT- #SRCK #CLOCK #BRKDN #SYNC- #CS+ #F1 #DSYND S #JM37 #XMT+ #REC- #ESFT #EXMT #BLOCK #SVC- T #STCK #CLOCK #SHIFT #MBSR #END #CLOCK BKSLB #IOPCS U #XMTE- FR3+ #SVC- #ENDI V TABLE 111-7.

PANEL 2... PORT O/LINE ADAPTOR # (WITHOUT DATA BREAK) A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 R202 R201 r R201 A. -B R201 R205 R205 R205 R205 R123 R123 R123 C O #FR3+ E #DYF H #LINEJ #LINE+ K #CLOCK L LINE+ M #FRZE N #FR3+ P #PATYR S #PTBF+ T #GND19 #GND20 #INVMK #INVMK #INVMK BAC07 #REC#XMT+ #PWCLR #-FMD+#IFMD #ADAC #START #GND19 #GND20 #PWCLR #PWCLR #BKRQ+ #SVC#RSTRT #FR3+ #REC#IFMD- #XMT+ #START #XMT#XMT- #REC+ #PWCLR #PWCLR #PAR1 #EBPC+ #PAR+ BAC05 BAC02 BAC06 BAC02 #CLOCK #INVMK #INVMK #TMRD+ #DLST+ #SRSVBACTY BAC01 BACTY BACO1 #CHRDN #STCK #CLSD#PWCLR #CLSD+ #CS#C S+ #I NVMK #SRSV+ #SRSV#ESRSV BACOO BAC33 #CHRDN N BRK DN #RQSD#PWCLR #RS 1 #ROSO+ #XTRQ#XTRQ+ BT1 #INVMK #XTRQ+ #XTRQBAC04 BAC04 NSRSV+ #EBPC+ #DLST+ #IFMD+ #ENBL+ #ENBL+ EACOO EAC06 EACO EAC07 #PAR+ # STRDY #RQSD+- #-TMRD+ - #ENBL+ #ENBL+ EAC02 EAC08 EAC03 EAC09 #XTRO+ #RING #CLSD+ #CARDT NENBL+ #ENB-L+ EAC04 FAC10 EAC05 EAC 11 #CFR3+ #CFR2+ #ENAX+ EAC 08 EAC09 #CFR1+ #CFRO+ #ENAX+ EAC10 EA 11 #RQSD+ #RQSD+ BKSLt-.. DIAD11 )ICTL A B C D E F H J K L M N P R S T U V #INVMK BAC07 #CLOCK #DTSY ( i. —A U #FR3+ #XMTV #PATY+ #REC+ N0 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 830 B31 B32 R301 Rill R121 R121 R121 ROO1 R1ll R603 R602 R205 R205 R235 R205 A 8 C D E F H J K L M 'N P R S #TMRD+ #RQSD+ #XMTND #CLSD+ #CARDT #XMTND #XMTND #XMTE#STRDY #XMTE#XMTND #FR3+ #FR2+ #FRO+ DOYND #DYND #FR1+ #DY#DYND #DY#EBPC+ #REC+ # YNO I FMD+ #IFMD+ #3YND #ESRSV #EP2 CT #RD+ #B #DTSY+ #E #ENZR #EP2 #ADAC #8 #REC+ #SR11+ ADRAC+ CT #IFMD+ #XMT+ BKSL# #A #EXMT #EP2 #BRKDN #E #IFMD+ #RD+ BKSL# #A #XTRQ+ #REC+ BBRK+ #R #XMT+ # IFMD+ BT1C #P #RECE- #ESRSV #PAR1 #D #RQSD- #XMT+ #RD- #P #CLSD- #XTRQ+ #REC+ #CARDT #IFMD+ #DY+ NSTRDY #PATY+ 'WD1 L ND ILOCK I ND 'WD2 NXND [LOC< kXND EC+ A RND )Y+ )ARND A B #GND59 #GND60 #GN361 C IOP4 NJMP59 #CLOCK #FR1+ #LDAUX #LDAUX 0 #ENBL- #CFRO- #CFR2- F #BLND I NVMK #FRZE #FRZE #ZPWCLR #PWCLR F #ENBL- #SVC- #CFRO- CFO- FR2- - H --- —------ #ENBL- #GND59 #FRO+ #FR2+ #CFR3+ #CFR2+ J #ZROSR NFRZE #EFRO #GN)61 BAC1 BACO9 K #XTRQ+ #PWCLR #EFRO #GND61 BAC11 BACO9 L #AXND #LDFR #JMP59 #LDFR #LDFR M #ENAX- aFRO+ _ FR2+ #LDAUX #LDAUX N #ENAX- #MBSR #IFMD- #FR1+ NFR3+ CFR+ #CFR3+ P NRD+ IOP4 #XMT- #CFL1- #CFR3- R #PATY- #ENAX- NIFMD+ FR- CFR3- S #PARND #LDAUX #REC- #GND60 #G'061 BAC13 BACOB T #PAR1 #RSTRT #GND60 NGN361 3AC10 BAC08 U #LDFR #LDFR _ _____ T U V TABLE 111-8.

Unclassified [ Secunty Classification DOCUMENT CONTROL DATA R&D (Security classification of title, body of abstract and indexing annotation must be entered when the overall report is classified) 1 1. ORIGINATING ACTIVITY (Corporate author).a. REPORT SECURITY C,ASSIFICATION Unclassified THE UNIVERSITY OF MICHIGAN CONCOMP PROJECT 2b GROUP 3. REPORT TITLE A 201A DATA COMMUNICATION ADAPTOR FOR THE PDP-8: PRELIMINARY ENGINEERING DESIGN REPORT 4. DESCRIPTIVE NOTES (Type of report and inclusive dates) Technical Report 5. AUTHOR(S) (Last name, first name, initial) WOOD, David E. 6. REPO RT DATE 7,. TOTAL NO. OF PAGES 7b. NO. OF REFS February 1968 134 8a. CONTRACT OR GRANT NO. 9a. ORIGINATOR'S REPORT NUMBER(S) DA-49-083 OSA-3050 b. PROJECT NO. Memorandum 15 | c. | 9b. OTHER RE PORT NO(S) (Any other number that may be assigned this report) d. 10. AVAILABILITY/LIMITATION NOTICES Qualified requesters may obtain copies of this report from DDC. 11. SUPPLEMENTARY NOTES 12. SPONSORING MILITARY ACTIVITY Advanced Research Projects Agency I 13. ABSTRACT This report discusses the design and use of equipment built for data communication to and from a PDP-8 through a 201A data set. The purpose of the data communication interface is to allow a PDP-8 to send and receive digital data through a 201A data set in half-duplex mode. Basic design objectives and decisions are described first. A brief overall system description together with a sketch of a data format scheme and programming considerations is followed by a detailed description of the interface logic. I 0 DD DFOR, 1473,D D I JAN'64 Unclassified Security Classification

Unclassified Security Classification L! 14. LINK A LINK B LINK C KEY WORDS ROLE WT ROLE WT ROLE WT Data Communication Logical Design Data Transmission Serial Synchronous Data Transmission Digital Computer Interface INSTRUCTIONS 1. ORIGINATING ACTIVITY: Enter the name and address of the contractor, subcontractor, grantee, Department of Defense activity or other organization (corporate author) issuing the report. 2a. REPORT SECURITY CLASSIFICATION: Enter the overall security classification of the report. Indicate whether "Restricted Data" is included. Marking is to be in accordance with appropriate security regulations. 2b. GROUP: Automatic downgrading is specified in DoD Directive 5200. 10 and Armed Forces Industrial Manual. Enter the group number. Also, when applicable, show that optional markings have been used for Group 3 and Group 4 as authorized. 3. REPORT TITLE: Enter the complete report title in all capital letters. Titles in all cases should be unclassified. If a meaningful title cannot be selected without classification, show title classification in all capitals in parenthesis immediately following the title. 4. DESCRIPTIVE NOTES: If appropriate, enter the type of report, e.g., interim, progress, summary, annual, or final. Give the inclusive dates when a specific reporting period is covered. 5. AUTHOR(S): Enter the name(s) of author(s) as shown on or in the report. Enter last name, first name, middle initial. If military, show rank end branch of service. The name of the principal author is an absolute minimum requirement. 6. REPORT DATE; Enter the date of the report as day, month, year; or month, year. If more than one date appears on the report, use date of publication. 7a. TOTAL NUMBER OF PAGES: The total page count should follow normal pagination procedures, ire., enter the number of pages containing information. 7b. NUMBER OF REFERENCES Enter the total number of references cited in the report. 8a. CONTRACT OR GRANT NUMBER: If appropriate, enter the applicable number of the contract or grant under which the report was written. 8b, 8c, & 8d. PROJECT NUMBER: Enter the appropriate military department identification, such as project number, subproject number, system numbers, task number, etc. 9a. ORIGINATOR'S REPORT NUMBER(S): Enter the official report number by which the document will be identified and controlled by the originating activity. This number must be unique to this report. 9b. OTHER REPORT NUMBER(S): If the report has been assigned any other report numbers (either by the originator or by the sponsor), also enter this number(s). 10. AVAILABILITY/LIMITATION NOTICES: Enter any limitations on further dissemination of the report, other than those I imposed by security classification, using standard statements such as: (1) "Qualified requesters may obtain copies of this report from DDC." (2) "Foreign announcement and dissemination of this report by DDC is not authorized." (3) "U. S. Government agencies may obtain copies of this report directly from DDC. Other qualified DDC users shall request through (4) "U. S. military agencies may obtain copies of this report directly from DDC Other qualified users shall request through PJ (5) "All distribution of this report is controlled. Qualified DDC users shall request through,P b If the report has been furnished to the Office of Technical Services, Department of Commerce, for sale to the public, indicate this fact and enter the price, if known. 11. SUPPLEMENTARY NOTES: Use for additional explanatory notes. 12. SPONSORING MILITARY ACTIVITY: Enter the name of the departmental project office or laboratory sponsoring (paying for) the research and development. Include address. 13. ABSTRACT: Enter an abstract giving a brief and factual summary of the document indicative of the report, even though it may also appear elsewhere in the body of the technical report. If additional space is required, a continuation sheet shall' be attached. It is highly desirable that the abstract of classified reports be unclassified. Each paragraph of the abstract shall end with an indication of the military security classification of the information in the paragraph, represented as (TS), (S), (C), or (U). There is no limitation cn the length of the abstract. However, the suggested length is from 150 to 225 words. 14. KEY WORDS: Key words are technically meaningful terms or short phrases that characterize a report and may be used as index entries for cataloging the report. Key words must be selected so that no security classification is required. Identifiers, such as equipment model designation, trade name, military project code name, geographic location, may be used as key words but will be followed by an indication of technical context. The assignment of links, rules, and weights is optional. I I GPO 886-551 Security Classification

UNIVERSITY OF MICHIGAN III3 9011 03lll27 484l 3 9015 03527 4854