Self-aligned-gate heterostructure field-effect transistors: Process development and device comparison.
dc.contributor.author | Lee, Ru-Liang | en_US |
dc.contributor.advisor | Terry, Fred L., Jr. | en_US |
dc.date.accessioned | 2014-02-24T16:17:23Z | |
dc.date.available | 2014-02-24T16:17:23Z | |
dc.date.issued | 1993 | en_US |
dc.identifier.other | (UMI)AAI9409748 | en_US |
dc.identifier.uri | http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:9409748 | en_US |
dc.identifier.uri | https://hdl.handle.net/2027.42/103802 | |
dc.description.abstract | A complete process for fabricating self-aligned, WSi$\sb{\rm x}$ gate field-effect transistors was developed to produce high-performance enhancement-mode devices for logic applications. Field-effect transistors (FETs) with different doping schemes in the insulator layer were designed for comparison purposes. The composition of WSi$\sb{\rm x}$ was found to be critical to having a high and thermally-stable gate Schottky barrier for FET operation. A Si/W ratio of 0.3 produces the highest Schottky barrier height (0.688 eV) on InAlAs after rapid-thermal annealing (RTA) at 750$\sp\circ$C for implanted-ion activation. The film composition is very sensitive to sputtering conditions and any small deviation from this optimal value will lead to deterioration of the Schottky barrier. WSi$\sb{\rm x}$ features as small as 0.18 $\mu$m with an aspect ratio of 6 were etched using reactive-ion etching processes in NF$\sb3$-containing plasmas for gate pattern definition. Silicon nitride gate sidewall spacers were fabricated by anisotropically etching a $\rm Si\sb3N\sb4$ film conformally deposited around the gates by plasma-enhanced chemical vapor deposition. The addition of spacers was found to be essential for device operation. Enhancement-mode heterostructure insulated-gate FETs (HIGFETs) $(V\sb{\rm th}$ = 0.115 V) and modulation-doped FETs (MODFETs) $(V\sb{\rm th}$ = 0.01 V) were fabricated. Extrinsic transconductances of 299 mS/mm and 337 mS/mm were observed on 1.25-$\mu$m HIGFETs and MODFETs, respectively. The HIGFET had an $f\sb{T}$ of 15.5 GHz and an $f\sb{\rm max}$ of 8.5 GHz. The $f\sb{T}$ was 21 GHz and the $f\sb{\rm max}$ was 12.5 GHz for the MODFET. Measurements on Hall transistors indicated that both devices have similar electron transport properties. It is believed that the MODFETs had better overall performance as a result of higher peak electron concentrations in the channel. A one-dimensional numerical model with a built-in thermionic-emission current routine for calculating gate leakage current was constructed to solve Poisson's equation, the Schrodinger equation, and current continuity equation self-consistently. The agreement between experimental results and theoretical prediction was excellent. | en_US |
dc.format.extent | 134 p. | en_US |
dc.subject | Engineering, Electronics and Electrical | en_US |
dc.title | Self-aligned-gate heterostructure field-effect transistors: Process development and device comparison. | en_US |
dc.type | Thesis | en_US |
dc.description.thesisdegreename | PhD | en_US |
dc.description.thesisdegreediscipline | Electrical Engineering | en_US |
dc.description.thesisdegreegrantor | University of Michigan, Horace H. Rackham School of Graduate Studies | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/103802/1/9409748.pdf | |
dc.description.filedescription | Description of 9409748.pdf : Restricted to UM users only. | en_US |
dc.owningcollname | Dissertations and Theses (Ph.D. and Master's) |
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