Circuit Techniques for Power Management Unit and Switched Capacitor DC-DC Converter.

Abstract

Efficient power management unit, efficient power conversion and energy efficient processor design have become important in the era of the Internet of Things (IoT), more than in the past, to address limited battery lifetime issue, which is mainly attributed to volume constraints and untethered property of IoT devices. In this work, such challenges have been tackled with the following solutions: ultra-low-power power management unit, ambient energy harvesting unit, and fully-integrated voltage down-conversion via switched-capacitor (SC) DC-DC converters. In the proposed ultra-low-power power management unit design, fully-integrated switched-capacitor-based power management unit (PMU) with self-adaptive conversion ratio for ultra-low power sensor platform was designed, and tested with a variety of harvesting energy sources such as solar, microbial fuel cell, and thermal energy sources. Also, in an attempt to reduce GIDL current that worsens leakage of sleep transistor with high input voltage of ~ 4V, reconfigurable sleep transistors were proposed. It was demonstrated that the reconfigurable sleep transistors are effective in reducing leakage in the domain where GIDL is dominant over subthreshold leakage. To achieve a wide range of output generation in fine-grained conversion ratio resolution, successive-approximation SC converter was proposed, and power conversion efficiency and SC converter losses were studied for a variety of topologies. Also, for output voltage ripple minimization of SC converter, on-chip flying-capacitance-dithering technique was proposed, and relation of ripple and power conversion efficiency was studied to highlight the benefits of small output voltage ripple. The last contribution made in this work is low-power configurable deep learning co-processor design. For the energy efficient and low power operation, a deep learning processor utilizing the following techniques was proposed and investigated: (1) non-uniform memory architecture (NUMA), (2) temporal and spatial locality, (3) weight matrix tiling, (4) variable data precision, variable multiplier width, and long one line of memory, and (5) energy-efficient data flow.