Circuit and microarchitectural techniques for processor on -chip cache leakage power reduction.

Abstract

On-chip L1 and L2 caches dissipate a sizeable fraction of the total power of processors. As feature sizes shrink and threshold voltages decrease, sub-threshold leakage is becoming the dominant component of this power consumption. In this study we examine various circuit and microarchitectural techniques for low-leakage on-chip caches, designed with nano-scale complementary-metal-oxide semiconductor (CMOS) technologies. First, a low-leakage circuit technique using dynamic voltage scaling for static random access memory (SRAM) is proposed. It is based on an SRAM cell that can be placed in a low power drowsy state. In a projected 70nm technology, the drowsy state reduces memory cell leakage power by 96% and has a fast wake-up to the active state of one or two cycles. Second, microarchitectural techniques for controlling L1 data caches are presented. They cut the leakage power of large data caches by putting the cold cache lines into a drowsy mode. The drowsy data cache is able to reduce the leakage energy by 75% without affecting performance by more than 0.6%. Third, the drowsy cache concept is extended to reduce the leakage power of instruction caches. Our results show that data and instruction caches require different control strategies to be effective. Furthermore, to reduce the bit-line leakage through the access transistors in drowsy caches, a predictive gated precharge is proposed. The combination of these two techniques reduces the leakage power by 72% with negligible (0.3%) run-time increase. Finally, we show that larger than normal slow L2 caches with high V_TH's, or smaller than normal leaky (low V_TH) L1 caches result in lower power two level cache systems, that leave the average access time unchanged: size can be traded for power in an unintuitive fashion. In summary, this study focuses on microprocessor on-chip caches designed with future technologies. We show that to effectively control leakage power with a minimum processor performance impact, it is necessary to consider both the circuit and microarchitecture simultaneously.