Circuits and Techniques for Cell-based Analog Design Automation in Advanced Processes

Abstract

Despite large advances in design automation of digital circuits to match the advance of Moore’s law, Analog design techniques have remained relatively unchanged. Recently, cell-based methodologies leveraging digital place and route tools have been explored in order to accelerate the design of common analog circuit blocks, such as Phase Locked Loops (PLLs). However, to date these designs have been implemented in older process nodes, and have otherwise failed to target the needs of the high speed processors which dominate the semiconductor industry. This thesis examines that state of cell-based analog design automation, and presents new techniques which will enable this approach to be used for analog blocks high speed processors. First, analytical modeling was performed for cell-based oscillators, removing the ad hoc circuit design process and enabling the number of iterative to design cycles to be drastically reduced. Additional circuit techniques which can be leveraged in cell-based PLLs were explored and two prototypes were implemented. In the first, a cascaded fast locking frequency generation circuit was created in a 28nm SOI process. This achieves fractional-N operation using an innovative controller, and design leverages binary search for fast locking. In the second, a 5GHz wide-bandwidth PLL for processor clocking was created in a 14nm FinFET process. This design achieves the widest output frequency range among synthesized PLLs. Finally, this design approach was extended to implement a phase interpolator for a clock and data recovery (CDR) circuit, enabling a fully synthesized CDR.