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Reduced-Memory Direct Digital Frequency Synthesizer Using Parabolic Initial Guess

dc.contributor.authorSodagar, Amir M.en_US
dc.contributor.authorLahiji, G. Roientanen_US
dc.contributor.authorAzarpeyvand, Alien_US
dc.date.accessioned2006-09-11T14:14:19Z
dc.date.available2006-09-11T14:14:19Z
dc.date.issued2003-02en_US
dc.identifier.citationSodagar, Amir M.; Lahiji, G. Roientan; Azarpeyvand, Ali; (2003). "Reduced-Memory Direct Digital Frequency Synthesizer Using Parabolic Initial Guess." Analog Integrated Circuits and Signal Processing 34(2): 89-96. <http://hdl.handle.net/2027.42/44067>en_US
dc.identifier.issn0925-1030en_US
dc.identifier.issn1573-1979en_US
dc.identifier.urihttps://hdl.handle.net/2027.42/44067
dc.description.abstractBased on the parabolic approximation, which was recently introduced by the authors, a new architecture for sine-output direct digital frequency synthesizers has been developed. Due to using this approximation, and also considering several memory-reduction techniques, the proposed architecture is so designed that needs only 728 bits read-only memory for mapping a 12-bit phase address to 10-bit sine amplitude. The synthesizer has also been implemented and the experimental results show its desired operation and performance.en_US
dc.format.extent161300 bytes
dc.format.extent3115 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypetext/plain
dc.language.isoen_US
dc.publisherKluwer Academic Publishers; Springer Science+Business Mediaen_US
dc.subject.otherEngineeringen_US
dc.subject.otherElectronic and Computer Engineeringen_US
dc.subject.otherSignal, Image and Speech Processingen_US
dc.subject.otherCircuits and Systemsen_US
dc.subject.otherFrequency Synthesizersen_US
dc.subject.otherDirect Digital Frequency Synthesis (DDS)en_US
dc.subject.otherParabolic Approximationen_US
dc.titleReduced-Memory Direct Digital Frequency Synthesizer Using Parabolic Initial Guessen_US
dc.typeArticleen_US
dc.subject.hlbsecondlevelElectrical Engineeringen_US
dc.subject.hlbtoplevelEngineeringen_US
dc.description.peerreviewedPeer Revieweden_US
dc.contributor.affiliationumEECS Dept., University of Michigan, Ann Arbor, MI, 48109en_US
dc.contributor.affiliationumEECS Dept., University of Michigan, Ann Arbor, MI, 48109en_US
dc.contributor.affiliationumEECS Dept., University of Michigan, Ann Arbor, MI, 48109en_US
dc.contributor.affiliationumcampusAnn Arboren_US
dc.description.bitstreamurlhttp://deepblue.lib.umich.edu/bitstream/2027.42/44067/1/10470_2004_Article_5110886.pdfen_US
dc.identifier.doihttp://dx.doi.org/10.1023/A:1021924700255en_US
dc.identifier.sourceAnalog Integrated Circuits and Signal Processingen_US
dc.owningcollnameInterdisciplinary and Peer-Reviewed


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