(2 -- - l j Design and Analysis of RFIC Subharmonic Double Balanced Mixers for Direct Conversion Applications by Kiran Nimmagadda A A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophv (Electrical Engineering) in The University of Michigan 2002 RL-1009 = RL-1009

~ Kiran Nimmagadda 2002 All Rights Reserved

To my amma and nanna, Usha Kumari and Subba Rao Nimmagadda ii

ACKNOWLEDGEMENTS I would like to thank everybody who helped me through my graduate studies at the University of Michigan. First and foremost. I would like to thank Professor Gabriel Rebeiz for being an outstanding advisor and a source of inspiration. At the end of my masters program in VLSI, I wanted to concentrate my further studies on analog circuit design and Professor Rebeiz was instrumental in convincing and supporting me to be the first student to do RFIC work at Michigan. This meant a lot of learning the hard way. but I would not trade the experience for anything. I would also like to thank Professor Achilleas Anastasopoulos. Professor Michael Flynn and Professor Amir Mortazawi for serving on my thesis committee. This work was supported by funding and support from the U.S. Army Research Office. Maxim Integrated Products and Conexant. Very many thanks to all the friends and colleagues in the TICS group for their friendship. support and camaraderie: Bernhard Schoenlinner. Jad Rizk. Jose Cabanillas. Laurent Dussopt. Matt Straayer. Guan Leng Tan. Jeremy Muldavin. Abbas Abbaspour-Tamijani. It was a great pleasure interacting with the "younger" students and I wish them the best in their grad school careers: Michael Chang. Tim Hancock. Helena Chan. Bryan Hung. Phill Grajek and Kamran Intesari. Thanks are also due to colleagues and classmates from my VLSI days who inspired me and taught me a lot: Afzal Mlalik. Arvind Salian. Alejandro Gonzalez. Mahesh Kumashikar and Mavukh Bhattacharva. Good friends are life's treasure and 1 am thankful for being fortunate to have had a few good ones along the way here at Michigan: Kareemullah Khan, Vijay Namsivavam. Abishai Daniel. Supriva Goverd-hanam. Ravikiran Sangras, Raju Saripalli. I iii

hope I have not missed anyone. A big hearty thank you goes to my cousin Lalitha's family, the Bhogineni's:.l(han. Lalitha. Lekha and Shvam - for their support. love and providing a home away. from home whenever I needed to get away from the hectic grad student life in Ann Arbor. Lalitha and Mohan's excellent home-made south Indian cooking is very much appreciated too. Thanks also to the tax-payers of India (sadly. there are too few of them in a country of a billion people) for subsidizing my world-class undergraduate education at the Indian Institute of Technology, Madras, for which I paid about $50 in tuition each year. I would not be here without that foundation. Finally. I would like to thank my parents, Usha Kumari and Subba Rao and my brother Sirish for being there from the beginning of it all. I could not have done this without their all-embracing and unconditional love and support. My parents instilled a love of learning and education in me and provided me the opportunities and freedom to pursue it - they will forever have my profound gratitude for that. iv

9MISSIN

TABLE OF CONTENTS D ED ICATION.................................. ii ACKNOWLEDGEMENTS......................... iii PREFACE.......................................... LIST OF TABLES................................. viii LIST OF FIGURES............................. ix CHAPTERS 1 INTRODUCTION............................. 1 1.1 Direct Conversion Receivers................... 1 1.2 Thesis Overview............................ 4 2 SUBHARMONIC MIXERS..................... 5 2.1 Recent research in subharmonic mixing.............. 3 SUBHARMONIC DOUBLE BALANCED MIXER: ANALYSIS................................ 12 3.1 Introduction........................12 3.2 Qualitative Description of the SDBMN.............. 12 3.3 DC Transfer Function of SDBMI................ 15 3.4 Gain of the SDBMI......................... 19 3.5 Distortion Performance of the SDBMI.......... 22 3.6 Noise Analvsis of the SDBM................. 23 3.7 Balanced Doublers........................ 23 4 SUBHARMONIC DOUBLE BALANCED MIXER: DESIGN 25 4.1 Introduction........................... 25 4.2 Comparison of SDBMI versus Frequency Doubler -Gilbert Cell Mixer............................ 26 4.3 Comparison Simulation Results................... 28 4.3.1 LO Feedthrough due to Coupling........... 28 vi

4.3.2 Noise Figure........................ 4.3.3 Two-Tone Test...................... 4.3.4 Power Consumption and Chip Area........... 4.4 Test &- Measurement Results of SDBM in Maxim Process.. 4.5 SDBM Circuit Design in Conexant 0.35/p BiCMOS Process 4.5.1 Mixer Core Design.................... 4.5.2 LO path design..................... 4.5.3 Bias Circuit Design................... 4.6 Test &- Measurement Results.................. 4.6.1 Deviation of Measured Results from Simulated Results 4.7 Balanced Frequency Doubler Circuit Design.......... 4.8 Balanced Frequency Doubler Test & Measurement Results. 34 34 36 37 37 38 40 41 44 50 52 55 5 IMPROVING SDBM LINEARITY.......... 5.1 Introduction..................... 5.2 Linearizing the RF Section............. 5.3 Design of Linear Subharmonic Mixers....... 5.3.1 Linear SDBM design............ 5.3.2 Transformer-based Linear SDBM Design 5.3.3 CMOS Subharmonic Mixers........ 5.4 Linear SDBM Analysis............... 5.4.1 DC Transfer Function.................. 58..... 58...... 59........ 6 1........ 6 1...... 65........ 69.... 69........ 69....... 72 —,............. I. 79 5.4.2 5.4.3 5.4.4 Noise Performance of Linear SDBM.. Linearity Performance of Linear SDBM Device Mismatch Effects........ 6 CONCLUSIONS AND FUTURE WORK..... 6.1 nth Harmonic Mixers............... 6.2 CMOS Subharmonic Mi-:ers........... 6.3 Active Quadrature LO Generation........ BIBLIOGRAPHY......................... 82 82 83 85 87 vii

CHAPTER 1 INTRODUCTION Over the past decade there has been a major interest in the design and manufacture of silicon based integrated circuits for communications applications. These applications include wireless communication systems such as cellular telephones. cordless telephones. global positioning systems etc., and wireline communications such as analog and digital broadcast television tuners, cable telephony etc. One of the overriding concerns in the development of these radio frequency integrated circuits has been the drive towards lower cost. lower power and smaller size solutions with adequate performance. Consequently, there has been substantial research interest in migrating from the traditional super-heterodyne receiver architecture for communication applications to the direct conversion receiver architecture. 1.1 Direct Conversion Receivers Traditionally, most wireless systems have used the superheterodyne receiver architecture (Fig. 1.1) where the incoming radio frequency (RF) signal is first downconverted to an intermediate frequency. filtered there and then downconverted to the 1

baseband where the information in the incoming signal is processed. This dual (or multiple) downconversion of the RF signal is venr useful in improving the receiver sensitivity and the IF filtering helps in solving the image problem. The IF filters are verv hard to integrate on a silicon IC in today's semiconductor technology and are a major impediment to integrating the entire receiver onto a single chip. One of the solutions is to use a direct downconversion receiver architecture (Fig. 1.2). where the incoming RF signal is downconverted directly to the baseband. This eliminates the need for the use of expensive off-chip filters, but has its own set of problems that need to be solved in order for the direct downconversion architecture to be useful in commercial applications. Diplexer/Filter LNA Mixer IF filter IF Amp Mixer2 IF2 filter Demodulation and Baseband _ Processing LO ([ L02[ c Figure 1.1: Super-heterodyne receiver architecture. One of the main problems with the direct downconversion receiver architecture is the problem of local oscillator (LO) self mixing, resulting in a time-varying DC offest at the mixer output. As seen in Fig. 1.3. the in-band LO signal leakes and radiates into the RF front-end, and mixes back with the LO signal creating a dc offset at the mixer output. The LO signal which is reflected from the RF front-end varies with the antenna load, and therefore the DC offset is time varying. Since the IF amplifier 2

Low Freq Diplexer/Filter LNA Low Pass Baseband Filter and - < i< Ks S e -Demodulation Baseband _ Processing LO Figure 1.2: Direct conversion receiver architecture. goes down to L)C in direct-conversion receviers and has a lot of gain, the time varying DC-offset will easily saturate the IF amplifier and render the system useless. RF -- signal+: dcLo(t)+dcj,, leakage & radiationr LO Figure 1.3: LO self mixing causes constant and time-varying dc offset. On the other hand. if the LO signal is out-of-band and the mixing is performed with a harmonic of the LO signal (for example, fI = — fRF-2fLo or fIF = fRF-3fLo), the result of the LO self-mixing will not be at DC and can be filtered at the IF output with a small capacitor. Subharmonic mixers accomplish this precisely Subharmonic 3

mixers also allow the use of lower frequency LO signals and ease the phase noisc requirement on the VCO's when compared to fundamental frequency mixing. At the time of writing this thesis. there is quite some research being done in lowIF receivers which combine the benefits of the direct conversion architecture and the classical superheterodyne architecture [6].[7]. 1.2 Thesis Overview This thesis presents a novel subharmonic double balanced mixer (SDBMI topology that can be used in direct conversion receivers [8]. Chapter 2 presents previous research in subharmonic mixing and compares and contrasts passive mixers - which are the major form of most previous subharmonic mixer implemenations. versus active mixers - which are relatively rare and a much recent form of subharmonic mixer implementations. Chapter 3 presents the crux of this thesis and includes a qualitativ e description of the SDBM topology, analytical expressions for DC performance. analvsis for linearity and noise performance, and generalization of the second-harmonic mixer topology to nth-harmonic mixer topology. The basic idea used in the SDBM is also shown to be useful for designing balanced doublers. Chapter 4 presents the design of a 1.9 GHz subharmonic mixer in SiGe bipolar technology, and presents the measurement results. The measured results of a balanced doubler are also shown. Chapter 5 presents a more linear version of the SDBI. Simulation results are presented for two different designs that improve the linearity of the mixer compared to the SDBMI design presented in chapter 4. Chapter 6 includes concluding remarks and future work. 4

CHAPTER 2 SUBHARMONIC MIXERS 2.1 Recent research in subharmonic mixing Subharmonic mixers in the microwave circuits field have been prevalent for a couple of decades now. It is possible to get subharmonic mixing even in the regular diode mixer by using the appropriate local oscillator (LO) filter and taking advantage of the nonlinear response of a well-pumped diode. However, in such mixers the mixing response at the fundamental frequency of the LO is greater than the mixing response at the second harmonic of the LO, and is a source of interfering signals and downconverted LO noise [9]. The fundamental mixing response is also an additional loss mechanism. since a large portion of the RF input power is converted to mixing frequencies near the LO and is radiated from the LO port. Hence, single diode mixers are rarely used in low-noise receivers. A better way to accomplish subharmonic mixing is to use an anti-parallel diode pair (APDP) as shown in Fig. 2.1. By using the anti-parallel diode pair. one of the diodes conducts during the positive half-cycle of the LO. and the other diode conducts during the negative half-cycle of the LO signal. As a result. the conductance 5

waveform of the APDP will have a fundamental frequency of twice the frequency of the LO signal. By applying the RF signal to this APDP. mixing is achieved with twice the LO frequency. Several papers [10],[11] have used this technique recently for using a subharmonic mixers in receiver designs. RF RF I F D1 D2 L^ LO Figure 2.1: APDP structure for subharmonic mixing. The APDP technique can be extended to diode ring mixers too. Diode ring mixers are balanced mixers since they eliminat the LO signal at the IF port without any special filters. Recent published results[12],[1],[13] use this technqiue to implement balanced subharmonic mixers for use in direct conversion receivers. Fig. 2.2 shows the implementation used by Matinpour et al. in [1]. All the mixers based on the APDP structure are passive mixers and just rely on the diodes to act as switches for the LO signal. Therefore. there is no amplification for the RF signal. Consequentiy, passive mixers (both fundamental and subharmonic) have a conversion loss from the RF port to the IF port. typically around 6 to 7 dB at 1-5 GHz. The most common active mixer is the Gilbert double balanced mixer which provides conversion gain in the mixing process. There has been some work recently 6

RF II II! Figure 2.2: APDP structure used in recent implementations of subharmonic mixers (after [1]). which modifies the basic Gilbert cell mixer to perform subharmonic mixing. Yamaji et al. [2] used the emmiter-coupled transistor pair (ECP) to perform harmonic mixing as shown in Fig. 2.3. The ECP has a limiting transfer charactersitic with odd symmetry, and a large signal applied to the base input results in a rectangular wave at the collector output. When the RF signal is superposed with the large LO signal at the input, the output rectangular wave is pulse-width modulated by the RF signal and results in harmonic mixing. The work in [2] uses two ECP's in a balanced fashion to implement a balanced harmonic mixer to result in no LO leakage at the IF output (ideally). Sheng et al. [3] employ a "two-level" LO switching core in place of the LO swtching quad in the standard Gilbert cell mixer. as shown in Fig. 2.4. The two levels in the LO core are driven by differential LO signals which are in quadrature with respect to each other. These two levels of switching effectively double the LO frequency if the

Vcc iR] R X Vout T Tl JTr Tr4 i, - Tr2 I!, JTr3 4Tr4 RF_~'?Vbfl! Vbizs6 LLO re Figure 2.3: Balanced harmonic mixer using emitter coupled pairs (after [2]). switching phases are offest by 90~. The above idea of using the quadrature LO for subharmonic mixing is very similar to the subharmonic double balanced mixer (SDBM) presented in this thesis. The main difference is the use of a "one-level'' LO switching core as shown in Fig. 2.5. By eliminating the second level in the switching core. this implementation of the mixer can be operated down to a power supply voltage of 1.5-2 V. Lee et al. [41 extend the idea above to use a multiple phase lower frequency LO signal to accomplish harmonic mixing. They propose a multiphase reduced frequency conversion (MPRF) technique in which the effect of mixing with a single-phase highfrequency signal can be obtained by multiplying by a set of multi-phase reduced frequency signals. The 12-phase downconversion mixer used to obtain mixing with the third harmonic of the LO is shown in Fig. 2.6. The above summary shows that subharmonic and nth-harmonic mixers are an 8

*^ 0 Q ll. I 14 tL Wb Figure 2.4: Subharmonic mixer with a two-level LO switching stage (after [3]). active area of research for RFIC receivers, and this thesis presents a novel low-voltage implementation. It is believed that the results presented in this work are state-ofthe-art and very competitive with other approaches. 9

RL RL I+ Vou - ---------- 'Ibi I u Figure 2.5: Simplified schematic of the novel Subharmonic DoubleBalanced Mixer (SDBM). 10

cT1 (D Oil ITt0 ~ chZ?............. - ---- - ------- -.-......... — i - a I I I I6 j 5.......................

CHAPTER 3 SUBHARMONIC DOUBLE BALANCED MIXER: ANALYSIS 3.1 Introduction In this chapter the novel subharmonic double balanced mixer (SDBM) is presented with qualitative and analytical descriptions. 3.2 Qualitative Description of the SDBM A simplified schematic of the Gilbert cell mixer is shown in Fig. 3.1. A modification made in this circuit is the reversal of the traditional RF and LO ports. the reason for which will become apparent once the SDBNM circuit is described. In this double balanced mixer topology, it is observed that the currents I1 and 1', switch at the rate of the LO frequency and are 180- out of phase. These currents are fed to the RF section. and the mixing between the RF and LO frequencies occurs in the current domain. For a subharmonic mixer. the mixing needs to occur between the RF frequency 12

RR-' + 3- C, L + o ______-_ _! [! Figure 3.1: Simplified schematic of the Gilbert cell mixer. and twice the LO frequency. So, if one can somehow generate 1, and 12 which switch at twice the LO frequency and which are 180~ out of phase. subharmonic double balanced mixing is possible. The novel circuit topology shown in Fig. 3.2 does this precisely. It should be noted that there are two LO ports with each port driven by a differential (0~-180~) voltage and the LO input at one port is 90~ out of phase with the LO input at the other port. The frequency doubling operation can be better understood by taking a closer look at the collector currents in the transistors in the LO section of the mixer. The collector currents in Q1. Q2. Q3 and Q4 are shown in Fig. 3.3. Notice the 0~. 1800. 90~. 2700 phase of the four collector currents iZc(Ql). Zc(Q2), ic(Q3) and Zc(Q4) respectively. It can be clearly seen that the current 1i. which is the sum of the collector currents in Q1 and Q2. is switching at twice the LO frequency. In a similar fashion. it can be seen that the current 12. the sum of the collector currents in Q3 and Q4. is also switching at twice the LO frequency. The LO signal applied differentially to the bases of Q3 and Q4 is 90~ out of phase with the the LO signal applied to Q1 and 13

V N RL RL '+ t Qout 8 VRF - J - Q5 Q6 7 Q8 ^, r, r Ibias Figure 3.2: Simplified schematic of the novel Subharmonic DoubleBalanced Mixer (SDBM). 14

Q2. As a result. the current A2 is 180- out of phase with respect to current I1 due to the frequency doubling effect. With 11 and 12 going into the RF section 180S out of phase. double balanced mixing occurs and with I1 and I2 switching at twice the LO frequency, subharmonic double balanced mixing is achieved. 3.3 DC Transfer Function of SDBM in this section, general analytical expressions for the operation of the subharmonic double balanced mixer utlizing bipolar juntion transistors are presented. The reader should refer to Fig. 3.4 for the circuit diagram and the various current definitions. For simplicity in the analysis. we assume that the bias current source IEE has an infinite output resistance. that the base resistance of each transistor is negligible. and that the output resistance of each transistor is infinite. The collector currents of the transistors Q1-Q2 can be related to the base-emitter voltages as follows: Ic - ]se T (3.1 ) IC2 ISE (3.2) where Is is the saturation current of the transistors, and V7 is the thermal voltage. Recognizing that I bl - I2 -= I. 'we have: = C L (3.3) /C2 Similarly. 'C3- ) (3.4) IC4 15

itt) i5Q2) i~lQ3) 1,/ i \ -II //, / 1/ II= i5Qfl - +i~Q2) 1/(2fLo ) _ li 1; I II 11(2f., ) / / I K; r i / ! i ii /! I v v 0 i-9 Figure 3.3: Collector doubling. currents in LO section illustrate the frequency 16

Re Vout IEE Figure 3.4: SDBM circuit with bipolar transistors. 17

Summing the collector currents of Q1-Q2 and Q3-Q4. we get: IC12 = IC2(1 - -) = IC2(1 e ) (3.5) IC2 and, IC3C4 IC4(1+ ) = C4(1+ e (3.6) IC4 N ow. assuming that the voltage sources l; and V2 have the saine common-mode voltage. the base-emitter voltages of Q4 and Q2 can be related as: ' be4 - Vbe2 - + ~ (3.7) 2 2 which can be rewritten as: IC4 (VI 4 = CV (3.8) IC2 From equations 3.5. 3.6. 3.8: IC12 1 1 + ( T -, x_ x =A (3.9) ]C34 ( ) I V + e(VT);e can express the currents entering the RF section (Q5-Q8) in terms of the bias current IEE and A as: A IC12 =( A )aFIEE (3.10) 1 C34 = (1- )Ct aFIE (3.11) Using the results of the DC transfer characteristic of emitter coupled pairs in [14]. we can express the collector currents of Q5-QS as: 18

a cF X IC12 3.1 IC5 = --- i aF x Ic12 Ic6 = (3. 13) 1+e.T 1 + ~vT OF x IC34 Ic7 = X 4 (3.14) 1+e VT aF x IC34 Ic8 = F X 34 (3.15) 1 + e ' ) And. the output voltage can be derived as: t = AI x R = (IC57 - IC68) x Rc (3.16) A-A e(T C VT out = CF2IE X AX (3.17) 1 A (1 A(T) (1 -e )) where A is as defined previously in terms of l; and IV. 3.4 Gain of the SDBM To get an understanding of the available gain from the SDB\M. we first calculate the low-frequency voltage gain of the mixer in Fig. 3.4 with the assumption that the pairs Q1-Q2 and Q3-Q4 experience complete, instantaneous switching at each zero-crossing point of V.LO If the LO waveforms have 50 percent duty cycle, the currents Ic12 and Ic34 from the LO section of the mixer will be square waves that are 180~ out of phase: have an 19

average value of aFIEE/2: an amplitude equal to tFI'EE- and a frequency of 2fL( The LO section currents can be expressed in time domain as: IC12 = aFIEE ( + - (1 - (-l))cos(2noLot)) (3.18) n =1 C34 FE= OF (2 - 2 Z(1 - (-1))cos(2 Lot)) (3.19) n 7T=1 Neglecting the higher LO harmonics. IC12 = CFIEE + -cos(2wLt)) (3.20) IC34 = OFIEE (2 - Cos(2Lot)) (3.21) Now. the RF section can be treated as consisting of two emitter coupled pairs formed by Q5-Q6 and Q7-Q8 as shown in Fig. 3.5. The small signal differential input voltage VRF(t) applied to the emitter coupled pair Q5-Q6 gets amplified to the output as -9mRC x VRF(t), where g, = ~ = 1 F'IE The output voltage is the difference between the differential output voltages of the two pairs Q5-Q6 and Q7-Q8. and can be expressed as: vcut(t) = ^F( C12 - 34 ) X VRF(t) (3.22) and. using equations 3.20 and 3.21. the output voltage in time domain can be approximated as: 2a2t(t) IEEc: 4 o(t) = xIEER -cos(2wOt) X VRF(t) (3.23) VT 7T 20

ccc RC Vout Vout56 - Vout78 R e e+ - -l-l +1'_ Vout56 Iout78 +'RFRF VR F -t 5 Q6 - - 07 Q8 22 2 Figure 3.5: RF section of the SDBM. Since multiplication of VRF(t) by cos2WLOt in the time domain is equivalent to shifting I RF(') by ~2wLO and dividing the result by a factor of 2. the output voltage of the mixer in frequency domain is: QF IEE 4Rc I F(X) = X - X F(' - 2aLO) (3.24) \VT 77 The voltage conversion gain is equal to the the output IF voltage. VI.- divided by the input RF voltage: 4AX = o IEE A, = 4RCa 2 (3.25) For Rc = 100 Q. IEE = 8 mA. and CaF = 0.99. the voltage gain of the mixer is about 30 dBV. At practical RF frequencies. the conversion gains of the circuit are lower than calculated above due to parasitic capacitances in the signal path. Also, the 21

LO) section transistors do not act as ideal switches and this will cause a reduction inll the gain too. More accurate values for the gain can be obtained by using full-model simulations in SpectreRF. 3.5 Distortion Performance of the SDBM The distortion performance of downconversion mixers is usually specified by the input third-order intermodulation intercept point (IIP3) and is due to the third-order non-linearities in the mixer circuit. The principal source of distortion in active mixers is the RF input devices non-linear conversion of signal voltage into current. Ideally. the LO switching section does not contribute to the non-linearity of the mixer. But. the sinusoidal nature of a practical LO drive and the non-linearities of the LO devices can also contribute to the overall distortion performance of the mixer. The distortion analysis of the SDBM is complicated due to the reversal of the standard RF and LO sections as in the Gilbert cell mixer. The RF section can be linearized using emitter degeneration as shown in Chapter 4. But. there is a limit to the amount of degeneration that can be used and this is due to the fact that the mixing is happening in the RF section instead of the traditional LO section. Since mixing is a fundamentally non-linear process. linearizing the RF section negates the mixing process. A better design of the SDBM is presented in Chapter 5. where the RF section can be linearized independant of the LO section and whose performance closely resembles that of traditional Gilbert type active mixers. 99

3.6 Noise Analysis of the SDBM The biggest contributors for the noise figure of the SDBMI are the thermal noise from the base resistance and the collector shot noise of the RF section devices. The LO section devices contribute noise also, but are difficult to analyze in the topology chosen for the SDBM where the traditional RF/LO sections are reversed. Please refer to Chapter 5 for the noise analysis of the more linear SDBM. 3.7 Balanced Doublers The SDBM concept can also be used to build balanced frequency doublers. A simplified schematic of a balanced doubler is shown in Fig. 3.6. From the DC transfer character analysis of the SDBM done previously, the output voltage of the doubler can be expressed as: Iout = QFIias( - ) (3.26) where. A is defined in equation 3.9. 1i -;nLO0 and V2 = lnZ90C. When the balanced doubler is driven by an input signal at frequency f,,,. the best performance in terms of the isolation between 2fn and fn 3f,. 4f, etc. in the output voltage spectrum occurs when the transistors Q1-Q4 are driven hard. In the ideal case. when transistors Q1-Q4 are driven hard. the currents IC12 and IC34 will be square waves of amplitude Ibas and frequency 2f,n. And. the maximum output voltage at 2f,, is 2Ib asRc. Most other integrated circuit implementations of frequency doublers use some form of the translinear circuit principles described in [5] and are implemented in various technologies [15]4[16].[17]. NMost' RFIC applications that use this multi-tanh 23

T RC RC + but Vin LO. x * i, %L9 t T Figure 3.6: Simplified schematic of a balanced frequency doubler. approach for frequency doublers need some form of LC-filtering in the load l171 to achieve adequate spectral purity of the second harmonic at the output. The balanced frequency doubler approach described here alleviates this problem. 24

CHAPTER 4 SUBHARMONIC DOUBLE BALANCED MIXER: DESIGN 4.1 Introduction To understand and evaluate the advantages and drawbacks of the SDBM concept compared to other implementations that tackle the LO self-mixing problem. several simulation studies were done using the devices available in the Maxim GST3 SiGe bipolar process. The GST3 is a new high-cspeed IC process technology based on silicon germanium (SiGe). which features double-polysilicon bipolar transistors fabricated using a self-aligned double-poylsilicon process that uses p-poly and n-poly to connect to the base and emitter. The transistors have a maximum f7 of 35 GHz. The process includes an NPN transistor. lateral PNP transistor. four lavers of metals, two different poly-Si resistors. MOS capacitors. high-Q MIM capacitors and thick upper level metal layers for on-chip inductors. The main implementation against which the SDBM was compared was the use of a multi-tanh frequency doubler followed by a Gilbert cell mixer presented by Meyer et al f17].:25,)

4.2 Comparison of SDBM versus Frequency Dou bler + Gilbert Cell Mixer A simplified schematic of the SDBM circuit designed in the Maxim GST3 process is shown in Fig. 4.1. The mixer is designed to operate at an RF frequency of 1.9 GHz and with an LO frequency of 900 MHz. resulting in an IF frequency of 100 MHz. The LO buffer stage which includes the RC-polyphase filter to generate the quadrature LO drive at 900 MHz is shown in Fig. 4.2. V c 100 1 5 1pF0 + 0iF — xx56 x56 x5! 1K 0.6H 0.6nH 0.6. 5pF L(TUL.jTPJ ~II?, LJtL. 5 pF N'LO o ---- \ - - -- ---, ------- ^ --- Q LO O - -' '~ L' '- 7 5I K * ~K 1K X t? 1K Biaslo - -. =. i hmA Figure 4.1: Subharmonic Double-Balanced Mixer (SDBM) schematic with an LO at 900 MHz and an RF at 1.9 GHz. Based on the work in [17]. a simplified schematic of the LO frequency doubler that was designed in the Mlaxim GST3 process is shown in Fig. 4.3. The frequency 26

'LO VT 0 - 0Q26 0.6 mA 9 f. 50 ohm match Inoi shown J not shown POLYPHASE FILT.R - A Figure 4.2: LO buffer and polyphase filter circuit at 900 MHz. 27

doubling is achieved by using a multi-tanh type circuit. Transistors Ql-Q4 perform the frequency doubling function and the inductive loads are used to peak the frequency response and attenuate the harmonics. Transistors Q5-Q6 form a simple differential pair and the inductive/resistive loads are chosen to supply a 600 meppk signal to the LO port of the double-balanced Gilbert cell mixer. A simplified schematic of the Gilbert cell mixer is shown in Fig. 4.4. with transistors Q7-Q8 forming the RF section and Q9-Q12 forming the LO quad. Degeneration inductances of 1 nH are used in the RF section of the mixer to improve linearity. A biasing scheme similar to the one in [17] and in the SDBMI design (which is described in detail in section 4.5.3) is used to provide a bias current of 8 mA in the mixer. 4.3 Comparison Simulation Results The SDBM and the Gilbert Mixer with a frequency doubler were simulated using Cadence Spectre and SpectreRF with Maxim's GST3 process device models. 4.3.1 LO Feedthrough due to Coupling For the LO to RF feedthrough simulations, several non-ideal effects were taken into account based on the models used at Maxim for the GST3 process: 1. A 33 pF bypass capacitor was assumed with a 0.8 nH series inductance on the Vcc pin. with an additional 5 nH inductance to an ideal V\cc source of 3 V. 2. To include capacitive coupling through the substrate, all parasitic capacitors were connected to the substrate node. which was then grounded through an inductor of 2 nH. 3. To include the parasitics due to the ESD protection setup, a 0.1 pF capacitor 28

10I0o NCC 300 5 n1i 3 3WX -jl 0LO I 4 nH 1.2 pF 0 -LO IN 1.2 pF i 1 2 MA ii (nxson10.9 mA Q 0.9 mA I Multi-tanh Frequency Doubler LO Buffer Figure 4.3: LO frequency doubler (900 MHz to 1.8 GHz) and buffer (1.8 GHz). 29

VLO 5^ x56 _> h X 5 pF 5 pF IlK InH lnH IK -- Biasl o -— i 50 otun match not shown) ~ 100! 8mA Figure 4.4: Gilbert cell mixer (standard design) used with the doubler circuit of Fig. 4.3. 30

to Vcc and a 0.1 pF capacitor to substrate was assumed for each port of the IC. An additional 0.1 pF was assumed for each bond-pad. 4. For package parasitics, a 2 nH inductance per lead was assumed. A mutual coupling coefficient of 0.3 was assumed for adjacent leads and 0.1 for non-adjacent leads. The IC was visualized to be bonded on a 10 pin package. The feedthrough was simulated for three different pin configurations (Fig. 4.5). LO+ IF+ RF+ LO+ O+ P+ LO- I F- RF- LO- LO- RFPin Pin Pin Vcc Configuration NC Vcc Configuration NC Vcc Configuration NC #1 #2 #3 RF+ NC IF+ NC IF+ NC RF- Gnd IF- Gnd IF- Gnd Figure 4.5: Pin configurations for feedthrough simulations (NC-No connection). With these additional impedances. the external matching networks at the RF and LO ports had to be slightly modified to get a 50 Q differential input impedance. For the Glibert cell mixer design. the matching network consisted of a series inductance of 13 nH followed by a shunt capacitance of 150 fF across the bases of the input transistors. For the SDBM design, the matching network consisted of a shunt capacitance of 1 pF followed by a series inductance of 7.5 nH in series with the bases of the input devices. A time domain transient analysis was performed on both the mixers with an RF input of -30 dBm and LO inputs of -10. -16 and -20 dBm. The voltages at the RF port are presented in Table 4.1. The voltages at the IF port are presented in Table 4.2. The voltages at fLo (900 MHz) and 2fLo (1.8 GHz) were translated to dBm values assuming 50 Q impedancesfat the RF port at the respective frequencies. 31

I I Subharmonic Double Balanced Mixer Doubler - Gilbert Cell Mlixer PLO PLO PLO PLo PL PL Pins Freq i -lOdBm -16dBm -20dBm -lOdBm -16dBm -20dBm Configl fLo 38.4pV 19pV 11.9A/V 86.3bpV 44.3V3 28.5pV 900MHz -78.3dBm -84.3dBm -88.5dBm -71.3dBm -7.ldBm -80.9dBm 2fLo 44pV 341/V 25.4tV 1.5mV 1.2m\V 0.8mV i 1.8GHz -77.2dBm -79.5dBm -81.9 dBm -46.4dBm -48.7dBm -51.8dBnm Config2 fLO 0.74V\ 0.2pV 11.9/pV 32.6pV 17.7pV 11.4XA' 900MHz -112.6dBm -123.7dBm -88.5dBm -79.7dBm -85dBm -88.9dBn 2fLO 0.24mV 0.3mV 25.4uV 1.5mV 1.2 mV 0.82mV 1.8GHz -62.4dBm -60.3dBm -81.9dBm -46.5dBm -48.7dBm -51.7dBm Config3 fLO 56.5iV 28.2/V 18.2uV 12.2/V 6.6N ' 4.1JV 900MHz -75dBm -81dBm -84.8dBm -88.3dBm -93.6dBm -97.7dBm 2fLO 0.12mV 0.14mV O.lmV 44.21V 38.44' i 27.52Vm 1.8GHz -68.4dBm -67.2dBm -69.8dBm -77.ldBm -78.3dBm -81.2dBm Table 4.1: Feedthrough simulations: Voltages at the RF port for different LO input power levels. The IF voltage at the IF port was converted to power gain using 20log(1 F/1 RF) - 6 dB. The -6 dB value is due to the 200 Q load at the IF port. The arrows in Tables 4.1 and 4.2 indicate the best conditions for the SDBMI and the doubler + Gilbert cell mixer. It is seen that the 2fLo feedthrough at the RF port is -77 to -82 dBm for both the mixers. However, a general look at Table 4.1 indicates that th e SDBM has lower 2fLo feedthrough levels on all pin configurations when compared to the doubler - Gilbert cell mixer. This is also true for Table 4.2 where the IF DC level of the SDB-M is nearly independent of the pin configuration. while the doubler Gilbert cell mixer is very dependent on the pin configuration. We therefore believe that the SDBNM is a more robust circuit than the doubler - Gilbert cell mixer with respect to LO feedthrough. 32

I I I Subharmonic Double Balanced Mixer] Doubler -+- Gilbert Cell'i NIL'xer PLO PLO PLO PLO PLO PLC,() Pins Freq -10dBmn -16dBrn -2OdBm -10dBnm -16dBm -20dBmn Configl fl 79.9rnVI 67.8 mV 51.3 mV 99 mV 98.8 mV 971. 6 rnV 100MHz 12dB 10.6dB 8.2dB 13.9dB 13.9dB 13.8dB fRF 1.9rnV 1MV 0.66mV 1.6mV' 0.88znV 0.153mV 1.9GHz -44.3dBm -49.8dBrn -53.6dBm -46.ldBm -51.2dBm -55.5dBM fLO 1.2rnV O.56mV 0.34mV 2.4mV lmV 0.54mnV 900MHz -48.4dBm -55dBmr -59.5dBm -42.5dBm -49.9dBrn -55.4dBm 21L0 lmV 1un 0.68mV 2.4mnV 2.1mV 1.3m'V 1.8GHz -49.6dBm -49.7dBm -53.3dBm -42.3dBm -43.7dBm -47.8dBrnm DC 0.23niV 0.2mV 76giV 177rV I11.3mV, 4.5 mV7 Co n.gfifcg 78.8mV 67mV 51.3mV 98.9mV 98. 7 mV 97'.5 mV7 100MHz 11.9dB 10.5dB 8.2dB 13.9dB 13.9dB 13.8dB fRF 2. 5 mV 1. 7 MN, 0.66mV 1.47mV 0.84mV7 0. 6 mnk 1.9GHz -42dBm -45.5dBm -53.6dBm -46.7dBm -51.5'dBm -54.5dBm fLo 31.O1iV 7.3pV 0.33mV 0.98mV 0.4mV i 0.2-mV' 900MHz -8OdBm -92.8dBm -59.5dBm -50.2dBrn -57.9dBm -64.5'dBrn 21L0 1.5m Tn lmv 0.68mV 7 MV 5.4mnV' 37 MV, 1.8GHz -46.4dBm -49.8dBm -5-3.3dBrn -33.2dBm -35.3dBm -38.8dBm DC___ _____ 0.84mv 1.4mV 76pi 79V 11.9mV, 5mV, Configr3 fIF 80.3mV 68mV 51.6 mV 99.2mV 99mV 9 7.8 MV I100MHz 12.1dB 10. 7dB 8.3dB 13.9dB 13.9dB I13.8dB 1.9GHz -43.ldBm -47.6dBm -50.3dBm -46.4dBm -51.5dBm -55.3dBmn fLuJ 1.6m'V 0.-76m fN? 0.45mV 1.8mV: lrnV 0.62mV 900MHz -45.9dBm - 52.4dBm -56.9dBm -45.1dBil -50.4dBm -54.2dBm 2fLO lmV 1.1mV 0.8mV 7mV 5.4mV, 3.6mV 1.8GHz -49.2dBm -49.ldBm -52dBrn -33.2dBm 33dm 38dm DC 0.28mV j 0.-622mVN 0.44mV~ 0.llmV 0.26rnV 0.22mV Table 4.2: Feedthrough simulations: Voltages at the IF port for different LO input power levels and with PRF- = -30 dBm. 33

4.3.2 Noise Figure The SDBM has a simulated noise figure of 7.6 dB and the doubler-Gilbert cell mixer has a simulated noise figure of 6.1 dB as per SpectreRF. The noise figure is virtually independent from the LO input power as shown in Fig. 4.6. If the buffers after the polyphase filter are designed as limiters in the SDBIM design, the noise figure (and gain) of the SDBM will remain relatively constant with respect to the external LO drive. lU; I I I l ~II 9.5 - 98 8.5 - -i J4 c I ~ - ~ 'SDBM:| _m7.5-...- — e..! z 7 6.5 Doubler + Gilbert cell mixer cp --- —--------— ^ —~ --- —----------- 6 -5.5 L 5 -16 -15 -14 -13 -12 -11 -10 LO input power (dBm) Figure 4.6: Noise Figure versus LO drive. 4.3.3 Two-Tone Test A transient analysis with two tones applied to the RF port was performed on the SDBEM and the Gilbert %Mixer. Two tones with equal power were applied at 1.89 GHz 34

and 1.91 GHz at the RF port. The input at the LO port was -10 dBm at 900 MIHz. The fundamental tones at 90 MHz and 110 MHz and the third order products at,7( MHz and 130 MHz were observed at the IF port. The harmonic signature for the SDBM1 is shown in Fig. 4.7(a) and for the Gilbert Cell Mixer is shown in Fig. 4.7(b). The third harmonic signature of the SDBM design shows a strange behavior and the reason is not fully known. It could be due to some harmonic component cancellation or addition due to various phases of the LO signals in the circuit. (a) SDBM harmonic signature for a two tone test 0 I I | Fundamental - 2 0........................ -40.....ir.. Order ntermods.. c -8o0- -.................... I:-i -100 1 --- -40 -35 -30 -25 -20 -15 -10 -5 Pin (dBm) ((b) Doubler+GCM harmonic signature for a two tone test E n L Fundamental -20 r- A 4.............................,.. O....e..i....... j ird Order Intermods -60 - / -80- - -100 ' ' i -40 -35 -30 -25 -20 -15 -10 -5 Pin (dBm) Figure 4.7: Harmonic signature in response to a two-tone test of (a) the SDBM (b) the doubler + Gilbert cell mixer. 35

The power gain of the SDBM is 12 dB and the input -1 dB compression point is -20 dBm. The power gain of the doubler - Gilbert cell mixer is 14 dB and the input -1 dB compression point is -20 dBm. The small extra gain (2 dB) in the Gilbert cell mixer can be traded off to improve the linearity by increasing the degeneration inductances. 4.3.4 Power Consumption and Chip Area For both the mixer designs, a power supply voltage of 3 V was assumed. The SDBMl design has a current consumption of 10.6 mA and the doubler Gilbert cell mixer design has a current consumption of 10.8 mA. The power consumption in both the designs is therefore nearly identical. The main difference in the area consumed by the two designs is in the amount of planar inductances used. In the SDBM design, four inductances of 0.6 nH eachi are used for degeneration in the RF section. The doubler -- Gilbert cell mixer design uses two inductances of 1 nH each for the same purpose. In addition to this. the doubler uses two inductances of 4 nH each and the buffer following the doubler uses two inductances of 5 nH each. This represents an additional inductance of almost 18 nH in the doubler - Gilbert cell mixer design over the SDBMI design. Therefore it was estimated that the SDBM will occupy a substantially reduced area when compared to the doubler-mixer approach. The exact value (30'-70%) will depend on the layout of the inductors and the space they will occupy on the chip. A summary of the simulation results for both the SDBMl and the doubler + Gilbert cell mixer are presented in Table 4.3. 36

Subharmonic Double Balanced Mixer Doubler - Gilbert Cell Mixer Supply Voltage 3 V 3V Current Consumption 10.6 mA 10.8 mA Gain 12 dB 14 dB Noise Figure 7.6 dB 6.1 dB P-ldB Compression Point -20 dBm 1 -20 dBm IIP3 Not Defined1 -6 dBm Total Inductance 2.4 nH 20 nH Table 4.3: Simulation results comparing SDBM with doubler + Gilbert cell mixer. 4.4 Test & Measurement Results of SDBM in Maxim Process The SDBM circuit design described above was fabricated using Maxim's GST3 process and the fabricated die were mounted on a test board and tested at the University of Michigan. Several different die were tested and they were not functional. The DC current drawn from the power supply source varied wildly and the reason the chip failed is not fully known. It is thought that the GST3 run was not successful since it was a 'test run" and the DC bia, could not be maintained. 4.5 SDBM Circuit Design in Conexant 0.35i BiCMOS Process A 2.5 GHz SDBMI design which includes the mixer core. a polyphase filter for quadrature LO generation and LO buffers was designed using the Conexant 0.354im 'The slope of the third order intermods at RF power level less than -30 dBm is around 2.3 and changes abruptly at -25 dBm. Therefore. a clear definition of IIP3 for this circuit is not avialable. At RF levels below -30 dBm. the third order intermods in the SDBMl are as low as in the doubler -t- Gilbert cell mixer. 37

BiCMOS process. The overall schematic of the design is shown in Fig. 4.8. The RF input is at 2.5 GHz and the LO input is at 1.2 GHz resulting in an IF output at 100 MHz. Conexant's BC35 process is a 0.35/im. four layer metal commercial BiCMIOS process with a maximum devices fT of 25 GHz. The process incorporates 0.35/im minimum sized CMOS devices in an n-well. a 3 V and 5 \ NPN transistor. a parasitic PNP transistor, two types of resistors (with resistivites of 100 Q/Z and 500 Q/E). a MINI RF capacitor. an RF varactor. and thick metal3 for inductors. RF 25 GHz LOi LO 1.2 GHz ' IF 100 MHz LO Buffer Polyphase Buffers SDBM Filter Figure 4.8: Schematic of the 2.5 GHz Subharmonic Double-Balanced Mixer (SDBM) circuit. 4.5.1 Mixer Core Design A simplified schematic of the subharmonic double balanced mixer core is shown in Fig. 4.9. Transistors Q1-Q4 form the LO section and are biased at node BiasI using a PTAT bias generator discussed in a subsequent section. Transistors Q5-Q8 form the RF section of the mixer. In order to keep the design simple. 100 Q resistive loads are used at the collectors of Q5/QG and Q7/Q8. Also. for low-voltage operation with I c=3 V. a 100 Q resistor is used for biasing instead of an active current source. It should be noted that the output impedance of a transistor based current source is of the order of a few 100 Q at 2.5 GHz and does not offer significant advantage over using an active current source. A tail current of 8 mA biases the mixer core. This 38

current was chosen to provide a good trade-off between the mixer gain. linearity and noise figure. Increasing the current beyond 8 mA poses dc voltage headroom problems due to increasing voltage drops across the bias and load resistors. The biggest noise contributor in the mixer core is the base resistance of devices Q5-Q8. The device sizes of Q5-Q8 are chosen to minimize the base resistance while keeping the current density in the devices at 70 percent of the peak-f7 current density. Having multiple base-emitter fingers in the device layout also helps in reducing the base resistance further. Inductive degeneration in the RF section is used to improve the linearity of the mixer and to also improve the input matching. There is a limit to which the RF section can be degenerated, since beyond a 2 nH inductance, the mixer gain degrades severely with increasing degeneration inductance. Fig. 4.10 shows the simulated voltage gain of the mixer versus the degeneration inductance. TI 5 ---- o +\V ' - o, 5 pF IF + Q ---( Bis2l Q5 6 Q7 Q8 1K 0,8 nH O'snH h>* 0.LO nH O. nH SF P VLO — i --- —- VLO/B Q Q4 5P IK i II K K Biasi o. mA Figure 4.9: Subharmonic Double-Balanced Mixer (SDBM) schematic. 39

SDBM section r en Xo 10 1 0 8 -E 4kI M 6 - I 4F 20 i l.|, 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Degeneration inductance in RF section of SDBM (nH) Figure 4.10: SDBM voltage gain versus degeneration inductance. 4.5.2 LO path design A simplified schematic of the entire LO path which includes the first stage of the LO buffer. polyphase filter and the second stage of LO buffers is shown in Fig. 4.11. The first LO buffer amplifies the LO signal coming from off-chip and provides voltage gain to counteract the 7.8 dB voltage loss in the polyphase filter. The outputs of the polyphase filter are amplified by differential amplifier limiting stages before being fed to the two LO ports of the mixer. The LO drive at the mixer was chosen to optimize the dynamic range and is around 500 mlpk. The polyphase filter outputs have phase and amplitude variation with LO input frequency. Nevertheless, the two differential LO quadrature signals maintain a 90~ phase difference over a wide bandwidth. Fig. 4.12 shows the final simulated voltages at different points in the LO path. Fig. 4.13 shows the amplitude and phase variation of the I/Q paths in the frequency range of 0.8-1.6 GHz. It can be seen that the close to a 90~ phase shift is 40

maintained over a wide bandwidth. POLYPHASE FILTER go Figure 4.11: LO buffer and polyphase filter circuit. 4.5.3 Bias Circuit Design The DC voltage at node Biasl is designed to be a PTAT (proportional to absolute temperature) voltage so as to keep the input impedance of the RF port stable with respect to temperature variations [17]. The dc voltage at the node Biasl is generated as shown in Fig. 4.14. The node Biasl is shunted to ground using a 10 pF capacitor in order that the impedance at the node appears as a ground at frequency of operation of the mixer (>1 GHz). This ensures that the noise from the bias circuit does not contribute to the mixer noise. Transistors Q9-Q14 form the basic PTAT bias cell where the emitter sizes of Q9 and Q10 have a ratio of 1:4 creating a lbe mismatch of (kT/q) x ln(4) which appears across the 1 KQ resistor producing the PTAT current. Q11 and Q12 form 41

LO Path Transient Analvsis 1.2 GHz LO input @ first buffer Output voltage of first LO buffer 1BL0r' 50cm ' r i i p, ri Tr p" 0.00 100rr: Ij 1 I > > -200rr \ -5 65.0- 70.Or 72.0r 74.Or 69r 71r 73~ 75r time (s ) time ( Output voltage after Polyphase Filter 1: Output voltage after Second Buffer 1 0O.T_ 6N8rr OOrrm 2.7- r1~ 0m \ f HeB r I 1 -200m 20.0'r -i~~~ ~ d~ J i;' \: \ \I \ \ 21m'\! Ii p V100 -600r671 696 70- 73- E2.0- 64.0r 66.0- 6B.Or time s time ( Figure 4.12: Simulated LO path voltages in time domain 42

16 14 12 10 6.e 4,0 2.0 0.0 LO Path AC Analysis 800-1600 MHz Smpltmde Respoue of I/Q Phu" Rsponme of I/Q -. -:Phae Difference of 1/Q -94.01 -9-.e. m -1WJ - 4 G - -94. -I2 - -20H0 9(.6: -96B. 00 12G 1.S 8ISG t5l.0 1.22 1.6 troq ( ftz ) 1re ( Ht2 ) frc ( Mz } 2 a Figure 4.13: Simulated LO path output voltages in the frequency domain. a cascode connection to improve the output impedance and the current matching in Q9 and Q10. The PTAT current is mirrored from Q13-Q14 to Q1 and Q20 with the appropriate multiplication factors provided by the emitter sizes of Q17 and Q20. Transistor Q15 is used to bias the pnp device Q16. which provides the base currents for the low 3 pnp devices Q13-14, Q17 and Q20. For bias purposes, the loading at the node Biasi by the LO section transistors Q1-Q4 appears as an x60 transistor with a base resistance of 0.25 kQ and an emitter resistance of 100 Q. To obtain the required 8 mA bias current in the mixer from the 400 gA PTAT current flowing through Q18 (x3 transistor). the base resistance of Q18 is chosen as (8 mA/400 pA)x2.25 KQ = 45 KQ. The 2.25 KQ resistor that is ratioed with the 45 KQ resistor is made up of the 2 KQ resistor attached to node Biasi. plus the 0.25 KQ resistance formed by the four 1 KQ resistors in parallel at the LO section transistors. In this current mirroring scheme. Q19 and Q21 form an npn-pnp current helper and allow operation down to 43

I, as low as 2.7 \ [17]. The DC voltage at node Bias2 is generated by simple voltage division using two diodes and a resistor connected to Icc. This is because the bias currents through Q5-Q& are already fixed by the PTAT bias current in Q1-Q4 and the node Bias2 is biased by a simple source so that the transistors Q5-Q8 are always operating in the forward active region. The bias currents for the LO path are derived from a bandgap biasing circuit that utilizes the same PTAT cell described above. V, gxll x12 QQ i x 216 11 45K' Q1 8 QI 0.Q 2!K 5K I IK 30K Figure 4.14: PTAT biasing circuit for node Biasl in the SDBM. 4.6 Test & Measurement Results The fabricated die (in the Conexant 0.35/L process) was mounted on a test board and the layout is shown in Fig. 4.15. The RF and LO differential ports on the die are probed using a differential probe which includes a balun to convert from differential mode to single ended coaxial mode. 44

SPECTRUM ANALYZER IF 100 MHz I L-. Figure 4.15: Layout of the test board for measurements. 45

The IF. VCC and G-ND pads on the die where -wire-blondied to copiana~r SrLiI on the test board. Fig. 4.16 shows a phiotomicrograph of thle chlip und~er tes Fig~ure 4.16: Photomicrograph of the SDBMi~ chip. The LO probe was matched to 100 ~2- wvith an S1l better than -10 cD- ove-r the frequencyv range of 800-1700 MHZ. and the RF probe wa>, mat ened over the( tremiency rangel of 1.3-2.3) GHz. Fig. 4.17 and Fi.1 4Th showV toe 51 1Theill, cV protbes respectively. The RF probe( hias 'i loss~ of 0.7-0.9 dE across, tlic frequencv rangu,( of 1.2-2.4 0hz. ancd the LC) probe ha> a loss of 0.4-0-.5 dB across~ the, frecinen cy range 01 0.8-1.4 GHz. DC block capacitor>ll are also integrated into the probs 18I,.I Although the mixer was designedco to work at C.b 0Hz. the mnea'suremnents snlow that the mixer woris well around at 1.9 GHz. All the rneasuremieni results' below showv the mixer operating at an. RE.F freouiencv of 1.9 GHz. withl ani LQ'- frequenicy of 40G

St1 FORWRRD REFLECTIO N LOG 1AG. ~RERF=0000dB 5.000dB/DIU ~.......... H............................................... CH S - Si RE:. PLANE 0.0000 mr WMRRKER 1 1.9000 Ghz -18.666 dB MARKER TO MAX MRRKER TO MIN i.-.....................................:..... - ^ -. — u.c — 0.0400 GHz 3.0000 Figure 4.17: RF probe Sll with a 100 Q differential load. 900 MHz resulting in an IF frequency of 100 MHz. Fig. 4.19 shows the mixer power gain versus RF input frequency with the LO input frequency at 900 MHz and, an LO input power of 0 dBm into the mismatched LO port (LO port was not externally matched). The RF probe effects have been normalized out of the measurements. A two tone test was performed to measure the input third order intermodulation point (IIP3) of the mixer. The two tones were at 1.89 GHz and 1.91 GHz resulting in fundamental tones at 90 MHz and 110 MHz, and third order intermods at 70 MHz and 130 MiHz at the IF output. Fig. 4.20 shows the fundamental and intermod powers with respect to the two tone input powers. Extrapolation of the two curves results in an IIP3 of -3 dBm. Fig. 4.21 shows a plot of the mixer gain at 1.9 GHz as the LO input power at 900 MHz is varied from -20 dBm to 0 dBm. The mixer operates well 47

3..i FORW4ARD REK.EOT"rN LOG tFi3. M REF =0. 20Q&"/DT *. 1.... f.................. f- S- - C,, ' REF. F p.(,.O/JCc. Fr,tr1ARk'ER rIRRKER TC M1R~ r1lKER TO K h 0.0400 GHZ ~.0020 Figure 4.18: LO probe Sll with a 100 Q differential load. down to an input LO power (mismatched) of -12 dBm as shown bO the gain versus LO power plot in Fig. 4.21. The measured DC differential output level at the IF port with an LO input of 0 dBm and a mismatched RF port is about 10 irV. It should be noted that it is hard to get accurate measurements at such low voltages. The meaured single side band noise figure of the mixer was 10 dB at an RF input of 1.9 GHz and an LC) input of 900 MHz. The measurement results are summarised in Table 4.4. The design kit from conexant also had only preliminary circuit models for the inductors. From the simulation results presented previously, it can be seen that the gain of the SDBNI is fairly sensitive to the degeneration inductance and any change in the actual value of the inductance on the die will cause a shift in the measured gain. The measurement results of the SDBM in comparison to other implementations 48

12 11 -'10 -N - I 7 6 -m i D 5 -4 -1.5 1.6 1.7 1.8 1.9 2 RF input frequency (GHz) Figure 4.19: SDBM measured gain versus the RF input frequency. Supply Voltage 3 V\ Mixer Core Current 8 mA LO Frequency 900 MIHz RF Frequency 1.9 GHz Conversion Gain 7.5 dB IIP3 -3 dBm Input P-ldB -8 dBm SSB Noise Figure 10 dB Table 4.4: Summary of SDBM measurement results 49

- 5 T - - - -10 --151 Fundamental -20 -i -25.0 O. -35r -40- 1 -45 _45r Third Order Intermods -50 --55 l ' -45 -40 -35 -30 -25 -20 -15 -10 -5 0 P. (dBm) in Figure 4.20: Measured SDBM harmonic signature at 1.9 GHz RF input. of subharmonic mixers as discussed in Chapter 2 is shown in Table 4.5. 4.6.1 Deviation of Measured Results from Simulated Results As was mentioned earlier. the measured results of the SDBMI show a frequency shift in the operation of the mixer. The main reason could be in the absolute value shift of the polyphase filter resistors and capacitors due to process variation. The value of the capacitors used in the polyphase filters was very small and it is thought that the models do not adequately account for the fringing capacitance of these small values capacitors. Conexant was continually updating the process models. but we did not have latest design kit here at the University to reflect these changes in the process models. A secondary reason could be the frequency response of the RF probe which is designed to work well at 1.9 GHz and tends to be mismatched beyond 2.6 GHz. 50

R — ' T —. -N 4- / 4 LO input power at 900MHz (dBm) L O input power at 900 MHz. U. 6 5 3r 2 --20 -15 -10 -5 0 LO input power at 900MHz (dBm) Figure 4.21: Measured SDBM gain at 1.9 GHz RF input versus the LO input power at 900 MHz. Yamaji et al Shimozawa et al Matinpour et al Sheng et al This work [2] [12] [13] [3] [19] CICC 1997 RFIC 1998 MTT Dec 2000 JSSC Sep 2000 RFIC 2001 i iLxer Type ECP APDP APDP Two level Single level i i _ Quadrature LO Quadrature LO IC( 2.7 \ - 2. 3.3 V 3 V I Imier, 5 m 2 A - 21 mA 2.8 A 8 mA i f 2 GHz 1.6 GHz 5 GHz 2 GHz 1.9 GHz LO power i 8 dBm 9 dBm 8 dBm 10 dBm 0 dBm Gain 5.6 dB -6 dB -17 dB 17.2 dB j 7.5 dB SSB NF i 17 dB dB 15 dB 12.8 dB 10 dB IIP3 -1 dBm 9 dBnm 6 dBm -5.1 dBm -3 dBm _________________________________________________i Table 4.5: Comparison of SDBM measurement results with other subharmonic mixer implementations 51

Both the linearity and noise figure performance of the mixer match the simulations closely. The measured gain of the mixer is lower than the simulated gain by about G dB. This could be explained by the variation of the load resistors from the simulated value. The load resistors were designed to be at 100 Q. The measured DC value at the IF port was 2.75 V. and assuming that the mixer has a tail bias current of S mA. the actual resitance of the load resistors is (3.0-2.75) V/4 mA = 62.5 P. The total simulated current of the chip was 15.68 mA and the current drawn from the 3 V power supply during testing was 15.82 mA. So. the mixer current should be fairly close to the assumed 8 mA. This lower value of the load resistor leads to a mixer gain of 9.4 dB which is better agreement with the measured value of 7.5-9 dB. 4.7 Balanced Frequency Doubler Circuit Design Using the idea of quadrature signal like in the LO path of the SDBM. a balanced frequency doubler circuit was be designed. Fig. 4.22 shows the schematic of the doubler circuit that was designed using the same Conexant 0.35 4m BiCMOS process. The input signal at 1.2 GHz is first applied to the polyphase filter to obtain the quadrature signals necessary for the function of the frequency doubler. The quadrature signals are then applied to the doubler core containing the transistors Q1-Q4. The bias current is set by the voltage at node Biasi which forces the current in the tail resistor to be 1.2 mA. The output voltage at double the frequency is then buffered through a differential amplifier formed by Q5-Q6. Fig. 4.23 shows the simulated response of the designed circuit as the input signal voltage is swept at 1.2 GHz and the various harmonics of the output voltage are plotted. It can be seen from the simulation that at large values of X i. the doubler circuit 52

(- V90p -- V90m -400 -3mA Vbias 120 1.2 mA Figure 4.22: Balanced frequency doubler circuit schematic.

'~lf& -120 - I i E -70 -60 -50 - +0 -30 -20 -10 0 P. (dBm) in Figure 4.23: Simulated response of the balanced frequency doubler with input at 1.2 GHz 54

performs well with more than 30 dB of isolation between the 2f,, component and other frequency components at the output. At small values of I,. the output showa frequency component at f,, that is very close to the 2f,, component. This is due to a mistake in the design. Due to the quadrature nature of the input signal driving transistors Q1-Q4, the commmon emitter point of the four transistors gets modulated with the input signal. This in turn modulates the bias current and shows up at the output voltage. This problem can be reduced by using better current sources with higher output impedances. 4.8 Balanced Frequency Doubler Test & Measurement Results Fig. 4.24 shows a photomicrograph of the balanced doubler fabricated in Conexant's 0.35 urm BiCMOS process. The balanced frequency doubler die was mounted on a test board similar to the one used for the SDBMi chip testing. The LO probe used for the testing of the SDBMI was used as the input signal probe and the RF probe used for the testing of the SDBMI was used as the output signal probe of the balanced frequency doubler circuit under test. As was the case with the SDBMi circuit. the measured response of the frequency doubler showed a shift in frequency. A.1 the measurements discussed below are done Nwith an input at a frequency of 900 MIHz and the resulting output at 1.9 GHz. Fig. 4.25 shows the output power of the doubler ar various harmonics as the input power is swept. It should be noted that the simulation results presented earlier in Fig. 4.23 are at an input frequency of 1.2 GHz. while the measured results shown in Fig. 4.25 are at 55

Figure 4.24: Photomicrograph of the balanced frequency doubler circuit an input frequency of 900 MHz. The simulation results at 900 NMHz are not presented here since the polyphase filter is designed to work at 1.2 GHz. and simulation results at 900 MIHz will not give an accurate representation of the operation of the circuit. It should also be noted that the input and output ports while measuring the doubler were not matched and the plot above does not give an accurate value of the gain of the frequency doubler circuit. In a real RFIC application using thile frequency doubler circuit. the impedance mismatch should not be a Droblem since the size of the core is small enough to consider the output as a voitage signal. 56

11 1 l -20 -30 - -40 E mI D -500 -o 0 1 IL-I -10 -5 P. (dBm) in Figure 4.25: Measured response of the balanced frequency doubler with input at 900 MHz 57

CHAPTER 5 IMPROVING SDBM LINEARITY 5.1 Introduction One of the big problems with the circuit topology of the SDBMI described in the previous sections is that the RF section cannot be linearized independent to the mixing process which is inherently nonlinear. The circuit topology shown in Fig. 5.1 solves this problem. The DC transfer characteristic of this topology that is presented at the end of this chapter shows that the operation of this circuit topology is very similar to the operation of the SDBM circuit. The RF section is formed by transistors Q1-Q2 and can be varied quite a bit to improve the linearity of the mixer as will be shown in subsequent sections. The LO section is formed by transistors Q3-Q1() and replaces the quad transistors in the traditional Gilbert mixer with the equivalent doubling configuration. The LO section is driven by quadrature signals to achieve subharmonic mixing as explained in the previous chapters. 58

r I-i I VVi!2! ':9 -Q Q L Q Q1;Q 0 i ri Q Q! b Figure 5.1: Circuit topology for a more linear subharmonic mixer 5.2 Linearizing the RF Section The linearity of the RF section consisting of a differential pair transconductor in the linear S)DBM, presented above can be improved using several techniques. The most straight forward technique is to use emitter degeneration in the RF section. In this case. the mixer gain (and noise figure when resistively degenerated) is traded off for linearity. The high frequency nonlinearity analysis equations presented in [20] show that for a degenerated differential pair transconductance stage. the mixer IIP3 is improved with increase in the bias current. It also shows that transconductance stages with inductive degeneration have smaller input-referred third order intermodulation than those with resistive or capacitive degeneration. Fong et al. [20] also show that a common-emitter transconductance stage can be biased at a lower current than a differetial-pair transconductance stage with the same linearity and transconductance. But this will involve a trade-off of choosing a single balanced mixer over a double balanced mixer topology which is will provide better 59

RF rejection at the IF port. The multi-tanh technique presented by Gilbert in [5] can be used as another alternative to linearize the RF section transconductance stage. In the basic form of this method. two differential pairs are operated in parallel each with a base offset voltage which splits the individual g, functions along the input voltage axis. The sum of these shifted g,'s extends the input voltage range (Fig. 5.2) and provides ani overall transconductance that is linear over this extended range. 1.1 -: C g I oI f; ' I! ___ w t O-. *12X ~8~ 4 C 4C 5 I2C IN (MVP) Figure 5.2: Extending input range using the multi-tanh technique: gm for a multi-tanh doublet(after [5]). Another alternative is to use transformers instead of a transconductance stage in the RF stage. As has been discussed previously- the input devices of the transconductance stage are the biggest sources of non-linearity in the mixer. If these devices are eliminated,. the mixer linearity performance can be dramatically improved. Fig. 5.3 shows a typical implementation of this concept. It is important to use cascode devices in the RF section before the RF signal currents are fed in the LO section. The 60

cascode devices provide isolation between the LNA and the mixer and also provide isolation between the RF and LO ports of the mixer. P Q E -,C i r QI QR0~ 1 RF180 Figure 5.3: Linear SDBM circuit utilizing a transformer in RF section 5.3 Design of Linear Subharmonic Mixers In this section. simulation results in Cadence SpectreRF will be presented for a linear subharmonic mixers utilizing the ideas discussed in the previous section. 5.3.1 Linear SDBM design The first design is based on the SDBM design utilizing Conexant's 0.35 Imn BiCNMOS process as discussed in Chapter 4. The circuit schematic of the linear SDBM is shown in Fig. 5.4. Transistors Q1-Q2 form the RF section of the mixer. As in the previous SDBMI design the 100 Q tail resistor is used to set the bias current of the mixer at 8 mA through a similar bias generator as discussed before. The bias current was not nmodified from the SDBMI design to provide a good basis for comparison of 61

the linear SDBMI with the SDBM design. The LO section transistors arc now half the size of the transistors used in the previous SDBNI design. while the RI section transistors are double the size. This keeps the current density in both the RF and LO section transistors at the same level as before ensuring the bias point corresponds to about 70 percent of the bias current corresponding to peak fT of the bipolar devices. The RF section is linearized using the same degeneration inductors used as in the SDBM3 design and have an inductance of 0.8 nH each. 100 100 i NV IF 1K Bias2 i Q 8,od- Q QQ1f: ~.-,Vo80 5K Ldegen = 0.8n Ldegen = 0.8n I 5K! Ia w _ Biasl 100 8mA Figure 5.4: Circuit schematic of the linear SDBM. A simplified schematic of the LO path used in the linear SDBM is shown in Fig. 5.5. This included the first LO buffer. the polyphase filter to generate the quadrature LO 62

signals and the second LO buffers which operate as limiters. A few changer were made in the design of the LO buffer from the things learnt from the SDB.M test and measurement results and from more experience in designing mixers. The limiting buffers now have transistors Q28-Q31 which are cascode devices that improve the frequency response of the buffers. This allows the LO waveform appearing at the mixer to have a better characteristic for linearity performance. Also. the polyphase filter design is modified to have a better chance of achieving the targeted center frequency of 1.2 GHz. The capacitors in the filter were increased to minimize the effects of fringing capacitance. This comes at the expense of increasing the area taken up by the filter. This design was simulated in Cadence SpectreRF with comparable results to the SDBMI design. The various mixer performance metrics that were simulated using this design are summarised in Table 5.1. ISupply Voltage 3 \ [Mixer Core Current 8 mA LO Frequency 1.2 GHz RF Frequency 2.5 GHz Conversion Gain 13.6 dB IIP3 -5 dBm l DSB Noise Figure 7.1 dB Table 5.1: Summary of linear SDBM simulated results with LdeQen = 0.8 nH The design described above can be further optimized for linearity by trading off the gain and some noise figure. This can be easily accomplished by increasing the degeneration inductance used in the RF section of the linear SDBM. Fig. 5.6 shows the tradeoffs involved by plotting the mixer gain. noise figure and IIP3 versus the degencration inductance used in the RF section of the mixer. As can be seen from 63

03pmA 0.5p 20 -j K i,5 2 s - L 26 LO ',, i! + o 7 - Figure 5.5: LO path for the linear SDBM design G '*L(

the figure. as the degeneration inductance is increased from 0.S nH to 2.- ni. ai improvement of 8 dB can be obtained in IIP3 with a corresponding degradation of 2 dB in noise figure of the linear SDBM. 0m S -' - 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 5 --- —--------- - 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 10 — i —.9 -0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 RF section degeneration inductance (nH) Figure 5.6: Simulated linear SDBM Gain, IIP3 and Noise Figure versus RF section degeneration inductance. 5.3.2 Transformer-based Linear SDBM Design Modern RFIC process technologies provide the capability to use planar inductors and transformers to add another dimension of creativity and design flexibility. From 65

the observation that the biggest contribution to the non-linearity of the RF secrion is the transconductance devices, the linearity of an active mixer can be improved bv eliminating these transconductance devices. The differential output current fromi the LNA can be directly fed into the mixer through the use of a balun/transformer. This improves the mixer IIP3 performance a lot. The disadvantage is that the mixer design will have to be coupled closely to the design of a very high gain LNA to compensate for the lower voltage gain and poorer noise performance of this type of mixer. A similar idea has been explored in [21]. but the idea was not extended to the design of highly linear mixers. A subharmonic mixer utlizing this idea was implemented using the balun available in the Conexant 0.35 gim BiCMOS process. For the sake of comparison with the linear SDB.M design of the previous section. the bias current in transformer-based design was kept at the same 8 mA. Fig. 5.7 shows the circuit schematic of the mixer used to implement this design. The LO path of the design is essentially the same as that in the linear SDBMI design and is shown in Fig. 5.5. The cascode devices Q1-Q2 are used to convert the incoming RF signal into the current domain. The RF currents are then commutated using the LO switching transistors. The linearity of this mixer topology is limited by the non-linearity of the current gain in the cascode devices (which essentially depends on the non-linearity of the i3 of the RF section transistors) and the non-linearity contributed by the LO section transistors when they are driven hard as switches. Hence. the LO drive has to be limited so as not to degrade the linearity of the mixer. Since there is no voltage gain ahead of the LO switching section as in the linear SDBNI. the LO section transistors dominate the noise performance. Whien the LO section transistors are turned on hard. they appear as cascode devices and their noise contribution is minimal. But. when 66

-T 100 100 l l ----— \ -- -- \0~ y ^g00 90~Q 7V200 0 Po 00 V1800 L 4 L Q5 ( Q7 Q _ 9 Bias: Q! — BiasI}' Q2 i0.62 L2 = 2.7n 4 = 2.7n k14= =0.69 - k13 = = 0.73 L = 3.1n L2 =3.1n k= 0.62 IRF0c IR180~ Figure 5.7: Circuit schematic of the linear SDBM with a transformerbased RF section. 1K

the LO section transistors are in transition. the LO section appears as a combiiatioIof differential pairs and the tranistor noise gets amplified to the output. HeCIle. the LO drive has to be as high as possible for the noise figure of the mixer ut, be minimized. Thus. the LO drive provides a classic trade-off between the linearity and noise performance of the mixer. and is chosen to be 450 mV'pk at the mixer. The dominant noise contributors in this topology are the collector current shot noise and the extrnisic base resistance thermal noise of the LO section transistors Q3-Q10. Since this kind of mixer needs to be designed closely with the preceding LNA. all the simulated performance metrics of the mixer will be presented in voltage units rather than power units as is the custom. If the mixer were to be operated as a discrete component. the input and output of the mixer would have to be matched and using power units would be appropriate. But, this topology is by design meant to be used in an integrated receiver type application and in such a case there is no need to match the mixer to the traditional 50 Q. Supply Voltage 3 \ M lixer Core Current iS mA LO Frequency 1.2 GHz RF Frequency 2.5 GHz Voltage Conversion Gain 4.5 dB IIP3 2.2 dBV = 9.2 dBm15o S: Equiv Input Noise 2.6 n\ //Hz Table 5.2: Summary of transformer based linear SDBM simulated results. The simulated performance( metrics of the transformer based linear SDBME are shown in Table 5.2. Compared to the linear SDBM. the transformer based linear SDBMI has about 14 dB to 6 dB (depending on the degeneration inductance in the linear SDBMI design) better IIP3. Since this design was not matched at the RF 68

input, the noise performance cannot be specified by noise figure and the equivalcnt input noise is used as a performance metric. The transformer-based design ha> ai higher equivalent input noise voltage of 2.6 nV/'\/Hz as compared to the 1.9 InV \Hz of the linear SDBM. But. the output noise in both cases is comparable due to the lower gain in the transformer based design. Thus. in applications that demand high linearirty this mixer topology shows promise when it is preceded by a high gain low noise amplifier. 5.3.3 CMOS Subharmonic Mixers The Gilbert cell mixer topology can be implemented using CMIOS devices too. and the the quadratic nature of the devices as opposed to the exponential behaviour of bipolar devices lends this implementation for better linearity when compared to bipolar active mixers carrying the same current. One drawback with CMIOS active mixers is that they tend to have significantly higher noise figure than their bipolar counterparts. The subharmonic mixer topology discussed so far in bipolar implementations can be adapted for CMOS processes also 5.4 Linear SDBM Analysis 5.4.1 DC Transfer Function The Linear SDBMI circuit topology has a DC transfer function that is very similar to the transfer function of the SDB-M presented earlier. The reader should refer to Fig. 5.S for the circuit diagram and the various current definitions. As in the case of the SDBMI analysis, it is assumed that the bias current source IEE has infinite output resistance, that tihe base resistance of eachti transistor is negligible. and that 69

the output resistance of each transistor is infinite.? R R - +V - - OUt I I -- - ---- IE i I - Q3 Q4 Q5 Q6 V, C -I / 1','-'7 i lc- I () I i! I Q8, Q, Q1(, - x'3 I Q2 "AIv i 'I i i -...._ Figure 5.8: Circuit schematic of the linear SDBM for DC transfer characteristic analysis Transistors Q1-Q2 form an emitter-coupled differential pair. and their collector currents are given by [141: C F IEE 1 JC2 -—.'E - C(,) (5.1) (5.2) 70

Now. realizing that transistors Q3-Q6 and lcl form a similar circuit topology as transistors Q1-Q4 and IEE in Fig. 3.4. and doing similar algebra as in equations 3.1 to 3.11. we get: ( 1 ^ \ IC34= 7 ) FIcl (5. ) IC56= (1 — C (5.4) where. ^ is given by: 1 1 + _ e_ __ - x (5-5) Similarly,. for transistors QT-Q10: 1c7s = (- ) ^Ic2 (5.6) IC7 1 O FrIC IC910 = F 1 FC2 (5.7) The output voltage is given by: 1 ut = i(JC34 - CC7S - IC56 - IC0910) X RL (5.8) Substituting equations 5.3-5.4 and 5.6-5.7 in 5.8. and simplifying the algebra. we get: (t = ) — ) alS2 EERLtanh ) (5.9)

which is very similar to the output voltage derived for the SDBMi circuit. For low frequency applications where linearity is not a concern, both the linear SDBNI and SDBM topologies with ideal circuit elements have exactly the same output voltage. 5.4.2 Noise Performance of Linear SDBM Both the RF and LO section transistors contribute to the noise figure of the linear SDBM presented in the previous section. The noise contribution of the RF section is analyzed quanitatively. while the LO section noise contribution is analyzed qualitatively. For the noise contribution of the RF section, which is an emitter- degenerated differential pair. the output noise contribution is calculated due to each of the noise sources in the RF section devices. This output noise is divided by the transconductance to give the input referred noise power and compared to the noise power generated by the source resistance to obtain the noise figure of the RF section of the mixer [22i. Fig. 5.9 shows the small-signal noise model used to derive the noise contribution of the RF section. It can be seen that the circuit is symmetrical and the half-circuit concept can be used to derive the noise figure. In this model. Zb is used to model the base extrinsic resistance and any series matching impedance. Z. is the base-emitter impedance and it includes C r. and Cb. Rs is the source resistance driving the mixer. and Z, is the input impedance of the RF section. The C,, of the transistors Q1-Q2 is neglected in this model. The output impedance of the bias current source can be absorbed into ZE. when needed to be taken into account. The noise figure contributions can be divided into three different sources - collector shot noise IC- = q27J). base shot noise (ZC = 2qIQ/3). and thermal noise contribution from the

resistive components of Zb and ZE. 'Ici Ic C2 Z Q2 i,7 RS Rs 4 Il______ l EE Zb out + 2-2 Rs V+Ib 2; 5 -S'S h Half-circuit model ZE for noise analysis Figure 5.9: Linear SDBM RI section model for noise analysis The output noise current power due the collector shot noise is 2q]J,. And, the transconductance io/s is 9m,/s., and can be derived as gZ,/(Z,, - Z - ZE-?S) and the equivalent input noise power due to the collector shot noise is given by: 2 2a x ( Z b - ZE )2 (5.10) vnc (0.10) i9mZ)2 where g, = I/\ 7I = IEE/(21; ) and. the noise factor contribution due to the collector shot noise can be obtained by dividing lp2 by the noise power due to the source resistance (4kTI?5). which when simplified gives: 73

iRC Zh - ZE - Zi! collector = 2g, ZRs The output noise current power due to the base shot noise is given by ((ZE - R, - Zb)6lZ )2 X 2qIQ/3. Using the same transconductance as in the case of the collector shot noise. the equivalent input noise power due to the base shot noise can be derived as: - 2qIQ x (ZE + RS ( Zb)2 Tb - 0(5.12 ) 3gm2 Once again. the noise factor contribution due to the base shot noise can be obtained by dividing oT72 by the noise power due to the source resistance (4kTR7s). which when simplified gives: Fba Rs + Zb ZE2 (Z. 13 23Rs Finally, the output noise current power due to the thermal noise in Zb and ZL- is given by i z )2 x 4kTR(Zb - ZE) and the equivalent input noise due to the thermal noise sources is given by: t - 4kTRc(Zb - ZE) (5.14) And. the noise factor contribution due to the thermal noise in Zb and ZE is given by: tC( ZZ - ZE) ( F tpermal (=Z, (5.15) Rs Using equations 5.11. 5.13. 5.15. the overall noise factor (linear) of the RF section can be expressed as: 74

F = 1 -- 2(Fcollector - Fbase i Ftherma!) (5.16: i and. noise figure NF = 10log(F) in dB. From the equations above, it can be seen that the collector shot noise contribution to the noise figure can be reduced by increasing gm, which can be done by increasing the bias current. The base shot noise contribution has an opposite dependance on gq, and is reduced by decreasing gm. Hence, there is an optimum bias current where the total shot noise contribution is a minimum. Rs provides another degree of optimization to minimize the total shot noise contribution to noise figure. while the thermal noise contribution decreases as Rs increases. Unlike discrete mLxers where Rs is typically fixed at 50 Q. in integrated circuit mixers Rs is the resistive part of the output impedance of the LNA preceding the mixer and can be used as a design variable to optimize the overall noise figure of the receiver. The thermal noise contribution can be reduced by making the device size as large as possible in order to reduce the extrinsic base resistance. Multiple finger base-emitter junctions can be used in layout to reduce this base resistaace further. As the RF section device size increases. Co increases and this hurts the linearity of the transconductance stage, increases feedback from the collector to the base. reducing gain and making impedance marching difficult. Thermal noise contribution can also be' kept to a minimum by using inductors for emitter degeneration instead of resistance. This comes at the expense of the much larger die areas of inductors. The noise contribution from the LO stage switching transistors is much more difficult to analyze quantitatively and needs highly mathematical treatment [23>. The factors that the circuit designer has control over that can enable the minimization of this noise contribution are LO drive. LO waveformr- shape. and LO section transistor i D

sizing. When the LO drive is high enough to turn one side of the LO section on and the other side off, the LO section devices appear as cascode devices and their noise contribution is minimized. Hence. large LO signal amplitudes are preferred to reduce the noise contribution of the LO section transistors. But. a large LO drive reduces the linearity of the switching stage. In bipolar transistor implementations of monolithici mixers. LO signal amplitudes between 300-500 mV are used to achieve low noise figure with acceptable linearity [24][25][19]. If the LO waveform is approximated as a square wave at a frequency of 2fLo, noise power at 2fLO=fRF. GfLO fRF. 10fLO fRF etc. will be downconverted to the IF port and appear as output noise as shown in Fig. 5.10. Assuming that the transconductance and output noise power of the RF section are constant at all frequencies. the LO switching stage will increase the input referred noise contribution from the RF section by a factor of (-)2 = 3.9 dB [23]. But, if the switching operation is done by a sine wave. the input referred noise contribution from the RF section would be increased by a factor of 2 (3 dB) due to the mixing of noise down from both the RF frequency and the image frequency. In practical circuit applications, this factor will be somewhere between 3 and 3.9 dB. It should be noted here that while the ideal LC) waveform for a Gilbert cell mixer is close to a square wave. the LO section of the linear SDBM.I design cannot be a square wave for subharmonic mixing to happen and needs to be closer to a sine wave. This is due to the rectification action of the doubling pairs of transistors that replace the LO quad in the traditional first harmonic mixer. To reduce the thermal noise contribution from the base resistance, rb of the LO section transistors. the device sizes must be reasonably large. Once again, there is a tradeoff with linearity as large device sizes lead to a large C., and switching of C., 76

Power i / ' ', / \ \ \ \ lF f L 6f 10f Frequency RFLO LO LO Figure 5.10: LO harmonics mix noise down to IF with the large LO signal reduces the mixer linearity. 5.4.3 Linearity Performance of Linear SDBM As in the case of the noise performance. both the RF section and the LO section of the linear SDBIMN contribute to the linearity of the mixer. Once again. the RF section can be analyzed quantitatively ari the LO section contribution is dealt with qualitatively due to the large signal behavior. Fong and lever [20]![22 derive the analytical expression for the third order intermodulation products for the general case of a differential pair transconductance with emitter degeneration. Since the RF section of the linear SDBMN is a differential pair with inductive degeneration. the volterra series equations derived in [20]f221 are applicable to the RF section of the linear SDBNM\ too. It was shown that the simplified analytical expression for the third order intermodulation products is given by: I i

\^31 1 lA1S) 3 X ( l-sceZb(s)- SCe,,ZE(s))l X I1 17. 21EE where. A1(s) is given by 2 X (1 - SC CZb(S) ZE(S) - STF9mZb(S) - ZES) - m Zb S)L - Zia )i - E(SZi (5.1S; where. g, = IEE/2I VT It can be seen from equations 5.17 and 5.18 that IIMI31 depends on the magnitude of 1 - SC3eZb(S) sCeZE(s). and hence a differential pair stage with inductive degeneration is more linear than a stage with resistive degeneration which in turn is better than capacitive degeneration. Also, the value of lIMf3 is proportional to the cube of the ratio of the small signal transconductance of the RF section devices (through the numerator of Al(s)) to the bias current (IEE). The LO section switching transistors also contribute to the 1113 products at the IF output of the mixer. Up to an extent. increasing the LO drive improves the linearity performance of the LO section. This:, because. a higher LO drive helps in keeping one side of the LO section turned on hard and the LO section devices behave as cascode devices which contribute little nonlinearity. But. as the LO signal amrplitude increases. switching the base-emitter junction capacitance (C.,) of the LC) sectionl devices results in excessive current being pumped into the common emitter points of the switching stage through C,, [26][231. Hence. at high LO drives. the linearity of the LO section decreases with increasing LO signal amplitude. For the same reason. the device size of the LO section transistors cannot be arbitrarily increased since this causes an increase in C., and hence worsens the linearity of the LO section. In processes with high f-. the LO section devices can be made to switch very rapidly and 78

the overall mixer non-linearity is dominated by the non-linearity of the RF section. But. in processes with low fT devices. the LO switching stage can be a significant contributor to the non-linearity of the mixer. 5.4.4 Device Mismatch Effects For the SDBM and linear SDBMI designs presented in this thesis. the doublebalanced nature of the mixers allow no RF and LO feedthrough to the IF port ideally. In reality, device mismatch effects will cause some feedthrough to the IF port. The effect of device mismatches between the LO section transistors in the linear SDBMl design is equivalent to having an amplitude mismatch between the quadrature LO drive signals due to the different loading on the LO buffer outputs. Fig. 5.11 shows the simulated RF feedthrough (relative to the RF input signal level) at the IF port for amplitude mismatch between the I and Q paths of the LO signal driving the mixer. Fig. 5.12 shows the RF feedthrough for phase mismatch between the I and Q paths of the LO signals driving the mixer. The LO feedthrough to the IF port does not sho an significant change due to the amplitude and phase mismatches of the I and Q paths of the LO signal driving the mixer. This is due to the large signal switching nature of the LO section of the mixer 79

5 10 15 Percentage amplitide mismatch in U/Q LO input 20 Figure 5.11: RF-to-IF feedthrough due to amplitude mismatch between the I/Q LO signals 80

I I ~-60F WOO -650 CL~ -70 |D-75- \ / \-80 - U-85 -90 --5 0 5 Phase mismatch h;tween /Q LO inputs (deg) Figure 5.12: RF-to-IF feedthrough due to phase mismatch between the I/Q LO signals 81

CHAPTER 6 CONCLUSIONS AND FUTURE WORK This thesis has presented novel circuit topologies for implementation of subharmonic double balanced mixers in RFIC process technologies. The basic SDBM topology was designed and fabricated in SiGe HBT (Maxim GST3) and BiCMOS (Conexant bc35) commercial processes. While the chip designed in the MIaxim process did not work functionally during testing of the fabricated die. the Conexant design was tested and measurement results are quite competitive to other subharmonic mixer design implementations. Qualitative and quantitative analyses for the various performance metrics (Gain. IIP3. Noise Figure) for the mixer design were also presented. Finally. simulation results were presented for linearizing the SDBMi design. 6.1 nth Harmonic Mixers The concept of using a qaudrature LO to obtain second harmonic mixing can be extended further to the design of higher order subharmonic mixers. The use of this concept for a third harmonic mixer is demonstrated in [41 as multiphase reducedfrequency conversion. The basic idea is that mixing with a single phase high frequency 82

periodic signal is equivalent to mixing with a set of reduced frequency muli-piiase periodic signals. If these signals are sinusoidal. as is the case in most RF system>. this can be demonstrated by the following equations: N I-Io SZ - X - - - sin(sRFt) = 2-1 sin - xt — ) (6. 1=0 ' - Using this concept. higher order harmonic mixers can be implemented. One of the problems to solve in order for these implementations to work is the design of precise phase shifters that can generate the multi-phase reduced frequency signals. One important application where these type of higher order harmonic mixers can be useful is in the design of fractional-N phase locked loops, where it is critical to choose the frequency plan carefully to avoid unwanted frequency spurs. High frequency implementations of these phase locked loops use mixers for dividing down in frequency and harmonic mixers can be used very effectively in these designs to limit unwanted frequency spurs. 6.2 CMOS Subharmonic Mixers The Gilbert cell mixer topology can be implemented using CHMOS devices too. and the the quadratic nature of the devices as opposed to the exponential behaviour of bipolar devices lends this impiemn-entation for better linearity when compared to bipolar active mixers carrying the same current. One drawback with CMIOS active mixers is that they tend to have significantly higher noise figure than their bipolar counte rparts. 83

The subharmonic mixer discussed so far in bipolar implementations can be adapted for CMOS processes also. Fig. 6.1 shows a CMOS version of the linear SDB1 topology. V c', T I VRF - Ml M M2 RF I Figure 6.1: Circuit topology for a CMOS subharmonic mixer Transistors M1-M2 form the RF section. which is a linear transconductance stage. This transconductance stage is more linear than a regular differential pair with a tail current source [27j. This can be seen from the following equations. The differential small signal output current for a differential pair with a tail current source of Ibias is: 84

-out = 2- W n t 1-.3: 0-L f pC.ox ~ where.?,, is the small signal differential output voltage. For the case of a linear transconductor shown above which contains two idential common-source MOSFET's biased at the same I 4 and driven by a signal v', whose amplitude is less than 2(I Iq - I T. the differential output current is given by: out = 2CL, (Igs -- T)n (6.4) which has a linear relation to the differential input signal. Transistors M3-M1(0 form the LO switching section. MIOS technology devices typically have much lower transconductance than their bipolar counterparts and the gain from the linear transconductance stage will not be very high. To get a decent amount of gain from the mixer. active loads need to used for low-voltage implementations. Nli1-M12 form the active loads for the mixer. and M13-M14 are necessary to deal with the high voltage swing at the output of the mixer. M13-M14 are biased in the linear region and act as MOS resistors and the center-tap is used to fo-ce the common-mode voltage to an optimal point for the output swing through a common-mode feedback network. 6.3 Active Quadrature LO Generation As was seen in this thesis, generating a quadrature LO signal is essential for the operation of active subharmonic mixers. The implementations shoIwn in Chapters 4 and 5 utiiize passive RC-networks in thile form of polyphascl filters to generate the requisite quadrature LCO signals. This method has tvwo disadvantages. One. the polyphase filter has considerable amount of voltage loss '6 dB ideally at resonance. more practically) 85

and the limited LO power available that is lost in the passive network needs to bc boosted again using LO buffers which can consume quite a bit of power. Secoind. as the frequencies of operation of receivers go up. the R.C component sizes in the polyphase filter network go down and it will be increasingly difficult to obtain these components with acceptably accurate resistance and capacitance. Active quadrature LO generation solves both these problems. Jose Cabanillas' excellent work [28] in quadrature VCO design here at the Universitv of Michigan would be a good method of generating quadrature LO signals. The beauty of this approach is that for an integrated receiver with on-chip VCO to generate the LO signal. the quadrature signals are directly available and just need to be buffered (for isolation) before being delivered to the mixer. Care should be taken in layout to ensure that both the I-phase and Q-phase path of the LO have the same parasitic effects on the way to the mixer. There have been several other implementations of quadrature VCO's in literature![29].30,[311.[321 that can also be used. Using a quadrature VCO along with a subharmonic mixer provides an attractive way of implementing a fully-integrated direct downconversion receiver.

BIBLIOGRAPHY

BIBLIOGRAPHY [1] B. Matinpour, C. Chun. S. Han. C. H. Lee, and J. Laskar, "A compact monolithic C-band direct conversion receiver." IEEE Microwave and Guided Wave Letters. vol. 21. no. 6. pp. 921-929. 2000. [2] Takafumi Yamaji and Hiroshi Tanimoto, "A 2 GHz Balanced Harmonic Mixer for Direct-Conversion Receivers." Proceedings of the 1997 Custom Integrated Circuits Conference. 1997. [3] Liwei Sheng. Jonathan C. Jensen. and Lawrence E. Larson, "A Wide-Bandwidth Si/SiGe HBT Direct Conversion Sub-Harmonic Mixer/Downconverter. IEEE Journal of Solid Sate Circuits. vol. 35. no. 9, pp. 1329-1337. Sept 2000. [4] Kyeongho Lee, Joonbae Park. Jeong-Woo Lee. Seung-Wook Lee. Hyung Ki Huh. Deog-Kyoon Jeong. and Wonchan Kim. "A Single-Chip 2.4 GHz DirectConversion CMOS Receiver for Wireless Local Loop using Multiphase Reduced Frequency Conversion Technique." IEEE Journal of Solid State Circuits. vol. 36. no. 5. pp. 800-809. May 2001. []1 Barrie Gilbert. "The Multi-tanh Principle: A Tutorial Overview.'' IEEE Journal of Solid State Circuits. vol. 33. no. L, pp. 2-17, January 1998. [6] Farbod Behbahani. John C. Leete. Yoji Kishigami. Andreas Roithmeicr. Koichi Hoshimo. and Asad A. Abidi. "A 2.4-GHz Low-IF Receiver for Wideband NWLAN in 0.6-/lm CMOS - Architecture and Front-End." IEEE Journal of Solid-State Czrcuits. vol. 35. no. 12. pp. 1908-1916. December 2002. [7] Jan Crols and Michel S. J. Steyaert. "A single-Chip 900 MHz CMOS Receiver Front-End with a High Perfromance Low-IF Topology," IEEE Journal of SolidState Circuits. vol. 30. no. 12. pp. 1483-1492. December 1995. [8] Gabriel M. Rebeiz and Kiran Nimmagadda. "Subharmonic Double-Balanced lixer," United States patent 6.348.830. February 2002. [9] Stephen A. Mlaas. Micorwave Mizzers. Artech House. 1993. [10] H. 1. Fujishiro. "SSB NIMIC mixer with subharmonic LO and CPNW circuits for 38 GHz band applications." Electronics Letters. vol. 37. no. 7, pp. 435-436. Mar 29 2001. 88

f[1' Yon-Lin Kok. Huei Wang. Mike Barsky. Richard Lai. Mike Sholiev. and Barrv Allen. "180 GHz sub harmonic InP-based hemt diode mixer." IEEE li? `ronu'(., and Guided letters. vol. 9. no. 12. pp. 532-534. 1999. [121 Mitsuhiro Shimozawa. Kenji Kawakami. Hiroshi Ikematsu. Kenji Itoh. Nobuvuki Kasai. Yoji Isota. and Osami Ishida. "IMonolithic even harmonic quadrature mixer using balance type 90 degree phase shifter for direct conversion receiver. Proceeedings of the 1998 IEEE Radio Frequency Integrated Circuits Symrposrum. 1998. [131 Babak Matinpour. Sudipto Chakraborty. and Joy Laskar. "Novel DC-OffseT, Cancellation Techniques for Even-Harmonic Direct Conversion Receivers." IEEE Transactions on Microvave Theory and Techniques. vol. 21. no. 11. pp. 1777 -1786. Nov 2000. [14j Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integratec Circuits. John Wiley. Inc.. 1997. [15' S. Ashok. "Integrable Sinusoidal Frequency Doubler" IEEE Journal of SolidState Circuits. pp. 341-343. April 1976. [161 Katsuji Kimura and Hiroshi Asazawa. "Frequency Mixer with a Frequency Doubler for Integrated Circuits." IEEE Journal of Solid-State Circuits, vol. 29. io. 9. pp. 1133-1137. September 1994.. [171 R. G. Meyer. W. D. Mack. and J. J. E. M. Hageraats. "A 2.5 GHz BICMIOS Transceiver for Wireless LAN's." IEEE J. Solid-State Circuits. vol. 32. pp. 2097 -2104. Dec 1997. [181 GGB Industries. http://www.ggb.com/diffprb.html. Picoprobc differcntzia probes. [197 Kiran Nimmagadda and Gabriel M. Rebeiz. "A 1.9 GHz Subharmonic Double Balanced MLxer for Direct Conversion Applications." in IEEE RFIC Synrposzum. May 20C01. [201 Keng Leong Fong and Rober) G. Mever. "High-frequency Nonlinearity Analysis of Common-Emitter and Differential-Pair Transconductance Stages." IEEE Journal of Solid State Czrcuits. vol. 33. no. 4. pp. 548-555. April 1998. [21' John R. Long and Miles A. Copeland. "A 11.9 GHz Low-Voltagc Silicon Bipolar Reciever Front-End for Wireless Personal Communications Systems." IEEE Journal of Solid State CZrcuHts. vol. 30. no. 12. pp. 1438-1448. December 1995. [o22 Keng Leong Fong. Designr and Optzrnization Techniques_ for Mlonolithic IRF Downconversion Mixers. Ph.D. thesis. University of California. Berkeley. 1997. 723] Chris D. Hull. Analysis and Optimization of Monolithic RF Downconvcrsion Receizers. Ph.D. thesis. University of California. Berkeley. 1992. 89

V[24 Keng L. Fong and Robert G. lever. "A Class AB lonolithic Mixer for 900 MIHz Applications." IEEE Journal of Solid-State Circuits. vol. 32. no. S. pp. 1166-1172. August 1997. [251 Keng L. Fong and Robert G. Meyer. "A 2.4 GHz Monolithic Mlixer for Wireless LAN Applications." in IEEE Custom Integrated Circuits Conference. May 1997. pp. 941-944. [26 R. G.:Meyer. "Intermodulation in high-frequency bipolar transistor integratedcircuit mixers." IEEE J. Solid-State Circuits. vol. SC-21. pp. 534-537. Aug 1986. [27] Ahmedreza PRofougaran. James Y.-C. Chang, Maryam Rofougaran. and Asad A. Abidi. 'A 1 GHz CMOS RF Front-End IC for a Direc-Conversion Wireless Receiver.'? IEEE Journal of Solid-State Circuits. vol. 31. no. 7. pp. 880-889. July 1996. [2)8 Jose Cabanillas. Laurent Dussopt. Jose M. L6pez-Villegas. and Gabriel MI. rebeiz. "A 900 MHz Low Phase Noise CMOS Quadrature Oscillator." in Proceedings of IEEE RFIC Symposim. May 2002. [29] C. J. M. Verhoeven. "A High-Frequency Electronically Tunable Quadrature Osillator." IEEE Journal of Solid-State Circuits. vol. 27. no. 7. pp. 1097-100. July 1992. [30] Ayman MI. ElSayed and Mohamed I. Elmasrv. "Low-Phase-Noise LC Quadrature V\CO Using Coupled Tank Resonators in a Ring Structure." IEEE Journal of Solid-State Circuits. vol. 36. no. 4. pp. 701-705, April 2001. [31] Marc Tiebout. "Low-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMIOS.".EE Journal of Solid-State Circuits. vol. 36. no. 7. pp. 1018-1024. July 2001. [32j Peter Vancorenland and Michiel S. J. Stevaert. "A 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO." IEEE Journal of Solid-State Circuits. vol. 37. no. 5. pp. 653-656. M\ay 2002. 90