Micromachined High-Q RF Filters and Resonators for Communication Filters Annual Report and Final Report to ARO Attention: Dr. Jim Harvey ARO AASERT By Linda P.B. Katehi The University of Michigan Ann Arbor, MI 48109-2122 July 1999 36963-1-T = RL-2511 I

Contract Number: DAAH04-96-1-0109 Contract Title: Micromachined High-Q RF Filters and Resonators for Communication Systems Final Reporting Period: June 1, 1998- May 31,1999 Graduate Students Partially Funded by this Program: Lee Harlee John Papapolymerou, Sergio Pacheco Katherine Herrick Faculty: Prof. Linda P.B. Katehi Comments: John Papapolymerou received his Ph.D in February 1999. He is now in University of Arizona as an Assistant Professor. Publications: 1. Lee Harle, John Papapolymerou, Jack East, Linda P.B. Katehi, The effect of slot positioning on the bandwidth of a micromachined resonator, 28th European Microwave Conference Proceedings, Oct. 1998, vol. 2, pp. 664-668. 2. R. F. Drayton, S. Pacheco, J-G. Yook, and L. P.B. Katehi, Micromachined Filters on Synthesized Substrates, IEEE M TT-S International Microwave Symposium Digest, Baltimore, MD, Vol.3, pp. 1185-1188, 1998. 3. Linda P.B. Katehi, Microtechnology in the Development of Three-Dimensional Circuits, presented in Microwaves and RF '98, October 1998, London UK. 4. Linda P.B. Katehi and Katherine Herrick, Si Micromachining for High-Frequency Circuits, Invited paper, ESA Workshop on Millimeter-Wave Technology and Applications, ESPOO, Finland, May 27-28, 1998. Technology Insertion: 1. The concept of High-Q Filters developed under this contract has now been extended to develop multipole filters and diplexers for communication systems. Specifically this concept is further developed for JPL/CISM for the development of the first miniaturized RF Front End. 2. The same concept has been extended to the development of Evanescent Mode Filters. This activity is now funded by DARPA. Patents: This concept has been patented recently. US Patent: 5,821,836 Appendices: 1. Appendix A: John Papapolymerou, Ph.D. Dissertation 2

2. Appendix B: Lee Harle, John Papapolymerou, Jack East, Linda P.B. Katehi, The effect of slot positioning on the bandwidth of a micromachined resonator, 28th European Microwave Conference Proceedings, Oct. 1998, vol. 2, pp. 664-668. 3. Appendix C: R. F. brayton, S. Pacheco, J-G. Yook, and L. P.B. Katehi, Micromachined Filters on Synthesized Substrates, IEEEM TT-S Internationl Microwave Symposium Digest, Baltimore, MD, Vol.3, pp. 1185-1188, 1998. 4. Appendix b: Linda P.B. Katehi, Microtechnology in the Development of ThreeDimensional Circuits, presented in Microwaves and RF '98, October 1998, London UK. 5. Appendix E: Linda P.B. Katehi and Katherine Herrick, Si Micromachining for HighFrequency Circuits, Invited paper, ESA Workshop on Millimeter-Wave Technology and Applications, ESPOO, Finland, May 27-28, 1998. 3

Project Summary Linda P.B. Katehi Radiation Laboratory Department of Electrical Engineering and Computer Science The University of Michigan Ann Arbor, MI 48109-2122 Summary The use of millimeter-wave technology in military and commercial applications has drawn the attention of the microwave community for more than three decades due to its advantages over other bands of the electromagnetic spectrum, as well as the lack of frequencies for new services. Since the size of any microwave circuit or component is dictated by the frequency of operation, implementation of the millimeter-wave region (30-300 GHz) can result in very small systems. This is extremely important for airborne and space applications, where launch and deployment costs depend heavily on the volume of the system that is to be deployed. Furthemore, millimeter-waves allow for antennas with high gain and directivity that are essential for point-to-point communication systems (e.g. between a satellite and an earth base station) and radars. For space and airborne applications attenuation through the earth's atmosphere is a major consideration. In general, the attenuation of the microwave energy increases with frequency with the exceptions of a few minima that occur at 35 GHz, 94 GHz, 140 GHz, 220 GHz etc. These "windows" of minimum atmospheric absorption make millimeter-wave. systems ideal for such applications. In addition, millimeter-waves unlike infrared and optical wavelengths have the ability to permeate fog, dust and smoke. Commercial applications of millimeter-wave systems include short-haul line-of-sight transmission links for personal communication networks (PCN's) that operate at 38 GHz, wireless cable at 28 GHz, wireless radio local area networks (LAN's) and mobile broadband systems. In recent years, research reports have also focused on automotive radar sensors for anti-collision radars at 77 GHz, intelligent cruise control and road transport informatics. Aircraft landing systems and earth remote sensing are other areas where millimeter-waves have been employed. The latter is of major significance due to the intense environmental studies currently under way and the changing conditions of our planet. Of course, military communication systems and radars as well as satellite communications were the first applications of millimeter-wave systems. Until the early 80's most of the millimeter-wave components and systems were built with waveguide technology (rectangular or cylindrical). Waveguides provide very lowloss, high quality factor circuits but are bulky and heavy thus imposing cost limitations on airborne and space systems. In addition, waveguide components are expensive to manufacture since they have to be precision machined one at a time, and at higher operating frequencies their fabrication complexity increases. The bandwidth of such systems is also limited by the operational bandwidth of the waveguides that are used. With the maturity of integrated circuit (IC) fabrication techniques and the increased need for high circuit 4

integration and compact designs, the microwave community has started focusing its improved reproducibility and reliability. Moreover, MMIC's can allow for broad-band operation if designed properly and easy integration of active devices such as diodes and transistors. As a result, entire communication and radar systems can now be fabricated on a single planar substrate or a multi-layered chip with vertical interconnects connecting the various layers. The operating frequency can also be increased, thus satisfying the high demand for new spectrum bands. As system requirements for faster data transmission in lighter compact designs drive the technology area, higher frequency design solutions with large density layouts that include radiating elements, passive circuitry, oscillator sources and have light weight, small size and optimum performance, are required. Such a design can be seen in Fig. 1.1 of appendix A and represents a monolithic transmit/receive system that operates at higher frequencies (Wband) and constitutes the RF front end of any communication or radar system. The transmitter includes a frequency multiplier that translates a lower frequency signal into a much higher one, an amplifier that increases the output power of the multiplier and an antenna that radiates the incoming energy. At the receiver, the high frequency signal captured by the antenna is amplified by a low noise amplifier (LNA) and is then down converted to a much lower one by a sub-harmonic mixer. For isolating a particular frequency spectrum, narrow band filters and diplexers can be implemented either right after the antenna or at other stages of the receiver. On-wafer packaging that reduces interaction between the different components and offers electrical and mechanical protection, as well as a means for heat dissipation, to both the transmitter and receiver can also be achieved. All of the passive and active components, including the package, can be fabricated on Silicon or GaAs substrate with standard integrated circuit fabrication techniques that would significantly lower the total cost. MMICs have the advantage of small size and weight, that further decrease the cost of airborne and space applications, low fabrication cost since they can be batch fabricated using standard IC techniques and MMIC's are designed and fabricated using planar circuit technology that usually implements two types of transmission lines: the microstrip line (Fig. 1.2(a)) and the coplanar waveguide (CPW). The air-dielectric interface that exists in both of these lines introduces several parasitic effects that are pronounced as the operating frequency increases. These effects include increased dielectric loss, substrate moding where the power can propagate inside the substrate in the form of unwanted modes, and dispersion. As a result, MMIC's operating at high frequencies (W band) can have some important limitations. These limitations are augmented by the non-availability of higher frequency solid-state oscillator sources that are difficult to fabricate. These sources are very important for heterodyne receiver applications where an incoming high frequency (RF) signal is down converted to a much lower frequency (IF) signal. The objective of this thesis is to find techniques that address these limitations encountered in planar, monolithically integrated passive and active circuits operating at higher frequencies (W band), with the goal of designing a monolithic One of the solutions to the restrictions imposed in passive MMIC's, makes use of the micromachining techniques. Micromachining is a technology widely used in the development of micro-electro-mechanical systems (MEMS), sensors and actuators and its implementation in the microwave field is relatively new. The first 5

application in microwave circuits was that of membrane supported antennas for imaging arrays. Other developments on antennas reported since then include microstrip patches suspended on a dielectric membrane over air or sitting on a substrate with periodically spaced holes in order to increase the radiation efficiency. Regarding planar resonators and filters, micromachining was used to suspend microstrip and CPW resonators on membrane in order to increase the quality factor and achieve filter designs with very narrow bandwidth and very small loss. With the trend to incorporate all microwave components on a single chip, as is the case of a monolithic transmit/receive system, there is an increased need to build high-Q resonators that can be monolithically integrated with the rest of the circuitry on the same substrate. High-Q resonators are the building blocks for narrow-band, low-loss filters that are used mainly in communication and radar systems. Traditionally, for microwave frequencies these resonators are made of rectangular and cylindrical metallic waveguides that offer very low loss and flexibility in tuning by inserting backshorts and screws. Waveguides, however, are heavy, large (especially at lower frequencies) and costly to manufacture since each component must be precision machined one at a time. In addition, waveguides do not allow for an easy integration with monolithic circuits and active devices. The implementation and maturity of micromachining techniques in the fabrication of microwave and millimeter-wave circuits allows us now to make miniature silicon or 6aAs micromachined waveguides or cavities that can be used for the fabrication of high- Q bandpass filters and multiplexers. The quality factor that can be achieved with this technique is much higher than the quality factor of traditional planar microstrip or stripline resonators either printed on a dielectric material or suspended in air with the help of a dielectric membrane. The latter type of resonators can give filters with less than 1 dB insertion loss and bandwidths exceeding 10%. This chapter discusses the development of a silicon micromachined high-Q X-band resonator that consists of a cavity, input and output microstrip lines and coupling slots. Experimental results of the performance of the resonator are shown and compared with simulations performed by Jui-Ching Cheng. In addition, the quality factor of the resonator is evaluated based on s-parameter measurements. The effects of different ambient temperatures and the positioning of the slots relative to the center of cavity on the response of the resonator are also presented and analyzed, as well as some on-wafer packaging considerations. An extensive study of these resonators is presented in Appendices A-E. 6

Appendix A: John Papapolymerou, Ph.D. Dissertation 7

MMIC PASSIVE AND ACTIVE STRUCTURES by Ioannis Papapolymerou A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in The University of Michigan 1999 Doctoral Committee: Professor Linda P.B. Katehi, Chair Associate Professor Kamal Sarabandi Professor Duncan G. Steel Research Scientist Jack R. East

~ Ioannis Papapolymerou 1999 All Rights Reserved

To my beloved mother, Areti-Eleni Spiliopoulou ii

ACKNOWLED GEMENTS I would like to thank my advisor, Professor Linda Katehi, for providing me with the opportunity to conduct this Ph.D. research. Her guidance, support, mentoring, encouragement, professionalism and enthusiasm for research made this difficult journey much easier and will always provide a source of inspiration and a guiding light for any future ventures. I am also grateful for her continuous financial support that allowed me to complete my work and attend several conferences. Furthermore, I am grateful to Professor Kamal Sarabandi, Professor Duncan Steel, and Dr. Jack East for serving on my dissertation committee along with Professor Katehi, and for their advice and counsel during this difficult process. I would also like to thank Professor Gabriel Rebeiz for the very useful and enlightening conversations on numerous scientific issues and Professor George IIaddad for his moral support all my years at the University of Michigan. I am deeply indebted to Dr. Imran Mehdi and Lorene Samoska of the Jet Propulsion Laboratory for the generous donations of numerous masks necessary for my projects, as well as for the measurements of the D-band doublers and the long conversations regarding active structure problems. I would like to express my gratitude to Dr. James Harvey and the Army Reseach Office for sponsoring the major part of my work. Other sponsors include the Office of Naval Research, JPL and Texas Instruments. iii 111

During my first years at the Radiation Lab I benefited greatly from the guidance, support and friendship of several "senior" students: Prof. George Eleftheriades, Dr. Walid AliAhmad. Dr. Apostolos Samelis, Prof. Thomas Weller, Dr. Chen-yu Chi, Prof. Rhonda Franklin-Drayton. Dr. lIristos Anastassiou, Dr. Gildas Gauthier, Prof. Sanjay Raman, Prof. Manos Tentzeris, Dr. Jui-Ching Cheng, Dr. Jong-Gwan Yook and Dr. Steven Robertson. Their impact on my life and career will always be remembered. Special thanks go to my officemate, Dr. Rashaunda Henderson, for her friendship all those years and the fruitful conversations on various issues of life and work. It has also been a privilege and a pleasure to work with so many talented students of Profs. Katehi and Rebeiz: Kavita Goverdhanam, Katherine IIerrick, Lee IIarle, James Becker, John Shumpert, Sergio Pacheco, Kyoung Yang, Kevin Lu, Costas Sarris, Rob Robertson, Eray Yasan, Bill Chappell, Thomas Schwarz, Saqib Jalil, N. Scott Barker, Tom Ellis, Joe IIayden and Jeremy Muldavin. I have enjoyed their company and learned much from them. I wish them success in their future endeavors. Especially, I would like to thank Leo DiDomenico and Andy Brown for their help and support during the last few weeks of my work. In addition, I would like to thank all those people in the Solid-State Electronics Lab that provided their technical expertise on several issues and with whom I shared endless fabrication time in the clean room: Dr. Bishnu Gogoi, Prof. Navid Yazdi, Dr. Doug Craig, Egor Alekseev, Don Sawdai, Erik Berg, Cheng-IIui Lin, HIerte Gebretsadik, Dimitris Papageorgiou, Tim Brock, Christine Tom, Terre Briggs and James Kempf. Needless to say, that I would not have been able to finish this long and demanding journey without the administrative and moral support of the Radiation Laboratory staff, past and present: Janice Rosan, Carol Truszkowski, Sharon Ryder, Michelle Shepherd, iv

Catherine Brown. and Patti Wolfe. To Peter, Mary and Stacy Karamanos I would like to express my appreciation for their love and support. To my mother, Areti-Eleni Spiliopoulou, I cannot find the words to express my deepest gratitude and love for devoting her entire life in my up-bringing and well being, teaching me wrong from right, supporting my career plans and encouraging me in difficult times. Finally, I would like to thank my wife, Jackie Karamanos, who has been a constant source of strength, courage, love and inspiration for all my years as a graduate student, and without whom I would not have fulfilled my dreams. v

TABLE OF CONTENTS DEDICATION....................................... ii ACKNOWLEDGEMENTS................................... iii LIST OF TABLES........................................ viii LIST OF FIGURES..................................ix LIST OF APPENDICES............................... xiii CHAPTERS 1 INTRODUCTION......................................... 1 1.1 M otivation..................................1 1.2 Silicon Micromachining................................ 6 1.3 Schottky Barrier Diode................................ 9 1.4 Measurement Techniques...............................15 1.5 Sim ulation Tools............................ 18 1.6 Dissertation overview.......................... 20 2 MICROMACIIINED PATCH ANTENNAS................................. 24 2.1 Introduction................................. 24 2.2 Reduction of the Effective Dielectric Constant (Technique I).... 26 2.2.1 Review of Technique.......................... 26 2.2.2 Theory of Radiation Efficiency.......................28 2.2.3 Ku-Band Micromachined Patch Antenna.................31 2.2.4 Efficiency Measurements........................ 34 2.3 Elimination of TMo Surface Wave (Technique II)................41 2.3.1 Theoretical Analysis........................... 41 2.3.2 Results.............................. 44 2.4 Conclusions................................... 45 3 MICROMACIIINED RESONATORS......................... 47 3.1 Introduction............................... 47 3.2 X-Band Micromachined Resonator........................ 48 3.2.1 Design and Fabrication.......................... 48 3.2.2 Theoretical and Measured Results.....................51 vi

3.3 3.4 Thermal Testing..................... Effects of Slot Positioning on Resonator Performance 57 60 62 3.5 Conclusions 4 GaAs MONOLITHIC MULTIPLIERS... 4.1 Introduction............. 4.2 Study of FGC lines......... 4.2.1 Fabrication......... 4.2.2 Results and Discussion... 4.3 W-Band Doublers.......... 4.3.1 Analysis and Design.... 4.3.2 Measurement System.... 4.3.3 Results and Discussion... 4.3.4 A Four Diode Design.... 4.3.5 Improved Designs...... 4.4 Conclusions............. 5 W-BAND MONOLITHIC MIXER.............. 5.1 Introduction...................... 5.2 Mixer Analysis and Design.............. 5.3 Results......................... 5.4 Conclusions...................... 6 CONCLUSIONS AND FUTURE WORK.......... 6.1 Conclusions...................... 6.2 Future W ork...................... 6.2.1 W-Band Micromachined Antennas..... 6.2.2 Micromachined IIigh-Q Filters and Diplexers 65 65 67 69 70 77 77 82 88 99 106 111 114 114 115 129 133 136 136 139 139 139 141 142 143 145 167 6.2.3 6.2.4 6.2.5 Improved and New Multipliers........ Sub-millimeter Wave Multipliers...... Monolithic Transmit/Receive Modules... A PPEN D ICES...................................... BIBLIOGRAPHY.................................... vii

LIST OF TABLES Table 1.1 Etch rates of different chemicals for SiO2 and Si3N4............. 8 2.1 Dimensions of the fabricated scaled model and regular antennas............ 33 2.2 Input impedance characteristics of the regular and scaled model antennas. 34 2.3 De-embedded efficiency for the scaled model and regular patch antennas at resonance..................................... 39 2.4 Efficiency results and dimensions for two scaled model antennas on duroid substrate with E,=10.8.................................... 40 2.5 Dimensions for the cored and conventional patch that were used in the FDTD sim ulations...................................... 44 3.1 Comparison of measured Q for several resonators at X-band.............. 57 4.1 Geometrical characteristics for the fabricated lines.....................74 4.2 Geometrical characteristics for the Q=2 multiplier.....................81 4.3 Geometrical characteristics for the Q=3 multiplier.....................81 4.4 Measured DC characteristics for the W-band fabricated diodes............. 91 4.5 Geometrical characteristics for the Q=2 four diode doubler...............102 4.6 Measured DC characteristics per diode for the four diode doubler design.. 102 4.7 Geometrical characteristics for the improved Q=2 multiplier.............. 108 5.1 Measured DC characteristics for the mixer diodes................... 121 5.2 Measured characteristics of the shunt stubs used in the mixer design........... 123 5.3 Calculated values for the equivalent circuit model of Fig. 5.6(b)....... 128 A.1 Design parameters for the antennas on Silicon substrate.................151 C.1 PECVD SiXNy deposition..................................160 viii

LIST OF FIGURES Figure 1.1 Monolithic transmit/receive module for communication and radar systems. 4 1.2 Planar transmission lines: (a) microstrip and (b) coplanar waveguide (CPW). 5 1.3 Anisotropic etching profile and geometry for the -<100>- oriented silicon wafer. 7 1.4 Pyramidal pits of a -<100>- silicon wafer for: a) a rectangular etch mask pattern and b) a random etch mask pattern and long etching time....... 8 1.5 Equivalent circuit for the Schottky-barrier diode................... 11 1.6 I-V characteristic of a Schottky diode on a semi-log plot............ 12 1.7 a) Disk type diode for MMIC applications and b) cross section of diode showing different components of the series resistance (from [14])......... 14 2.1 Geometry of the micromachined patch antenna.................. 27 2.2 Text fixture with micromachined antenna mounted................... 32 2.3 Measured return loss for the scaled model patch antenna reff=2.3 (etched) and regular patch antennas E,=2.2 and er=10.8.....................33 2.4 (a) E-plane and (b) II-plane radiation patterns for the three antennas under test............................................ 35 2.5 System diagram of the efficiency measurement setup.............. 36 2.6 Measured efficiency for the scaled model and regular patch antenna designs. 37 2.7 Measured efficiency versus the ratio of the distance c over the substrate thickness t.......................................... 38 2.8 Micromachined antenna for the elimination of TMo mode.............. 41 2.9 Surface wave field pattern for the regular antenna and the micromachined antenna................................................ 43 2.10 Normalized electric field inside the dielectric versus distance from the center of the antenna for the micromachined (cored) patch and regular patch..... 45 3.1 The X-Band micromachined resonator...................... 49 3.2 The structure of the proposed micromachined bandpass filters............... 50 3.3 CPW-to-microstrip transition for 500pm thick silicon substrate......... 51 3.4 Measured results for a 50 Q microstrip line that implements the transition of Fig. 3.3................................................ 52 3.5 Fabricated X-band resonator on two 500pm silicon wafers.............. 53 3.6 Simulated and measured results for the resonator of Fig. 3.1: (a) return loss and (b) insertion loss........................................ 54 ix

3.7 Measured and simulated S-parameters for the resonator of Fig. 3.1 around resonance................................................ 55 3.8 Computed z-component of the electric field density on the bottom of the cavity (from Jui-Ching Cheng [1])........................... 56 3.9 Measured insertion loss of the micromachined resonator under different temperatures....................................... 58 3.10 Measured and simulated results for the resonator with the slots positioned at 1/8L and 3/8L................................. 61 3.11 Measured results for the two resonators with different slot positions..... 62 3.12 Micromachined resonator with on-wafer packaging................... 63 3.13 Simulation results fot the packaged and non-packaged resonator......... 63 4.1 FGC lines on GaAs with a polyimide overlay....................... 69 4.2 Effective dielectric constant vs. frequency for the various FGC lines..... 72 4.3 Attenuation per physical length vs. frequency for the various FGC lines... 72 4.4 Attenuation per guided wavelength vs. frequency for the various FGC lines. 73 4.5 Attenuation per guided wavelength for lines on GaAs with different Zo... 75 4.6 Attenuation per guided wavelength for lines on quartz with different Zo.. 75 4.7 Attenuation per guided wavelength vs. characteristic impedance Zo for lines on GaAs and quartz at three different frequencies: fi=19.1 GIIz, f2=50 GIlz and f3=94 GIIz................................... 76 4.8 Block diagram of the doubler configuration (from F. Brauchler [2])........ 77 4.9 Multiplier configuration with passive circuits....................... 80 4.10 Libra simulation for the W-band multipliers: (a) circuit schematic and (b) harmonic balance analysis test bench............................ 83 4.11 Simulation results for the W-band multipliers: (a) efficiency vs. input frequency with an input power of 20 and 17 dBm for Q=2 and 3, respectively and (b) output power vs. input power at f=39.7 and 38.7 GIIz for Q=2 and 3, respectively............................................. 84 4.12 Block diagram of the measurement system used to evaluate the performance of W-band doublers......................................... 85 4.13 Photograph of the actual system that was used for the multiplier measurements. 86 4.14 Output power vs. frequency of the TWT measured at the flange of the waveguide system for a fixed position of the attenuator............. 87 4.15 Fabricated Q=3 W-band doubler............................... 89 4.16 SEM photo of fabricated Schottky diode..................... 90 4.17 Doping profile for the wafer used to fabricate the W-band doublers..... 90 4.18 Total capacitance vs. bias voltage for the Q=2 and Q=3 diodes......... 91 4.19 Measured results for the Q=2 doubler: (a) efficiency and return loss vs. frequency for an input power of 20 dBm and (b) output power and efficiency vs. input power at 76.3 GIIz................................ 92 4.20 Simulated results for the Q=2 and Q=3 doublers with measured diode DC parameters and input power of 20 and 17 dBm, respectively......... 94 4.21 Simulated return loss for the Q=2 and Q=3 doublers with measured diode DC parameters and input power of 20 and 17 dBm, respectively......... 95 x

4.22 Measured results for the Q=3 doubler: (a) efficiency and return loss vs. frequency for an input power of 17 dBm and (b) output power and efficiency vs. input power at 70 GIIz...................................96 4.23 Theoretical analysis for the diode bandwidth: a) equivalent circuit model and b) results based on equation 4.6..............................98 4.24 Multiplier configuration with passive circuits and four diodes.............. 100 4.25 Simulated results for the four diode doubler: a) efficiency vs. input frequency for an input power of 20 dBm and b) output power vs. input power at 41.25 G Iz............................................... 101 4.26 Photograph of the fabricated four diode doubler................. 103 4.27 SEM photo of two diodes in series............................ 103 4.28 Efficiency and return loss vs. output frequency of the four diode doubler for an input power of: a) 20 dBm and b) 23 dBm............................... 105 4.29 Output power and efficiency vs. input power at 74 GI1z for the four diode doubler............................................. 107 4.30 Simulation of four diode doubler including the measured diode characteristics for an input power of 20 dBm.............................. 107 4.31 Simulated results for the output circuit of the doubler with the wide (new) and narrow (old) stubs................................. 109 4.32 Efficiency and return loss vs. output frequency for doublers fabricated on a new wafer and Pi,=20 dBm: a) improved Q=2 design and b) old Q=2 design.110 5.1 Schematic of the monolithic FGC based sub-harmonic mixer (from S. Raman [93])......................................... 116 5.2 SEM photograph of: a) back-to-back diodes with 2pm diameter and b) channel under the diode fingers................................ 119 5.3 Current-voltage characteristic of the anti-parallel pair of Schottky diodes used in the mixer design................................... 120 5.4 Measured capacitance versus bias voltage for a single mixer diode with curvefitted data..................................... 120 5.5 Measured S-parameters for the: a) LO grounding stub and b) the RF grounding stu b....................................... 122 5.6 RF bandpass filter used in the mixer design: a) circuit layout for two stub sections and b) equivalent circuit model for one stub section............. 125 5.7 S-parameters vs. frequency for the mixer bandpass filter: a) measured and IE3D simulated data and b) IE3D simulated and Libra equivalent circuit data. 126 5.8 Libra simulation for the x2 subharmonic mixer: a) circuit schematic and b) harmonic balance test bench................................127 5.9 Conversion loss vs. RF frequency for different LO power levels.............129 5.10 Fabricated FGC line monolithic mixer...........................130 5.11 Block diagram of the system used for the mixer measurements............ 131 5.12 Measured and simulated data for the diode with Rs = 40Q: a) SSB conversion loss vs. RF frequency for optimum LO power and b) SSB conversion loss vs. LO power at fRF = 80GIIz........................ 132 5.13 Simulated and measured results for the RF/LO and LO/IF isolation of the mixer versus LO frequency................................ 134 6.1 Conceptual diagram of a monolithic micromachined diplexer............. 140 xi

6.2 Micromachined FGC lines ([3])...................................... 142 6.3 Conceptual block diagram of a monolithic multiplier/mixer pair with FGC line technology for on-wafer measurements........................ 143 A.1 Capacitor model for the micromachined patch with (a) the radiating edges into the high-index substrate and (b) with the radiating edges over the mixed air-substrate region.......................................... 147 A.2 Geometry of the micromachined patch antenna......................... 148 A.3 Effective dielectric constant vs. air-gap thickness for the silicon micromachined patch............................................ 148 A.4 Return loss measurement of the regular and micromachined patch antenna printed on a full thickness substrate and substrate with mixed air-silicon thickness ratio (1:1), respectively........................ 150 A.5 Radiation patterns for (a) the micromachined antenna on Silicon and (b) the regular antenna on Silicon..................................... 152 B.1 Cross section of the GaAs wafer used for the fabrication of active structures. 153 xii

LIST OF APPENDICES APPENDIX A QUASI-STATIC MODEL FOR TIIE EVALUATION OF TIIE EFFECTIVE DIELECTRIC CONSTANT AND EXPERIMENTAL RESULTS FOR 2 PATCI ANTENNAS ON SILICON........................... 146 FABRICATION PROCESS OF W-BAND AND D-BAND MULTIPLIERS 153 FABRICATION PROCESS FOR MONOLITHIC MIXERS AND MULTIPLIERS IN A TRANSMIT/RECEIVE MODULE............... 159 B C xiii * * Xlll

CHAPTER 1 INTRODUCTION 1.1 Motivation The use of millimeter-wave technology in military and commercial applications has drawn the attention of the microwave community for more than three decades due to its advantages over other bands of the electromagnetic spectrum, as well as the lack of frequencies for new services. Since the size of any microwave circuit or component is dictated by the frequency of operation, implementation of the millimeter-wave region (30-300 GIMz) can result in very small systems. This is extremely important for airborne and space applications, where launch and deployment costs depend heavily on the volume of the system that is to be deployed. Furthemore, millimeter-waves allow for antennas with high gain and directivity that are essential for point-to-point communication systems (e.g. between a satellite and an earth base station) and radars. For space and airborne applications attenuation through the earth's atmosphere is a major consideration. In general, the attenuation of the microwave energy increases with frequency with the exceptions of a few minima that occur at 35 GIIz, 94 GIIz, 140 GIlz, 220 GI~z etc. These "windows" of minimum atmospheric absorption make millimeter-wave 1

systems ideal for such applications. In addition, millimeter-waves unlike infrared and optical wavelengths have the ability to permeate fog, dust and smoke. Commercial applications of millimeter-wave systems include short-haul line-of-sight transmission links for personal communication networks (PCN's) that operate at 38 GILz. wireless cable at 28 GIIz, wireless radio local area networks (LAN's) and mobile broadband systems [4]. In recent years, research efforts have also focused on automotive radar sensors for anticollison radars at 77 GIlz. intelligent cruise control and road transport informatics. Aircraft landing systems and earth remote sensing are other areas where millimeter-waves have been employed [5]. The latter is of major significance due to the intense environmental studies currently under way and the changing conditions of our planet. Of course, military communication systems and radars as well as satellite communications were the first applications of millimeter-wave systems. Until the early 80's most of the millimeter-wave components and systems were built with waveguide technology (rectangular or cylindrical). Waveguides offer low-loss, high quality factor circuits but are bulky and heavy thus imposing cost limitations on airborne and space systems. In addition, waveguide components are expensive to manufacture since they have to be precision machined one at a time, and at higher operating frequencies their fabrication complexity increases. The bandwidth of such systems is also limited by the operational bandwidth of the waveguides that are used. With the maturity of integrated circuit (IC) fabrication techniques and the increased need for high circuit integration and compact designs, the microwave community has started focusing its attention on Monolithic Microwave/Millimeter-wave Integrated Circuits (MMIC's). MMICs offer the advantages of small size and weight, that further decrease the cost of airborne and space applications. low fabrication cost since they can be batch fabricated using standard IC techniques and 2

improved reproducibility and reliability. Moreover, MMIC's can allow for broad band operation if designed properly and easy integration of active devices such as diodes and transistors. As a result, entire communication and radar systems can now be fabricated on a single planar substrate or a multi-layered chip with vertical interconnects connecting the various layers [6], [7]. The operating frequency can also be increased, thus satisfying the high demand for new spectrum bands. As system requirements for faster data transmission in lighter compact designs drive the technology area, higher frequency design solutions with large density layouts that include radiating elements, passive circuitry, oscillator sources and have light weight, small size and optimum performance, are required. Such a design can be seen in Fig. 1.1 and represents a monolithic transmit/receive system that operates at higher frequencies (W-band) and constitutes the RF front end of any communication or radar system. The transmitter includes a frequency multiplier that translates a lower frequency signal into a, much higher one, an amplifier that increases the output power of the multiplier and an antenna that radiates the incoming energy. At the receiver, the high frequency signal captured by the antenna is amplified by a low noise amplifier (LNA) and is then down converted to a much lower one by a sub-harmonic mixer. For isolating a particular frequency spectrum, narrow band filters and diplexers can be impemented either right after the antenna or at other stages of the receiver. On-wafer packaging that reduces interaction between the different components and offers electrical and mechanical protection, as well as a means for heat dissipation, to both the transmitter and receiver can also be achieved. All of the passive and active components, including the package, can be fabricated on Silicon or GaAs substrate with standard integrated circuit fabrication techniques that would significantly lower the total cost. 3

Multiplier 1f \ ~Mixer Amplifier Filter/Diplexer Antenna Transmitter Receiver Figure 1.1: Monolithic transmit/receive module for communication and radar systems. MMIC's are designed and fabricated using planar circuit technology that usually implements two types of transmission lines: the microstrip line (Fig. 1.2(a)) and the coplanar waveguide (CPW) (Fig. 1.2(b)). The air-dielectric interface that exists in both of these lines introduces several parasitic effects that are pronounced as the operating frequency increases. These effects include increased dielectric loss, substrate moding where the power can propagate inside the substrate in the form of unwanted modes, and dispersion. As a result, MMIC's operating at high frequencies (WV band) can have some important limitations. These limitations are augmented by the non-availability of higher frequency solid-state oscillator sources that are difficult to fabricate. These sources are very important for heterodyne receiver applications where an incoming high frequency (RF) signal is down converted to a much lower frequency (IF) signal. The objective of this thesis is to find techniques that address these limitations encountered in planar, monolithically integrated passive and active circuits operating at higher frequencies (W band), with the goal of designing a monolithic 4

transmit/receive module that offers optimum performance and minimum cost. Signal line Substrate Ground plane (a) Ground Ou Signal line Substrate Ground plane (b) Figure 1.2: Planar transmission lines: (a) microstrip and (b) coplanar waveguide (CPW). One of the solutions to the restrictions imposed in passive MMIC's. makes use of the micromachining techniques. Micromachining is a technology widely used in the development of micro-electro-mechanical systems (MEMS), sensors and actuators [8] and its implementation in the microwave field is relatively new. The first application in microwave circuits was that of membrane supported antennas for imaging arrays [9]. Other developments on antennas reported since then include microstrip patches suspended on a dielectric membrane [10] over air or sitting on a substrate with periodically spaced holes [11] in order to increase the radiation efficiency. Regarding planar resonators and filters, micromachining was used to suspend microstrip and CPW resonators on membrane [12]- [13] in order to increase 5

the quality factor and achieve filter designs with very narrow bandwidth and very small loss. All of the previous mentioned examples illustrate the potential of micromachining to circumvent the problems associated with planar circuits operating at high frequencies. For active MMIC structures, frequency multipliers and mixers operating in W-band and D-band have been realized. Frequency doublers on GaAs using microstrip line technology with 25% efficiency at 94 GItz and 2.8% efficiency at 320 GIz have been reported [14]-[15]. A modified version of the CPW line, the Finite Ground Coplanar (FGC) line, was used to fabricate a 40/80 GIlz doubler with 15-16% efficiency and wide bandwidth [16]. A hybrid x2 subharmonic mixer on silicon with the diodes flip-chip bonded achieved a conversion loss of 7 dB at 94 GIIz [17]. The excellent results obtained with all of the above active MMIC structures demonstrate the capability to integrate active devices with passive circuits in planar environments at high operating frequencies with very good performance. 1.2 Silicon Micromachining Silicon has been used as a mechanical material in order to make miniature devices and components since the early 70's, with the first applications in the areas of sensors and transducers. The major process that gives silicon "chips" the various shapes and geometries is micromachining. When a silicon wafer is immersed in an appropriate chemical, then it starts to etch with the process depending on the etchant, the orientation of the wafer and the presence of dopants. The most commonly used etching systems are: a) ethylene diamine, pyrocatechol and water (EDP), b) KOII and water, c) IIF, IIN03 and acetic acid and d) Tetramethyl Ammonium Hydroxide in water (TMAII) [18],[19]. Except for IF-Nitric, all of these chemical etchants are anisotropic. This means that the etch rate strongly depends on the crystallographic orientation of the wafer. 6

Dielectric Etch Mask <100> <111> 2 L= t4.74 <100> Si wafer Figure 1.3: Anisotropic etching profile and geometry for the -<100>- oriented silicon wafer. The crystal lattice of the silicon wafer is described by the "Miller indices", which express directions and planes within the crystal using three integer numbers [20]. For EDP, KOII and TMAII the anisotropic behavior is due to the fact that -<111>- surfaces are attacked at a much slower rate than all other crystallographic planes (etch-rate ratios as high as 1000 have been reported). Fig. 1.3 shows the etching profile of a standard -<100>- oriented wafer, used for all of the work presented in this thesis. In this case, the etchant proceeds rapidly in all directions that are perpendicular and parallel to the surface of the wafer until the -<111>- planes become exposed, where the etching effectively stops leaving a. sloping side wall in the profile with a 54.740 angle [21]. Any rectangular hole oriented on the surface of the wafer in the -<110>- direction, will result in a pyramidal-shaped pit when an anisotropic etchant is used (Fig. 1.4(a)). If the silicon is etched long enough, any randomly shaped closed pattern will also result in a rectangular pit as seen in Fig. 1.4(b). The -<100>- silicon etch rate for EDP is approximately 1.2ym/min at 1100C, and for 22% TMAII solution it is 1.0Lm/min at 900C. An important factor in determining the appropriate etchant is its selectivity towards different masking films. For SiO2 and Si3N4 that are widely used as a mask etch the 7

<110> mask outline etch profile A <110> mask o - -- - ------- - - - -- ---- - - Dutline (a) (b) Figure 1.4: Pyramidal pits of a -< 100>- silicon wafer for: a) a rectangular etch mask pattern and b) a random etch mask pattern and long etching time. corresponding rates can be seen in Table 1.1 [22], [23]. From this table we observe that for long etches Si3N4 is preferred for KOII and IIF-IIN03, whereas for EDP and TMAII both dielectric films can be used. In addition, the etch rate for SiO2 in TMAII is almost four orders of magnitude lower than those of -< 100>- and -<110>- crystallographic directions, depending on the solution temperature and concentration. Etchant SiO2 (nm/min) Si3N4 (nm/min) IIF-IIN03 10-30 low EDP 1-80 low KOII 1-10 low TMAII 1 1-10 Table 1.1: Etch rates of different chemicals for SiO2 and Si3N4. 8

1.3 Schottky Barrier Diode The Schottky barrier diode has been used in numerous millimeter-wave mixer and multiplier applications since the early 70's. The rectifying or Schottky barrier type junction is formed by placing a metal of higher work function in intimate contact with an n-type semiconductor of lower work function [2]. Platinum, Ti and gold are the most commonly used anode materials for fabricating GaAs diodes [24]; gold and aluminum have also been used. although these materials have poor reliability. The size and shape of the anode are selected to give the appropriate electrical characteristics (junction capacitance and series resistance) for the intended application. The circular anodes of microwave and millimeter-wave diodes vary in diameter from less than 1.5 pum to 20,um. For practical reasons a large number of anodes are defined on the surface of a single chip and are isolated from each other by an oxide or nitride layer or by selective etching (mesa) around each diode. An ohmic contact is also formed on the substrate, and for GaAs alloyed gold- germanium is most commonly used. In thermal equilibrium, a depletion region forms within the semiconductor at the metal interface that is positively charged, since all of the mobile electrons are absent and only the ionized donor atoms are present. The width, W, of the depletion region assuming a uniform doping ND can be found by solving Poisson's equation to be [25]: 2E( Vb,- V) qND(1) where c is the dielectric constant of the semiconductor, ND is the doping concentration in the n- layer, q is the electric charge of the electron, Vb- is the built-in potential and V is the applied voltage at the anode. The charge Q, and capacitance XC, per unit area can be 9

evaluated from: Q = qNDW = /2q~ND(Vi - V) (1.2) __Q / qeNw _ e C Q \2(VbDV) W (1.3) Equation 1.3 can also be written as: Cj = C(V) = - (1.4) 1 vb, where Cjo is the zero bias capacitance given by: Cjo = NDC (1.5) The relationship linking the current, I, through the diode with the applied voltage NV, can be found with the help of thermionic emission-diffusion theory [25]: qV I = Is(e,,' - 1) (1.6) where Is = A"T2Se kT (1.7) In equations 1.6,1.7 n is the ideality factor of the diode, k is Boltzmann's constant. T is the temperature in Kelvin, 1~b is the barrier height, S is the junction area and Am is the effective Richardson constant which is approximately 4.4 Acm-2I2 for a metal-GaAs contact. The ideality factor, n, is an indication of how much the diode deviates from the perfect case (n=l) and is a measure of the quality of the junction. It is used to account 10

Figure 1.5: Equivalent circuit for the Schottky-barrier diode. for any type of imperfections in the junction and for phenomena that cannot be explained with the thermionic diffusion theory. Typical values of n range from 1.05 to 1.3. The equivalent circuit of a Schottky-barrier diode can be seen in Fig. 1.5 [24]. The diode consists of three elements, two of which, the junction capacitance and resistance, are non-linear. The junction resistance Rj accounts for the generation-recombination current, the diffusion current and the surface leakage current. The parasitic series resistance R, which is a result of the undepleted high resistivity epitaxial material, is also non-linear but varies slightly both in forward and reverse bias. In mixers and multipliers R, can be a very significant loss mechanism. One way to measure R, is to plot the diode I-V characteristic on semi-log coordinates. If there was no loss in the junction the I-V would follow the straight line, as indicated by equation 1.6. However, because of the loss (i.e. R,) the I-V characteristic deviates from the ideal line and the difference AV between the expected and actual voltage for a particular value of current I yields R, as follows (see Fig. 1.6): Rs= (1.8) The capacitance Cj of the diode can be measured with the help of an LCR meter for 11

CURRENT (5A) CLOSEST-FIT UNE -/ 1000.0 - I 1 mA Vd - 0.017V V = 0.520 AV / I - 17l 100.0 I- 10-4 I oexp(-qV / KT) 384 x 1013 A 10.0 AV = 0.062 = AV/ 0.05783 1.072 1.0 -- -DATA POINTS I I I l 0.40 0.50 060 0.70 DIODE VOLTAGE (V) Figure 1.6: I-V characteristic of a Schottky diode on a semi-log plot. different biasing conditions. Once Rs and Cj, are found, a figure of merit for the diode, the cutoff frequency fc can be evaluated from: 1 fc 2 rRC (1.9) 27rR,Cj, Usually, for the calculation of the cutoff frequency the dc quantities of the diode are used, without taking into account high frequency skin-effects and parasitics. For MMIC applications the planar disk type Schottky diode shown in Fig. 1.7(a) is commonly used (this type of diode was used in the work presented in this dissertation). In this mesa-type diode both contacts (anode and cathode) are on the top surface of the chip and the current through the device flows down from the anode and spreads laterally around the base of the mesa before flowing out of the cathode [14]. Assuming that the current is confined within a skin depth 6, the series resistance can be broken in several components 12

(Fig. 1.7(b) ), and the analytical equations for these componenta are given by the following equations [26], [27]: - W Rn = (1.10) on r a2 R1 = 2 2 (1.11) R2 = (1.12) 4rrab5. R3 2 — n(b) (1.13) PrPs 1 c 6s R4 = pmPs -n() + -(AIo(3c) + BKo(,c)) + (AI(3b) + BKo(3b))] (1.14) Pm6s + Ps6m 2 b Ps Pm where A 1 pmKi(itb) p,8K,(3c) A= 2a' [ 6 c + b ] (1.15) 2w73Z\ 6mC 6,b 1 pm1 (]3b) psl(f~c) B 1 2 p7rmAI[ + Ps c ] (1.16) 27r/3A 6mC 6,b A= IiCc)Kij(/b) - Ij(3b))K1(/c) (1.17) + Ps) (1.18) Pc is the ohmic contact resistance, 6E and 6m are skin depths, ps and Pm are resistivities, oa and am are conductivities, in the substrate and metal regions, respectively. In() and Kn() are modified Bessel functions of the first and second kind, respectively. The total series resistance, therefore, of the disk-type diode of Fig. 1.7(a) is: Rs = Rn + R1 + R2 + R3 + R4 (1.19) For a W-band (40 to 80 GIIz) multiplier diode with a=4.8 pm, b=8.3,um. c=12.3,ump an epi-layer thickness of 4000 A and a doping of lx1017cm-3 Rs n 1.5Q from equation 1.19, 13

n' region Schottky Anode / Ohmic Contact n+ region (a) Schottky Anode a 1 b / c - at jR Ohmic Contact / T T R R3 AlGaAs Semi-Insulating GaAs (b) Figure 1.7: a) Disk type diode for MMIC applications and b) cross section of diode showing different components of the series resistance (from [14]). 14

while for a mixer diode with a=1.1 jam, b=3.1 im, c=7 Mm, an epi-layer thickness of 2000 A and a doping of 3xl017cm-3 Rs 6.4Q. The efficiency of a Schottky-barrier diode that is used as a varactor is expressed as the quality factor, Q, which is the ratio of the energy stored in the junction to the energy dissipated by it [25]: wCjRj 1 Xin 1 + 2CRjR C (1.20) 1.4 Measurement Techniques Measurements on monolithic microwave/millimeter-wave circuits are performed using an IIP 8510C Vector Network Analyzer (VNA). The analyzer is capable of measuring the S-parameters of various circuits from 2 to 118 GIIz,with three different test sets. From 2 to 40 GI1z, the 8516A test set is used with coaxial cables having K-connectors at the end. These cables are connected to model 40A probes from GGB Industries that are designed for on-wafer measurements up to 40 GI1z. From 40 to 60 GIIz, the synthesizer of the VNA drives the 83556A mm-wave source module that uses frequency multipliers (triplers) in order to produce the range of interest. The module is connected to a waveguide system that includes couplers and mixers for sampling the incident/reflected energy and downconverting the measured signals to the 1.2 MIIz baseband. At the end of the waveguide system there is a waveguide-to-coax transition that leads to a 1.89 mm connector where the coaxial cable is attached. The other end of the cable is connected to model 67A probes that; are used to measure the planar circuit. The measurement is controlled and recorded with the 85105A millimeter wave controller. The same controller is used for W band measurements from 70 to 118 GhIz. In this case, the W85104A modules are used to produce the frequencies of interest 15

from those of the synthesizer with the help of quadruplers. The output of the XV band test set modules is a WR-10 adaptor that is connected to a long piece of WR-10 waveguide. The waveguide is followed by model 120A-BT probes that have a WR-10 adaptor and a bias-tee network for biasing active structures (such as multipliers and mixers) during measurements without affecting the RF frequencies. All the different models of probes that were mentioned are compatible with coplanar-waveguide transmission lines and consist of three tips, two for the ground and one for the signal, that launch the CPW mode into the planar passive or active structure. The distance between the center tip and each of the outer tips is called the probe "pitch" and is either 150 or 100,m (for most of the measurements in this thesis it is 150,am). The system available for measurements does not cover the range from 60 to 70 GIlz and therefore, in the graphs presented herein this band will be presented either with a straight line or a gap in the data. In order to measure the S-parameters of a circuit, the errors introduced by the various components of the network analyzer, the cables/waveguides, the connectors, the adaptors and the probes must be removed. The process of removing these errors is called calibration or de-embedding. The two methods that are widely used for calibrating the VNA are the Short-Open-Load-Thru (SOLT) and the Thru-Reflect-Line (TRL). In the SOLT method the system is calibrated up to the end of the probe tips and, thus, the errors introduced from the probe to planar circuit transition are not accounted for. For a full two port calibration, error correction is achieved by measuring four standards (open, short, 50 Q load and thru line) with known responses. The model that represents the various mechanisms of error in the system and is used for de-embedding, consists of twelve error coefficients (for a one port calibration three standards are used and three error coefficients are calculated). By measuring four known standards a system of twelve equations with twelve unknowns is 16

formed and solved. The error coefficients are then loaded into the VNA and calibration is achieved on-line. In the TRL method, the reference planes for the measurement are inside the planar circuit and the errors from the probe-to-circuit transition as well as the transmission lines before the device under test (DUT) can be de-embedded [28], [29]. The standards that are used in this method are fabricated on the same wafer with the DUT and consist of a thru line, one or several delay lines and a short or open. With appropriate selection of the standard dimensions, the designer has the flexibility to define the reference planes anywhere in the circuit before the DUT of interest. The length of the thru line is twice the distance between the point where the probe tips touch the circuit and the reference plane. Usually, the length of the thru line is equal to a wavelength at a particular frequency of interest but any arbitrary length can also be chosen. The length of the reflect standard is half the length of the thru line and depending on the type of line a short or an open is used. For a microstrip configuration an open is much easier to fabricate since a short would require a via hole, while for a CPW configuration a short is usually preferred. For the delay lines, the lengths are A/4 longer than that of the thru line at various frequencies. These frequencies are determined by the user to ensure a good calibration over the entire band of interest. The delay lines allow the network analyzer to compute calibration coefficients so that the proper phase response of the DUT can be found. For this reason, a delay line is "good" as long as 0.5 <I sin(31) 1< 1 where 1 is the excess length of the delay line, over the frequency range of interest. If the previous relationship is not true for the entire band, then several delay lines that meet the previous criterion must be designed in a way that they overlap and cover all the range. Each delay line will therefore be effective in a sub-region of the entire frequency band. The best phase correction results 17

are possible when 31 is closer to 900 or 2700. One restriction of the TRL method stems from the maximum length of the delay lines that must fit in the available wafer area. If multiple columns of calibration standards are needed on the wafer, then the length of the lines should be designed to account for the amount of space available. The resonance frequency may have to be altered in order to obtain shorter delay lines, if they are too long for multiple columns. The National Institute of Standards and Technology (NIST) has developed a program called.Aultical [30],[31], that performs a TRL calibration of the IIP8510C VNA on line and runs under IITBasic in a Windows 3.11 environment. This program makes the TRL calibration faster and more convenient. Rather than defining standards on the IIP8510C VNA, the standards are quickly defined on screen by editing a calibration menu and corrections or alterations can be made rather easily. Multical is capable of calculating the error coefficients and loading them in the lIP8510C VNA so that the user can measure the S-parameters of the SUT directly. Besides the scattering parameters, Multical can plot and analyze various data such as propagation constant, attenuation, effective permittivity, characteristic impedance and capacitance of a line. 1.5 Simulation Tools Monolithic microwave/millimeter-wave integrated circuits are designed and analyzed with the help of commercially available or built-in house software. Presently, there is an abundance of computer programs that can solve both passive and active structure related problems. It is up to the designer to select the software that is most suitable for the geometry under investigation, in terms of accuracy in results, minimum running time and memory size. For the structures that will be presented in this thesis, the available programs 18

are based on two methods: a) the quasi-static analysis and b) the full wave analysis. In the first method, the quasi-static, the electromagnetic problem is solved with the help of ideal transmission line theory without taking into account any parasitic or secondary effects. The best known program based on this method is lIP EEsof Libra [32] developed by Hewlett-Packard. Libra implements circuit models for each different section of the DUT (transmission line, capacitor, resistor, inductor, diode, transistor) as well as measurement data provided by the user for a specific component of the structure, in order to calculate scattering parameters or any other functions. It can also incorporate ohmic and dielectric loss, based on simple models, for more accurate simulations. For active structures, such as frequency multipliers and mixers, Libra can perform a harmonic balance analysis yielding conversion loss, embedding impedances, return loss and output power spectrum. An optimizer can also be used to match modeled data to either measured data or results obtained from a full wave analysis. In the second method, the full wave technique, Maxwell's equations are solved and all components of the electric and magnetic field are evaluated. With this approach all effects of the electromagnetic structure are taken into account. The solution to Maxwell's equations is achieved with the implementation of several numerical techniques. Finite Difference Time Domain (FDTD) is one of these techniques, where Maxwell's differential equations are replaced by finite difference equations that are algebraic in form [33]. The value of a dependent variable at a point in the solution region is related to the values of some neighboring points. Therefore, a grid or mesh of points that are related to each other is created and boundary conditions are applied to the points on the outer surfaces or edges of the grid. The most famous scheme in FDTD is Yee's cell [34] that relates the electric and magnetic field components in a cubic cell. For an unbounded or radiating structure an 19

appropriate absorber that simulates free space must be used so that the grid is truncated and finite. One of the advantages of FDTD is that it can be applied to non-planar geometries, such as micromachined micromave and millimeter-wave structures. Another numerical technique that is used for the solution of electromagnetic problems is the method of moments. This method is more appropriate for unbounded or radiating structures and is based on converting an integral equation into a matrix equation using basis functions or weighting functions. Once the matrix elements are found, the equation is solved and the parameters of interest are calculated. Two popular programs that implement the method of moments for MMIC's are IE3D and Sonnet [35],[36]. For a planar circuit. the geometry is first entered in both of these programs with the help of a geometrical editor and then a grid is created by dividing the conducting areas into cells. In each cell, the electric currents are the unknowns that are found from the solution of the appropriate matrix equation. From the currents the electric and magnetic fields as well as the scattering parameters are derived. For more complex geometries and inhomogeneous media the Finite Element Method (FEM) is used. where the solution region is divided into a finite number of subregions or elements. In each element the equation of interest is first derived and then all of the elements are assembled together into a system that is solved. A commercial program that makes use of FEM for solving various electromagnetic structures is IIFSS by IIP-EESOF [37]. IIFSS has the capability of solving both planar and non-planar (e.g. micromachined) MMIC structures. 1.6 Dissertation overview Several passive and active MMIC structures are presented in this dissertation, with the objective of showing that a transmit/receive system with enhanced performance at high 20

operating frequencies can be monolithically integrated on a single chip. The design of the circuits was realized by using software tools and by creating microwave models, while the fabrication was done with standard IC fabrication techniques and the electrical performance was tested with various equipment. The dissertation is organized into two main sections: the presentation of passive monolithic circuits on silicon and the presentation of active monolithic circuits on GaAs. It comprises of 6 chapters and three appendices. Chapter 2 deals with micromachined patch antennas on high-index materials. Two techniques that enhance the antenna performance are implemented. In the first technique that was developed by R.F. Drayton [38] an air-cavity is created under the patch by removing material. Efficiency measurements for antennas fabricated on Duroid substrate, according to this method, that resonate in Ku-band are performed to validate the technique. Results show an increase of 28% for a 75%-25% air-dielectric substrate region when compared to a regular high index patch. The dependence of the efficiency improvement on the cavity placement relative to the patch radiating edges is also investigated. It is shown that in order to improve the antenna performance a minimum distance equal to two times the substrate thickness is required between the cavity and radiating edges. Return loss measurements and radiation patterns for the fabricated antennas are also demonstrated. An increase of 64% in the micromachined antenna bandwidth is observed, as well as smooth E-plane patterns. In the second technique the dimensions of the rectangular antenna are adjusted so that the dominant TMo mode is suppressed and simulated results with FDTD are presented. The aim of this effort is to show that integration of planar radiating elements on high dielectric constant substrates with optimal performance is feasible, thus allowing for high circuit density and compact designs. Chapter 3 presents the implementation of micromachining for high-Q resonators. A fully 21

monolithically integrated cavity resonator with very low loss and narrow bandwidth that surpasses the performance of traditional planar resonators is fabricated and tested. Design considerations for the resonator can be found in [1]. Measured results show a quality factor of 506. a bandwidth of 5% and an insertion loss of 0.36 dB. The measurements are compared with simulations done by Jui-Ching Cheng [1], based on a hybrid FEM/MoM technique that he developed. In addition, the performance of the resonator under different ambient temperatures is presented and analyzed. The dependence of the resonator response on the location of the coupling slots relative to the center of the cavity is also demonstrated, along with some on-wafer packaging schemes. This resonator can be used as a building block for the fabrication of narrow-band low-loss filters necessary in various communication systems. Chapter 4 presents GaAs monolithic frequency multipliers based on FGC line technology for W band. This type of multiplier was first demonstrated by Brauchler [2] and for a Q=2 design an efficiency of 15-16% at 80 GIlz and a wide bandwidth (12%) were achieved. Designs for higher efficiency and output power are pursued here. The characteristics of FGC lines with and without a polyimide overlay used for passivation are given first and then results from different line geometries and impedances are compared. The dependence of the line loss on its geometry rather than the substrate material is shown. A two-diode Q=2 doubler with different anode areas than [2] is designed with 17.2% efficiency, 10% bandwidth and 66 mW output power at 76.3 GILz. A Q=3 doubler is also designed and fabricated and results show an efficiency of 22%, a bandwidth of 8.5% and 50 mW output power. A W-band doubler with four diodes, 12.5% efficiency and 115 mW maximum output power, which is the highest in that band, is also presented. In addition, a method that increases the multiplier efficiency by changing the topology of the FGC passive circuit is described and measured results that exhibit 20-25% performance improvement are shown. 22

Chapter 5 presents a monolithic FGC W-band x2 subharmonic mixer on GaAs that will be part of a fully monolithic transmit/receive module, as well as a novel fabrication technique that allows the fabrication of both FGC based multipliers and mixers with air-bridges for the passive circuits and channel etched fingers for the diodes on the same substrate. A single-sideband conversion loss of 11 dB is achieved at 79 GI1z for an IF frequency of 4 GI~z, an LO power of 8.8 dBm and epi-layer parameters that are a compromise between the optimum doubler and mixer ones. Chapter 6 summarizes the work presented in the dissertation with conclusions and recommendations for future work. Appendix A revisits the fundamentals of the first technique used in chapter 2 for the performance enhancement of patch antennas, while appendices B and C describe the various fabrication steps that were followed for the realization of monolithic multipliers and mixers. 23

CHAPTER 2 MICROMACHINED PATCH ANTENNAS 2.1 Introduction The first component of the monolithic transmit/receive module that will be studied is the radiating structure. For a planar environment the microstrip antenna has been widely used and implemented in a broad range of applications from communication systems (radars, telemetry and navigation) to biomedical systems, primarily due to its simplicity, conformability, low manufacturing cost [39], and enormous availability of design and analysis software. Integration, however, of the microstrip antenna in a compact circuit design, such as the monolithic transmit/receive module, that is typically achieved in a high index material is in direct contrast to the low index substrates needed by antenna performance requirements. The ideal solution requires the capability to integrate the planar antenna on electrically thick low index regions while the circuitry remains on the high index regions in the same substrate. In the past, this requirement was satisfied by selecting the substrate that offers optimum component performance; unfortunately this led to hybrid integration schemes and high development cost. As the frequency increases, however, this approach becomes increasingly difficult and costs are prohibitively high. 24

Microstrip antenna designs show significantly degraded performance in high index materials, such as silicon and GaAs, used for monolithic architectures due to the pronounced excitation of surface waves in these substrates. As a result, the antenna has lower efficiency, reduced bandwidth, degraded radiation patterns and undesired coupling between the various elements in array configurations. Optimum antenna performance depends on the choice of dielectric material as well as the choice of feeding network and is achieved when the radiated power occurs primarily as space waves with little or no components of "undesired" surface waves. Such microstrip designs are typically fabricated on electrically thick, low index materials and characterized by maximum antenna bandwidth and efficiency as reported by a vast number of theoretical and experimental researchers. Only a few experimental approaches have been put forth to resolve the excitation of substrate modes in microstrip antennas. In 1984, a substrate-superstrate configuration [40] using a horizontal antenna element showed an increase in the radiation efficiency. Superstrate materials such as GaAs or Si, however, require a very thin substrate thickness that yields exceedingly small values of radiation resistance. In the past three years, researchers have begun to use physical substrate alterations as a means of perturbing the surface wave excitation. Circular patch designs in duroid [41] are based on the choice of an appropriate patch radius to suppress the excited surface waves. Given the patch radius for a desired operation frequency, the antenna is forced to resonate at the first higher order mode (TM120) rather than the dominant (TM11o) one. Other approaches rely on suspending the rectangular patch over an air cavity through the use of a membrane or over closely spaced periodic holes in the substrate (either drilled or micromachined) [10], [42], [11]. This chapter presents two different techniques based on the implementation of micromachining technology, that address the previously mentioned problems of patch antennas 25

on high-index substrates. In the first technique developed by R.F. Drayton [38]. material is removed laterally in a region under and around the patch antenna in an effort to locally reduce the dielectric constant. Experimental results for Ku-band antennas fabricated on Duroid substrate show a significant increase in antenna efficiency and smoother radiation patterns. when compared with a regular rectangular patch. A minimum distance equal to two times the substrate thickness between the radiating edges of the patch and the edges of the machined area is also required in order to enhance the antenna performance. In the second technique, the resonant length of the patch is adjusted in order to minimize the dominant TMo surface wave mode [43]. Because the dimensions required to suppress the surface wave are larger than the dimensions for the desired frequency of operation, dielectric material is removed in an area only under the patch. Simulation results with FDTD show a significant decrease in the excited surface waves between the micromachined antenna and the regular one. 2.2 Reduction of the Effective Dielectric Constant (Technique I) 2.2.1 Review of Technique To integrate patch antennas into circuit designs on high index substrates without losing the advantages of low index materials, the regions in the substrate which will house the radiating elements must have low index of refraction. This is achieved by using micromachining to eliminate a portion of the substrate material as can be seen in Fig. 2.1. The micromachined antenna configuration that was developed by R.F. Drayton consists of a rectangular patch centered over the cavity, sized according to the effective index of the 26

- A ------------ - - - - b? I * - I I I a Figure 2.1: Geometry of the micromachined patch antenna. cavity region and fed by a microstrip line. To produce the mixed substrate region, silicon micromachining is used to laterally remove the material from underneath the specified cavity region resulting in two separate dielectric regions of air and silicon [38]. In order to predict the effective dielectric constant of the mixed air-silicon region for varying thickness ratios underneath the antenna, a quasi-static model based on series capacitors is used [38]. A detailed description of this model along with results can be found in Appendix A. From Fig. A.3 of Appendix A we observe that an effective dielectric constant of approximately 2.2 is achieved for a mixed air-silicon ratio of 1:1 (model with AL=O) or 3:1 (model with AL calculated from [44]). Based on these results, two antennas (one micromachined and one regular) with resonant frequencies in the K-band were fabricated on Silicon by R.F. Drayton [38]. Preliminary measurements of the return loss indicated an increase in the bandwidth of the micromachined patch when compared with the regular patch. In addition, radiation pattern measurements showed a much smoother E-plane pattern for the 27

micromachined antenna (for more details see Appendix A). Both of these measurements provide the first indicator of a potential increase in total radiation from the antenna. Efficiency measurements, however, need to be made in order to observe the increase in power radiated into space waves as opposed to power radiated into surface waves. Since the existing test equipment operated at a lower frequency, a scaled model of the antenna on Silicon was fabricated on a mixed air-substrate cavity and was realized by machining a high-index (10.8) duroid substrate. For comparison purposes, conventional patch designs on both high and low index materials were also fabricated. In the following sections, the theory of radiation efficiency is described first and then the antenna performance is characterized based on bandwidth, radiation pattern and efficicency measurements. 2.2.2 Theory of Radiation Efficiency In order to measure the radiation efficiency of the patch antenna a radiometric method was used [45], [46]. This method is based on the fact that a lossy antenna under test (AUT) pointed at a cold load/target will generate more noise power than a less lossy antenna pointed at the same target. Antenna efficiency is obtained by characterizing the system receiver first and then the composite system (system receiver plus antenna). The output powers PH and PC measured at the receiver when connected to a hot and cold 50 Q load, respectively, are given by [47] PH = KTHLBGr + Pr (2.1) PL = KTCLBGr + Pr (2.2) 28

where K is Boltzmann's constant, G, is the receiver gain, B is the effective bandwidth of the receiver and THL=295 K, TcL=77 K are the hot and cold load temperatures, respectively. The ratio of the two powers can be defined as PH _ KTHLBG, + P (2.3) PC - KTCL BGr + Pr If we divide both the numerator and denominator of equation 2.3 with KT OBGr and we recall that [47] T F,- 1 (2.4) where F, is the noise factor of the receiver system and To=295 K, then by solving for F, equations 2.3, 2.4 yield THL - YrTcL + To(Y, - 1) (25) FT = (2.5) Since To = THL=295 K equation 2.5 gives (THL - TCL). F THL(1 - 1/Y,) (2.6) Individual AUTs are measured in the composite system to obtain hot and c(old measurements where the black body absorber (Ecosorb), placed in front of the antenna element in a way that covers all of its radiation pattern, has been held at room temperature (THA= 295 K) for the hot load and has been immersed in liquid nitrogen (TCA= 77 K) for the cold load. Note that the 50 Q calibration load is submersed into the liquid nitrogen. The resulting composite system noise factor is expressed as 29

F (THA - TCA ) ( THA(1 - I/Yc) ( where the measured power ratio of the antenna, Yc, is PAH/IPA. Since the measured output noise powers of the receiver and the composite system with the hot load are known, the antenna gain can be obtained from the following expressions Pf = KTHLBGrFr (2.8) PA = -KTHABGrGAFC (2.9) where Gr and GA are the receiver and antenna gain, respectively. After dividing the two hot load power equations [2.9 by 2.8] and substituting in the noise factor parameters, Fr (equation 2.6) and FC (equation 2.7), the antenna gain expression becomes PH - pc GA P - A (2.10) P H - p c L L Equation 2.10 assumes equal temperatures for the 50 (Q load and AUT in either the hot (THL = THA=295 K) or cold (TCL = TCA=77 K) load measurement. A modified gain expression is shown in 2.11 that accounts for temperature differences observed in the application of the test methodology in the measurement of the cold 50Q load and AUT. Since the absorber is immersed into liquid nitrogen and then removed to cover the antenna, the cold temperature is slightly elevated and is assumed to be TCA=88 K based on past experience with this measurement [48], while the 50 Q load, submersed continuously into the liquid nitrogen, maintains a constant temperature, T(CL, of 77 K. Hence, 30

pH - PC GA = 1.038- A A (2.11) 2.2.3 Ku-Band Micromachined Patch Antenna Since the available measurement set-up imposes an operating frequency range between 12.5 and 13.5 GILz, several rectangular patch designs were fabricated on duroid substrates of high (10.8) and low (2.2) index constants with substrate thickness, t, of 635 and 500 ym, respectively. Scaled model micromachined antennas were also fabricated in which the cavity is created by machine milling. The final geometry is similar to those shown in Fig. 2.1 without the sloping sidewalls, and the dimensions for the various antennas can be found in Table 2.1, where the parameters a and b are given by their actual values and not the average ones since the sidewalls are vertical. To describe the findings of the various patch configurations investigated, the notation used in the following sections refers to antennas on full thickness substrates as "regular" high- (10.8) or low- (2.2) index designs and those printed on a mixed air-duroid cavity as scaled models. Each patch is fed by a 50Q microstrip feedline. is fabricated on a 75 mm2 substrate, and is mounted in the test fixture shown in Fig. 2.2. Since the micromachined scaled model antenna resides over the mixed dielectric material, approximately 3.65 mm of the feed line has an impedance based on the mixed air-duroid region compared to the feedline of regular antennas on full thickness material. The width of the feeding line (560 ym) for the scaled model patch is maintained over the mixed region and is the same with the width of the 50 Q line on full substrate resulting in a characteristic impedance of approximately 96 Q. The return loss is measured (Fig. 2.3) and the input impedance values referenced at the RF connector are shown in Table 2.2; notice the good agreement between the scaled 31

10 cm *- 0 - ground plane Figure 2.2: Text fixture with micromachined antenna mounted. model and regular low index antenna. In Fig. 2.3 the bandwidth of the scaled model increases from 1.4% to 2.3%, a 100% increase over the -10 dB bandwidth of the regular patch printed on the high index material. Since bandwidth is inversely proportional to the quality factor, Q,defined as the ratio of total energy stored in the antenna to the energy dissipated or radiated from the antenna, the increase in bandwidth provides the first indicator of an increase in total radiation (space and surface waves) from the patch. This increase in bandwidth was also observed in the silicon micromachined antenna. It should be noted here that the return loss measurement of the micromachined patch exhibits a second resonance around 12.4 GIz, that is due to the presence of a low permittivity cavity inside a high dielectric constant area. Radiation patterns (Fig. 2.4) were also taken for the three antennas and in order to minimize the interaction between the connector and the antenna during the antenna during the measurements a small piece of absorber is placed over the RF connector to reduce the effects of secondary reflections on the antenna pattern. In Fig. 2.4(a) the "regular" high index pattern has a large peak in the E-plane at approximately -50~ degrees, indicating large power leakage 32

0 -5 CP 1-1N u: o (A 0 3 0S cf -10 -15 -20 -25 -30 -35 12 12.5 13 13.5 14 Frequency (GHz) Figure 2.3: Measured return loss for the scaled model patch antenna freff=2.3 (etched) and regular patch antennas er=2.2 and e,=10.8. Patch t(mm) tai(mm) L(mm) w(mm) a(mm) b(mm) c(mm) Regular 0.635 0 3.750 4.420 0 0 0 (10.8) Scaled Model 0.635 0.476 7.624 6.676 15.190 14.478 3.783 (10.8) (75%) Regular (2.2) 0.500 0 7.570 7.340 0 0 0 Table 2.1: Dimensions of the fabricated scaled model and regular antennas. 33

Patch Input Impedance (Q) Resonant Frequency (GIIz) Feed Line Length (mm) Regular 49.2-j0.37 12.84 27.6 (10.8) Scaled Model 67.5-jl.04 13.165 27 (10.8) Regular (2.2) 67.5-j0.14 13.044 34 Table 2.2: Input impedance characteristics of the regular and scaled model antennas to surface waves. This behavior is also observed in [10]. In contrast, the scaled model patch has a much smoother E-plane pattern and is very similar to the E-plane pattern of the "regular" low index antenna. As expected, the II-plane patterns (Fig. 2.4(b)) are similar in all cases. The differences between the E-plane pattern of the antenna on highindex duroid (Fig. 2.4(a)) and the E-plane pattern of the antenna on Silicon (Fig. A.5(a)) (both antennas are "regular") can be attributed to the slightly different dielectric constant. the different experimental set-up used for the pattern measurements and the fact that the distance between the antenna and the edge of the finite ground plane is not the same in terms of guided wavelengths. 2.2.4 Efficiency Measurements The system configuration [11] is illustrated in Fig. 2.5 and has component specifications consisting of an RF bandpass filter with an insertion loss of 3 dB in the 12.5 to 13.5 GIIz range and a mixer intermediate frequency (IF) of 1.5 GIz. Since the calibration plane of the system is at the RF connector, the measured efficiency values include the feed line, connector and mismatch losses. In order to determine the de-embedded antenna efficiency, the losses must be determined and extracted. The losses associated with the feed line 34

E-Plane 0 -5 a-10 (D a. -25 Degrees (a) H-Plane II I 0 - -5 - I I... i... I.. I — -....., I I. I..- - 0. a, CD.-,a: -10 - -15 - -20 - -25,,,'.. ----.. Regular (2.2) -- — Micromachined (10.8) - Regular (10.8).., 1,,, 1,,, I,, ~ I I I: I I I I I -60 -40 -20 0 Degrees 20 40 60 (b) Figure 2.4: (a) E-plane and (b) II-plane radiation patterns for the three antennas under test. 35

Hot/Cold:M mW' -Absorber 1 — Anenna in - -.. T-st Fixture '-. - - - -- - -Reference Plane 1" LNA-G=+21 dB -3 dB RF Filter -3 dB LO Power Meter 14-15 GHz Mixer 14-15 GHz Mxer +31 dB -3 dB +31 dB -3 dB YIG Filter +33 dB - 3dB -1.5 dB 30MHz Figure 2.5: System diagram of the efficiency measurement setup. lengths (Table 2.2) are calculated using IIP Momentum [11], [32]; the RF connector loss is based on an empirical value; and the mismatch loss is determined from the measured return loss data. In Fig. 2.6, the measured efficiency data, which are averaged values, show 73~3% for the scaled model having an air-substrate thickness ratio of 3:1 and 56~3%/ for the "regular" antenna printed on the high index material. The patch printed on 2.2 duroid was found to have an efficiency of 76~3%. It should be noted here, that during the efficiency measurements the absorber that covered the radiation pattern of the patch antennas was placed at least one inch (2.54 cm) above the antenna plane in order to avoid perturbing the near field. Based on the far-field approximation formula (rff > 2D2/A, where D is the maximum antenna dimension) for the patches with the dimensions of Table 2.1 rff > 1cm. In Table 2.3, a summary of the measured efficiency, specific losses, and de-embedded 36

i, tI Il I I i I l 80 70 60 2 50 4 40 30 20 --- Scaled Model c ref2.3) i e 0 reff h R Redgular ( a =2.2) 10 10 --- Regular ( e=10.8) 0 12.5 13 13.5 Frequency (GHz) Figure 2.6: Measured efficiency for the scaled model and regular patch antenna designs. efficiency are documented. The scaled model case shows sensitivity to the distance c between the radiating edges of the antenna and the edges of the micromachined cavity. From the results summarized in Table 2.4, it can be observed that for an air-substrate thickness ratio of 1:1 and separation c=O, the efficiency of the scaled model is similar to that of a patch on high index substrate. However, when the distance is at least twice the substrate thickness, 2t, for the same air-substrate thickness ratio, the de-embedded efficiency increases by about 10%. This is further validated in the measured data shown in Table 2.3 for a distance of c=3. 7183mm (6 times the substrate height, 6t). The improvements observed are attributed to the presence of fringing fields that usually extend one to two times the thickness t beyond the radiating edges of the antenna into the substrate environment. The above results emphasize the importance of the air-substrate thickness ratio on bandwidth, and also the importance of the distance between the radiating edge of the antenna and the micromachined cavity in order to enhance the antenna's efficiency. A plot of the measured efficiency versus the ratio 37

75,, 6 5 /; - / /65 660 X 55 5 0.l l-i. l l. - l. l l ll 0 1 2 3 4 5 6 7 Ratio c/t Figure 2.7: Measured efficiency versus the ratio of the distance c over the substrate thickness t. of the distance, c, between the cavity and the radiating edges over the substrate thickness, t, can be seen in Fig. 2.7. The de-embedded efficiencies of the individual antenna elements (see Table 2.3) are 85% for the micromachined scaled model and 66% and 82% for the antennas on 10.8 and 2.2 duroid substrate, respectively. The latter values are in good agreement with the calculated efficiencies of 86% and 67% for the regular low and high-index antennas, that can be found in [11]. As a result, the efficiency of the micromachined patch increases by 28% over the high index patch and the efficiency performance approaches the patch on low index duroid within the bounds of measurement error. When the modified efficiency expression (Eq. 2.11) is used to account for differences in the cold measurement of the 50 Q load and AUT, the measured and de-embedded efficiencies increase by 2-3%c as seen in Table 2.3. In this case, no significant difference is observed between either approach since the accuracy of the measurement system is 3%. 38

Antenna Regular Scaled Model Regular E =10.8 er=10.8 E,.=2.2 Measured Efficiency Based on Eq. (8) 56% 73% 76%; Based on Eq. (9) 58% 76% 79% Mismatch loss (dB) 0 (100%) 0.05 (99/c) 0.08 (98%) Connector loss (dB) 0.15 (97/c) 0.15 (97/c) 0.15 (97%) Feed line loss (dB) 0.56 (88%) 0.48 (90%) 0.1 (98%) Total loss (dB) 0.71 (85%) 0.68 (86%) 0.33 (93%) De-embedded Efficiency Based on Eq. (8) 66% 85% 82%c Based on Eq. (9) 68% 88% 85% Table 2.3: De-embedded efficiency for the scaled model and regular patch antennas at resonance 39

Patch Antenna Mixed air-substrate Mixed air-substrate thickness ratio (1:1) thickness ratio (1:1) c=0 c%2t t (mm) 0.635 0.635 tair (mm) 0.330 0.330 L (mm) 5.415 7.624 w (mm) 6.676 6.676 a (mm) 5.415 10 b (mm) 10.590 14 Measured efficiency 52% 65% Total loss (dB) 0.69 (85%) 0.69 (85/%) De-embedded efficiency 61% 76% Table 2.4: Efficiency results and dimensions for two scaled model antennas on duroid substrate with cr=10.8 40

2.3 Elimination of TMo Surface Wave (Technique II) 2.3.1 Theoretical Analysis Our purpose is to design a rectangular patch antenna with a suppressed TMo surface wave mode. In our analysis we assume that the operating frequency of the antenna and the substrate thickness are such that the higher order surface mode is not excited. Thus, elimination or suppression of the fundamental mode should be sufficient in order to minimize the surface wave losses. According to the equivalence principle and the cavity model for a patch, in terms of radiation a rectangular microstrip antenna can be modeled as a rectangular loop of magnetic current. From the cavity model, the electric field of the dominant TM10 mode for the geometry shown in Fig. 2.8 is given by EZ =Acos( T) (2.12) b C b0 a ~b x Yl Figure 2.8: Micromachined antenna for the elimination of TMo mode. where a,b are the width and the resonant length of the patch, respectively. Here the assumption is made that the patch is fed in such a way that only the TM10o mode is excited. Thus, the radiating edges will be at y=0,b. The equivalent magnetic current at these two 41

edges is M = 2E x 5n= 2Ax (2.13) As it is known, a single ILertzian magnetic dipole, oriented in the x direction at a height z' above the ground, will give rise to a TMo surface wave field given by [41] I = (z Z II)H)(TMop) sin(O) (2.14) where I3TIMo is the propagation constant of the TMo0 mode and K(z, z') is an amplitude factor that depends on the height of the source and the observation point. By integrating over the two radiating edges of the rectangular patch for the magnetic current, distribution, the total surface wave field radiated by the magnetic currents takes the form = 44Bjz) II(2)(P p) tan() cos(a b(.5 = -4A ( (2) (/3TMo) tan() cost(/M sin(O)) sin(/3TvMo cos()) (2.15) PT-Mo 42 2 where B(z) = K(z, z)dz' (2.16) In order to derive the above expression the far field approximation for the phase of the radiated surface wave is used. The pattern of equation 2.15 is shown in Fig. 2.9 (dashed line). By setting b = nulls are placed at the location of the peaks of the lobes at 13TM q = 2, 3- so that four minor lobes replace the two major lobes (Fig. 2.9- solid line). As a result, the surface wave pattern is reduced. Choosing b according to the above formula, results in greater resonant length than the one chosen for the design frequency. In order to overcome this decrease in operating 42

Cored 0=x/2 - - -Conventional 90 (p-plane 0.2 120 60 \ 30 0.1 0.05 / 0 0 210\ \ / 330 240 300 270 Figure 2.9: Surface wave field pattern for the regular antenna and the micromachined antenna. frequency, the material in a rectangular region under the patch is removed, thus creating a lower effective dielectric constant which will permit the desired increase in operating frequency. The length of this "cored" region is found from the transcedental equation (2.17), which is derived from the field expressions of the dominant mode of the cavity, after applying the boundary conditions at the various interfaces: 2 b)(K1 ( ) - tan(Kb)( an2(K (b - b)) - KO) = 0 (2.17) 2 KO 2 K1 where KIo and K1 are the propagation constants in the air and dielectric regions, respectively. By creating this "cored" region under the patch according to 2.17, the antenna is forced to resonate at the first or second higher order mode depending on the choice of b' (Eq. 2.17 yields two solutions other than b' = b which is a trivial one). As a result the radiation pattern of the micromachined antenna will be altered, since at the second resonance there is a null instead of a maximum, at boresight and at the third resonance the pattern exhibits secondary or minor lobes (i.e the major lobe of the first resonance breaks into several lobes). 43

Patch Type Conventional Cored b (mm) 1.894 6.665 a (mm) 1.0 1.0 b'(mm) 0 2.174 c (mm) 0.615 1.058 Table 2.5: Dimensions for the cored and conventional patch that were used in the FDTD simulations. If the application that the patch antenna will be used requires one maximum at boresight and broad beamwidth, then only the trivial solution (i.e. b' = b) of 2.17 can be used. In the latter case, of course, the material is removed in the entire area underneath the patch. 2.3.2 Results In order to test the accuracy of the previous analysis a rectangular patch with a resonant frequency of 22.5 GIIz was designed on Silicon with e,=11.7 and a substrate thickness of 500pm. Since for the given substrate, higher order surface modes exist above 40 GIIz elimination only of the dominant TMo mode is sufficient. The micromachined patch was compared with a regular patch on the same substrate and with the same resonant frequency. The dimensions of the two patches are given in Table 2.5 and the results from the FDTD simulations [49] can be seen in Fig. 2.10. Measurement of the normal field inside the dielectric region showed a suppressed electric field for the cored antenna, which was more than 10 dB lower than the field of the conventional patch (Fig. 2.10). Measurement of the reflection coefficient also with the help of FDTD, showed good agreement between the resonant frequencies of the cored patch and the conventional patch. 44

-15 —,, I I I I:1 11 - * - Cored -2 0- * * Conventional - ~-25 30 W -3 — L - E L res Probe Point E 0 -4 0 — - 5 — Distance, d - 5 0 - I i! |!. |: I! Ii-i. 0 10 20 30 40 50 Distance, d (mm) Figure 2.10: Normalized electric field inside the dielectric versus distance from the center of the antenna for the micromachined (cored) patch and regular patch. 2.4 Conclusions Two different techniques for the reduction of surface waves in microstrip patch antennas were presented in this chapter. In the first technique, material was removed laterally underneath and around the patch in an effort to reduce locally the dielectric constant [38]. Experimental results of a micromachined patch fabricated on high-index Duroid showed superior performance when compared with a regular patch on the same substrate. The impedance bandwidth and the efficiency of the antenna increased by as much as 64% and 28%, respectively. The E-plane radiation patterns of the micromachined patch were also much smoother than those of the regular patch. In addition, for the micromachined antenna it was shown that placement of the antenna's radiating edges with respect to the edges of the cavity is critical to improving the power radiated as space waves (i.e. the efficiency) and must be at least twice the substrate thickness. 45

In the second technique, the resonant length of the rectangular patch was adjusted to a critical value in order to suppress the dominant TMo surface wave mode. Since this value is larger than the regular length of the antenna for a specific frequency of operation. a cored region that decreases the resonant frequency but forces the patch to operate at the first or second higher order mode was created underneath it. Simulation results with FDTD between a regular patch and one designed according to this technique, showed a substantial decrease in the electric field inside the dielectric. Both of the techiques presented in this chapter result in the enhancement of the antenna performance and indicate that patch elements can be integrated in compact MMIC designs on high-index environments. 46

CHAPTER 3 MICROMACHINED RESONATORS 3.1 Introduction With the trend to incorporate all microwave components on a single chip, as is the case of a monolithic transmit/receive system, there is an increased need to build high-Q resonators that can be monolithically integrated with the rest of the circuitry on the same substrate. IIigh-Q resonators are the building blocks for narrow-band. low-loss filters that are used mainly in communication and radar systems. Traditionally, for microwave frequencies these resonators are made of rectangular and cylindrical metallic waveguides that offer very low loss and flexibility in tuning by inserting backshorts and screws. Waveguides, however, are heavy, large (especially at lower frequencies) and costly to manufacture since each component must be precision machined one at a time. In addition, waveguides do not allow for an easy integration with monolithic circuits and active devices. The implementation and maturity of micromachining techniques in the fabrication of microwave and millimeter-wave circuits [50] - [51] allows us now to make miniature silicon or GaAs micromachined waveguides or cavities that can be used for the fabrication of highQ bandpass filters and multiplexers. The quality factor that can be achieved with this 47

technique is much higher than the quality factor of traditional planar microstrip or stripline resonators either printed on a dielectric material or suspended in air with the help of a dielectric membrane [12], [13]. The latter type of resonators can give filters with less than 1 dB insertion loss and bandwidths exceeding 10%. This chapter discusses the development of a silicon micromachined high-Q X-band resonator that consists of a cavity, input and output microstrip lines and coupling slots. Experimental results of the performance of the resonator are shown and compared with simulations performed by Jui-Ching Cheng [1]. In addition, the quality factor of the resonator is evaluated based on s-parameter measurements. The effects of different ambient temperatures and the positioning of the slots relative to the center of cavity on the response of the resonator are also presented and analyzed, as well as some on-wafer packaging considerations. 3.2 X-Band Micromachined Resonator 3.2.1 Design and Fabrication The X-Band resonator shown in Fig. 3.1 (for design see [1]) consists of input and output microstrip lines that reside on top of a Silicon wafer and couple energy via slots into a micromachined cavity that is formed inside a second wafer. The energy that is coupled to the cavity can travel through it in the form of a propagating or evanescent wave. Evanescent waves give the advantage of using smaller cavity sizes since the modes are operating below cut-off frequency. This resonator can be used as a building block for the fabrication of high-Q filters, such as the one shown in Fig. 3.2. Several wafers are stacked together and one or more cavities are formed inside them. Energy is coupled from one cavity to the other with the help of slots, whose size, position and orientation controls the coupling. The 48

8.177 = 1/4L 16 0.41 ' ~ < 0.5 / Unit: mm 16.354= 0.465=H 32.354 = L Figure 3.1: The X-Band micromachined resonator. relative position of the slots with respect to the input and output microstrip lines controls the coupling to the input and output ports. Usually, the lines extend Ag/4 beyond the center of the slots. Vertical stacking of the wafers greatly reduces the occupied area when a lot of resonators are needed in a high-Q filter design. The resonator of Fig. 3.1 is a half-wavelength cavity that supports the dominant TE101o mode. For simplicity we will assume that the cavity walls are vertical and, thus, for the given dimensions the resonant frequency can be found from [52] C 71~ fres = )2 + ()2 = 10.277 GIIz (3.1) The resonator was simulated using a hybrid Method of Moments (MoM)/Finite Element (FEM) technique developed by Jui-Ching Cheng [1] and was fabricated using standard micromachining techniques. Two silicon wafers, 500,um thick, with 1.45,pm thermally grown oxide deposited on both sides were used [53]. The two microstrip lines on the top wafer were 49

— Z* **^Af00z *-***I**^ *!* ***.** ***** **^**BZ *^z —Zw @~z v@ @ — P I | | " Top View. l@ 9 * ******* * --- --— ** --- ---- ||w@ -N^ - -*/ --- - *VzB@@ Microstrip Lines Coupling Slots Microstrip Lines ___. \ x\\ Side View Figure 3.2: The structure of the proposed micromachined bandpass filters. gold electro-plated with a total thickness of 7.5 /im in order to minimize losses. Infrared alignment was used in order to correctly align the two slots on the back of the wafer with the microstrip lines printed on the other side. The cavity was fabricated on the second wafer by using chemical anisotropic etching (EDP or TMAII) until a depth of about 465im was achieved. When the wafer was etched. it was metallized in the evaporator with a total metal (Ti/Al/Ti/Au) thickness of 2jim. The two wafers were then bonded together with silver epoxy glue at a curing temperature of 150~C. The alignment between the two wafers was achieved by opening windows on the top wafer during the etching process to align to marks that were placed on the second wafer. In order to measure the resonator with on-wafer probing, a coplanar waveguide (CPW)-to-microstrip transition (Fig. 3.3) that provides a match to the 50 Q feeding lines was incorporated. The grounds of the CPW and the microstrip lines are set at an equal 50

1970 So 220 100 410 120'41 -375 Unit:urn l 2 0 - ~ ~ L -. - via 985 Figure 3.3: CPW-to-microstrip transition for 500pum thick silicon substrate. potential with the implementation of via holes. Fig. 3.4 shows the measured results for the S-parameters of a 2.48 cm long 50 Q line on 525 yum thick silicon substrate that employs the transition of Fig. 3.3. As it can be seen, the matching of the CPW to the microstrip line is excellent (S11 < -35dB, S21 - ~0.02dB). 3.2.2 Theoretical and Measured Results The fabricated resonator of Fig. 3.5 was measured with the help of the IIP8510C vector network analyzer and two 150pm pitch GGB probes. The reference planes for the measurement are at the middle of the slots and de-embedding was achieved using a ThruReflect-Line (TRL) calibration with the standards fabricated on the same wafer. Simulated and measured results 1 of the entire structure can be seen in Fig. 3.6 where very good agreement is observed. A more detailed measurement around the first resonance (Fig. 3.7) Simulation done by Jui-Ching Cheng [1]. 51

1in, ll I -10 1 -20 -:S21 -:S11 E ~ -30 -40,\. / ' I v / \1 \, / ' -50,1, -60 5 10 15 Frequency (GHz) Figure 3.4: Measured results for a 50 Q microstrip line that implements the transition of Fig. 3.3. gives a resonant frequency of 10.285 GIIz which is very close to that of a cavity with vertical walls, as calculated by equation 3.1. Fig. 3.7 also reveals an excellent agreement between the measured results and the simulations of the hybrid technique. The small difference (1%/c) in the center frequency is partly due to the finite accuracy in modeling the non-vertical slopes of the cavity and partly to the inherent numerical error of our simulation technique. Fig. 3.8 2 shows the z-component electric field density on the bottom of the cavity at the resonant frequency. The field pattern matches well with that of the first resonant mode of a half-wavelength rectangular cavity of similar size. The strongest field is located at the center of the cavity (the figure is drawn according to the physical dimensions of the cavity) where the peak of the standing wave exists, whereas at the four corners the intensity is minimal as expected. In order to evaluate the unloaded Q (Qi) of the cavity the losses due to the excess length 2Calculation done by Jui-Ching Cheng [1]. 52

Figure 3.5: Fabricated X-band resonator on two 500pim silicon wafers. of the lines from the reference planes, that is needed to tune the slots, must be removed. For this reason the ohmic loss on the feeding lines is found from the TRL standards and is used to compute the loss on the two open end stubs extending beyond the center of the slots. For the measured results shown in Fig. 3.7 this loss has already been de-embedded. The loaded Q (Ql) of the cavity defined as fres (3.2 Qi = - (3.2) where fresl10.285 GI~z is the resonant frequency and Af3-dB=0.5 GI~z is the 3-dB bandwidth, is found equal to 20.57. The external Q of the resonator, Qe, that includes the input/output loading effects, can be found from [54] S21(dB) =20logio(Ql1 (3.3) Qe where S21I was measured to be 0.36~0.04 dB. The error in the measurement is attributed to the accuracy of the calibration technique. Equation 3.3 gives Qe=21.44~0.1. Knowing 53

20 Frequency (GHz) 35 (a) -5 -10 I i - -15 -I / \ \,; ' 1\:' -20 -50 / / 305 10 15 20 25 30 35 -35 -40 --:measured -:simulated -45 --50 5 10 15 20 25 30 35 Frequency (GHz) (b) Figure 3.6: Simulated and measured results for the resonator of Fig. 3.1: (a) return loss and (b) insertion loss 54

10 Freq (GHz) 13 Figure 3.7: Measured and simulated S-parameters for the resonator of Fig. 3.1 around resonance. Qe and Qi we can find Qu from the known relation 1 1 1 1 Using the above definitions and the measured results, Qu is found to be equal to 506~55. The theoretical value of Qu for the dominant TE1o1 mode of a rectangular metallic cavity can be calculated from [52] Q ^ ___ (klolLW)3IHZo35 Qu 27r2Rm(2W3II + 2L3II + W3L + L3W) (3.5) where Rm = |- is the resistive part of the surface impedance exhibited by the conducting wall with a conductivity a and a skin depth 6, = ~~. For the cavity with the dimensions of Fig. 3.1 and a conductivity of a = 3.8 x 107S/m (Aluminum) equation 3.5 gives Qu - 526, which is very close to the measured value. 55

0 0.1 02 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 02 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Figure 3.8: Computed z-component of the electric field density on the bottom of the cavity (from Jui-Ching Cheng [1]). The performance of the proposed micromachined resonator is compared with that of other X-band resonators, both planar and non-planar, and the results are summarized in Table 3.1 (for the first cavity of Table 3.1 see [55]). As seen by this table, the micromachined cavity has a Q similar to a metallic waveguide cavity with the same dimensions, but it has the advantage of maintaining a planar form that allows for easy integration with MIC and MMIC structures. Despite its planar character, the micromachined cavity has a Q that is four times higher than that of traditional microstrip resonators (QU=125). Higher values of Q can be achieved with the micromachined resonator if more than one wafer are stacked together (or thicker silicon wafers are used), as indicated both by eq. 3.5 and the first cavity of Table 3.1, where the height II is 10.2 mm in contrast with 0.465 mm of the fabricated circuit. This gives the potential for the realization of planar/monolithic high-Q filters and multiplexers. 56

type size (mm x mm x mm) Qu non-planar metal (rectangular) 19.8x22.9x10.2 8119 metal (rectangular) 16x32x0.465 526 planar micromachined cavity 16x32x0.465 506 membrane-microstrip [54] 5.3x7. lx0.35 234 microstrip [54] 2.65x3.55x0.5 125 Table 3.1: Comparison of measured Q for several resonators at X-band. 3.3 Thermal Testing In communication and radar systems that use narrow-band filters and multiplexers, the thermal stability of the different components and sub-systems is of paramount importance. A small drift in the resonant frequency of a high-Q filter can result in out-of-band operation leading to performance deterioration or even system failure. This section presents measurements on the response of the micromachined resonator when operating under different ambient temperatures. The structure of Fig. 3.1 was tested 3 with an IIP8510 and a probe station whose stage temperature could be controlled. The system was calibrated up to the probe tips with an SOLT calibration and the temperature varied from 250C to 145~C. Due to the nature of the calibration the losses due to the microstrip lines and the CPW-to-microstrip transitions were not de-embedded. Results can be seen in Fig. 3.9, where we observe that the resonant frequency fres = 10.3 GI~z does not shift with the increase in temperature but is rather maintained at the same value. The expected change in the dimensions of the cavity due to the temperature variation can be found from [56]: 3Measurements performed at M/A-COM Company. 57

-1 -2 _ -3 5 -- 425 C 4 --— 40 C --- 55 C ---- 70 C -5I/ / - 00 C --— 130 C // --- 145 C -6 L/ --- —--- * ----- 10 10.1 10.2 10.3 10.4 10.5 Frequency (GHz) Figure 3.9: Measured insertion loss of the micromachined resonator under different temperatures. (T2) = I(Tl) + al(T)(T2 - T1) (3.6) where a is the temperature coefficient of expansion, T1 and T2 are the initial and final temperatures, respectively, and 1(T1), 1(T2) are the lengths at the initial and final temperatures, respectively. If we use a= 2.33 ppm/~C, which is the temperature expansion coefficient of silicon [18], T1 = 25~C, T2 = 145~C, L(25)=32.354 mm and W(25)=16.354 then equation 3.6 yields L(145)=32.363 mm and W(145)=16.358 mm. When inserted in equation 3.1, the new dimensions of the cavity at a temperature of 1450C give a resonant frequency of fres = 10.274GHIz, which is a change of 0.03% from the initial value and is in good agreement with the measured results. It should be noted here that the resolution of the network analyzer for the thermal testing was 50 MHz. This excellent behavior relative to temperature changes. makes the micromachined resonators ideal for the fabrication of 58

narrow-band filters that operate under different environment conditions. Regarding the insertion loss, Fig. 3.9 shows that it increases with temperature (from 1.66 dB to 2.4 dB) with the effect being more pronounced above 115~C. Up to that temperature the degradation is due to the increased number of intrinsic carriers that reduce the bulk resistivity of the wafer and, thus, increase the dielectric loss of the microstrip lines. From figures 3.2 and 4.4 of [57] for T=115~C N 0 4xl012cm-3 and p 650cm2/(V - s), respectively. If the mobility and the carrier concentration are known then the silicon resistivity can be found from [27] P = N = 2.4xlO3Qcm (3.7) The dielectric loss tangent, tan6, can then be evaluated from equation (2.21) of [47] tan6 = = 0.0062 (3.8) WEo(r where f=10.3 GItz and Er = 11.7. The dielectric loss of a microstrip line can also be found from equation (4.207) of [47] Katoe( eeff - 1)tan= ad -= an = 1.55Np/m = 13.5d/m = 0.0135dB/mm (3.9) 2VIT-ef7(Er - I) where (eff = 6.35. The total length of the two microstrip lines from the probe location to the coupling slots is approximately 23 mm and, therefore, the additional dielectric loss will be 0.31 dB. This result is in very good agreement with the insertion loss difference between 115~C and 25~C, S21(115) - S21(25) = 2 - 1.67 = 0.33 dB. For temperatures above 115~C the insertion loss increases more rapidly. This is due to the silver epoxy glue that is used to bond the two wafers, whose characteristics change with temperature above 120~C where curing takes place. A good solid wafer bonding is critical for the loss of the cavity resonator, 59

since small gaps between the wafers can cause energy to leak out of the cavity and radiate. Therefore, instead of using silver epoxy glue a more reliable eutectic bonding techique needs to be developed that will assure the low insertion loss of the micromachined resonator at different temperatures. It should be noted here that the thermal testing measurement was only performed once and was not repeated. 3.4 Effects of Slot Positioning on Resonator Performance For the resonator of Fig. 3.1 the two coupling slots are positioned at 1/4 and 3/4 of the cavity length L from the shorter edges of the resonator. In this section we study the effect of different slot positions on the response of the micromachined structure. A resonator with the slots located at 3/8L and 5/8L from the shorter edges was fabricated, using two 500 pm thick silicon wafers with PECVD nitride grown on both sides [58]. The depth of the etched cavity was about 470 Mm and the metallization thickness was 3 pm. Measurements were done using the lIP8510C network analyzer and the TRL calibration technique with the reference planes at the center of the slots (same method as the original resonator), while simulations were run using the IIFSS software. A comparison of the simulated and measured results can be seen in Fig. 3.10, where a small discrepancy (1%) in the resonant frequency can be observed. This can be attributed to the inherent numerical error of the simulation technique. The measured resonator exhibits a bandwidth of 2% (210MhIz) at a resonant frequency fres=10.525 Gh1z and an insertion loss of 1.1 dB. Measured results from both resonators can be seen in Fig. 3.11, where we observe that in the new resonator the bandwidth is reduced by 58% (from 500 to 210 Mhz) while the insertion loss is increased by 0.74 dB (from 0.36 to 1.1 dB). This indicates that by changing the position of the slots relative to the center of the cavity, we can change the bandwidth 60

9.5 10 Frequency (GHz) 11.5 Figure 3.10: Measured and simulated results for the resonator with the slots positioned at 1/8L and 3/8L. of the resonator at the price of changing the loss at the same time. In the previous case the bandwidth was reduced and the loss was increased, as expected, since the quality factor of the resonator is mainly determined by the propagating mode of the cavity and not the slot positions. However, when the two slots are very close together, evanescent modes can be excited that alter the Qu of the resonator. A bandwidth greater than 500 MhIz can be achieved if the two slots are positioned closer to the cavity edges. From Fig.3.10 we can also observe a slight asymmetry in the response around the resonance. This is due to the close proximity of the two microstrip lines (0.4A9) which allows power coupling from one to the other directly via substrate modes. In order to eliminate this effect and make the response more symmetric around resonance, we can use on wafer packaging [59] as seen in Fig.3.12 to isolate the microstrip lines from one another both on top and inside the substrate. For this purpose an IIFSS simulation was run with one perfect electric conductor on top of the structure and another placed between the two lines shorting 61

8 8.5 9 9.5 10 10.5 11 11.5 Frequency (GHz) Figure 3.11: Measured results for the two resonators with different slot positions. the top conductor with the slot ground plane. Fig. 3.13 shows the results of the simulation for the geometry of Fig. 3.12, where it can be seen that packaging reduces the suspected coupling occuring below 10.3 GILz by as much as 4 dB. The small coupling of about -16 dB below 10 GIIz can be attributed to evanescent modes that are excited around the slots inside the cavity. These modes cannot be avoided since the slots are so close together. 3.5 Conclusions A micromachined resonator that consists of a cavity, input and output microstrip lines and coupling slots has been fabricated and tested. Measurements have shown an unloaded quality factor Qu of 506, a bandwidth of 5% and an insertion loss of 0.36 dB. Thermal testing has demonstrated that the resonant frequency of the structure does not drift when ambient, temperature increases. Different positioning of the coupling slots with respect to the center of the cavitv has also shown that it is possible to alter the resonator bandwidth at the price 62

Figure 3.12: Micromachined resonator with on-wafer packaging. 8 8.5 9 9.5 10 10.5 11 11.5 Frequency (GHz) Figure 3.13: Simulation results fot the packaged and non-packaged resonator. 63

of changing the insertion loss; a 2% bandwidth with a loss of 1.1 dB has been measured for slots located at 3/8L and 5/8L from the shorter edges of the cavity. Implementation of on-wafer packaging is also possible in order to reduce direct coupling between the microstrip lines when they are close together or achieve shielding of the structure and isolation. The resonator presented in this chapter offers the advantage of having a quality factor which is much higher than that of traditional microstrip or stripline resonators, while maintaining the planar character of the circuit and allowing for easy integration with MIC or MMIC structures and active devices. It also offers reduced weight and size and lower cost when compared with waveguide resonant systems. This resonator can be used for the design and fabrication of planar high-Q filters and multiplexers. 64

CHAPTER 4 GaAs MONOLITHIC MULTIPLIERS 4.1 Introduction For a monolithic transmit/receive module operating at millimeter and sub-millimeter wavelengths, local oscillator sources are necessary. At lower frequencies transistor sources are available and two terminal devices such as Gunn oscillators provide power up to approximately 150 GIIz, but harmonic multipliers are the main RF sources at higher frequencies. A detailed summary and review of multiplier performance can be found in [60], [61]. Most multipliers are based on Schottky barrier diodes with early multipliers using a honeycomb anode chip with a whisker contact across a waveguide mount. Whisker contacted diodes have very low parasitics, but are difficult to handle, can have problems with thermal cycling and vibrations and have performance that is critically dependent on the shape of the whisker. Even with these problems, whisker contacted multipliers were the most common millimeter and submillimeter wave sources until the late 1980s. A typical low power whisker contacted multiplier had 35% efficiency at 98 GIIz [62]. In 1987 Bishop et. al. proposed the microchannel structure as an alternative high frequency planar diode [63]. This structure was much easier to handle and could also be used to fabricate multiple diodes for the same 65

mount. An example of this type of multiplier is given by Rizzi et. al. [64] and has a peak output power of 55 mWV at 174 GI~z and a peak efficiency of 25% using a balanced combination of two diode pairs. More recently, Erickson [65] has demonstrated a fixed tuned planar four diode doubler centered at 150 GlIz that has a 28% peak efficiency, a 3 dB bandwidth of 130-168 GI~z and an output power of 25-40 mW. In addition, Potterfield [66] has fabricated a fixed-tuned 40 to 80 GIIz doubler employing a linear array of 6 Schottky diodes with 48% efficiency and 80-100 mW of output power. Planar diodes are approaching the performance of their whisker counterparts. Most millimeter wave multipliers are based on waveguide circuits. Waveguide circuits have the low loss and high Q needed for efficient multiplier operation and can also include tuners and backshorts needed to optimize for peak performance. However, waveguide mounts are complex and become more difficult and expensive to machine with increasing frequency and smaller size. An alternative approach uses many diodes and quasi-optical techniques to greatly increase the power output [67], [68]. This approach allows the power generation and tuning to function on a spatial grid with each grid element having printed tuning elements. The result is usually increased power and reduced efficiency when compared with waveguide multipliers. Another multiplier approach is monolithic or MMIC multipliers. Many similar MMIC multipliers can be fabricated at the same time using integrated circuit fabrication techniques and thus producing low cost circuits. However, planar circuits tend to have higher loss and lower Q when compared to waveguide ones and it is also more difficult to include tuning elements. Even with these limitations, some very useful MMIC multipliers have been reported. Chen et. al. [14] described a planar MMIC multiplier with an output power of 65 milliwatts and an efficiency of 25% at 94 GHIz using a microstrip circuit. Bruston [15] has also demonstrated a microstrip based doubler from 66

160 to 320 GI~z with 2.8% efficiency. The latter multiplier, however, suffers from moding problems due to the nature of the transmission line that is used. Filipovic [69] designed a balanced varactor multiplier based on grounded-CPW and slotline transmission media with Schottky varactor diodes that yielded an efficiency of 1% at 90 GIz. CPW technology has also been implemented in the design of a Ka-band (18/36 GIIz) FET MMIC doubler that exhibited a maximum conversion gain of 3 to 6 dB [70]. Brauchler [2] used the Finite Ground Coplanar (FGC) line, which is a modified form of the coplanar waveguide, to build a 40 to 80 GIlz doubler with 15-16% efficiency, at least 10 GILz bandwidth and 72 mW of output power. This chapter presents several GaAs FGC line based doublers designed for a higher efficiency and output power in W-band than the ones demonstrated in [2]. The characteristics of FGC lines on GaAs with different geometries and impedances covered with a polyimide overlay for passivation are first presented and compared with similar lines on quartz, which is a low loss substrate. W band multipliers that consist of two Schottky diodes with input Q's of 2 and 3 are then demonstrated and experimental results are compared with simulations. A doubler that has four diodes and can give more output power is also designed and tested. Finally, a method that can increase the efficiency of a doubler by altering the passive circuit design is investigated and experimental results are presented. 4.2 Study of FGC lines High performance line structures are an important part of MMIC design and fabrication at millimeter-wave frequencies [16], [71]. The lines that are traditionally used in planar circuit design are microstrip and coplanar waveguide. For a given substrate thickness and cross section conventional microstrip lines have increasing dielectric loss with frequency. 67

One solution to this problem is to use a low loss material such as quartz as a substrate. However, this requires bonding active circuits onto the quartz, which increases fabrication complexity especially at higher frequencies, while at the same time the requirement for thinned substrates is still important to satisfy in order to avoid moding. CPW lines on the other hand can support parallel plate waveguide modes that can be suppressed with the help of via holes. These vias introduce parasitics and increase fabrication complexity. An alternative transmission line to the ones discussed before is the FGC line, which is a modified Coplanar Waveguide (CPW) structure with improved performance at millimeter wave frequencies [72]. It consists of three strips, one for the signal and two for the ground. similar to the CPW line, but with ground strips that are narrow. The main advantage of the FGC lines is that the cut-off frequency of higher order modes can be controlled in a way that they are far away from the desired band of operation of the structure under test. As a result, parallel plate modes are not excited and vias are not required for ground equalization. The permittivity and attenuation characteristics of FGC lines on GaAs and Si have been extensively investigated by several researchers [73], [2], [74]. Experimental results show that a nearly TEM mode propagates over a wide frequency range (2-118 GIlz) and that loss is mainly ohmic. The use of semiconductor substrates, therefore, will have a small effect on the line loss properties. In addition, the implemetantion of full thickness substrates and the elimination of via holes for mode suppression reduces the cost and complexity of MMIC design and fabrication at millimeter-wave frequencies. Since passivation is an important part of active structure design and fabrication, it is desired to study its effects on the FGC line properties. Polyimide is a well characterized dielectric material that has been extensively used in the past as a passivation layer and as a substrate for the fabrication of microstrip lines [75], [76], [77]. In this section we investigate 68

Signal-Strip Ground-Strips q 'A Polyimide Film Figure 4.1: FGC lines on GaAs with a polyimide overlay the effect of a thin polyimide coating on top of the GaAs FGC lines and compare their performance with low loss quartz based lines. The cross section of the fabricated FGC lines can be seen in Fig. 4.1. Four configurations were fabricated and tested: a) FGC lines on GaAs with Zo=40, 50 and 60 Q, b) FGC lines on GaAs with a 2 im thick polyimide overlay and Z0 = 50 Q, c) FGC lines on GaAs with a 3 Mm thick polyimide overlay and Zo = 50 Q and d) FGC lines on quartz with Z0=70, 90 and 100 Q. 4.2.1 Fabrication The FGC lines were fabricated on a 525 jlm thick semi-insulating GaAs wafer and a 165 Jim thick quartz wafer. The FGC line signal-strip (w), slot (s) and ground-strip (wg) widths were 50, 45. 160 Mm. respectively and correspond to a 50 Q line for GaAs substrate and to 90 Q for quartz substrate. The characteristic impedances were calculated with equations (7.11)-(7.12) of [78] that yield the impedance of a coplanar waveguide line. However, as it was shown in [2] the coplanar strucure confines the electric field near the center of the structure and, thus, truncating the CPW line in a way that does not change the fields 69

near the outer edge of the ground strip will not significantly change the characteristic impedance, effectivity permittivity and loss of the line. The impedance of the resulting FGC line, therefore, is almost the same as that of a CPW line with the same signal and slot widths for an appropriate ground width. The lines were created by using standard lift-off process with a total metal thickness of 1 pm. For a metal alloy that consists primarily of gold and aluminum the skin depth at 40 GIIz is 6s 0.4pm and,therefore, for that frequency the total metal thickness is equal to 2.5 skin depths. After the lines were formed, polyimide Pyralin PI2545 was spun at 4 Krpm and 2.5 Krpm on top of the lines for two GaAs wafers, in order to get a thickness of 2 gm and 3 ym respectively. The pre-cure temperature for the polyimide film was 140~ C and the hard-cure 2000 C, while the baking time was set to 30 minutes and 3 hours respectively. At the beginning and the end of the FGC lines the polyimide was chemically etched in order to allow the probe tips of the measurement system to be in electrical contact with the lines. The relative dielectric constant of the polyimide film is 3.5. The test FGC lines consisted of a thru line with a length of 1.0 mm, a short with a length of 0.5 mm and 3 delay lines with 1.388 mm, 4.106 mm and 10 mm lengths respectively. 4.2.2 Results and Discussion All of the mesurements for the FGC line characteristics were performed with an IIP8510C network analyzer and a probe station using a variety of RF probes. De-embeding was achieved by performing a Thru-Reflect-Line (TRL) calibration with the help of Multical [30], a measurement program available from NIST. This program also provides the effective dielectric permitivity and attenuation characteristics of the lines under test, from the delay line measurements. 70

The effective dielectric constant of the various line configurations is shown in Fig. 4.2. As can be seen, the nearly constant behavior of ~eff over the entire frequency range indicates the propagation of a nearly pure TEM mode. In addition, we observe that the thin film of polyimide is responsible for a slight increase in ceff for both the 2pm polyimide (1.4%) and the 3pim polyimide (2.8%) when compared to that of bare FGC lines. This result is expected since the polyimide thickness is a very small fraction of the line dimensions and, therefore, the filling factor, q, for the polyimide layer that determines its contibution to the total value of the effective dielectric constant according to equation (7.52) of [78] is almost zero. More intuitively, for such a small thickness compared to the signal and slot widths the amount of electric field lines residing in the polyimide is minimal. Fig. 4.3 shows the attenuation per physical length for the four different cases. The straight line between 60 and 70 GIIz represents a gap in the data. As can be seen, the polyimide increases the attenuattion constant with the effect being more pronounced in Wband (12%) and for the thicker polyimide (23% in W-band). The quartz has the smallest attenuation for all the lines. This lower loss when measured in dB/cm is due to the lower effective dielectric constant and higher characteristic impedance of the FGC line on quartz (90 Q compared to 50 Q for GaAs). At 60 GIIz, which is the center of the measurement band, the attenuation for the quartz, bare GaAs, 2 um polyimide overlay and 3 jm polyimide overlay lines is 1.1 dB/cm, 1.7 dB/cm, 2 dB/cm and 2.1 dB/cm, respectively. The results of Figs. 4.2 and 4.3 are in very good agreement with similar results shown in [73], [2], [74] and [75]. Since in most microwave circuits lengths are expressed in terms of guided wavelengths, the attenuation per guided wavelength for the four different lines has been evaluated and is shown in Fig. 4.4. The results are comparable for all four cases with GaAs (bare or with polyimide) being slightly better than quartz. This indicates that the loss of 71

M l I I I I u 7 6 I. LU 4 -: Bare GaAs —: 2 microns polyimide -.: 3 microns polyimide quartz 3 -V -% - -L _______ _____ _.. wj i I I 0 20 40 60 80 100 120 Frequency (GHz) Figure 4.2: Effective dielectric constant vs. frequency for the various FGC lines. -: Bare GaAs 5 -:2 microns polyimide -.: 3 microns polyimide E 4-..: quartz 3... - 0 20 40 60 80 100 120 Frequency (GHz) Figure 4.3: Attenuation per physical length vs. frequency for the various FGC lines. 72

FGC lines is ohmic in nature and independent of the substrate material. As a result, FGC lines are very good candidates for high frequency application circuits, such as multipliers and mixers. Furthemore, we can conclude that the thin layer of polyimide that covers the FGC lines on GaAs for passivation purposes slightly increases the attenuation of the lines. 45 -: Bare GaAs -: 2 microns polyimide 4 - - -.: 3 microns polyimide i 35..:quartz 0 C I3". 2 - ~1.5 -1 - 0.5 0 20 40 60 80 100 120 Frequency (GHz) Figure 4.4: Attenuation per guided wavelength vs. frequency for the various FGC lines. Since the characteristic impedances for the lines investigated were different for GaAs and quartz, additional lines with varying dimensions and impedances were also fabricated. The impedance range for the two substrates corresponds to a convenient range for line fabrication. The line dimensions and the corresponding ZO were calculated with the design equations (7.92) of [78] and can be seen in Table 4.1. From the measured attenuation per physical length, the attenuation per guided wavelength was evaluated and can be seen in Fig. 4.5 for GaAs and Fig. 4.6 for quartz. From Fig. 4.5 we observe that the 50 and 60 Q lines have practically the same attenuation while for the 40 Q line there is an increase of about 100% at 60 GIz which is the center of the entire frequency range. Similarly, from 73

Fig. 4.6 we observe that the attenuation for the 90 and 100 fQ lines is almost the same and that the 70 Q line exhibits a 60% increase from the other two lines at 60 GIIz. These results are expected since the line attenuation can increase considerably if the slot width is decreased a lot, as is the case of the 40 Q and 70 Q lines on GaAs and quartz, respectively, where the slot width is reduced to a third (s % 15upm) of its initial value (s=45 nm). Similar trends where the total line attenuation almost doubles when s+w/2 is half of its original value have been found by other researchers [79], [80]. We should note here that the small ripple observed in the 90 and 100 Q lines is due to ripple in the mismatched measurement system. substrate w (um) s (ium) Zo (Q) GaAs 50 15.45 40 GaAs 50 64.5 60 Quartz 50 18.61 70 Quartz 50 64.5 100 Table 4.1: Geometrical characteristics for the fabricated lines. In order to better understand the behavior of the FGC lines versus impedance, the measured attenuation per physical length data were curve fitted to a a + bdf function and the extracted functions were used in order to evaluate the attenuation per guided wavelength for three different frequency points in the center of each measured band. The final results can be seen in Fig. 4.7 for both quartz and GaAs, where we observe that the attenuation increases as the impedance is decreased. This behavior can be explained from the fact that low-impedance lines have narrow slots and, therefore, the current density at the edges of the slots is higher resulting in more loss. Similar graphs showing the dependence of the 74

7 6 I I I I..: 40 Ohms - 50 Ohms -: 60 Ohms i i j J a3 o1 2 1 I "0i 2 6 I 0 20 40 60 80 100 120 Frequency (GHz) Figure 4.5: Attenuation per guided wavelength for lines on GaAs with different Zo. 7r I I I I 6 -jf5"; - 0!) 34 *z '13 1-' 2 n..: 70 Ohms -: 90 Ohms -: 100 Ohms,.i i0 20 468 0 20 40 60 80 100 120 Frequency (GHz) Figure 4.6: Attenuation per guided wavelength for lines on quartz with different Zo. 75

40 50 60 70 80 90 100 Characteristic Impedance (Ohms) Figure 4.7: Attenuation per guided wavelength vs. characteristic impedance Zo for lines on GaAs and quartz at three different frequencies: fi=19.1 GIIz., f2=50 GIIz and f3=94 GIIz. attenuation on the characteristic impedance of a coplanar line can be found in [78]. In terms of loss in dB/Ag a 50 or 60 Q line on GaAs is equivalent to a 90 Q line on quartz. However, we should note that the 50 Q and 60 Q GaAs lines have the same geometrical dimensions with the 90 Q and 100 Q lines on quartz respectively, indicating a strong dependence of the total line loss on the geometrical characteristics rather than the substrate material and thickness. This feature makes FGC lines ideal for high frequency MMIC's. Having found that in terms of loss GaAs and quartz are equivalent for the same FGC geometry, the choice of material for a substrate depends on other design criteria. If low cost is a major issue then quartz can be chosen with the active devices being flip-chip bonded to it. On the other hand if the active devices must be monolithically integrated with the rest of the circuitry, then GaAs is more appropriate with a thin overlay of polyimide for passivation. GaAs is also more suitable for applications above 120 GIIz where the flip-chip 76

- Schottky Diodes RF Input Doubler Output Matching and Matching and Isolation Network ~ Isolation Network Figure 4.8: Block diagram of the doubler configuration (from F. Brauchler [2]). bonding process increases fabrication complexity considerably. 4.3 W-Band Doublers 4.3.1 Analysis and Design The configuration of the multiplier designs was based on two parallel Schottky barrier diodes that give very good efficiency and output power, as shown by Brauchler [2]. As can be seen in Fig. 4.8, the multipliers consisted of two Schottky diodes connected between the signal line and the ground, with appropriate matching and isolation networks at the input and output ports. The matching networks at the input and output ports provide the appropriate conditions in order to matchan the ofundamental and second harmonic, respectively, while the isolation network at the input side blocks the second harmonic and the isolation network at the output side blocks the fundamental frequency. The goal was to realize multipliers having diodes with input Q's of 2 and 3 and higher efficiencies than the ones presented by Brauchler [2]. A nonlinear multiple reflection program that includes velocity saturation, forward conduction and avalanche breakdown, modified from the code described by East et. al. [81] was 77

used to design the multipliers. The varactor diode is usually specified and the multiplier is designed around it in conventional multiplier design. In this work, the diode parameters become part of the design process; the operating frequency sets the doping level, and the peak RF voltage swing limited by the breakdown voltage set the active epitaxial layer width. Multiplier operation varies from a resistive mode where the current is dominated by conduction current, to a reactive or varactor mode where the current is dominated by the pumping of the depletion layer capacitance. The diode input Q is a measure of the operating mode. Resistive or low Q multipliers have modest efficiencies and wide bandwidths, while reactive multipliers have higher efficiencies and smaller bandwidths. The impedances in high Q circuits are more sensitive to small variations in the dimensions of the lines in the experimental circuits. high Q multipliers also have a larger RF voltage swing across the active device than a lower Q multiplier, for a given available pump power. This limits the pump power in high Q multipliers [81]. Waveguide multipliers can be designed for higher Q, with modest differences in the design vs. realized impedances adjusted with tuners and backshorts. Similar impedances in an MMIC multiplier are fixed, with the bias point being the only available "tuning". The multiple reflection code was modified to adjust the diode area and bias so that the required embedding impedances could be realized for designs with diode input Q's of 2 and 3. The Q=2 diodes had an epitaxial layer doping of 1017/cm3, a thickness of 4000 A and an area of 75,m2 per diode with a bias tuning voltage of-3.0 V, whereas the Q=3 diodes had an area of 66 Pm2 per diode with a bias tuning voltage of -6.0 V. It should be noted here that there is no fundamental difference between the Q=2 and Q=3 diodes (areas are almost the same) except for the bias voltage. This can be explained from the fact that Q oc 1/RdCd (Rd and Cd are the diode resistance and capacitance, respectively) and, thus, increasing the Q 78

requires a smaller RdCd product. Since Rd has a modest variaton with the bias voltage and Cd has a much larger one, increasing the applied voltage yields a smaller capacitance Cd and therefore a larger Q [82]. For the multiplier reflection program the series resistance of either diode was assumed to be 2 Q, which is slightly higher from Rs = 1.459 that equation 1.19 yields for a diode with a 9.6,m diameter (73,um2 area) and the epi layer-parameters mentioned before. The zero bias junction capacitance can be found from equation 1.5 and is 79 fF for the Q=2 diode and 69 fF for the Q=3 diode. The calculated single diode input impedance was 52.3-jlOO Q and 52.4-j160.8 Q for the Q=2 and Q=3 diode, respectively, at the fundamental frequency. The diode output impedance was 41.2-j56 Q for the Q=2 diode and 50.4-j96 Q for the Q=3 diode, at the second harmonic. The reflection program also gave an efficiency of 34% for the Q=2 multiplier and 39% for the Q=3 multiplier. Once the diode input impedances have been calculated, the passive circuitry that will provide the appropriate matching and isolation can be designed with the help of Libra. For simulation purposes the diodes were assumed to be a series combination of a resistor and a capacitor with values found from the known impedances. The design of the multipliers was based on 50 Q FGC lines at the input and output ports, a second harmonic trap at the input side and a fundamental trap at the output side. High impedance line sections that acted as inductors, connected the main line of the multipliers to the diodes in order to cancel out their average capacitance. A block diagram of the passive circuitry with the diodes can be seen in Fig. 4.9. For a 40 to 80 GHIz doubler, the trap at the input side consisted of a Ag/4 open stub at 80 GhIz connected in parallel with a Ag/4 section of line at the same frequency. This combination of Ag/4 segments of line, imposes an open for the 80 GhIz signal looking towards the input side at the point were the inductive lines are connected to the main 50 Q line. Similarly, at the output a Ag/4 open stub at 40 GIIz was connected in parallel with a 79

F I 49Q B II 49/42 Q Q 50 Q 50 Q 50 Q A Input fo C B 49/42 Q E G H Output 2ft F I I 49fQ Figure 4.9: Multiplier configuration with passive circuits. Ag/4 section of line at 40 GIIz, in order to block the fundamental frequency signal. A low impedance section was also used at the output side in order to match the relatively low real part of impedance of the parallel combination of the two diodes. The lengths of the different FGC line sections were calculated with Libra, where the diodes were modeled as a resistor in series with a capacitor and the line segments were modeled as ideal transmission lines with known characteristic impedance, attenuation and effective dielectric constant. The dimensions of the 50 Q line were w=50,m. s=45,m. Wg = 160prn and correspond to a higher order mode cut-off frequency of approximately 180 GIIz. For FGC line sections other than the 50 Q, the properties and geometrical characteristics can be found in [2]. The purpose of each simulation was to optimize matching of the diodes both at the input and output, while at the same time optimize the blocking capability of the traps. Results for the Q=2 and 3 multipliers are summarized in Tables 4.2 and 4.3, respectively. When the lengths of the different FGC line sections were determined, the harmonic balance test bench of Libra was used to evaluate the efficiency of the multipliers. A schematic 80

Section Section Description w (/m) s (/m) Length (/m) A 50 Q signal launch structure 50 45 500 B 49 Q open-end balanced stub 20 20 331 C 50 Q standard section 50 45 375 D 71 Q diode feed lines 20 80 210 E 50 Q standard section 50 45 709 F 49 Q open-end balanced stub 20 20 709 G 21.5 Q low impedance section 120 10 300 II 50 Q signal launch structure 50 45 500 Table 4.2: Geometrical characteristics for the Q=2 multiplier. Section Section Description w (um) s (gm) Length (jm) A 50 Q signal launch structure 50 45 500 B 42 Q open-end balanced stub 50 19 346 C 50 Q standard section 50 45 360 D 71 Q diode feed lines 20 80 268 E 50 2 standard section 50 45 702 F 49 Q open-end balanced stub 20 20 682 G 21.5 n low impedance section 120 10 307 II 50 Q signal launch structure 50 45 500 Table 4.3: Geometrical characteristics for the Q=3 multiplier. 81

of the test bench can be seen in Fig. 4.10. For this analysis, the Schottky diodes were modeled with their DC parameters (series resistance, zero-bias capacitance, ideality factor and reverse leakage current). Optimum results can be seen in Fig. 4.11, where the Q=2 multiplier yields an efficiency of 20.5% and a bandwidth of 23% (9 GIIz) at 39.7 GIIz for an input power of 20 dBm and a bias of -2.5 V, while the Q=3 multiplier gives an efficiency of 26% and a bandwidth of 14% (5.5 GHIz) at 38.7 GlIz for an input power of 17 dBm and a -5 V bias. The efficiencies are lower than the ones given by the multiple reflection program since Libra accounts for the losses in the passive circuits as well as any possible mismatches between the diode impedances and the rest of the circuitry. Simulating the Q=2 and Q=3 multipliers without any loss in the various line segments yields an efficiency of approximately 32% and 40%, respectively, for the same bias and diode parameters that were used in the previous simulations. 4.3.2 Measurement System The system that was used to evaluate the performance of the W-band multipliers can be seen in Figs. 4.12 and 4.13. and consists of two different sub-systems at the input and output sides. More specifically, at the input the IIP8510C network analyzer drives the 26-40 GI~z mm-wave source module that is connected to a Travelling Wave Tube (TWT) via an attenuator. The attenuator helps control the output power level of the TWT that provides more power at the input of the multipliers in order to get as much efficiency as possible. The output of the TWT is connected to a waveguide system that includes mixers, isolators and attenuators needed for the measurement of the return loss via the analyzer, as well as a 20 dB coupler that is connected to a power meter used for sampling the power provided by the TWT at its output port. The waveguide system is followed by a waveguide-to-coax 82

;.... (- -i I5 i 2..;..... E.:,, EJ|~:,..3 I — ~ Lis-'~:'~" La ~.' 1^.0 o harmonic balance analysis test bench., — ~ ~..,~.os v- -,~,' ' D D r-0;. ro -o Irc,.,:,,.r,., 1o,,,O vo,.2-. -— 0 - ~-. o.;,-or.a -

30 25 20 t^ 15 e.-m i 10 E o 5 0 30 35 40 45 Frequency (GHz) 50 (a) 20 15 10 -5 E 5 T3 = 0 -5 -10 -15 0 5 10 15 20 Pi n(dB) | n m 25 30 (b) Figure 4.11: Simulation results for the W-band multipliers: (a) efficiency vs. input frequency with an input power of 20 and 17 dBm for Q=2 and 3, respectively and (b) output power vs. input power at f=39.7 and 38.7 GIIz for Q=2 and 3, respectively. 84

variable 8510C VNA mm-wave source -- attenuator TWT 26-40 GHz DC power po er supply O meter ---- W- W/G |power W/G sy- meter - WR-10 W/G MMIC/ to coax tem power W-band K-band sensor probe probe Figure 4.12: Block diagram of the measurement system used to evaluate the performance of W-band doublers. transition, a coaxial cable and a K-band 150 1um pitch GGB industries probes. The subsystem at the output side consists of a W-band 150 Mm pitch probe with a bias-tee that is connected to a long piece of WR-10 waveguide. A DC power supply is connected to the bias tee of the probe with the help of a coaxial cable and is used to reverse bias the Schottky diodes. The output of the WR-10 waveguide is connected to a power sensor from 60-90 GIlz followed by a power meter that measures the output power. The combination of the two sub-systems limits the output measurement frequency range from 60 to 80 GIIz. In order to measure the efficiency of the multipliers the losses introduced by the different components must be found so that they can be de-embedded from the measured data. In addition, for return loss measurements the sub-system at the imput needs to be calibrated with one of the known calibration techniques. The losses of the various components are measured first with the IIP8510C analyzer. For the input side the system is calibrated at the waveguide flange just before the W/G-to-coax transition with the help of a short, an offset short and a load. Once this is done, the transiton with the cable and the probe are connected. The loss introduced by these three components is evaluated by measuring a planar short, open and 50 Q load standard at the end of the probe tips. Assuming that 85

Figure 4.13: Photograph of the actual system that was used for the multiplier measurements. the three components constitute a system with unknown S-parameters S11,,S22 and 521, measuring the return loss of the three standards yields a system of three equations with three unknowns: Sl1 - load (4.1) = 2rltoad - short - Fopen (4.2) 1 short - open S12 =21 = (522- 1)(rload - ropen) (4.3) When this system is solved, the loss (i.e. S21 when S11,5S22 are below 10 dB) for the input side is found to be about 5.8~0.3 dB from 35 to 40 GItz. Similarly, for the output system the loss is found to be approximately 3 dB. Once the losses have been found for each frequency point, they can be de-embedded and the input power can be referenced at the end of the probe tips. Similarly, the losses at the output are extracted and the power at the end of the MMIC doubler can be found. 86

4 -114 0 36 Frequency (GHz) 40 Figure 4.14: Output power vs. frequency of the TWT measured at the flange of the waveguide system for a fixed position of the attenuator. Knowing both the input and the output power at the two ends of the multiplier allows us to evaluate the efficiency over the entire measured frequency range. Regarding the measurement of the return loss, the system is calibrated with the help of a one port Short-Open-Load calibration. Since the return loss will be measured with a relatively high input power drive and is also dependent on the frequency response and impedance of the TWT, the output power of the TWT versus frequency is measured first. The input system is calibrated at the waveguide flange and the attenuator is set at a certain position. A second power meter connected to the flange measures the power at that point and the results are shown in Fig. 4.14. From Fig. 4.14 it is clear that the output power of the TWT decreases as the frequency increases in a non-linear way. In order to make, therefore, measurements with a constant input drive the attenuator needs to be adjusted accordingly. In order to make a return loss measurement versus frequency at a constant input power 87

level, the frequency range of interest is divided into 3 sub-regions with the criterion that at each sub-region the output response of the TWT will not change a lot (no more than 2 dB). This is necessary because the TWT has a different impedance for different power levels and calibrating the system at a particular power, where the impedance has a certain value. does not guarantee that the correct return loss will be measured at a different power and impedance since the system will have changed. The first sub-region is from 34 to 37.5 GlIz, where the power of the TWT is almost constant, and the attenuator is set to provide 20 dBm of input power at 36.25 GIz. The second sub-region is from 37.5 to 38.5 GlIz and the attenuator is set to provide the desired power level at 38 GIz, while the third one is from 38.5 to 40 G(Iz and the reference frequency for the attenuator is 39.25 GI~z. Calibrating each sub-region one at a time with the attenuator set to provide a desired input power to the doubler (in this case 100 mW) at the center of the band, ensures that the necessary adjustments to the attenuator value that are required to maintain the desired power level for each frequency point of the band will not affect greatly the calibration coefficients and alter the measured data. In this way, the measurement of the return loss can be done automatically with the help of the IIP8510C network analyzer. 4.3.3 Results and Discussion The Q=2 and Q=3 multiplier circuits, designed for an 80 GlIz output frequency, were printed on a semi-insulating GaAs wafer after the doped active layer was etched away (for details on fabrication see appendix B). The total metal thickness of the passive circuits was 1ym, which for a 50 Q line (w=50 1um, s=45,m, Wg=160,m) yields a loss of 1.55 dB/cm at 40 GItz and 2.32 dB/cm at 80 GItz. A picture of the fabricated Q=3 doubler can be seen in Fig. 4.15, while an SEM photo of the Schottky diode can be seen in Fig. 4.16. The 88

Figure 4.15: Fabricated Q=3 W-band doubler. DC characteristics of the diodes were measured with an I1P4155A semiconductor parameter analyzer and an IIP4285A precision LCR meter. The doping profile of the wafer used for the fabrication of the doublers was extracted by measuring the C-V characteristic of a test diode with 220 um anode diameter, and is shown in Fig. 4.17. As can be seen, the doping density is almost constant and equal to l.lxlO17/cm3 which is very close to the IxlO17/cm3 value quoted by the manufacturer. The built-in voltage potential was also calculated from the capacitance measurement of the test diode to be Vbi = 0.95V The measured C-V characteristics of the Q=2 and Q=3 fabricated diodes are shown in Fig. 4.18, where the actual data are curve fitted to an equation of the form Cjo Ct = Cp + (4.4) 0. 95 where Ct, Cp, Cjo are the total, parasitic and zero-bias capacitances respectively. After curve fitting with equation 4.4, the parasitic and zero-bias capacitances for the Q=2 diode were found to be 19 and 98 fF, respectively. Results for the Q=2 and Q=3 diodes are summarized in Table 4.4, where we observe 89

Schottky anode Air-bridge Circuit mel Ohmic cathc -Mesa Figure 4.16: SEM photo of fabricated Schottky diode. 2 101 7, "q.8 ci 4.6.Q1.4 -2 1 101 7 101 7 101 7 101 7 I I I I I I I I I I I I I I I Ir 101 7. l l,,,!.. l l l l l.. l l,,,, 1000 1500 2000 2500 3000 3500 4( Distance (A~) )00 Figure 4.17: Doping profile for the wafer used to fabricate the W-band doublers. 90

1.4 10-13 1.2 10 13.., -, r,, r T - T r! r T 1 X 1 10-13 8 10-14 6 10'14 4 10 14 -Q=2 Q=3 / I 1 2 10-14 L -10 I I I I I I II -8 -6 -4 -2 Bias Voltage (V) 0 2 Figure 4.18: Total capacitance vs. bias voltage for the Q=2 and Q=3 diodes. that the zero-bias capacitances are a bit higher than the ones expected for both diodes. This is due to fabrication tolerances in the mask making process that resulted in diode diameters larger by 1.2,m than the ones anticipated. For the parasitic capacitances an electrostatic simulation of the anode area, the ohmic and the air-bridge in Maxwell [83] yields a value around 10 fF. An additional 1-2 fF are expected from the parasitics between the air-bridge and the high-doped n+ layer. The ratio of the maximum over minimum capacitance, Cmax/Cmi,, for the Q=2 and 3 diodes ranged from 2.5 to 2.7. Diode input Q Rs(Q) Cjo (fF) C, (fF) 71 I, (fA) VBR (V) fc (GIz) 2 2.2 99 19 1.16 180 -11.8 614 3 2.2 88 13 1.15 185 -11.8 717 Table 4.4: Measured DC characteristics for the W-band fabricated diodes. 91

20 15.10 1 0Z -5 '".-10 7 20 15 3 0 0o ~J l 0 7 20 15 l-, 10 5 0 1 -5.~ n 72 74 76 78 80 Frequency (GHz) 1 U (a)................... a " L ' ' --- - r./- — '- --- -- - -- --- 0/ | — Output Power -a -- Efficiency 20 15 10 C;o~ 5 Im w 0 i - -5 1 10 iI I I -I - 5 15 20 25 Input Power (dBm) 30 (b) Figure 4.19: Measured results for the Q=2 doubler: (a) efficiency and return loss vs. frequency for an input power of 20 dBm and (b) output power and efficiency vs. input power at 76.3 GIIz. 92

Measured results for the Q=2 doubler are presented in Fig. 4.19(a) where we observe that a peak efficiency of 17.2% was achieved at 76.3 GI~z and a -3.5 V bias with a return loss of -4.5 dB and a -3 dB bandwidth of at least 10% (8 GINz). We should note here that for each frequency point the bias was optimized for maximum efficiency. A comparison between the measurements and the Libra simulations of Fig. 4.11(a) reveals a shift in the optimum frequency, that is due partly to the higher junction capacitance which is a result of the enlarged fabricated diode and partly to the parasitic capacitance. The 17.2% measured efficiency is in good agreement with the predicted Libra value of 20%. A Libra simulation that includes the parasitic capacitance of 19 fF yields an efficiency of approximately 17%, as can be seen in Fig. 4.20, verifying the fact that parasitics tend to degrade the diode performance and overall circuit efficiency. If we account for the 1.5 dB circuit loss at 76 GIIz and the -4.5 dB return loss then the de-embedded efficiency becomes 36.5% which is a bit higher than the 34% value calculated by the multiple reflection program. The small discrepancy can be attributed to the sensitivity in the measurement of the return loss for different bias voltages. The ripple that is present in the efficiency measurement is partly due to the coaxial cable of the system set-up and partly to the different bias voltage used at each frequency point for maximum output efficiency (measurements with a waveguide part instead of a coaxial and at a nearly constant voltage level are much smoother as it will be shown in the next section). The suppression of the fundamental frequency measured at the output of the multiplier with the lIP8510C was -18 dB. Figure 4.19(a) also shows that the measured return loss increases with frequency. This behavior is typical of a matching network that achieves very good matching of the diode impedance at a particular frequency, with increasing mismatching as the frequency deviates from the optimal point. The expected return loss trend for the Q=2 multiplier can be seen in Fig. 4.21, where we observe that 93

25 I I 20 -. ~ ~ I I,, -,, F ~ - 30 35 40 45 50 Frequency (GHz) Figure 4.20: Simulated results for the Q=2 and Q=3 doublers with measured diode DC parameters and input power of 20 and 17 dBm, respectively. a minimum is reached around 34 GILz and beyond that point the return loss increases. Figure 4.21 also reveals that increasing the bias voltage and, thus, the diode input Q tends to degrade the return loss of the multiplier (this effect will be explained later in the chapter). The output power at 76.3 GIz for a varying input power can be seen in Fig. 4.19(b), where a maximum of 66 mW was achieved for an input power of about 26 dBm. In the same figure we can also observe that the efficiency decreases for input power levels greater than 22 dBm with a final value of 15.5% at 26 dBm, due to current saturation in the diodes. The measured output power of 66 mW is in very good agreement with the 70 mW value from the simulated results. Since power availability was limited by the measurement system and the diode burn-out point, evaluation of the multiplier performance at even higher power levels was not possible. For the Q=3 multiplier the measured results are shown in Fig. 4.22. The peak efficiency 94

0 -2 > \ / e - \ / i wa - 12,, /, 3 6 - Q=2 2 -8-.12 -------------- 30 35 40 45 50 Frequency (GHz) Figure 4.21: Simulated return loss for the Q=2 and Q=3 doublers with measured diode DC parameters and input power of 20 and 17 dBm, respectively. and return loss were 22.0% and -5 dB, respectively, at 70 GlIz and a voltage of -5.5 V while the -3 dB bandwidth was approximately 8.5% (6 GI~z). Taking into account the 0.7 dB circuit loss at 70 GItz and the -5 dB return loss, yields an efficiency of 37% which is very close to the 39% value predicted by the reflection program. In addition, the measured efficiency is in good agreement with the 25.5% Libra result. The lower measured peak frequency can be attributed to the larger area of the fabricated anode (25% increase) and the parasitic capacitance, as well as the increased sensitivity of the diode impedance to small variations in the dimensions of the lines which makes it more difficult to match it at a specified frequency. A re-evaluation of the doubler's efficiency in Libra including the parasitic capacitance of 13 fF yields a value of approximately 22% at 73 GIz, as shown in Fig. 4.20. The input power level for the Q=3 multiplier was 17 dBm, in contrast with the Q=2 multiplier where the input level was 20 dBm. For higher input power levels the efficiency of the Q=3 multiplier 95

25 - 20 15 — 10 0 -5 -10, 66 ' l....25 20 ---- 25 m 102 - 5 7 7 - 0 - -5 7, I -10 73 74 67 68 69 70 71 72 Frequency (GHz) (a) S *&~ lz - o w 0 zo & C 25 20 15 10 5 0 z -5 ', ', I ' ' 1 ' I ' ' ' ' I ', ',,. _ '" -... 0.,/ -A- Output Power / -- o --- Efficiency 1, 1 I, I,,, I,,,,ll I,, 25 20 15. 10 |.0 c *5 g o I 5 10 15 20 25 Input Power (dBm) 30 30 (b) Figure 4.22: Measured results for the Q=3 doubler: (a) efficiency and return loss vs. frequency for an input power of 17 dBm and (b) output power and efficiency vs. input power at 70 GIIz. 96

decreased significantly; a 15% value was measured at 24 dBm as can be seen in Fig. 4.22(b). This is expected. since for higher Q's the RF voltage swing across the diode increases for a given available RF power, leading to increased saturation effects in the device and limiting the maximum input power before burn out. If we model the diode as a series resistor and capacitor that is connected to an RF source and a matching impedance, as shown in Fig. 4.23(a), then it is possible to deduce an equation for the voltage accross the diode [82]. The diode Q at the input frequency is Qd = Xd/Rd = -l/(wCdRd) and if we assume conjugate matching for maximum power transfer then Rs = Rd and Xm = wLm = -Xdi. As a result, the current flowing in the loop is Irf = Vrf/(2Rd) and the voltage Vd across the diode can be written as Vd = IrfZd = -iQd). (4.5) From equation 4.5 it is clear that for a given RF power the voltage across the diode increases as the input Q increases. Therefore, a higher input Q multiplier will have a larger voltage swing that will lead to increased saturation effects in the device. A maximum output power of approximately 50 mW was measured for an input power of 400 mW. The Q=3 doubler also has a smaller bandwidth than the Q=2, since both the the diode and embedding impedances vary more rapidly with frequency, mismatching the input pump power. In order to better understand this behavior, the return loss bandwidth for an input diode Q of 2 and 3 with an impedance of 50-j1OO Q and 50-j150 Q at 40 GIIz, respectively, was evaluated based on the circuit model of Fig. 4.23(a). The reflection coefficient is given by Zn - 50 j(wL - ) Zin + 50 100 + j(wL - c) 97

R=50 Q I Lm Rd i, Diode VRF Zin (a) -15 CD 2-20 ~ -25 E -30 a: 40 Frequency (GHz) 50 (b) Figure 4.23: Theoretical analysis for the diode bandwidth: a) equivalent circuit model and b) results based on equation 4.6. 98

where L = -1 for w = Wmatch. If we plot the amplitude of the reflection coefficient for the Q=2 and 3 diodes used to design the multipliers, then from Fig. 4.23(b) we observe that the -10 dB bandwidth for the Q=2 case (12 GIIz) is 1.5 times larger than the Q=3 bandwidth (8 GIIz). This is in good agreement with the 1.4 bandwidth ratio that can be found from Fig. 4.20 and the 1.33 ratio of the measured results (8 GIIz versus 6 GIIz). Higher Q multipliers, therefore, can achieve more efficiency with less bandwidth than lower Q's, but at smaller input power levels resulting in smaller output power due to the saturation effects [82]. 4.3.4 A Four Diode Design This section presents the design, analysis and experimental results of a W-band doubler from 40 to 80 GIIz with four Q=2 diodes, that can achieve higher output power. The configuration of such a doubler is similar to the one shown in Fig. 4.9, except that two diodes in series instead of one are connected at each parallel branch, and the addition of a low impedance section at the input for matching purposes (see Fig. 4.24). For the diodes, the assumption is made that each one has the same area as the diodes used in the doubler of the previous section (75,um2), and as a result the input impedance at the fundamental is 52-j106 Q while the output impedance at the second harmonic is 41.2-j56 Q. The series resistance and zero-junction bias capacitance are also assumed to be 2 Q and 75 fF, respectively, per diode for analysis purposes. The matching and isolation networks at the input and output side were first designed in Libra, where the diodes were modeled as a series combination of a resistor and a capacitor. Quarter wavelength open-end stubs were placed at the input and output that block the second harmonic and fundamental, respectively. The diodes were connected to the main 99

G I492 C 1 149Q 71Q 31 Q 50 Q 50 Q A B Input fo D F H I Output 2fo C I 492 G |[ 490 Figure 4.24: Multiplier configuration with passive circuits and four diodes. 50 Q line with high impedance inductive lines. In order to achieve a good matching at the input a low impedance section had to be inserted before the open-end stubs that trap the second harmonic. The dimensions and lengths of the various line segments, according to the schematic of Fig. 4.24, can be seen in Table 4.5. With the lengths of the different line sections specified, the performance of the doubler was simulated in the harmonic balance test bench of Libra. Each diode was simulated with a pn junction model of known DC parameters (series resistance, junction capacitance, reverse leakage current etc.). Optimum results can be seen in Fig. 4.25(a), where an efficiency of 18% and a 3 dB bandwidth of 17% are achieved at 41.25 GIIz for a bias voltage of -5 V, which is twice the voltage used in the two diode case. Fig. 4.25(b) also shows that an output power of 100 mW or more is feasible for an input power greater than 30 dBm. The four diode doubler was fabricated on the same wafer that was used for the fabrication of the Q=2 and Q=3 doublers (Nld=1x1017cn-3 thickness= 4000 A), after the active epilayers were etched away from the diodes. A photograph of the actual doubler can be seen 100

20 15 e 5 30 35 40 45 Frequency (GHz) 50 (a) E m3 I=j Q) w 16. cm 4. 0 30, 20 -10 - r rt- 10 I I I. I I I I.I... I I I.I I I I I TI I I T!I I I1 1 1 I 1I I II I I I I... I I.. I I I.. -20 I illll L 1I1I11 I1 I I L1I 0 5 10 15 20 25 Input Power (dB.) - - - - - - - - 30 35 (b) Figure 4.25: Simulated results for the four diode doubler: a) efficiency vs. input frequency for an input power of 20 dBm and b) output power vs. input power at 41.25 GIMz. 101

Section Section Description w (pm) s (rim) Length (jm) A 50 Q signal launch structure 50 45 500 B 31 Q low impedance section 100 20 660 C 49 Q open-end balanced stub 20 20 331 D 50 Q standard section 50 45 354 E 71 Q diode feed lines 20 80 180 F 50 Q standard section 50 45 709 G 49 Q open-end balanced stub 20 20 682 II 21.5 Q low impedance section 120 10 380 I 50 fl signal launch structure 50 45 500 Table 4.5: Geometrical characteristics for the Q=2 four diode doubler. in Fig. 4.26, where we observe low impedance sections both at the input and the output, and a close-up of the diodes in Fig. 4.27. The diode DC characteristics were measured first and results are summarized in Table 4.6. The parasitic capacitance per diode was found to be 21.5 fF, which is a bit higher (10%) than the corresponding value of the Q=2 two diode design. Table 4.6: Measured DC characteristics per diode for the four diode doubler design. In order to measure the performance of the four diode doubler the system of Fig. 4.12 was reconfigured in a way that the losses of the sub-system at the input are minimized. More specifically, the coaxial cable that connected the waveguide-to-coax transition to the 102

Figure 4.26: Photograph of the fabricated four diode doubler. Figure 4.27: SEM photo of two diodes in series. 103

input K-band probe was replaced with WR-28 segments of waveguide. The transition was placed at the end of WR-28 segments and was connected to the GGB probe via a 3.5 mm male-to-male adaptor. With this substitution the losses of the input sub-system were found to be 3.5~0.3 dB and could allow for more available input power. In addition, a WR-10 E-II tuner was placed at the output side after the probe, so as to minimize any mismatches between the output part of the multiplier and the diode impedances. It is expected that the E-IL tuner would increase the measured efficiency by a small percentage due to the improved matching conditions at the output side of the monolithic doublers. Efficiency measurements for the doubler with the dimensions of Table 4.5 can be seen in Figs. 4.28(a), 4.28(b) for an input power of 20 and 23 dBm, respectively. Figure 4.28(a) shows that a 12.5% efficiency was achieved at approximately 74 GIIz with a return loss of -15 dB and a minimum bandwidth of 12.5% for an input power of 20 dBm and a bias voltage of -3.5 V. For a 23 dBm input power and the same bias voltage the efficiency did not change significantly but the return loss became better especially for output frequencies above 76 GItz (at 40 GILz return loss went from -5 dB to -9 dB), as seen in Fig. 4.28(b). This means that pumping the four diode combination harder changes the impedances in a way that the input matching is improved, under the condition that the bias voltage does not change substantially. It should also be noted here that the E-II tuner at the output improved the power coming out of the multiplier by 5 to 10%, when compared to the measurement with no tuner. The measured output power versus input power at 74 GlIz is shown in Fig. 4.29, where an output power of 115 mW was achieved for an input of 1130 mW and a -12 bias voltage. Without the E-II tuner the output power for the same input drive was measured to be 105 mW. Both of these measured output powers are the highest reported for a monolithic 104

15 10 5 0 -- Efficiency -- - - - Return Loss - / - - - - - I ^-^^^'____ 15 10 co 0. -5 = -10 -15 5 -10 -15 70 72 74 76 Frequency (GHz) (a) 78 80 20 10 0 -10 -20 -30 -40 _ s! \, ------—., Efficiency - - — Return Loss Lv 20 10 0 - 0 -30 -20 -30 I I I I I I I I I.. I i I -40 80 70 72 74 76 Frequency (GHz) 78 (b) Figure 4.28: Efficiency and return loss vs. output frequency of the four diode doubler for an input power of: a) 20 dBm and b) 23 dBm. 105

W-band doubler. The return loss of the doubler for 1130 mW of input was approximately -10 dB, which is higher than the -30 dB value for 200 mW of input. However, at 200 mW the bias voltage is much lower (-3.5 V) than the -12 V value. Several measurements have shown that an increase in the bias of the diodes results in the degradation of the measured return loss. This can be explained from the fact that for a given passive circuit design with the stubs adjusted to match a certain device impedance, increasing the voltage will increase the imaginary part of the diode impedance and therefore deviate from the optimal matching point and deteriorate the return loss. The simulated return loss results of Fig. 4.21 corroborate this explanation, since the Q=3 multiplier that has a higher return loss is biased at a higher (more negative) voltage. A higher imaginary part, however, increases the input Q of the diode and can yield a higher multiplier efficiency. The four diode doubler design gave a higher output power than the two diode one but at a lower efficiency, since the two diodes in series can sustain much more input power before they reach the burn-out point. A Libra simulation of the doubler taking into account the parasitic capacitance and a -3.5 V bias voltage, yields an efficiency of 13% at 39 GIIz and 17% bandwidth (see Fig. 4.30), which are in good agreement with the measured results. Therefore, the parasitics and the lower applied voltage decrease the estimated efficiency by approximately 25% (from 18% to 13%). 4.3.5 Improved Designs In the multiplier designs presented in the previous section, the 50 Q parallel open end stubs had a different geometry than the standard 50 Q line. More specifically, for the stubs w=s=20 Mim while for the main 50 Q line w=50 yjm, s=45 Jim. The smaller slot and center 106

?,PQr s s-< 0 o 3 c, 3! 0 25 20 15 10 5 0 -5 e-, / -- Output Power — e —Efficiency -!111111111 | I 25 20 15? 10 0 5 - 10 15 20 25 Input Power (dBm) 30 35 Figure 4.29: Output doubler. power and efficiency vs. input power at 74 GIIz for the four diode 14 12 8 w 6 2 0 30 35 40 Frequency (GHz) 45 50 Figure 4.30: Simulation of four diode doubler including the measured diode characteristics for an input power of 20 dBm. 107

Section Section Description w (/im) s (/m) Length (/im) A 50 Q signal launch structure 50 45 170 B 50 Q open-end balanced stub 50 45 318 C 50 Q standard section 50 45 375 D 71 Q diode feed lines 20 80 210 E 50 Q standard section 50 45 694 F 50 Q open-end balanced stub 50 45 709 G 21.5 Q low impedance section 120 10 300 II 50 Q signal launch structure 50 45 190 Table 4.7: Geometrical characteristics for the improved Q=2 multiplier. conductor width increase the attenuation of the stubs to about 0.23 dB/mm at 20 GIz, when the attenuation of the regular 50 Q line is about 0.12 dB/mm at 20 GItz, almost half the value (both lines have a metalization thickness of lIm). One way to improve the efficiency of the doublers would be to replace the shunt stubs with new ones that have wider slot and signal line widths, in an effort to reduce the ohmic loss of the circuit. From the 50 Q FGC lines studied so far the one with w=50 /m, s=45um and Wg = 160pm has the optimum behavior in terms of loss. For this reason, the output circuit of the doubler with the two different geometries of the stubs was simulated in Sonnet (Fig. 4.31), and results indicated a 1-1.5 dB decrease in the total loss around 80 GI~z. Such a difference can lead to a 20-25% improvement of the doubler's efficiency. A doubler design with input diode Q of 2, two diodes and an area of 75 pjn2 per anode was implemented. An epi-layer with a 4000 A thickness and a Ixl017cm-3 doping density, as in the previous section, was assumed. The wafer, however, used for the fabrication of 108

-4 5 4 - -7 8 - U — - / / ---- -old stub 9 / new stub -10 40 50 60 70 80 Frequency (GHz) Figure 4.31: Simulated results for the output circuit of the doubler with the wide (new) and narrow (old) stubs. the new multipliers was different from the wafer used before. The shunt 50 Q stubs had w=50 um and s=45,m, while the line segments at the input and output ports were made shorter. Geometrical characteristics for the new doubler are summarized in Table 4.7. Since the wafer that was used was physically different, the old doubler design was repeated just for comparison purposes. Efficiency measurements with the same system that was used in the four diode doubler case (only waveguide components at the input and E-II tuner at the output), for the new and old Q=2 design can be seen in Fig. 4.32. The improved doubler design exhibited a 14.8% efficiency at 75.5 GI~z and a bias voltage of -2.2 V with a minimum bandwidth of 13.2% (10 GItz) and a -15 dB return loss, while the old design gave an efficiency of 11.5% at 76.6 GI~z and a bias voltage of-2.1 V with a 13% minimum bandwidth and a -10 dB return loss. Clearly, the new design has a higher efficiency than the old one, but none of them surpasses the performance of the Q=2 doubler presented in the previous section. When the 109

20 10 - e.E -20 -30 -40 I I I I I ' 1 I T I I I I I I I I r - / _.- - -.. - - / -.. - '- - | Efficiency - ----- Return Loss.,,I,,, I.., I,., I.,, 20 10 -10. -20 I Q -30 -40 J0 1111111111111111111 70 72 74 76 Frequency (GHz) (a) 78 8 15 10 o - ci eCm c. 5 0 ' ' ' [ I ' I [ ' I ] ' ' I ' [ Efficiency - - - - - Return Loss - "~ 15 10 5 -5 rd &M o ^ O e - -10 -15 0 10 -15 I I I I I, I i I I i I I i 70 72 74 76 Frequency (GHz) 78 8 (b) Figure 4.32: Efficiency and return loss vs. output frequency for doublers fabricated on a new wafer and Pi2=20 dBm: a) improved Q=2 design and b) old Q=2 design. 110

doping profile of the new wafer was measured, it was found that the doping density had a value of 0.5x1017cm-3 instead of x1017cm-3. This is a major difference and for a given anode area a smaller doping can decrease the diode efficiency [82] and alter the diode and embedding impedances. In addition, the optimum bias voltage of the new doublers was around -2 V which is lower than the bias voltage applied to the old ones (-3.5 V for the Q=2 and -5.5 V for the Q=3). Most of the multiplier measurements and the simulations with the multiple reflection program showed an increased efficiency for biases above -3 V, while lower values were achieved for biases between -2 and -1 V. Simulating a 40 to 80 Gl~z doubler with the multiple reflection program for a doping density of 0.5x1017cm-3 and a bias voltage of -2 V yields an efficiency of 28% instead of 34% which was the original result. Since the circuit losses are the same in both multipliers if we take into account the -9 dB return loss and the effect of the parasitic capacitance the efficiency is found to be around 13.5%, which is close to the 11.5% measured value. The combination, therefore, of the lower doping concentration and optimum bias point leads to the reduction of the efficiency, when the same design on the old and new wafers are compared. However, when the improved doubler with the wider stubs is compared to the original design and both circuits are fabricated on the same wafer, the new design yields a higher efficiency (25 %/ increase) proving that further improvement of the multiplier performance is feasible if the passive circuit loss is reduced. 4.4 Conclusions FGC lines on GaAs with a thin overlay of polyimide were fabricated and tested. Experimental results showed a negligible increase in the effective dielectric constant and a small increase in the attenuation per physical length, when compared with bare FGC lines on 111

GaAs. The attenuation per physical length of FGC lines on GaAs with or without polyimide was higher than that of FGC lines on quartz. The attenuation per guided wavelength, however, was almost the same for all types of lines investigated in this chapter, indicating that the total loss of FGC lines with the same geometry is independent of the substrate material. This allows for the use of a thin layer of polyimide over FGC lines on GaAs without increasing the total loss in actual circuits while providing passivation at the same time. In addition, the attenuation of the lines decreased in a non linear fashion versus characteristic impedance. As a result, FGC lines with a polyimide overlay can be used in millimeter wave receivers and transmitters fabricated on GaAs, where the active devices are monolithically integrated with the other circuitry and do not need to be flip-chip bonded as in the case of quartz. Monolithic doublers with two diodes and input Q's of 2 and 3 were also designed, fabricated and tested. The Q=2 multiplier had an efficiency of 17.2% at 76.3 GI~z, a minimum bandwidth of 10% and a maximum output power of 66 mW, while the Q=3 multiplier yielded an efficiency of 22% at 70 GI~z, a bandwidth of 8.5% and a maximum output power of 50 mW. These are the highest reported values for both efficiency and bandwidth regarding monolithic multipliers. The microstrip doubler designed by Chen [14] yielded an efficiency of 25% at 94 GILz but no bandwidth information was provided. All the monolithic results, however, reported thus far in the literature cannot surpass the performance of waveguide doublers, such as the one by Porterfield [66] where a 48% efficiency and 17% bandwidth were achieved at 80 GItz. The optimum efficiency for the Q=2 design was achieved at a higher input power level from the Q=3 design (20 instead of 17 dBm) since the RF voltage swing accross the diode increases with the quality factor, leading to increased saturation effects in the device for a given available RF power and thus, limiting 112

the maximum input power before burn-out. For this reason, the efficiency of the Q=3 doubler also decreased considerably with increasing input power. Furthemore, the Q=2 doubler had a wider -3 dB efficiency bandwidth than the Q=3 which is expected because the diode and embedding impedances vary more rapidly with frequency, mismatching the input pump power. In addition, a Q=2 doubler with four diodes was designed, fabricated and tested. This doubler exhibited a 12.5% efficiency at 74 GIIz with a minimum bandwidth of 12.5%, while the maximum measured output power was 115 mW which is the highest reported for a monolithic doubler in W-band. Finally, a method to increase the efficiency of the multipliers was presented. By selecting wider slot and signal strips for the open-end stubs the loss of the output circuit decreased by approximately 1 to 1.5 dB at 80 GIz. Efficiency measurements for a new doubler with wider open-end stubs on a low doped wafer (ND = 0.5xl017cm-3) yielded a value of 14.8%, compared to 11.5% for the old doubler (narrow stubs) fabricated on the same low doped substrate. 113

CHAPTER 5 W-BAND MONOLITHIC MIXER 5.1 Introduction The receiver of a monolithic transmit/receive system used either for a communication or a radar application, downconverts an incoming RF signal to a much lower intermediate frequency (IF) for further processing (filtering and amplification). Since the goal of the monolithic chip is to have both transmitter and receiver on the same substrate, the subharmonic mixer design is ideal for the frequency down-conversion because the local oscillator that provides the fundamental frequency of the multiplier in the transmitter can also be used for mixing in the receiver, assuming that it has an appropriate bandwidth. As a result, there is no need to have two different sources on the chip that operate at different bands. For the sub-harmonic mixer the RF signal is approximately the n-th harmonic of the local oscillator, and if mixing occurs at an even harmonic a non-linear device with an antisymmetric current-voltage characteristic, such as an anti-parallel pair of Schottky diodes, is typically used [84]. This type of mixer has been used extensively in the millimeter and sub-millimeter wave regions, because its main advantage is the fact that for those regions where LO power is scarce the LO frequency is only half the RF frequency. One drawback, 114

however, is that the anti-parallel diodes must be pumped at relatively high LO power levels unless a separate bias for each device can be provided [85]. Several researchers have implemented a sub-harmonic mixer design either in a waveguide [86], [87] or quasi-optical [88] configuration, with very good noise temperature and conversion loss performance even at frequencies as high as 640 GlIz. For a planar environment, microstrip based designs in W-band have been realized with Schottky diodes [89] and IIFET's [90] giving a conversion loss of 10 and 22 dB, respectively. A self-oscillating subharmonic MMIC mixer with microstrip lines and a p1IEMT transistor has also given an average measured DSB conversion loss of 15 dB [91] from 70 to 85 GI~z. Coplanar integrated balanced mixers using PM-IIEMT technology for automotive applications operating at 77 GIIz with a conversion loss of about 9 dB have also been demonstrated [92]. More recently, a hybrid sub-harmonic coplanar waveguide mixer on silicon substrate has shown a conversion loss of 7 dB, at an RF of 94 GI~z and an LO power of 8.5 dBm, and a DSB noise temperature of 650 K [93]. This chapter presents the analysis and design of a monolithic FGC based sub-harmonic mixer, that is fabricated on the same substrate with a W-band doubler and operates at 80 GItz. The development and experimental results of back-to-back mixer diodes are shown first. The passive circuits necessary for the mixer are also designed, fabricated and tested. Finally, measured and simulated results of the mixer performance are demonstrated. 5.2 Mixer Analysis and Design The x2 sub-harmonic mixer that will be part of the transmit/receive module is designed to operate at an RF of 76-80 GI~z, an IF of 2-4 GIlz and an LO of 38-39 GItz. The goal is to downconvert the 76-80 GlIz signal produced by the multiplier at the transmitter to 115

, fF Optional IF Matching r - Network I I L -- RF Blocking Stub /4 @ RF.. RF Diodes fLo I I Optional -- -I RF Matching A Network L LO Grounding Stub 4LO @ LO I I I - - _______ -I Optional LO Matching Network Figure 5.1: Schematic of the monolithic FGC based sub-harmonic mixer (from S. Raman [93]). an intermediate frequency of 2-4 GIIz at the receiver. A schematic of the mixer can be seen in Fig. 5.1 ([93]), where we observe that it consists of a back-to-back pair of diodes, a band-pass filter and several stubs for blocking and isolation at different frequencies. The entire design is monolithic and the transmission media are FGC lines. This is the first attempt to make a monolithic sub-harmonic mixer using finite ground coplanar technology. Since the mixer will co-exist on the same substrate with a multiplier for the purpose of a transmit/receive module, the epi-layer used for the fabrication of the doubler diodes will also be used for the mixer diodes. This is critical because for optimum mixer performance at millimeter-wave frequencies a thin low-doped (n-) epi-layer is required in order to minimize the series resistance, whereas for the doubler the epi-layer is usually thicker and of lower doping concentration. As a result, a compromise in the epi-layer parameters and, therefore, in the performance of the transmit/receive module needs to be reached. The W-band multipliers presented in chapter 4 had an n- layer thickness of 4000 A and doping of 1x1017cm-3. For the sub-harmonic mixer the n- thickness is 2000 A and the doping 116

3x101cm-3, although for best results in W-band a 700-900 A thickness would be ideal. The higher doping density required for the mixer will increase the efficiency of the doubler but lower the output power since saturation effects wil be more pronounced. The diameter of the mixer diodes, in contrast with the multiplier diodes, is small and equal to 2 gem in order to minimize the RsCt product. An even smaller diameter (1 tm) is desirable but fabrication constraints are imposed from the optical lithography system. The diode technology used for the fabrication of the multipliers cannot be implemented in this case because of the very small dimensions. For this reason a new fabrication technique was developed (for details see Appendix C) where the diodes have an etched surface channelfinger design without an air-bridge connecting them to th e circuitry. The latter also contributes to the reduction of the parasitic capacitance caused by the presence of the air-bridge. The n+ layer of the mixer diodes has a thickness of 2pm and a doping greater than 5xl018cm-3. The fabrication procedure for the mixer can be summarized as follows: * PECVD SiXNy deposition of 2400 A * Schottky well formation by RIE etching of SiTNY * Ohmic contact definition with Ni/Ge/Au/Ti/Au deposition * Finger/anode definition and Ti/Pt/Au evaporation * Mesa etch to isolate areas around the diodes * Circuit metal deposition with Ti/Al/Ti/Au deposition * Surface channel etch to isolate diode fingers * Air-bridge formation for passive circuits 117

It should be noted here that the mesa-isolation etch is performed in two steps: in the first step a small rectangular area around the back-to-back diodes is protected and the epi-layers are removed from everywhere except for that rectangular region. This procedure ensures that the passive circuits will be deposited on semi-insulating GaAs arnd, therefore, the various FGC line segments will exhibit the characteristics shown in chapter 4. During the first etch, however, the diode fingers connecting the anode with the ohmic cathode are not isolated and as a result the diodes will have increased parasitics. For this reason, a second etch that removes the material underneath the diode fingers is performed after the passive circuit deposition. The new fabrication process also includes the formation of electro-plated air-bridges necessary for the passive circuits. To the author's knowledge this is the first time where air-bridges are formed on circuits that include small anode area diodes with fingers suspended in air. This fabrication technique allows for the realization of small channel etched diodes that have low parasitics, and for FGC lines with air-bridges used to suppress undesired modes. The advantages, therefore, from both the improved devices and the FGC lines can lead to enhancement of the overall system performance. A photograph of the fabricated back-to-back diode pair can be seen in Fig. 5.2. The DC current-voltage characteristic of a 2,um in diameter anti-parallel Schottky diode pair can be seen in Fig. 5.3, while the C-V measurement of a single diode is shown in Fig. 5.4. The measured data of Fig. 5.4 are curve-fitted with equation 4.4 in order to extract the parasitic and zero-bias junction capacitance of the diode. All of the diode parameters are summarized in Table 5.1. The junction capacitance per anode was 9-10 fF while the parasitic capacitance was 3 fF. The parasitic capacitance Cp is partly due to the capacitance between the region under the diode finger and around the anode and partly between the diode finger and the ohmic contact. For the anti-parallel pair the total parasitics were 6 fF. 118

(a) 1 -- — ~ (b) Figure 5.2: SEM photograph of: a) back-to-back diodes with 2pm diameter and b) channel under the diode fingers. 119

0.01....- I....I.... I '-' 0.01 0.005 -0.005 -0.01 I - 1 -0.5 0 0.5 1 V as(V) Figure 5.3: Current-voltage characteristic of the anti-parallel pair of Schottky diodes used in the mixer design. 14 13 12 - 11 I 10 c9.C 1 o u 8 7 6.... I I... I I. I....... I. I I I I..... / / _ - - - meas. // ~ - -6 -5 -4 -3 -2 Bias Voltage - 1 (V) 0 1 Figure 5.4: Measured capacitance versus bias voltage for a single mixer diode with curvefitted data. 120

Table 5.1: Measured DC characteristics for the mixer diodes. yielding a total capacitance Ct=26 fF. Since the series resistance of the diodes was Rs=7 Q the figure of merit cut-off frequency of the back-to-back pair was approximately 875 GIIz. The junction capacitance of 9-10 fF is slightly higher than the one expected (6 —7fF) due to the small increase in the diameter (2.2 yim instead of 2) of the fabricated diodes that results from the various processing steps. Regarding the passive cicuits of the mixer, at the RF side there is a band-pass filter from 70-90 GIIz that prevents IF leakage to the RF port and a Ag/4 open-end stub at the LO frequency so that there is good isolation between the RF and LO ports without affecting the RF signal. An RF matching network that matches the diode impedance seen at the RF frequency is optional. At the IF port there is a Ag/4 open-end RF blocking stub placed A9/4 away from the diodes, that prevents leakage of the RF signal to the IF path without attenuating the IF signal. At the LO port there is a Ag/2 short circuited stub at the RF frequency so that the RF signal does not leak to the LO port, while the LO signal passes unaffected. The addition of matching networks at both the IF and LO ports for matching the IF and LO diode impedances, respectively, is also optional. The various passive elements of the mixer were realized using FGC line techology with a 50 Q main line that had w=50 Mm, s=45 pm and Wg=160 um, as in the case of the multipliers. Both the RF and LO grounding shunt stubs had a characteristic impedance of 50 Q and the same line dimensions with the 50 Q main line, in contrast with the w=s=20 pm parallel stubs used in the doublers. Several stubs were designed, fabricated and tested 121

0 20 40 60 80 100 120 Frequency (GHz) (a) 0 - S 'I-5 - -10 \ / m-15 -20,,\ 1-25 - a-35 - -40 -:S21 -45, -40 20 40 60 80 100 120 Frequency (GHz) (b) Figure 5.5: Measured S-parameters for the: a) LO grounding stub and b) the RF grounding stub. 122

Stub Length Open-circuit Resonance Short-circuit Resonance Design (|m) fres (GIlz) S21 (dB) fres (GI~z) BW (-10dB) LO Grounding 726 79.12 -0.24 40.1 43.4% (17.4 GIz) RF Grounding 708 40.7 -0.13 82.96 19.8% (16.4 GIz) Table 5.2: Measured characteristics of the shunt stubs used in the mixer design. with the goal to achieve as good performance as possible. Measurements for the RF and LO grounding stubs at the LO and RF port, respectively, can be seen in Fig. 5.5, while results are summarized in Table 5.2. The scattering parameters were measured with a TRL calibration and the reference planes were located at the cross-junction of the parallel sections with the main line that connects the two ports. As seen from Table 5.2, the insertion loss for both stubs at the open-circuit resonance is very small, while at the short-circuit resonance the LO grounding stub has twice the bandwidth of the RF grounding stub due to the different resonant frequency (fresLO fresRF/2). The effect, therefore, of the stubs on the attenuation of the RF and LO signals traveling towards the diodes should not be substantial and should not deteriorate the mixer performance. It is worthwile to note here that the smaller loss of these stubs when compared with the doubler stubs (0.23 dB/mm at 20 GILz), is due to the fact that the signal line and slot widths are wider than those used in the doubler. The RF bandpass filter was realized using open-end series stubs [2], [93] that can provide the appropriate bandpass characteristics. Since one section has a relatively wide bandwidth, a two section design was chosen in order to effectively block the IF from leaking at the RF port. A schematic of the filter along with the equivalent circuit model for one open-end stub, which is based on [94], can be seen in Fig. 5.6. Each finger of the stub is A9/4 long at 123

resonance translating an open to a short and thus allowing the signal to pass. At twice the resonant frequency the stub is electrically Ag/2 long, maintaining the open character and blocking the corresponding frequency. For a band-pass centered at 80 GIIz the length L of each finger was calculated from L= ( = 354,um, where an effective dielectric constant of 7 was assumed based on the FGC line results of chapter 4. Since the main 50 Q line has w=50 gum, s=45 um and Wg=160,m the width of the each finger and slot was 10 ym. Due to the increased width, when compared with the filter presented in [93], this filter is expected to have less loss. Simulated results for the filter of Fig. 5.6(a) with IE3D can be seen in Fig. 5.7(a), where an insertion loss of 0.43 dB is predicted at 80 GIIz with the method of moments technique. Measured results with a TRL calibration for the filter are also shown in Fig. 5.7(a), where an insertion loss between 0.46 and 0.63 dB was achieved between 70 and 90 GIz. The loss at 80 GIlz was 0.55 dB while for 2-4 GIIz it was -33 to -27 dB, thus, providing an excellent block for the IF signal. The agreement between the simulated and measured data is very good, as witnessed from Fig. 5.7(a). In order to run a harmonic balance analysis of the mixer in Libra the filter response at higher harmonics has to be evaluated. One way to achieve this is to use the model of Fig. 5.6(a) for one stub in a cascaded configuration that represents the two-stub filter, and fit the simulated IE3D data with the modeled data in Libra. The equivalent circuit model with known element values can then be inserted in the harmonic test bench. Initial values for the lumped resistors, capacitors and inductors can be found from equations (22)-(27) of [94]. Results for the calculated lumped element values of Fig. 5.6(b) are summarized in Table 5.3 and a comparison between the scattering parameters of the JE3D simulation and the equivalent circuit simulation in Libra can be seen in Fig. 5.7(b). 124

L = 354 L - 354 Dim:gm (a) LI Cs L3 L2 Cn Cf2 (b) Figure 5.6: RF bandpass filter used in the mixer design: a) circuit layout for two stub sections and b) equivalent circuit model for one stub section. 125

0 20 40 60 80 100 Frequency (GHz) (a) -5 - S21 g-15 --20 SIl 0 \I 3 -:IE3D 3 -:Eq. model I -35 j -40 0 20 40 60 80 100 Frequency (GHz) (b) Figure 5.7: S-parameters vs. frequency for the mixer bandpass filter: a) measured and IE3D simulated data and b) IE3D simulated and Libra equivalent circuit data. 126

flL '1 t.42 (a) L51 _ _ _ _ _ IEl ml.4 - 2:1 5; 5 4* 4. 4. 44 (b) Figure 5.8: Libra simulation for the x2 subharmonic mixer: a) circuit schematic and b) harmonic balance test bench. 127

Table 5.3: Calculated values for the equivalent circuit model of Fig. 5.6(b). The next step in the analysis is to perform the harmonic balance simulation in Libra, so that the mixer response can be evaluated. This is possible since the various stub lengths, the equivalent circuit of the bandpass filter and the DC diode characteristics are known. Each section of FGC line can be modeled as a physical transmission line with known attenuation and effective dielectric constant, while for the diodes a pn junction model with known DC parameters will be implemented. A test bench, where the mixer is inserted, is created and the LO and RF frequencies are varied accordingly for different LO power levels. The circuit schematic and test bench used in Libra can be seen in Fig. 5.8. Results for the conversion loss in the upper side band of the mixer are shown in Fig. 5.9, where a 6.5 dB value is achieved at an RF frequency of 80 GIIz, an IF of 4 GHIz and an LO power of 6 dBm. The RF and LO diode input impedances were also calculated for the same parameters and found to be ZiRF=27.7+j9.8 Q, ZinLO=41-j59.5 Q for PLO=6 dBm, taking into account the transmission line segments that are around the devices. The IF load for the previous results was 50 Q. Since Libra does not yield the IF output impedance a code developed by Kormanyos [88] for subharmonic mixers based on the original code of S. Maas [95] was used. For IF frequencies between 2 and 4 GI~z the program yielded an impedance around 56 Q and the result did not vary with different terminations (short, 50 Q) of the higher RF and LO harmonics. 128

8. I I.. I I.. I I. I I I I I I I: I I I 7.5 6.5. 6 =-s- 4 dBm --— 5 dBm = - -- -6 dBm V 55 - -o —7 dBm - 76 78 80 82 84 fRF (GHz) Figure 5.9: Conversion loss vs. RF frequency for different LO power levels. 5.3 Results The mixer that was designed in the previous section was fabricated on a GaAs wafer with an n- epi-layer thickness and doping of 2000 A and 3xlO1cm-3, respectively, and a 2 jm thick n+ layer with a doping greater than SxO18cm-3. The size of the actual circuit was 2.2 mm x 1.9mm and a picture of it can be seen in Fig. 5.10. The metal thickness of the evaporated FGC line segments was 1 Mm, which is equal to 2.5 skin depths at 40 GIz and 3.5 at 80 GIIz, while the metal thickness of the gold electro-plated air-bridges was 3-3.5,m. The air-bridges are located at various points in the circuit so that the coupled slotline mode is suppressed and the different stubs are in parallel connection with the main 50 Q line and not in series. The measurement system that was used for the on-wafer evaluation of the singlesideband downconversion loss can be seen in Fig. 5.11. The 80 GItz RF signal is provided 129

Figure 5.10: Fabricated FGC line monolithic mixer. by the W85104A mm-wave source module that is connected to the IIP8510C network analyzer thru a 10-dB WR-10 directional coupler used for power sampling. In order to comply with the dynamic range of the power meter the thru port of the coupler is connected to the W-band power sensor and the coupled port is used for the RF signal extraction. This configuration is necessary since the power level of the RF signal is around -20 dBm and cannot be measured with accuracy from the Anritsu power sensor and meter. The output of the coupled port is then connected to a long section of WR-10 waveguide that leads to the 120A-B3T W-band GGB probe. The 35-40 GIIz LO signal is provided by an IIP 83640L synthesized source thru a short semi-flexible cable and a K-band GGB probe. It should be noted here that the available LO power level was limited by the specifications of the synthesizer. The IF signal is extracted from a K-band GGB probe that is connected to an IIP 8564E spectrum analyzer via a cable. The losses of the various cables, coplanar probes and waveguide sections were extracted by measuring each one of them with either the network or the spectrum analyzer. For the RF and LO port the loss was found to be 130

W-Band module Spectrum 0 O Analyzer 10dB K-band coupler RF probe - LOWRU- * LO source MMIC^ (synthesizer) power II W-band K-band sensor J probe probe power j meter U Figure 5.11: Block diagram of the system used for the mixer measurements. approximately 3 dB while for the IF port the loss was around 1.3 dB. Once the losses are known the measurements can be calibrated at the end of the probe tips, as shown in Fig. 5.10. The measured single sideband (SSB) conversion loss versus RF frequency for an IF of 4 GIIz can be seen in Fig. 5.12(a), where the LO power for each frequency point is the optimum depending on the availability of the synthesizer for that particular point. A minimum conversion loss of 11 dB was achieved at 79 Gl~z for an LO power of 8.8 dBm, while the 3 dB bandwidth was more than 11% (9 GIIz). The very broadband performance of the mixer can be attributed to the fact that there are no matching networks that typically improve the conversion loss but narrow the bandwidth. Fig. 5.12(b) also shows the conversion loss for different LO power levels at an RF of 80 GIIz. Due to power limitations the maximum available LO power was around 7.6 dBm and resulted in a conversion loss of 11.3 dB. Comparing the measured results with those of Fig. 5.9, a 4 dB discrepancy in the value of the conversion loss is observed. A DC measurement of the I-V characteristic for the actual diodes on the mixer circuit revealed a high value for the series resistance Rs = 40Q. 131

"0 VI 0 O em ro 0 * 6 00 u 14 13 12 1 1 Z 0 - - I.. I................I. "I I I, I I I I I I I I O —O-* - — O- -O — -"e O — O- Measured - - e - - Simulated 10 9 8 I I 1 %p 74 76 78 80 fRF (GHz) 82 84 86 (a) I.U: c 0 L? 30 25 20 15 10 5 0 2 4 6 8 LO Power (dBm) 10 12 (b) Figure 5.12: Measured and simulated data for the diode with Rs = 40Q: a) SSB conversion loss vs. RF frequency for optimum LO power and b) SSB conversion loss vs. LO power at fRF = 80GIIz. 132

Simulated results with diodes having the same characteristics as the ones on the measured mixer can be seen in Fig. 5.12, where good agreement can be observed within 0.5 dB. The increased value in the series resistance can be attributed to a yield problem that resulted in performance degradation for several devices. Possible reasons for this problem include insufficient etching of the low-doped layer from the small ohmic cathodes, misalignment between the anode, the cathode and the finger, incomplete removal of the nitride from the anode, as well as a combination of those. Isolation measurements between the various mixer ports were also performed. For the LO/IF isolation the W-band probe of the RF port was terminated in a 50 Q load and the rest of the system portrayed in Fig. 5.11 was kept the same. Simulated and measured results can be seen in Fig. 5.13, where the measured isolation was better than 24 dB for LO frequencies between 37 and 40 GIIz. From the Libra simulations the LO/IF isolation is expected to be better than 25 dB. The LO/RF isolation was measured by terminating the IF port in a 50 Q load and replacing the W-band probe of the RF port with a K-band probe connected to the spectrum analyzer. Results can also be seen in Fig. 5.13, where an isolation better than 20 dB was achieved between 37 and 40 GIIz. It should be noted here that the previous measurements were calibrated at the end of the probe tips by removing the losses of the various components. 5.4 Conclusions A monolithic FGC based W-band mixer has been designed, fabricated and tested. The epi-layer parameters are the same with those of a monolithic multiplier since the mixer is intended for use in a monolithic transmit/receive module. The choice for the epi-layer thickness and doping, therefore, is a compromise between the optimum one for either a 133

0 p --- —--------------------------- - LO-RF sim - - LO-IF sim: "A" -LO-IF meas -10 -- LO-RF meas V - 15 = - 20 "2 -51-^ ss^ ^ ^ 30 -35 ~ -^.- - -40 37 37.5 38 38.5 39 39.5 40 Frequency (GHz) Figure 5.13: Simulated and measured results for the RF/LO and LO/IF isolation of the mixer versus LO frequency. doubler or a mixer design. In order to achieve diodes with low parasitics and small anode areas a novel fabrication technique that combines channel etched finger type diodes and FGC lines with air-bridges has been implemented. In this technique, once the diodes are formed on the epi-layers a small rectangular area around them is isolated and the active layers are etched from everywhere except for that region, without removing any material underneath the finger. After the deposition of the passive circuits, a second etch creates the channel under the diode fingers and the process ends with the formation of the airbridges for the various FGC line sections. Measured results for the W-band mixer that was fabricated with this technique and included diodes with a diameter of 2.2,um, yielded a minimum single sideband conversion loss of 11 dB for an RF of 79 GlIz, an IF of 4 GlIz and an LO power of 8.8 dBm. The 3-dB bandwidth is also greater than 11% (9 GIIz) and covers the entire measurement band (75-84 GI~z). The observed discrepancy between the 134

measured (11 dB) and simulated loss (6.5 dB) was due to a relatively high series resistance of the diodes caused by a device yield problem in the wafer. A mixer with the excellent characteristics of back-to-back diodes measured in other parts of the wafer should give a conversion loss closer to the expected one. The LO-RF and LO-IF isolations of the mixer are better than 25 dB for LO frequencies of 38.5-40 GIIz and 37.2-39.5 GIIz, respectively. The mixer presented in this chapter is the first effort of a monolithic W-band FGC line design that can be combined with a monolithic multiplier on the same substrate and have a performance that is comparable with that of state-of-the-art subharmonic mixers. This will allow for the realization of monolithic transmit/receive modules operating at millimeter wavelengths that combine small size, high circuit density and excellent performance. 135

CHAPTER 6 CONCLUSIONS AND FUTURE WORK 6.1 Conclusions This thesis has presented a collection of work on active and passive monolithic microwave integrated circuit structures that can be used in the design of a monolithic transmitter/receiver module for application in radar and communication systems. For the passive elements silicon micromachining was used to enhance the performance of circuits such as antennas and filters, while for the active elements the finite ground coplanar (FGC) line technology was used to design multipliers and mixers on GaAs. Two techniques that can increase the radiation efficiency of rectangular patch antennas on high index materials were studied. Both of them were based on the removal of dielectric material under the radiating element in an effort to either reduce the effective dielectric constant or suppress the dominant surface wave mode. Measured results for Ku-band patches fabricated on Duroid substrate with the first method showed a bandwidth and efficiency increase of 64% and 28%, respectively, as well as sensitivity of the radiation improvement on the placement of the machined cavity relative to the antenna. This result is the first reported for an increased efficiency rectangular patch antenna that does not 136

implement dielectric membranes for the suspension of the patch or holes drilled in the substrate. Simulated results with the finite difference time domain technique for the second method exhibited a substantial decrease of the electric field inside the substrate. This is the first attempt to suppress with an analytical based design the TMo mode of a rectangular patch antenna on high dielectric constant material. Micromachining was implemented for the design and fabrication of a monolithic high-Q X-band resonator that consists of microstrip lines, coupling slots and a rectangular cavity. Measured results showed an unloaded quality factor Q., of 506, a bandwidth of 5%, an insertion loss of 0.36 dB and good thermal stability. Different positioning of the slots with respect to the center of the cavity also showed the possibility to alter the resonator's response; a 2% bandwidth with a loss of 1.1 dB were measured. This is the first report of a fully monolithic resonator that can achieve a quality factor higher than that of traditional planar microstrip or stripline resonators either printed on a dielectric material or suspended in air with the help of a dielectric membrane. FGC lines on GaAs with a thin overlay of polyimide as well as lines oil quartz were studied. Experimental results showed that the polyimide covering the FGC lines has a negligible effect on the dielectric constant and causes a small increase in the attenuation. The total loss also of lines with the same geometry is independent of the substrate material and is mainly ohmic. This is the first report on characteristics of FGC lines with polyimide and on the effect of different substrate material and different geometries. Monolithic FGC based W-band doublers for higher efficiency and output power were also designed, fabricated and tested. Measurements for a Q=2 doubler with two parallel diodes yielded an efficiency of 17.2%, at 76.3 GIIz, a minimum bandwidth of 10% and a maximum output power of 66 mW, while for a Q=3 doubler an efficiency of 22% at 70 137

GIiz, a bandwidth of 8.5% and an output power of 50 mW were measured. These values for both the efficiency and bandwidth are the highest reported for monolithic multipliers. The microstrip doubler designed by Chen [14] yielded an efficiency of 25% at 94 GIIz but no bandwidth information was provided. All the monolithic results, however, reported thus far in the literature cannot surpass the performance of waveguide doublers, such as the one by Porterfield [66] where a 48% efficiency and 17% bandwidth were achieved at 80 GIIz. Measured results for a four diode doubler (two parallel pairs) design showed an efficiency of 12.5% at 74 Gliz, a minimum bandwidth of 12.5% and a maximum ouput power of 115 mW which is the highest reported for a monolithic doubler in W-band. In addition, a method to increase the efficiency by reducing the loss of the shunt open-end stubs used in the multipliers was studied. Preliminary measurements showed that a 20-25% improvement is feasible. Finally, a monolithic FGC line subharmonic mixer in W-band was designed, fabricated and tested. A novel fabrication technique that allows the co-existence of both small and large channel etched finger type diodes with passive circuit air-bridges was implemented. This is the first report of such a fabrication scheme that can be used for the realization of a multiplier and a mixer on the same substrate. Measured results for the mixer yielded a single sideband conversion loss of 11 dB at an RF frequency of 79 GILz, an IF of 4 GIIz and an LO power of 8.8 dBm, as well as a 3 dB bandwidth greater than 11%. This is the first report of a monolithic subharmonic mixer in W-band with FGC line technology. 138

6.2 Future Work 6.2.1 W-Band Micromachined Antennas The first technique presented in chapter 2 where material is removed only in a portion under the patch antenna and not through all of the substrate, can be implemented for the fabrication of high efficiency planar antennas and arrays in W-band. At such high frequencies power lost to surface waves can be reduced by using thin substrates (typically Ad/10) and,thus, at 94 GIIz a 100 Mm thick silicon wafer will be needed. The radiation efficiency, however, of a patch on such a thin substrate will be greatly reduced. A solution, therefore, where thick substrates are partly micromachined can be implemented in order to avoid problems associated with thin substrate materials or with dielectric membranes used to suspend the antenna. Preliminary measurements of a micromachined rectangular patch at 94 GIIz have shown very encouraging results [96], making this type of antenna very attractive for the vertical integration of antenna arrays at millimeter-wave frequencies. 6.2.2 Micromachined High-Q Filters and Diplexers The micromachined high-Q resonator presented in chapter 3 of this thesis is the first step for the realization of fully monolithic high-Q filters and diplexers. A possible filter layout was shown in Fig. 3.2, where energy is coupled from the input and output microsrtip lines to the corresponding cavities via slots. Slots are also used to couple energy between the different cavities. An increased number of cavity-resonators is desired in order to achieve a narrow bandwidth response. For a filter design a relationship between the cavity physical parameters (size, slot positions) and an equivalent circuit/electric model is necessary so as to formulate design equations that could be used for the realization of a specific response. Since 139

alignment and bonding between the different wafers is very critical for the loss performance, techniques that are more reliable and robust need to be found. A eutectic thin-film bonding process that can be incorporated with the rest of the standard fabrication steps would greatly reduce the cost and increase reliability. In addition, if a thin film is used instead of the silver epoxy glue bonding can be more uniform, less lossy and less rough. For better alignment, the pyramidal pits that are created from the anisotropic micromachining can be used as receptacles for microspheres between wafers and greatly increase accuracy. Another possibility is to use very thin fibers going through via-holes created inside the silicon substrate. In order to reduce the size of the cavities but still maintain the narrowband low-loss characteristics micromachined evanescent mode [97], instead of propagating, filters can be pursued. Coupling Slots Microstrip Lines Cavity fI Cavity f Coupling Slots Stripline Microstrip Line Figure 6.1: Conceptual diagram of a monolithic micromachined diplexer. For communication systems diplexers that separate the different bands of an incoming RF signal are very important. A monolithic approach with low loss and narrow bandwidth that makes use of micromachining is shown in Fig. 6.1. In this case, a stripline is carrying the 140

RF signal and two cavities with different sizes and, therefore, different resonant frequencies that are centered around the bands of interest are used to extract the two corresponding signals. Coupling between the stripline and the cavities can be achieved with slots and controlled by their relative location. 6.2.3 Improved and New Multipliers From the doubler results presented in chapter 4 it is clear the the ohmic or circuit loss limits the performance of FGC based multipliers. Techniques, therefore, or methods that can decrease the passive circuit loss need to be investigated. One approach that was proposed in chapter 4 and was based on the optimum slot and signal width design in terms of loss for the open-end shunt stubs, yielded encouraging results. The fabrication of those improved designs should be repeated on a wafer similar to the one that gave the best overall efficiency for the Q=2 and Q=3 doublers. Another way to reduce the loss of FGC lines is to micromachine grooves in the slots in an effort to eliminate the dielectric material in the aperture regions, where the electromagnetic fields are concentrated [3] (see Fig. 6.2). Measured results for silicon substrate have shown a loss improvement of up to 1 dB/cm in W-band. GaAs micromachining has been successfully used in the past to fabricate membrane suspended planar antennas for automotive applications [42]. Plating of the FGC lines to a 3 gm thickness (instead of lm that results from the evaporation) can also contribute to reducing the ohmic loss, especially at the input side of the doublers where the skin depth is larger. For a four diode doubler realization, the low impedance section at the input side necessary for impedance matching further increases the circuit loss (low impedance lines have higher loss as shown in chapter 4). An alternative to this is to design a four diode doubler 141

Signal Line Wg S Ground Lines Figure 6.2: Micromachined FGC lines ([3]). with each diode having twice the area of the previous ones. As a result, the diode impedance will be reduced by a factor of two but the series combination of two diodes will have the same impedance as one smaller diode and, thus, not require the low impedance section at the input for matching. Such a doubler should give an efficiency around 16-17%c and achieve an output power higher than 150 mW. Besides doublers, a monolithic W-band finite ground coplanar tripler can be pursued. Matching and isolation networks at the input and output sides can be implemented with appropriate bandpass filters. 6.2.4 Sub-millimeter Wave Multipliers One of the advantages of FGC circuits is that they can be easily scaled to higher frequencies. A D-band doubler from 90 to 180 GILz with broadband performance can, therefore. be pursued. Since the novel fabrication technique that was introduced in chapter 5 allows the co-existence of finger type diodes with low parasitics along with air-bridges for the FGC 142

LO - 39/38 GHz 10/20 dB Coupler lr-..,& c:. inptOutput IF - 2 /4 GHz 0 - Doubler -W.. ---- \y )-^ 40 GHz 80 80 GHz 80 GHz s Mixer Power Meter Transmitter Receiver Figure 6.3: Conceptual block diagram of a monolithic multiplier/mixer pair with FGC line technology for on-wafer measurements. circuits, a D-band doubler design based on this technique would be highly recommended in order to maximize the efficiency. A two diode design where the area of each device is small or a four diode design with larger areas can be implemented. To the author's knowledge a broadband monolithic doubler has not been realized yet in D-band. 6.2.5 Monolithic Transmit/Receive Modules The novel fabrication technique that was presented in chapter 5 paves the way for the realization of a monolithic FGC based transmitter/receiver in W-band with good performance and wide bandwidth. A design that incorporates a 40 to 80 GIIz doubler together with a x2 subharmonic mixer at 80 GIIz, as the one shown in Fig. 6.3, can be pursued. A 10/20 dB FGC line coupler is used to sample the RF power that exits the doubler and enters into the mixer, so that on-wafer measurements are possible. Since the same substrate will host both the multiplier and the mixer a compromise in the epi-layer parameters has to be reached. For this reason the mixer fabrication has to be repeated first in order to get the correct diode characteristics and measure the corresponding conversion loss. At the same time a doubler design with channel etched finger type diodes on a low doped layer with 2000 A thickness and 3x1017cm3 doping needs to be evaluated. The final design that can 143

be pursued is that of a monolithic transmitter and receiver on separate wafers but with the same parameters that also include micromachined patch antennas for increased radiation efficiency. 144

APPENDICES 145

APPENDIX A QUASI-STATIC MODEL FOR THE EVALUATION OF THE EFFECTIVE DIELECTRIC CONSTANT AND EXPERIMENTAL RESULTS FOR 2 PATCH ANTENNAS ON SILICON A.1 Calculation of Reduced Dielectric Constant A cavity model developed by R.F. Drayton [38] is used to predict the effective dielectric constant of the mixed air-silicon region of the micromachined antenna (Fig. A.2) for varying thickness ratios underneath the patch antenna. A quasi-static model, based on series capacitors, is used to determine the patch capacitance in the mixed region (Fig. A.1) C e eff A t (A.1) where eeff = Crefflo. For simplicity the walls of the cavity are asumed to be vertical and the effective dielectric constant (Ereff) is estimated by the following expression: L + 2AL frtng _ cavsty -reff =- Ecavity( L + 2/AL ) (A.2) 146

L AL L AL It air Cf to j Itt Cair Lt air (a) (b) Figure A.1: Capacitor model for the micromachined patch with (a) the radiating edges into the high-index substrate and (b) with the radiating edges over the mixed air-substrate region. where (fringe fair + (Esub - Eair)Xair (A.3) (cavity fair + ((sub - (air)X fringe (air sub ecavity = - - - - (A.4) =air + (5sub - (air)Xair In the above expressions, ~cavity represents the relative dielectric constant of the mixed substrate region and (fringe represents the relative dielectric constant in the fringing fields region. Equation A.2 includes the open-end effect extension length AL to the antenna which can be found from [44], where (fringe is the permittivity used for the calculation of AL. The thickness parameters, Xair and Xfringe, are ratios of the air to full substrate thickness in the mixed and fringing field regions, respectively. For the silicon micromachined case shown in Fig. A.l(a) xfringe is taken as zero, whereas for the case of Fig. A.l(b) Xfrnge-Xair. A plot of the theoretical and measured effective dielectric constant versus the air gap thickness for silicon substrate (,E=11.7) can be found in Fig. A.3, where an effective dielectric constant of approximately 2.2 is achieved for a mixed air-silicon ratio of 1:1 using the capacitor model (eq. A.2 with AL=O) and 3:1 ratio for the capacitor model with AL extension length (eq. A.2 with AL calculated from [44]). The dimensions for the micromachined patch that was used to produce the results of Fig. A.3 can be found in Table A.1 147

Ir.-..- -—. -- -- - -- I a I/a.. -.. - - -. - - - - - - -- ----------- -. 0 It,.',,,/ % < / F___ _ ___ Figure A.2: Geometry of the micromachined patch antenna. 12 u 10 — o — Capacitor Model (CAP) A CAP with AL Extension * FDTD Method ~ Measured 8 6 A Q 4- - A A A A X 2 - | ^<^c^ ^ 0 20 40 60 80 100 Air Gap Thickness, x (%) air Figure A.3: Effective dielectric patch constant vs. air-gap thickness for the silicon micromachined 148

(parameters a,b and c are actual values since the walls are assumed vertical). Included also in Fig. A.3 is a data point based on the finite difference time domain model of the micromachined patch geometry. The FDTD calculation was based on a 3-D full-wave scheme that yields the return loss of the micromachined antenna and the effective permittivity of an 1:1 air-silicon substrate for a range of frequencies. Once the resonant frequency is determined from the return loss, the effective permittivity of interest is found. Only one case of airsilicon substrate ratio has been simulated with FDTD in order to validate the quasi-static results for the effective dielectric constrant of the antenna that was fabricated and tested. Regarding the measured ("micromachined") data point of Fig. A.3, the resonant frequency of the fabricated antenna was measured and [98] was used to extract the dielectric constant of the substrate for a patch having the same dimensions as the measured one. In the following section, experimental data will be presented that prove the superiority of this type of micromachined antenna. The conventional and micromachined antennas will be defined as a patch fabricated on a regular substrate or as a patch fabricated on a substrate that has locally reduced index region, respectively. A.2 K-Band Micromachined Patch Two antennas were fabricated by R.F. Drayton [38] on silicon, with resonant frequencies in the K-band and air/substrate thickness ratios of 1:1 (see Table A.1 for dimensions). In the silicon micromachined patch (SMP) antenna, the conductor has been electroplated to a metal thickness of approximately 3.2 Mm and the substrate is chemically etched (EDP process) in a single etch step underneath the antenna. Since the walls of the resulting cavity are not vertical due to the anisotropic etching, dimensions for a, b and c in Table A.1 represent average values. The lower ground plane is achieved by attaching adhesive 149

0 e-10 1-20 I ---— Regular — Micromachined -30-. I. { |... | *... 10 15 20 25 30 Frequency, GHz Figure A.4: Return loss measurement of the regular and micromachined patch antenna printed on a full thickness substrate and substrate with mixed air-silicon thickness ratio (1:1), respectively. copper tape of 25.4 gm thickness and the size of the silicon substrate where the antennas were fabricated was approximately 2.8 cm x 3 cm. Return loss measurements are shown in Fig. A.4 and were obtained using an IIP 8510 Network Analyzer where the bandwidth (ISI~< -10 dB) increases from 2.9% for the "regular" antenna to 5% for the SMP. Since bandwidth is inversely proportional to the quality factor, Q,defined as the ratio of total energy stored in the antenna to the energy dissipated or radiated from the antenna, the increase in bandwidth provides the first indicator of an increase in total radiation from the antenna. Efficiency measurements, however, need to be made in order to observe the increase in power radiated into space waves as opposed to power radiated into surface waves. Radiation patterns were also taken for the two antennas and the results are shown in Fig. A.5 where significant differences in the E-plane pattern are observed, while the Il-plane patterns remain similar as expected. For measurement purposes, the silicon substrates that hosted the antennas were mounted on a 5.6 cm x 5 cm metallic holder that served as 150

Patch t(mm) tatr(mm) L(mm) w(mm) a(mm) b(mm) c(mm) Regular 0.355 0 2.019 4.08 0 0 0 Microma- 0.355 0.165 3.616 3.445 3.616 8.108 0 chined Table A.I: Design parameters for the antennas on Silicon substrate the ground plane. The silicon antenna pattern exhibits many ripples, that are due to the diffraction of strong surface waves from the edges of the finite ground plane, in contrast to the micromachined antenna pattern that is much smoother. Conclusive evidence, needed to show the suppression of surface waves, is obtained by evaluating the antenna gain and measured efficiency. 151

E-Plane a II I I I I lu-...A.. i.i... 1. 0 MM- 15 - -25 -.1 I I I I I T-I u I I I I I I I I I I I I 'I I I I I I I a I I I I I I I I II I I I I I I a I I, H-Plane 0 --10 -15-.-20 -25 --60 -40 -20 0 20 40 60 Degrees............................. I I I I I -60 -40 -20 0 20 40 60 Degrees (a) E-P lane H-Plane I I I I ~0 to w - 10 0 w - 15 cu Q -20U -25 0 - m -10 - 00 Q-15 -CIO w 20 - -25-. I I I I I I I I I I I I I -, I I I I I i I a I I I I I I I I I I I I I I I I I a a a I i.... iI a I IEW I = I iII. iI. II - -i..;....1....1 I I I I I I -40 -20 0 20 40 Degrees -60 -40 -20 020 40 Degrees 60 (b) Figure A.5: Radiation patterns for (a) the micromachined antenna on Silicon and (b) the regular antenna on Silicon. 152

APPENDIX B FABRICATION PROCESS OF W-BAND AND D-BAND MULTIPLIERS B.1 Wafer Preparation A cross section of the GaAs wafer used for the fabrication of frequency doublers can be seen in Fig. B.1. The epi layers consist of a 4000 A (W band) or 2000 A (D band) thick nlayer with a 1017 and 3xlO17cm-3 doping density, respectively, and a 2,um thick n+ layer with a doping density greater than 5x1018cm-3. Both of the previous layers as well as an AlGaAs layer used to stop the etch are supported on a semi-insulating GaAs substrate. * Clean the wafer in heated Xylene for 2 minutes, Methanol for 1 minute, heated Acetone n- GaAs 4,000/2,000 A ____/ n+ GaAs 20,000 A _- AlGaAs 500 A S.I. GaAs 625 gim i GaAs 2,000 A Figure B3.1: Cross section of the GaAs wafer used for the fabrication of active structures. 153

for 2 minutes, and IPA for 1 minute. * Etch native oxide in BIIF for 30 seconds to 1 minute. * Bake for dehydration on the hot plate at 130~C for 2 minutes. B.2 Ohmic Cathode Contact * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 4.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds (the intensity of the aligner is set to 20 mW/cm2). Next, pattern the "ohmic" image by exposing for 3-4 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.2 minutes. Develop the photoresist with AZ-327 MIF developer for 30 seconds. Finally, bake at 110~C for 1 minute in order to further strengthen the resist for a BIIF dip. * Remove the photoresist scum in the plasma asher at 80 XV and 250 mT of 02 for 1 minute. * Etch through the epitaxial low doped layer with II3PO4: II202: II20 (1:1:8) for 20 seconds (2000 A thick n- layer) or 36 seconds (4000 A thick n- layer). * Etch the native oxide with BIIF for 15-20 seconds. * Deposit ohmic metal layers of Ni/Ge/Au/Ti/Au (250/325/650/450/2500 A) in the e-beam evaporator. * Lift-off in heated PRS-1000 photoresist stripper for 60 minutes. 154

* Anneal the ohmic contacts using hot plates at 2400/4050/2400C for 20/40/20 seconds. B.3 Schottky Anode Definition * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 4.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "anode" image by exposing for 3-4 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.2 minutes. Develop the photoresist with AZ-327 MIF developer for 30 seconds. Finally, bake at 110~C for 1 minute in order to further strengthen the resist for a BIIF dip. * Remove the photoresist scum in the plasma asher at 80 W and 250 mT of 02 for 1 minute. * Etch the native oxide with BIIF for 15-20 seconds (must load into evaporator no later than 2 minutes). * Deposit Schottky barrier metal layers of Ti/Pt/Au (500/500/3000 A) inII the e-beam evaporator. * Lift-off in heated PRS-1000 photoresist stripper for 60 minutes. B.4 Mesa Etch * Lithography: Spin IIMDS adhesion promoter and AZ5214-E photoresist at 2.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the 155

edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "etch" image by exposing for 4.5 seconds with the MJB-3. Develop the photoresist with AZ-327 MIF developer for 45 seconds. Finally, hard bake on the hot plate at 130~C for 1 minute. * Remove the photoresist scum in the plasma asher at 80 W and 250 mT of 02 for 1 minute. * Etch mesa with N114011: 1202 (1:24) for 25-30 seconds (etch rate is 4y/m/min). Rinse but without drying, immediately follow with an oxide etch in NII40II: I20 (1:15) for 15 seconds. * Remove the photoresist in Acetone and IPA. B.5 Circuit Printing * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 2.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "circuit" image by exposing for 3-4 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.2 minutes. Finally, develop the photoresist with AZ-327 MIF developer for 20-30 seconds (initially 20 secs and then 5 sees increments). * Deposit the circuit metal layers Ti/Al/Ti/Au (500/6000/500/3000 A) in the e-beam evaporator. 156

* Lift-off in heated PRS-1000 photoresist stripper for 3 hours. B.6 Air-Bridge Formation B.6.1 Post Definition * Lithography: Spin IIMDS adhesion promoter and PR1827 photoresist at 3.0 Krpm for 30 seconds each. Pre-bake on the hot plate at 105~C for 1 minute. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 1 minute and developing in AZ-327 MIF for 45 seconds. Next, pattern the "post" image by exposing for 9-10 seconds with the MJB-3. Finally, develop the photoresist with MF351:I20 (1:5) developer for 30-45 seconds. * Remove the photoresist scum in the plasma asher at 80 W and 250 mT of 02 for 1 minute. * Contour bake for 2 minutes on a metal block which has been heating in a 130~C oven for at least 30 minutes. * Deposit the plating membrane of Ti/Au/Ti (500/2000/500 A) in the e-beam evaporator. B.6.2 Span Definition * Lithography: Spin PR1827 photoresist only at 3.0 Krpm for 30 seconds. Soft bake in the oven at 80~C for 20 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 1 minute and developing in AZ-327 MIF for 45 seconds. Next, pattern the "span" image by exposing for 18-20 seconds with the 157

MJB-3. Finally, develop the photoresist with MF351:II20 (1:5) developer for 30-45 seconds. * Remove the photoresist scum in the plasma asher at 80 W and 250 mT of 02 for 1 minute. * Dektak the photoresist profile and record the photoresist height around the air-bridges. * Remove the top layer of Ti with IIF:HI20 (1:10) for 5-6 seconds. * Electroplate the air-bridges with 2-3~pm of Au. B.6.3 Sacrificial Layer Removal * Flood expose with the MJB-3 for 3 minutes and develop the photoresist with MF351:1I20 (1:5) developer for 1 minute. * Remove the top layer of Ti with ILF:I20 (1:10) for 5-6 seconds. * Remove the middle layer of Au with Au etchant solution for 1 minute. * Remove the bottom layer of Ti with ILF:HI20 (1:10) for 5-6 seconds. * Remove the first layer of photoresist in heated PRS-1000 resist stripper for 60 minutes. * If there is photoresist scum then remove with plasma asher at 150 W and 250 mT of 02 for 5 minutes. 158

APPENDIX C FABRICATION PROCESS FOR MONOLITHIC MIXERS AND MULTIPLIERS IN A TRANSMIT/RECEIVE MODULE. C.1 PECVD SiXNy Deposition * Clean the wafer in heated Acetone for 2 minutes and IPA for 2 minutes. * Etch native oxide in NII401I: H20 (1:15) for 30 seconds. * Bake for dehydration on the hot plate at 130~C for 2 minutes. * SiNy deposition of 2400 A according to table C.1. C.2 Schottky Well Formation The pattern is aligned to the edges of the wafer in such a way that the diode fingers are parallel to the slow undercut direction ( 111 >). * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 6.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 159

Gas/Flow SiI4/30 scem Gas/Flow NH3/6.4 scem Gas/Flow Ar/40 seem Pressure 100 mT Power 20 W Time 80 min Temperature 300~C Thickness 2400 A BIIF etch rate 850 A/min Index of refraction 1.85 Table C.1: PECVD SiXNy deposition. 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds (the intensity of the aligner is set to 20 mW/cm2). Next, pattern the "schottky" image by exposing for 3 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.5 minutes. Develop the photoresist with AZ-327 MIF developer for 40 seconds. If the small features have not developed then repeat in increments of 10 seconds. * Reactive Ion Etch (RIE):Dry etch the SiXNy from 2400 A to 200-300 A. Not all of the nitride should be removed, because the plasma will damage the GaAs surface. Insert the wafer in the plasma etcher and use 02 and CF4 for a total etch time of 3-3.5 minutes. Initially do a 1 min etch and then continue with 20 second etches. The etch depth can be monitored using a Leitz MPV-SP dielectric thickness measurement 160

system that measures the Si:VNy in rectangular areas of 100um x 300im. These rectangles should be in different areas of the wafer. C.3 Ohmic Contact Definition * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 4.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "ohmic" image by exposing for 3 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.5 minutes. Develop the photoresist with AZ-327 MIF developer for 30 seconds. Finally, bake at 110~C for 1 minute in order to further strengthen the resist for a BIIF dip. * Reactive Ion Etch (RIE): Remove the SiXNy from the areas of the ohmic contact by doing a 5 min plasma etch. * Etch through the epitaxial low doped layer with II3P04: II202: II20 (1:1:8) for 20 seconds (2000 OA thick n- layer) or 36 seconds (4000 A thick n- layer). * Etch the native oxide with BIIF for 15-20 seconds. This etch also undercuts the SixNy layer which is beneficial in the reduction of stress when the ohmic contacts will be annealed. * Deposit ohmic metal layers of Ni/Ge/Au/Ti/Au (250/325/650/450/2500 A) in the e-beam evaporator. * Lift-off in heated PRS-1000 photoresist stripper for 60 minutes. 161

* Anneal the ohmic contacts using hot plates at 2400/4050/2400C for 20/40/20 seconds. C.4 Finger/Anode Definition * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 4.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "finger" image by exposing for 3 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.5 minutes. Develop the photoresist with AZ-327 MIF developer for 30 seconds. Finally, bake at 110~C for 1 minute in order to further strengthen the resist for a BIIF dip. * Remove the remaining SiXNy and native oxide with a BIIF etch for 30 seconds (must load into evaporator no later than 2 minutes). * Deposit Schottky barrier metal layers of Ti/Pt/Au (500/500/3000 A) in the e-beam evaporator. * Lift-off in heated PRS-1000 photoresist stripper for 60 minutes. C.5 Mesa Etch In this step the epi layers are removed everywhere from the wafer except for small rectangular areas around the diodes. This is necessary so that the passive circuits are sitting on semi-insulating GaAs and not active layers. The finger etch will follow after the circuit deposition. During the design of the mask for this layer, enough space should be left around the diodes in order to minimize the undercut. 162

* Lithography: Spin HIMDS adhesion promoter and AZ5214-E photoresist at 2.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "etch" image by exposing for 4.5 seconds with the MJB-3. Develop the photoresist with AZ-327 MIF developer for 45 seconds. Finally, hard bake on the hot plate at 130~C for 1 minute. * Reactive Ion Etch (RIE): Remove the SiXNy from the areas that will be etched by doing a 5 min plasma etch. * Etch mesa with NII40II: II202 (1:24) for 25-30 seconds (etch rate is 4Ym/min). Rinse but without drying, immediately follow with an oxide etch in N I401: II20 (1:15) for 15 seconds. * Remove the photoresist in Acetone and IPA. C.6 Circuit Printing * Lithography (image reversal): Spin IIMDS adhesion promoter and AZ5214-E photoresist at 2.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "circuit" image by exposing for 3-4 seconds with the MJB-3. Post-bake on the hot plate at 130~C for 1 minute. Flood expose with the MJB-3 for 1.2 minutes. Finally, develop the photoresist with AZ-327 MIF developer for 20-30 seconds (initially 20 secs and then 5 secs increments). * Deposit the circuit metal layers Ti/Al/Ti/Au (500/6000/500/3000 A) in the e-beam 163

evaporator. * Lift-off in heated PRS-1000 photoresist stripper for 3 hours. C.7 Finger Etch In this step the epi layers underneath the fingers of the diodes are etched. * Lithography: Spin IIMDS adhesion promoter and AZ5214-E photoresist at 2.5 Krpm for 30 seconds each. Pre-bake on the hot plate at 110~C for 2 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 45 seconds and developing in AZ-327 MIF for 30 seconds. Next, pattern the "finger etch" image by exposing for 4.5 seconds with the MJB-3. Develop the photoresist with AZ-327 MIF developer for 45 seconds. Finally, hard bake on the hot plate at 130~C for 1 minute. * Reactive Ion Etch (RIE): Remove the SiNy from the areas that will be etched by doing a 5 min plasma etch. * Etch mesa with N140II: 1202 (1:24) for 15-20 seconds (etch rate is 4im/min'). Rinse but without drying, immediately follow with an oxide etch in NII401: II20 (1:15) for 15 seconds. * Remove the photoresist in Acetone and IPA. C.8 Air-Bridge Formation C.8.1 Post Definition * Lithography: Spin IIMDS adhesion promoter and PR1827 photoresist at 3.0 Krpm for 30 seconds each. Pre-bake on the hot plate at 105~C for 1 minute. Remove the 164

edge beaded resist by exposing the edges with the MJB-3 aligner for 1 minute and developing in AZ-327 MIF for 45 seconds. Next, pattern the "post" image by exposing for 9-10 seconds with the MJB-3. Finally, develop the photoresist with MF351:120 (1:5) developer for 30-45 seconds. * Remove the photoresist scum in the plasma asher at 80 XV and 250 mT of 02 for 1 minute. * Contour bake for 2 minutes on a metal block which has been heating in a 130~C oven for at least 30 minutes. * Deposit the plating membrane of Ti/Au/Ti (500/2000/500 A) in the e-beam evaporator. C.8.2 Span Definition * Lithography: Spin PR1827 photoresist only at 3.0 Krpm for 30 seconds. Soft bake in the oven at 80~C for 20 minutes. Remove the edge beaded resist by exposing the edges with the MJB-3 aligner for 1 minute and developing in AZ-327 MIF for 45 seconds. Next, pattern the "span" image by exposing for 18-20 seconds with the MJB-3. Finally, develop the photoresist with MF351:H20 (1:5) developer for 30-45 seconds. * Remove the photoresist scum in the plasma asher at 80 W and 250 mT of 02 for 1 minute. * Dektak the photoresist profile and record the photoresist height around the air-bridges. * Remove the top layer of Ti with IIF:II20O (1:10) for 5-6 seconds. 165

* Electroplate the air-bridges with 2-3yum of Au. C.8.3 Sacrificial Layer Removal * Flood expose with the MJB-3 for 3 minutes and develop the photoresist with MF351:11J20 (1:5) developer for 1 minute. * Remove the top layer of Ti with IIF:H20 (1:10) for 5-6 seconds. * Remove the middle layer of Au with Au etchant solution for 1 minute. * Remove the bottom layer of Ti with IIF:HI20 (1:10) for 5-6 seconds. * Remove the first layer of photoresist in heated PRS-1000 resist stripper for 60 minutes. * If there is photoresist scum then remove with plasma asher at 150 W and 250 mT of 02 for 5 minutes. 166

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Appendix B: Lee Harle, John Papapolymerou, Jack East, Linda P.B. Katehi, The effect of slot positioning on the bandwidth of a micromachined resonator, 28th European Microwave Conference Proceedings, Oct. 1998, vol. 2, pp. 664-668. 8

The effects of slot positioning on the bandwidth of a micromachined resonator Lee Harle, John Papapolymerou, Jack East and Linda P.B. Katehi Department of Electrical Engineering and Computer Science The University of Michigan, 1301 Beal Avenue Ann Arbor, MI 48109-2122 Abstract This paper presents the effect of slot positions on the bandwidth and the response of a micromachined high.Q X-Band resonator formed by a micromachined cavity. Theory and experiment indicate that a narrow-band low-loss response can be achieved by changing the placement of the slots relative to the center of the cavity As a result, narrow-band, low-loss, monolithic filters with small weight and planar characteristics can be designed I Introduction Microwave high-Q resonators are traditionally made of metallic rectangular or cylindrical waveguides that are heavy in weight, costly to manufacture and difficult to integrate with monolithic circuits. Recently it has been shown by Papapolymerou et al [1] that a low-loss, high-Q resonator can be fabricated in a planar environment by using standard micromachining techniques shown by Drayton et al [2]. The X-Band resonator shown in Fig. 1 consists of input and output microstrip lines that reside on top of a silicon wafer and couple energy via slots into a micromachined cavity which is formed on a second wafer. The energy that is coupled to the cavity can travel through it in the form of a propagating or evanescent wave. Measureents have shown an insertion loss of 0.36 dB and an unloaded quality factor Qu of 506 that is in good agreement with the theoretical value of a rectangular metallic cavity of similar size, as in Collin [3]. This resonator can be used as a building element for the design and fabrication of narrow-band, low-loss filters and multiplexers made of multiple cavities of the same or different size. Energy between cavities is coupled via slots of different shapes and positions. Originally the slots are placed at 1/4 and 3/4 of the cavity length from the shorter edges of the cavity. Herein. we investigate both experimentally and theoretically the effects of reducing the distance between the two slots on the bandwidth and the insertion loss. In addition, theoretical results indicating the effect of packaging on the performance of the resonator will be presented.

II Results and Discussion The resonator shown in Fig. 1 with the slots positioned at 3/8 and 5/8 of the cavity length from the shorter edges has been fabricated using two high resistivity 500 plm thick silicon wafers, with PECVD (plasma-enhanced chemical vapor deposition) nitride grown on both sides of the wafers. The microstrip lines are formed on the top surface of the first wafer by gold electroplating to a total thickness of 6 pm. CPW (co-planar waveguide) to microstrip transitions are included in order to measure the resonator with on-wafer probing. Via holes establish the same potential for the CPW and microstrip line ground planes. The cavity is fabricated on the second wafer by using chemical anisotropic etching (TMAH water based solution) up to a depth of 470,um and is then metallized to a thickness of approximately 3 pm. The two wafers are finally bonded together using silver epoxy glue that is cured at 1500C. The fabricated resonator was measured using a TRL (Thru-Reflect-Line) calibration referenced at the slots and the measurements are compared with theoretical results in Fig. 2. Theoretical results were obtained by using the Hewlett-Packard High Frequency Structure Simulator [4]. As can be seen from Fig. 2 there is very good agreement between the simulated and measured response. The small discrepancy (1%) in the resonant frequency can be attributed to the inherent numerical error of the HFSS software and fabrication tolerances. The measured resonator exhibits a bandwidth of 2% (210 MHz) at a resonant frequency of 10.525 GHz. After de-embedding the loss on the two open end stubs extending beyond the center of the slots, the insertion loss is measured to be -1.1 dB. Comparison of these results to those presented in Papapolymerou et al [1] can be seen in Fig. 3 where we observe a 58% reduction in the bandwidth (from 500 to 210 MHz) and a 0.74 dB increase in insertion loss. These results indicate that by altering the positions of the coupling slots relative to the center of the cavity we can change (increase or decrease) the resonator bandwidth at the price of increased loss. This is expected since the Qu of the resonator is determined by the cavity and is independent of the slot positions. Preliminary simulations and measurements of the resonator with the slots positioned at 1/8 and 7/8 of the cavity length from the shorter edges show a bandwidth much greater than the original 500 MHz bandwidth. Prom Fig. 2 we can also observe a slight asymmetry in the response around the resonance. This is due to the close proximity of the two microstrip lines (0.4 AX) which allows power coupling from one to the other directly via substrate modes. In order to eliminate this effect and make the response more symmetric around resonance we can use micromachined on-wafer packaging as in Drayton et al [5] to isolate the microstrip lines from one another both on top and inside the substrate. For this purpose an HFSS simulation was run with one PEC (perfect electric conductor) plane placed on top of the structure and another placed between the two lines Shorting the top PEC to the slot plane. Results can be seen in Fig. 4, where we observe that packaging reduces the suspected coupling occuring below 10.3 GHz by as much as 4 dB. In addition, we observe that there is a Stall coupling of about -16 dB below 10 GHz that can be attributed to evanescent modes excited around the 'Slts inside the cavity. Presently study is under way to further understand the effect of evanescent modes and rProve out-of-band rejection. In a micromachined filter design with multiple cavities evanescent modes can be used instead of propagating ones to decrease the size of the cavities since these modes operate below cut-off. III Conclusions The effects of slot positions in a micromachined resonator have been presented. Although the Qu is determined the cavity itself, the bandwidth is determined by the relative position of the slots. Specifically. when the slots 665 28th European Microwave Conference Amsterdam 1998

are placed closer to the center of the cavity, the bandwidth is reduced and the insertion loss is incr close proximity of the slots produces evanescent modes that affect the shape of the response around res e as well as direct coupling between the microstrip lines that can be eliminated with appropriate package. the structure. of IV Acknowledgement This work is supported in part by the U.S. Office of Naval Research under Grant No. 00014-95-1.1299 in part by the U.S. Department of Defense Research and Engineering (DDR&E) Multidisciplinary Univerai Research Initiative (MURI) on "Low Energy Electronics Design for Mobile Platforms" and managed by the Army Research Office (ARO) under grant DOD-G-DAAH04-96-1-0377. References [1] J. Papapolymerou, J.C. Cheng, J. East and L.P.B Katehi, "A micromachined high-Q X-Band resonator, IEEE Microwave and Guided Wave Letters, Vol. 7, No. 6, pp. 168-170, June 1997. [2] R.F. Drayton, T.M. Weller and L.P.B. Katehi, "Development of miniaturized circuits for high-frequenc. applications using micromachining techniques," International Journal Microcirc. Elec. Packaging, Vol. 18 No. 3, pp. 217-224, 1995. [3] R.E. Colin,Foundations for Microwave Engineering. New York: McGraw-Hill, 1966, pp. 322-325. [4] HP 85180A High-Frequency Structure Simulator User's Reference, Hewlett-Packard Company, 1994. [5] R.F. Drayton, R.M. Henderson and Linda P.B. Katehi, "Monolithic packaging concepts for high isolation in circuits and antennas," IEEE Transactions on Microwave Theory and Techniques, Vol. 46, No. 7, pp. 900-906, July 1998.

12.177 = 3/8L 0.5 32.354 = L Figure 1: X-Band Resonator 9.5 10 Frequency (GHz) 11.5 Figure 2: Measured and simulated results for the resonator of Fig.1. 667 28th European Microwave Conference Amsterdam 1998

S21 e -20 0t -25 --30 'I -35 —:resonator of this paper \ -:resonator of [1] -40 -45 -9; '; ' ~ -- 8 8.5 9 9.5 10 10.5 11 1.5 Frequency (GHz) Figure 3: Measured results for the two resonators with different slot positions. Sil -5 -10 - -15 -.. S21 E -20 -25 Q.\ Figure 4: Simulated response of the packaged and non-packaged resonator.

Appendix C: R. F. Drayton, S. Pacheco,. Yook, and L. P.B. Katehi, Micromachined Filters on Synthesized Substrates, IEEE MTT-S International Microwave Symposium Digest, Baltimore, MD, Vol.3, pp. 1185-1188, 1998. 9

TH1A-5 Micromachined Filters on Synthesized Substrates R. F. Drayton1. S. Pacheco2. J.-G. Yook2. and L. P.B. Katehi 'EECS Department The University of Illinois at Chicago Chicago, IL 60607 (USA) drayton @eecs.uic.edu Abstract - Effective frequency spectrum usage requires high performance filters with a sharp cut-off frequency and high stopband attenuation. Stepped impedance lowpass designs achieve this with large ratios of high and low impedance values. In high index materials, however, such as Si (11.7) and GaAs (12.9), these ratios are around 5 which significantly limit filter performance. This paper presents the use of Si micromachining to produce synthesized substrates with stepped-impedance low filter designs. Of the two designs, one offers a reduction of the low impedance value while the other offers an increase of the high impedance value to produce Z!i/ZL ratios that are 1.5 to 2 times larger than conventional designs. 1.0 INTRODUCTION Efficient frequency spectrum usage by a diversity of communication-related applications (i.e. wireless, collision avoidance radars, etc.) demand development of high performance filters. In high frequency monolithic designs developed on high dielectric constant semiconductor materials, planar filters like stepped impedance ones suffer from less-steep cut-off frequencies and poor attenuation in the stopband. Optimum performance is achieved with large ratios of high and low impedance values which produce sharp cut-offs between the pass and stopband and high attenuation levels in the stopband. The dynamic range of realizable impedances in high index materials, however, is reduced considerably compared to designs on low index ones. Therefore, filters designs that rely on this mechanism for high performance are nearly impossible to realize in high index materials. In many filter designs, performance is greatly affected by the ability to accurately realize prototype filter elements (i.e. capacitor and inductors) in equivalent transmission line components. These inductive and capacitive values, therefore, are highly dependent on the available high and low characteristic impedances of the chosen transmission type. This paper presents a novel method for developing microstrip filters in high dielectric constant materials. Si micromachining is used to produce synthesized substrates in order to realize impedance values not com 2The Radiation Laboratory. EECS Department The University of Michigan Ann Arbor. MI 48109 (USA) katehi @ engin.umich.edu monly realizable in conventional substrates. These synthesized substrates have regions that are locally altered to reduce the thickness of the material. These alterations can result in two arrangements: (a) a reduced thickness microstrip region for a microstrip line, which decreases value of low-impedance line or (b) a reduced effective dielectric constant based on a combination of silicon/air, which increases the value of the high-impedance line. 2.0 DESIGN /FABRICATION APPROACH 2.1 Synthesized Low-Impedance Sections This filter design is implemented using commercially available CAD tools, such as HP's Libra and MDS, on full thickness substrates. The design for the synthesized substrate is then transformed using Linecalc to determine appropriate dimensions for impedances on thinner substrates. The overall objective in this approach is to develop an equivalent design with a locally thinned substrate that produces impedance values that are lower than the conventional design. In the work presented, a 7- section Butterworth filter is developed for a conventional and micromachined design using impedance values of 20 and 100 ohms. This was done to explore the impact that a synthesized substrate (i.e. reduced thickness region) would have on the filter response. While this design has not been optimized to include lower capacitive values (i.e. less than 20 ohms), an improved design will be developed and will be presented at the conference. The filter design and dimensions are given in Figure 1 and Table 1. Note that the inductive regions remain identical to the conventional design while the capacitive sections are developed on 50 micron thick regions to produce equivalent capacitance to the reference filter design. The circuits are printed on high resistivity Si with a thickness of 100 microns. The low impedance sections are developed on 50 microns thick regions that have been etched using KOH anisotropic etchant [1]. The etched cavity regions produce a sloped sidewall angle of 54.7~ 1185 0-7803-4471-5/98/S 1 0.00 c 1998 IEEE 1998 IEEE M'17-S Digest

that results in a gradient of 35.4 microns at each low impedance edge. Each design has a 50 ohm microstnp line and is fed by a coplanar waveguide probe pad that converts the on-wafer probe excitation to a microstrip mode. The circuits have 3.4 microns of electroplated Au and have a 2.5 micron ground plane metallization of Cr/ Al/Cr/Au that has been evaporated to cover the entire wafer surface. These are attached to a secondary wafer for additional support with similar metal composition. 2.2 Synthesized High Impedance Sections In this approach, dielectric material is removed using the etching process described earlier in the high impedance sections of the filter. This reduces the dielectric constant [2] and hence, produces a higher characteristic impedance. In this case, the inner walls of the cavities are not metallized as in the previous case and this results in very high impedance sections with much wider microstrip lines for the same impedance value (i.e. 70 microns vs. 3.2 microns on 250 um thick Si substrate). As shown in Figure 2 and Figure 3, the effective dielectric constant and characteristic impedance of microstrip lines on silicon micromachined substrates can be found using the full-wave FEM simulation for various geometrical factors [3]. Using the above approach, a 0.5 dB equi-ripple Tshebychev 7-section stepped impedance lowpass filter has been designed on 250 um thick silicon substrate, where 90% of the Si material has been removed from under the high impedance section of line (see Figure 4). The dimensions of each section have been tabulated in Table 2. Observe that the high impedance section width is increased by more than 20 times in the synthesized design compared to the regular one. 3.0 RESULTS The filter response presented shows measured results that are compared to numerical simulations generated either from HP's Libra, or full-wave FEM models developed at University of Michigan. The response is measured on a Cascade Microtech 9100 Probe station with 150 micron air coplanar waveguide probes and an 8510C Network Analyzer. All data was measured using the TRL calibration to eliminate the effects of the probe tips and feedlines in the measurement. 3.1 Synthesized Low-Impedance Sections The study presented compares the performance of the filter on the synthesized substrate to the conventional substrate. In the low impedance sections, the line width decreases from 380 microns on the 100 micron thick sub strate to 190 microns on the 50 micron thick region. As shown Figure 4. the response is very similar to the conventional design. To accurately assess. the performance of the micromachined design, Figure 4 shows the response of the filter compared to FEM simulation. The FEM results. which model the performance of the filter on the etched substrate, show a response that is shifted down by I GHz. In this case. bowtie tapers were introduced to offer a transition along the etched angle profile in the low impedance section. The measured and modeled data in Figure 5 produced nearly identical results which indicates that the etch angle does effect the phase delay of the various sections. The response curves of this design are very similar to the regular one, with better attenuation in the stop band as well as a better cut-off frequency. In Figure 4, the radiation loss is compared to all three designs. The higher loss in the bowtie design is believed to be due to the sharp comers along the discontinuity edge. Overall, this approach has shown merit and the synthesized and regular designs yield similar loss. Lower impedance values will be investigated to produce larger ZH/ZL ratios. Furthermore, the effect of the sloping walls will be evaluated to provide a better understanding of the impact of this type of design on filter performance. These new findings will be presented at the conference. 3.2 Synthesized High-Impedance Sections The lowpass filter on synthesized high-impedance sections (see Figure 6) has been analyzed using the fullwave FEM. In this design, a cavity region is formed where 90% of the silicon substrate has been etched away underneath the high-impedance section. Each cavity region has a width of 190 gm and lengths corresponding to the given high-impedance line section. As shown in Figure 7, the simulation results show very good stop and passband characteristics which are very close to those of ideal filter. The radiation loss of the filter is about -10 to -12 dB in the frequency region of interest. Note that the high attenuation level in the stopband is mainly attributed to the large ratio between the high and low impedance value of the filter. 4.0 CONCLUSION This paper presents two approaches to improve the performance of high frequency planar designs that rely on large ratios of high and low impedance sections. We have shown filter responses that are equal to if not better than those on regular designs. Either the high or low impedance synthesized filter designs can improve the ZH/ZL ratio by a factor of 1.5 to 2 by reducing the low impedance section by half or increasing the high impedance 1186

sections by 1.5. Furthermore. with the use of Si micromachining synthesized substrates are easily realizable in high index semiconductor materials that are commonly used in high speed monolithic design. 5.0 ACKNOWLEDGEMENTS This work has been supported by the MURL/ARO-Low Power Electronics Program. Special thanks to Mr. Jianpei Wang for his assistance during the fabrication at University of Illinois at Chicago. REFERENCES [1] K. E. Bean, "Anisotropic Etching of Silicon," IEEE Transactions on Electron Devices, Vol. ED-25, No. 10, pp 1185-1193, October 1978. [2] I. Papapolymerou. R. F. Drayton, L. P. B. Katehi, "Micromachined Patch Antennas", IEEE Trans. on Antennas and Propagation. Vol. 46, pp. 275-283, Feb. 1998. [3] J.-G. Yook, N. Dib and L. Katehi. "Characterization of High Frequency Interconnects Using Finite Difference Time Domain and Finite Element Methods", IEEE Transactions on Microwave Theory and Techniques, Vol. 42, pp. 1727-1736, Sept. 1994.. i.. ~...: microstrtp lrw -- back-side meta liz atlan Figure 1 Circuit Layout for Micromachined Filter with Synthesized Low Impedance Section. Section Width Width (ohms) (h=100) (h=50) 1 (100) 135 10 10 2 (20) 270 380 190 3 (100) 684 10 10 4(20) 480 380 190 5(100) 684 10 10 6(20) 270 380 190 7(100) 135 10 10 Table I Synthesized Low-Impedance Design. Design A filter dimensions with synthesized low impedance sections: All dimensions are in microns. to -.-. -~. 1.-. ~ ~ | -. 6 * < -, 4'.1; L2 - I1 -- --.14 7. A " I '4g. AI Is - - lo. Air f.1 ~1 0 I I 0 I 2 3 4 5 6 7 W/H1 a Figure 2 Effective Dielectric Constant Data. 2W..... 180 - * ~ r 160, 40 i 120 - 20 - 0 - O, Si t l. Air" i - 23. Air 7S S5i 0. AIrSC0 S i75. Air A2 St 90. Air 10 Si 100. Alr 0 0 1 2 3 4 5 6 7 8 W/l! Figure 3 Characteristic Impedance of the synthesized high impedance sections of line. Section Width Width (impedance in ohms) Lng (h=250) (10:90) 1 (30) 268 500 500 2(150) 498 3.2 70 3 (30) 500 500 500 4(150) 600 3.2 70 5(30) 500 500 500 6(150) 498 3.2 70 7(30) 268 500 500 Table 2 Synthesized High-Impedance Design. Design parameters on regular thickness Si having height =250 microns and synthesized high impedance sections based on a 10:90 percent ratio of Si:Air regions. The total substrate height is 250 microns and all dimensions in the table are in microns. 1187

It - qp= sso v - - - - - - - — 10 - 10 --20-,/ -40 --- ' - so* -_ * i * " = G If c - -. --- — -. 5I - S. U. -!J- LI:- S!!-Conventional o. S21-Conventional -*SII-Svnthesized (Low~*.- S21-Svnthesized (Lowr* SII FEM 7 o S21 FEM; -50 t, —..., 15 20 25 30 35 40 Frequency [GHzJ 0.4 I.... I - I.. - i.. rrcrostn p Ine - h A - MC I 7 4,I 71 17 back-side met al lization 4 Figure 6 Circuit Layout for NMicromachined Filter with Synthesized High Impedance Section. f..4 0 0 0.3 - Conventional --- Synthesized (Low) - - Synth. (Low).Bowtie T j i n C - - X - r::Epwqwwq 0.2 - O-W 0.1 -, F. I I I I I........ v 15 20 25 30 35 15 20 25 30 35 40 Frequency, [GHz] Figure 4 Synthesized Low-Impedance Filter Design. (a) Filter response with measurement and modeled results. (b) Total Loss calculations between two designs. 15 20 25 30 35 40 Frequency [Gliz].,......... i, _ I I I v r vu _ -10-, -20 -= -30 --40 --40-1 S-S \ --- sll.S........ S21-S ~ S 1-F * S21-F — e —. * w - * * * f d., '-.o..*. ynth. (Low)-Bowtr ynth. (Low)-Bowti FEM FEM Figure 7 Synthesized High Impedance Filter Design. Simulation based on Finite Element Method. (a) Effective Dielectric Constant Design curves for mixed Si/Air region. (b) 7-Section Tshebychev Filter Response........... 15 20 25 30 35 40 Figure 5 Comparison of FEM to Bowtie Response. 1188

Appendix D: Linda P.B. Katehi, ficrotechnology in the Development of ThreeDimensional Circuits, presented in Microwaves and RF '98, October 1998, London UK. 10

10A.1 Novel circuits and antennas for high frequency applications L P B Katehi, University of Michigan, USA Ann Arbor, MI 48109-2122, USA Tel: +1 313 647 1796 Fax: +1 734 647 2106 High frequency applications impose very strict requirements on circuit performance including low loss, low dispersion and negligible parasitics. Presented herein are novel approaches that offer flexibility to the design of circuits and antennas by allowing for on-wafer packaging and locally reduced substrate thickness to achieve excellent electrical performance. The fabrication of these circuits is based on conventional Si/GaAs/InP fabrication techniques and, as such, they preserve their monolithic character while at the same time allow for high density and threedimensional integration. Micromachined high-frequency circuits with integrated packaging offer lightweight and controllable parasitics, which makes them appropriate for hand-held communication systems and miniature intelligent millimetrewave sensors where system requirements impose strict limits on electrical performance. Recent advances in semiconductor processing techniques allow for integration in all of the directions of the three-dimensional space. The capability to incorporate one more dimension, and a few more parameters, in the circuit design, leads to revolutionary shapes and integration schemes. These circuit topologies have reduced ohmic loss and are of free parasitic radiation or parasitic cavity resonances without losing their monolithic character. Integration capabilities are thereby extended and performance is optimised. The evolution of micromachined circuits and antennas for operation in microwave and millimetrewave frequencies is still in its infancy. However, presented here is a description of recent accomplishments in this area, with emphasis on the effort performed at the University of Michigan. There are two techniques which have shown promise for use, and which extensively use micromachining to realise novel circuits. The first utilises dielectric membranes to support transmission line and antenna configurations and emphasises optimisation of circuit performance. The second technique introduces new concepts in packaging such as adaptive or conformal packaging and, in addition to improvement in performance, it emphasises size/volume/cost reduction. The merits of each approach, in relation to electrical performance, fabrication and compatibility will be presented, and the impact of the newborn technologies to the state of art will be discussed. 304

M1+RF 98 * 29 September - 1 October 1998 * London * UK Microtechnology in the Development of ThreeDimensional Circuits Linda P. B. Katehi Electrical Engineering and Computer Science Department The University of Michigan, 1301 Beal Av. 3240 EECS Build. Ann Arbor, MI 48109 katehi eecs.umiclh.edu Introduction Over the past forty years the progress of technology and the invention of the transistor have made it apparent that very small transmission lines compatible with planar solid state technology are needed to effectively couple power of microscopic devices, such as integrated circuits, into macroscopic systems, such as satellite communication systems. It is solid state device technology that has driven the development of planar Monolithic Microwave Integrated Circuits (MMICs) that dominate today's communications systems. This technology has allowed for the design of small RF circuits that combine many functions on a single circuit while providing high performance and low cost. Spacecraft communications systems have benefited tremendously from these advances as applied to microelectronics and VLSI (Very Large Scale Integration), and have experienced steady decreases in both cost and communication system mass. During the past two decades the scale of integration, available materials, batch-production yields, reliability, and raw performance of high-frequency and high-speed components have steadily improved. Thus, many frequency and speed requirements previously met with large volume and weight components are now achievable with miniature lightweight and highly reliable devices. However, cost reduction has recently achieved a plateau indicating that conventional planar technology has reached its limitations and cannot address the needs of the next generation of communication systems and microwave or millimeter-wave radars. Future communication satellite systems must have minimal spacecraft mass for smaller launch vehicle employment. In addition to reduced size, to maximize returned data and minimize ground operation costs, communication systems are moving up in frequency to Ka-Band (25-40 GHz). This will enhance solar system exploration, global environment understanding, and development of the information superhighway. Furthermore in addition to decreasing spacecraft size, the functionality of the platforms are increasing, necessitating the use of highly integrated sensors and instruments [1]. One area of improvement in reducing size is electronic packaging, which can account for up to 30%

M+RF 98 * 29 September - I October 1998 * London * UK of the overall spacecraft mass, and the telecommunication subsystems, which account for 15% or more of the dry mass. Based on this information, advanced high-frequency microelectronics high-density integration and on-wafer packaging is a key to reducing volume and mass, while improving performance. - X-Band Waveguld.~ -Transfer Switch.Ls (WTS) X-Band Dlplecer Waveguide High- Frequency Transnmisioii ULne Technology Total Mass: -2.8kg Volume: 2874.4 cnl3 Is5mn -.4 \-4mN I 3) - -: "nd As " j -W I: Iz5.,:.l Total Mass: ~3 g Volume: 2.4 cm3.... (a) (b) Fig. 1. Satellite communications. (a) Today's technology. (b) Future technology. The next leap beyond the current state-of-the art for the presently used multichip module (MCM) is the development of a technology which can provide monolithic integration of Si (or SiGe) circuits, advanced micro-electromechanical (MEMS) devices, micromachined analog components (e.g. filter/multiplexers), and digital CMOS based processing circuits into one wafer. Figure 1 shows both traditional and future front-end communication satellite implementations. The use of electronics in space poses interesting but grand challenges. It also provides the opportunity for using revolutionary concepts in circuit design, fabrication, and implementation to achieve what is considered by today's standards as ultimate performance, minimal volume, and very low cost. Circuit miniaturization can be easily achieved by means of true three-dimensional integration where circuits are laid in all spatial dimensions. This approach has been effectively used in the design of microprocessors and has resulted in a dramatic reduction of size and an unbelievable increase in speed. In combined digital and low-frequency analog applications, multilevel integration results in circuits with multiple power and ground planes and with stripline or microstrip signal lines transitioning between various levels using plated-through vertical interconnects. This integration approach has been proven very effective for clock rates on the order of a few hundred megahertz generating signal harmonics reaching into the low gigahertz range [2]. A similar approach was

M+RF 98 * 29 September - I October 1998 * London * UK recently used to provide high-density integration (HDI) in high-frequency RF circuits, and provided vital integration solutions for frequencies up to K-band. This HDI approach relies on the use of microstrip technology on very thin (10-20 gim) polyimide layers to provide lines that transition to various planes while sharing the same ground printed at the lowest level of the three-dimensional interconnect structure [3].The use of a single ground, that does not follow the microstrip lines as they transition into the various planes, in addition to high ohmic loss due to the narrow signal lines (5-34 gim), limits this approach to only a handful of applications and relatively low frequencies of operation. Ifrrafurmhlned 1 rmnauihotl U1n P 'vi -I v --, -'-.g Mdid L.,Figure 2: Novel Vertical Interconnect Geometries When conventional lines such as microstrip and coplanar waveguide are tested in a threedimensional environment, their performance typically degrades at higher frequencies due to parasitic radiation and coupling, as well as parasitics from metallized packages or carriers. To avoid these parasitic mechanisms, novel transmission line designs are required (see Figure 2). In this presentation, we will review various types of transmission lines on high-resistivity silicon appropriate for RF applications and discuss the beneficial performance trends and circuit architectures as operating frequencies increase to the millimeter-wave regime. Furthermore, we will discuss issues involved with packaging and interconnects for use in three-dimensional vertically integrated circuits. Acknowledgments This work has been funded by the US Army Research Office, JPL, DARDA, and DARPA/Hughes. References 1. L. P. B. Katehi, Aerospace report, 1998. 2. J.-G. Yook, L.P.B. Katehi, K.A. Sakallah, R.S. Martin, L. Huang, and T.A. Schreyer," Application of System-Level EM Modeling to High-Speed Digital IC Packages and PCB's, "IEEE Transactions on Microwave Theory and Techniques, MTT-45, No. 10, pp. 1847-1856, October 1997. 2. 3. P. D. Cooper, P.A. Piacente, and R. J. Street, "Multichip-On-Flex Plastic Encapsulated MHDI-Low Cost Substrates Manufacturing for Microwave and Millimeter wave Modules,"MTT-S 96, San Francisco, June 17-21, pp. 219-222. 3. 4. K. J. Herrick, T.A. Schwarz, and L.P.B. Katehi, "Si-Micromachined Coplanar Waveguides for Use in High-Frequency Circuits, "IEEE Transactions on Microwave Theory and Techniques, MTT-46, No. 6, pp. 762-769, June 1998.

Appendix E: Linda P.B. Katehi and Katherine Herrick, Si Micromachining for HighFrequency Circuits, Invited paper, ESA Workshop on Millimeter-Wave Technology and Applications, ESPOO, Finland, May 27-28, 1998. 11

SI-MICROMA CHINING IN MM- WAVE CIRCUITS Linda P.B. Katehi and Katherine Herrick The University of Michigan, Ann Arbor, MI introduction Despite the excellent characteristics and results in all MMIC implementations, high power has remained a challenge. The low-power output of solid state sources along with their low-impedance, further hindered by conventional transmission line characteristics, results in even lower efficiencies. From a device perfornance point of view, it is obvious that traditional planar line techniques introduce high losses due to the excitation of substrate wave modes. While parasitic radiation is inherent to microstrip and cannot be suppressed, ground connections can be achieved by use of via hole technology. Via holes, however, result in high parasitic inductance and parasitic radiation leading to a substantial device gain degradation which has a detrimental impact on circuit operation at millimeter-wave frequencies. Conventional coplanar technology also provides limited solutions to some of these problems by bringing the ground plane to the proximity of the active devices at the cost of additional parasitic effects such as the excitation of parallel plate and microstrip modes, thus resulting in increased fabrication complexity. These effects require geometry modifications and transmission media, such as channelized waveguides, which are difficult to implement, especially at higher frequencies. All solutions which have been proposed to eliminate parasitic modes have been proven quite ineffective, thus making conventional microstrip and coplanar transmission line approaches less attractive for use in millimeter wave MMICs. In an effort to increase generated power reduce loss and design cycle, a new generation of MMICs is needed. RF Si micromachining is an excellent approach that provides solutions to the above problems. To realize a new generation of MMICs, micromachining of GaAs or InP based devices and circuits needs to be explored in terms of its suitability for MMIC realization and packaging. Micromachined CPW Transmission Lines During the past five years our group at the University at Michigan has undertaken an extensive effort on the development of a high-frequency micromachining technology [l]-[3]. This technology is based on a simple idea: to introduce, through established MMIC processes, structural changes in the semiconducting wafers (Si, GaAs or InP etc.) to improve circuit performance, attain additional functionality and introduce new integration capabilities. This approach has shown tremendous potential in transforming existing MMICs into a new generation of devices and circuits which are characterized by a substantial increase in 0-7803-3887-1/98/$1 0.00 ( 1998 IEEE. 85

generated power capability and considerable cost benefits [4]. This concept has been successfully implemented in finite ground coplanar waveguide circuits operating in Ka-, V- and W-band circuits and has demonstrated excellent loss reduction. Figure 1 shows these micromachined coplanar wavgetuides where material has been removed from the aperture regions resulting in lower ohmic, dielectric and parasitic radiation loss. Figure 2 shows loss measurements vs. line undercut and indicates loss performance in these lines similar to the membrane lines that have so far exhibited the lowest recorded loss after the metallic waveguide. These lines can be fabricated on full thickness substrates with no wafer thinning or via holes needed. The line characteristics do not depend on the conditions on the back side of the wafer, so several wafers can be stacked to form a three dimensional structure with no effect on the line characteristics. The lines propagate a near TEM mode with very little dispersion. The effective dielectric constant of the micromachined finite ground coplanar waveguide lines is constant within +/- 1% from 4 to 110 GHz, while junction parasitics are very weak. These properties simplify the design of millimeter-wave components and provide excellent electrical performance. Results for specific filters and power dividers will be shown and discussed during the presentation. FIGURE 1. High-Performance Micromachined Finite Ground Coplanar Waveguide Silicon-Etched CPW Slots 40-50-40 Anisotropic Etch (EDP) Isotropic Etch (HF/Nitric) /I-** - r w ugyCI g 2 —.- p- *- * f, ' t W.' ':/ A;, *. 86

FIGURE 2. NlLeasured Losses and Effective Dielectric Constant vs. Undercut at 50 G;Hz. 4 ~ 3.5 ~ 3 ~ 2.5. 2 1.5 $a ~ '1 J_ -- XO-40-XO -- Microshield -g-45.20-45 -? 5.....*............................... i...........................................................................-..................:.............................................. '................ -0-40 — -80 i iN.. -4 — i: i............R..................'.......t le b~~ ~ i.... h..?..i...?.... i...i...T... I -— % 6 ': 4:d;-^ w Ia 2 icruectiv'e Dielectric Constanitj IT II T IIi I 1 I 0.5 I J I I I -2 0 2 4 6 8 10 12 14 Undercut I I I I I I I I I I I I I I I I I I I I..... I I I I........... 11 -5 0 5 10 15 20 25 30 35 Undercut Micromachined CPW W-Band Components The micromachined finite ground coplanar waveguides described above have been used in the design of a four-resonator W-band-pass filter as shown in Figure 3. The Si substrate has been etched away from the main lines and the resonator apertures to allow for reduced loss. The filter was fabricated and its measured performance is shown in Figure 4. FIGURE 3. Micromachined W-Band Filter 7 --- 87

The measured results show a loss of 0.8 dB at 94 GHz, an improvement of 0.8 dB over a similar finite ground coplanar filter with an insertion loss of 1.6 dB at the same frequency. FIGURE 4. Scattering Parameter Measurements for the Filter of Figure 3. 0 -10 -20 -30 -40 -50 20 40 60 80 100 Frequency (GHz) References 1. R.F. Drayton, T. M. Weller, and L. P. Katehi, "Development of Miniaturized Circuits for High-Frequency Applications using Micromachining Techniques," International Journal of Microcircuits and Electronic Packaging, Third Quarter, 1995. 2. S.V. Robertson, L.P.B. Katehi and G.M. Rebeiz, "Micromachined Self-Packaged W-Band Bandpass Filters," in 1995 IEEE MTT-S Digest, pp. 1543-1546. 3. Linda P.B. Katehi, "Novel Transmission Lines for the Submillimeter-Wave Region," IEEE Proceedings, Vol. 80, No. Il, Nov. 1992, pp. 1771-1787. 4. K. Herrick, T. Schwartz and L.P.B. Katehi, "W-Band Micromachined Finite Ground Coplanar Waveguide Filters," 1997 International Symposium on Microwave Theory and Techniques, Denver, Colorado, June 1997. 88