T H E U N I V E R S I T Y O F M I C H I G A N Memorandum 19 A CYCLIC CHECK COMPUTER FOR ERROR DETECTION Kenneth E. Burkhalter CONCOMP: Research'' in Conversational Use of Computers F..H. Wes'te:r'ive I,t., >'.Pr.ject Director ORA Pro j'e c.t. 07.449 suppor-ted b-y: ADVANCED RESEARCH PROJECTS AGENCY DEPARTMENT OF DEFENSE WASHINGTON, D oC CONTRACT NO. DA-49-083 OSA-3050 ARPA ORDER NO. 716 administered through: OFFICE OF RESEARCH ADMINISTRATION ANN ARBOR June 1968

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TABLE OF CONTENTS Page LIST OF FIGURES..................................... v I. INTRODUCTION.. O............................ 1 II. DESIGN DISCUSSION............................. 2 a. Error Checking............................ 2 b. Design Objectives......................... 4 III. SYSTEM DESCRIPTION........................... 5 IV. PROGRAMMING AND CONTROL CONSIDERATIONS....0... 10 V. DETAILED LOGIC DISCUSSIONS. o................. 12 IOP Decoding and Device Selection........... 12 Character Buffer............................ 17 Residue Register Control.................... 19 Residue Register Mod 2 Adders................ 23 Residue Register............................. 26 Shift Control and Mode Storage................ 26 PDP-8 Added Circuitry........................ 30 APPENDIX A. UTILIZATION MODULE LIST AND CIRCUIT NAME MAP............................... A-1 APPENDIX B. CONNECTOR MAPS......................... B-1 APPENDIX C. DIAGNOSTIC PROCEDURES.............. C-1 iii

LIST OF FIGURES Figure Page 1 General Block Diagram................. 6 1.1 CRC-16 BCC Generation....................... 7 1.2 CRC-12 BCC Generation.................. 8 2 Cyclic Check Computer-Example Routines...... 13 3 IOP Address Decode AC Buffers............. 14 4 Character Register......................... 18 5 Residue Register Control.................... 20 6 IN/OUT Gating Residue Register.............. 22 7 MOD 2 Adders............................. 24 8 Generator Shift Register................... 27 9 Run and Mode Control......................o 28 10 Additions to PDP-8 CPU.................... 31 B1 Cable Layout Map........................... B-2 B2 Connector Map............................... B-3 B3 Connector Map............................ B-4 B4 Connector Map............................ B-5

A CYCLIC CHECK COMPUTER FOR ERROR DETECTION I. INTRODUCTION This report discusses the design and use of a hardware device to compute from an input message stream a residue, modulo a program-selectable polynomial, which serves as an errordetecting check over the message itself. The purpose of this device is to free the support processor (the Data Concentrator PDP-8 in this case) from the software overhead burden of checksum computation, which may require up to 500 microseconds per input character in the case of the PDP-8. It is readily possible to compute-the same checksum by hardware methods in 4 microseconds! In addition, the reduced time required allows the computation to be accomplished in real time rather than task time, thus allowing simpler programming conventions. The cyclic check generator is composed of two registers which are loaded and read under program control. The character register is loaded with the new input character and the residue register is loaded with the last computed residue (zero for the first time through). After executing the start command the processor then reads the new contents of the residue register to obtain the current check digits. Since the cyclic check interface holds the PDP-8 in PAUSE state until checksum computation is completed, the programmer is always guaranteed to have the current results available when the residue register is read after initiating computation. The generator is capable of operating in three different modes to compute the residue on 6, 8, or -1

-212 bit wide characters, following IBM binary synchronous communication conventions. This report will serve as a progress report for those interested in project technical progress, and as a maintenance manual for those responsible for future system maintenance. Basic design discussions and objectives will be described first, followed by a brief overall equipment description with detailed logic explanations and programming considerations. Finally, maintenance software is included to aid in hardware debugging. II. DESIGN DISCUSSION a. Error Checking Probably some of the most important developments, in the area of error-detection and error-correcting codes, over the past decade have pertained to cyclic codes. Encoding procedures for these codes are relatively easily implemented in hardware using a shift-register with feedback connections, or they may similarly be emulated by software techniques. This method of error checking, called cyclic redundancy checking (CRC), is always done at the receiving station and is computed over each physical message block, excluding only certain control characters under special circumstances. The CRC technique is a much more powerful means of block checking a message than is a longitudinal-redundancy check or mod-2 add over the message stream. It is especially useful in

-3detecting burst errors which may cause several successive bits or even whole characters of the message to be altered. Algebraically a cyclic code is defined in terms of a generator polynomial P(X) of degree n-k, where a message of k binary digits is encoded by appending n-k binary digits as a check then transmitting the K information bits followed by the n-k check bits. Thus, it is convenient to think of d_- N K - - N-K ~ MESSAGE BITS - - CHECK BITS i these binary digits as the coefficients of a polynomial in the dummy variable X; for instance the message 101011 is represented 3 by the polynomial X5 + X + X + 1 o To encode a message polynomial G(X), it is divided by the generator polynomial P(X), where the division is formed over the Galois field of two elements, consisting of the integers modulo two; that is, the field consists of the two elements 0,1. Carries are ignoredo The remainder R(X) from the above division becomes the check polynomial and is appended to the original message. Thus, n-K X G(X) = Q(X)P(X) + R(X) where Q(X) is the quotient and R(X) the remainder resulting n-K from the division of X G(X) by P(X). The message polynomial G(X) is premultiplied by XK to obtain a vector

-4for which the first n-K components are zero (to allow subsequent addition of the residue), and the last k components, arbitrary information (message) symbols. Rewriting the above equation, and letting F(X) equal the encoded message, we have n-K F(X) = X G(X) - R(X) = Q(X)P(X) or since, in modulo two arithmetic, subtraction and addition are the same, F(X) = X G(X) + R(X) In short, the code symbols are just the message polynomial expressed modulo the generator polynomial P(X). b. Design Objectives In order to obtain a flexible interface for the cyclic redundancy generator (CRG) the following design objectives were set forth; 1. There must be generality without an extensive I/O instruction set required. 2. The PDP-8 accumulator (AC) should be automatically cleared after writing a CRG register to save that programming overhead. 3. The CRG should accommodate several different character sizes and be able to compute at least the IBM-compatible CRC-16 and CRC-12 checksums.

-54. Since the generator requires a variable execution time depending on character size it seemed desirable to be able to stop the PDP-8 processor for the required time, rather than following the start command to the CRG with the maximum required number of NOP's. These objectives were met with the resulting hardware constructed within 3/4 of a standard DEC 1943 mounting panel. In addition, minor modifications were required to the PDP-8 to allow the hold off, or extended pause, facility to be implemented. The allowed input character sizes to the CRG were restricted to only three widths consisting of 6,8,or 12 bits. The choice of a character size by the programmer results in the appropriate generator polynomial feedback taps being set up, as well as enabling the correct register gating paths for input and output. III. SYSTEM DESCRIPTION A general block diagram of the main CRG registers is shown in Figure 1. The character buffer is loaded with the incoming message character prior to computing the new residue. As this buffer is loaded a mode flip-flop is also set accordingly to either byte (8-bit character) or word (6- or 12-bit character) mode. The setting of this mode flip-flop determines which generator polynomial shall be applied to the residue register and also enables the correct data paths for subsequent residue register I/O0

AC BUS IN AC4-11 ACO-11 AC4-11 AND AND AND BCH READ BCL READ BYTE MODE FBTAP1 I BYTE MODE WORD FBTAP2 ORD MO 12-BIT M OAR<I -1 ~ 1 8-B CHARDE, WORD MODE I CHARACTER'BUFFER.4 5 6 2.1 7 g! 0 14, REGISTER AC BUS OUT Figure 1. General BCk Diagram. LOAD CHAR4B6-IT C-ARr-4 bBYBCHMRIT 12-BIT CH.BC'WIBYTE BYTE 8-BIT CHAR MODE WORD MODE u 6 U 12-BIT CHAR o AC BUS OUT Figure 1. General Block Diagram.

-7I/O transfers to or from the PDP-8 AC are automatically routed from or to the residue register according to the current mode setting, with all data right-adjusted in the AC. The residue register contains six mod-2 adders between various stages for implementation of two different checking polynomials. The appropriate adders are enabled by the operating mode, set up at the time the input character is loaded. In the byte mode of operation the generator polynomial [P(X)] used is 16 15 2 X +X +X + 1 The resulting encoded message allows the receiver to detect any burst error of length 16 or less, as well as more than 99,9997% of all errors of greater length. The above 15 polynomial has the prime factors (X+l) and (X +X+l) Figure 1ol represents a simplified version of CRG register for CRC-16 block check accumulation. Received or Transmitted Character Bits to be included in BCC accumulation - -0 1 2 J 4 5 6 7 8 9 10 11 12 13 14 15 Feedback Data Figure 1.1. CRC-16 BCC Generation

-8When operating in the 6- or 12-bit word mode the CRG utilizes the generator polynomial 12 11 3 2 X + X + X + X + X1 o This polynomial has the prime factors (X+1) and (X ll+X +1) and enjoys burst error detecting properties similar to the first polynomial for shorter length bursts. It will detect any burst-error length of 12 or less, and detect more than 99,995% of all bursts of greater length. Figure 1.2 illustrates the operation of the CRG register for CRC-12 block check accumulation. Received or Transmitted Character Bits to be included in BCC accumulation o 0 1 2 3 4 5 6 7 8 9 10 11 Feedback Figure 1.2. CRC-12 BCC Generationo Table 1 summarizes the PDP-8 IOT assignments for this device. Only the residue register can be both read and written; the character buffer is written onlyo Note that the write into the residue register is a ones transfer or "inclusive-or," thus the register normally would be cleared before writing, however, circumstances may well dictate a need for ORing. The RD,

_9_CLRand WR modifiers are assigned to the sequence of IOP pulses so that micro-operations are performed in the order listed. TABLE I PROGRAM MNEMONICS AND FUNCTIONS IOP PULSE FUNCTION DVC ADR MNEMONIC 1 2 4 Access to low-order part of block check 54 BCL RD CLR WR (residue) register Access to high-order part of block check 55 BCH RD CLR WR register Load character buf- 56 LCM6 * fer, and set mode LCM8 * LCM12 * * * Compute Cyclic 57 CCC * checksum Note that the character buffer is loaded in a pseudo-serial fashion with a few more bits of a character (assuming a character size greater than six) on each successive IOP pulse.

IV. PROGRAMMING AND CONTROL CONSIDERATIONS The CRG is controlled by the resident PDP-8 supervisor via four sets of IOT instructions. These were summarized in Table 1 in the previous section. Since the device will be used in a multiprogramming environment, the hardware design was tailored in a direction that allowed rapid execution of code, in order that results could be rapidly obtained and the CRG and DSR program freed for other users. For this reason the register load instructions result in the PDP-8 AC being cleared so that another word may be fetched as rapidly as possible, without necessitating a prior clear of the AC. Similarly, the CRG automatically "stops" the PDP-8 in the PAUSE state while the new checksum is being generated. As soon as results are available, the PDP-8 is allowed to execute the next instruction, which would normally be a READ of the residue register to obtain the new checksum just generated. This technique allows the results to be obtained in the shortest possible time, without the need for NOP's or JMP *-1 loops, to timeout the computation period required. The first thing required of the program, by the CRG, is information about the subsequent mode of operation, that is, what check polynomial should be used and what gating paths should be set up for transfers into and out of the residue register. The programmer must therefore load the character buffer with the incoming character, since this act sets the CRG mode flip-flop, and determines all following actions -10

-11until another character of a different mode is loaded. The character load and mode set instruction has been designated "LCM" for Load Character and set Mode. It is modified by one of three digit suffixs, namely 6, 8, or 12 as a reminder of the character size. These three modifiers are assigned IOT pulses 1, 3, and 7 respectively, since each succeeding pulse loads the character buffer in an incremental pseudo-serial fashion. After the character buffer has been loaded, the programmer is free to load the residue register in any order conv:enient. Gating to and from this register is automatically routed from the appropriate bits in the AC depending on the mode setting. Note that all information is assumed to be rightjustified in the AC on input, and is placed thusly on output. As the 8-bit character-oriented checking polynomial is of degree 16, a 16-bit residue register is required to compute the checksum. The two bytes of this register are addressed via the BCL for Block Check Low instruction, which fetches the right-most, or low-order, 8 bits of the register, and by the BCH, for Block Check High instruction, which handles the 8 high-order, or left-most, bits. Since the 6- and 12-bit character sizes utilize a checking polynomial which is 12 bits wide, a whole PDP-8 word is used to contain the results. Further) since the input to the residue register is on the high-order side, this register may be read and written via a single transfer between the host processor, using the high-order gating instruction BCH. After all registers have been loaded,

-12execution of a new checksum is started by the CCC instruction, which is a mnemonic for Compute Cyclic Check. As mentioned previously, this instruction also halts the PDP-8 until the new checksum is available. The instruction following the CCC would normally be a read to obtain the new contents of the residue register. Figure 2 demonstrates some sample programming sequences which compute a checksum under either mode of operation. The programs are intended to be imbedded in a multiprogramming environment, thus the previous residue contents are assumed to be pointed to by the two indirect vectors which would be set up prior to entering these sections of code. By convention, the residue is always reset to an all-zero value before computing a check over a new message. V. DETAILED LOGIC DISCUSSIONS IOP Decoding and Device Selection Figure 3 illustrates the IOT and device address decoding for the RCGo Since there are four device addresses required to control all registers and to start checksum execution, this field of four is decoded as a group by the 4-input gate at module position A08. Its output is labeled BLK+ and signifies selection of one of the four subdevices within the block. The block select signal is inverted and used to enable the three IOP gates used for selection and buffering of the IOP pulses. In most instances a device ANDs one of the

-13ASSEMBLER DEFINITIONS RD OPD 1 CLR OPD 2 WR OPD 4 BCL OPD 6540 BCH OPD 6550 LCM6 OPD 6561 LCM8 OPD 6563 LCM12 OPD 6567 CCC OPD 6571 * 8-BIT MODE OF OPERATION * ASSUME UCBPTH POINTS TO HIGH-ORDER 8 BITS OF CHECKSUM, AND UCBPTL POINTS TO THE LOW-ORDER BITS OF THAT SUM IN THE UCB. * TAD CHAR FETCH NEW INPUT CHARACTER LCM8 SET 8-BIT MODE AND LOAD CHAR BUF TAD* UCBPTH NOTE AC CLEARED BY LCMB INSTRUCTION BCH CLR+WR WRITE IS AN INCLUSIVE OR TAD* UCBPTL BCH INSTRUCTION ALSO CLEARS AC BCL CLR+WR THIS CLEARS AC ALSO CCC START COMPUTING NEW CHECKSUM BCH RD GUARANTEED TO BE DONE BY NOW DCA* UCBPTH NEW CHECKSUM BACK TO UCB BCL RD DCA* UCBPTL ***** ALL DONE AT THIS POINT ***** 6- OR 12-BIT MODE OF OPERATION THEY DIFFER ONLY IN THAT 6-BIT MODE IS SET BY LCM6, WHILE THE 12-BIT MODE IS SET BY LCM12. TAD CHAR LCM12 TAD* UCBPTH BCH CLR+WR NOTE BCH MUST BE USED IN THIS MODE CCC BCH RD DCA* UCBPTH ~~~* ~~***** ALL DONE ***** Figure 2. Cyclic Check Computer —Example Routines.

-14BIOP1- BIOPl+ D A F Np N BIOP1B08 Bll BIOP2- BIOP2+ H A K sN RBIOP2K S B08 Bll BIOP4- BIOP4+ L A N ]- BIoP4N U BMB03-' R Bl l BMB04+ T A A09 AACOO+ BMBO5- BACOO+ F N AACOOBMB06BMB6- R121 A07 A14 A0BMB0 CCC+ BAC01+ F AAC01+ AAC01BMB08- F O 8 Pc A08 AA 1 42 BAC02+ F A- AC02BMB07+ BBCH0 + J K K BMB08 L BC- A07 A14 A10 A09 AAC03+ RMB0 O AdL0. BAC03+ F AAC03BMBO7+ PBCL LLM M A N BCL- A07 A14 BMB08+ LB 0 A AC 14 All A10 A0 AAC04+ IO+M BAC04+ F AAC04H N CIO BMB08+ A LC+N A07 A14 ALCIO+ LCIO - N LCB10 All A08 A0 J9 S S BCH+ f~G~qS~-r~ECLR-' AO7 A14 BAC1l+ A c F AAC6-' BCL+ H D A GECLR+ AACA6+ P B1 0 F A07 A14 P.~A D ACCLR+ 2.2ps A19 AACsO7+ M - A9 BACO7+ F AAC07E F BIOPl+ SSj-~`RD E LAC0 E. EAAC 7T A2S B07 B14 BAC08+ F - AAC08BAC09+ F AAC09B14 PWRCLR 7.PCLR+ B..AA1 U —T B07 B14 A 9 BACll+ AACF N AAC11B07 B14 Figure 3. IOP Address Decode AC Buffers.

-15buffered IOP pulses with its own subdevice select to form a useful signal. Each of the block subdevices, except the character buffer (LC signal), is enabled by the select out from one of the 2-input gates located below the block select decoder on the drawing. Since the character buffer clear signal uses a PDP-8 basic timing pulse instead of an IOP pulse, provisions had to be included in this subdevice selection to insure that an IOT instruction was really being executed by the processor. Thus the LC signal goes true only if the BLOCK is selected and the subdevice is selected and an IOT instruction is being executed by the PDP-8. The IOT instruction signal is derived internally in the PDP-8 and is brought out as an extra lead on the high-order AC input cable. This is further discussed in the latter part of this section under the heading, "PDP-8 Added Circuitry." As mentioned above, the subdevice selection outputs are further ANDed with IOP pulses at the various devices themselves to form the desired gating or control functions. The PDP-8 AC clear signal is formed at the lower left-hand corner of the drawing by ANDing IOP4 with a residue register select, OR by the recovery of level LCCLR+ which is formed by a character buffer select (LC+) and IOPl+. This level transitions from -3 volts to ground 2.25 microseconds after the leading edge of IOP1 and triggers the AC clear, pulse amp. If the PDP-8 is adjusted according to manufacturer specifications,IOP4 should follow IOP1 by 2 microseconds,

-16+20 however, there may be a -40 percent variance on that figure, thus the delay is set to clear the AC after the latest expected occurrence of the leading edge of IOP4. If in doubt, this delay should be set high (longer) rather than low. The AC may even be cleared as late as the next computer cycle, as the soonest it could be manipulated would be at T1 time, if the next instruction were one of the operate group microinstructionso Note that although in the one case the AC is cleared as the residue register is being written, due to the storage time of the register DCD gate inputs there are no problems as the "rug is pulled out from under." When loading the character buffer, it is not possible to use IOP4 to clear the AC, since the buffer load command may be executed using only one, two, or all three of the IOP pulses. Thus the AC clear signal LCCLR+ is developed just after IOP4 time by the delay triggered by IOPlo The 12 buffers on the lower right-hand corner of the drawing are used to obtain both polarities of the AC output signalso Note that the input buffers are W500 emitterfollowers which have minimum loading effects upon the PDP-8 AC. These were used since there are several other DEC-provided devices across the AC lines, as well as the Data Concentrator o

-17Character Buffer The 12-bit character buffer is documented in Figure 4. The discerning observer will note that it actually contains 13 bits. The thirteenth is used as described below for a flag bit to stop shifting operations. The character buffer is loaded from the AC in a pseudo-serial fashion by the execution of one or more contiguous IOP pulses. This register is automatically cleared prior to loading by the CCLR+ line. This clear is developed by the selection of this subdevice and the occurrence of timing pulse Tlo Recall that the first IOP pulse does not arrive until 500 nanoseconds after T1 (as developed within the PDP-8), thus again there is adequate time for the register to stabilize before any operations are attempted upon it. IOP pulse 1 and the selection of this subdevice load the low-order 6 bits from the AC into the character buffer and set C05 as a shift stop flago The setting of this flag always ensures that this register contains a nonzero value. Shifting is stopped by a detection circuit (described within Figure 9) that-determines when the character buffer has gone to zero, indicating that the loaded character has been shifted out. If the buffer is being loaded with a character size greater than 6 bits, then additional IOP pulses will follow IOPl. The second IOP pulse (IOP2) causes the contents of AC bit 5 to be jammed into the previously set C05 flip-flop, and AC04 to be strobed into C04, which is still cleared at this time, At the same time C03 is now set as the

I E IJ IR IJ R IP' IL ~O IJ M t 12S Lo L coi I _, CO3 C03 C04 AACo5 LC+ L-CT + 2 C 2+ C03- L03+ CS+ O. + ~~ 2 —-S Coo- +C —+ Cl. +~-' -+ -- BIOP4+ EE AAC03- AACAA- CO4 F 2 F 126|FlA26 | 7|Fl2 LCC+ ( T VH' _ AACOO+ AACOO+ AAC08 + C0AA C1+ + IR ip E I J IR iP rE J- R P IE IJ D.C+ L C C+ L C + LcgCL+ Co6 CO7 C08 CH C 0 4+ FllA25 Fll.6 Fl26 F 1A27 lA F12 CCLR+b'I N D' IFZ N DIIC,9 U1 T T L' LC5 CT + + Figure 4. Chrt Ro gi 9-ACOr-.'LACO+ AA CO 6'+:AAC07 +AAC00+ AAC01+ AAC10+ AAC C4+ A20 A10 A10' A10 D ooL H L'T UC L ~ PA LC LG C CO C 0 88LCS+ A C 09-A LCT+ A CCLR+ BIOP1+ BIOP2- FBIOP4- K BT1- N1J LC+ Figure 4. Character Register.

-19new shift stop flag. Finally, if IOP4 occurs, it jams AC03 into C03 and strobes ACOO-AC02 into C00-C02. As in all other cases the bit immediately to the left of the most significant character bit is set as the shift stop flag. Thus flip-flop C12S is set as the flag. All of the control pulses required for this register are developed at the bottom of Figure 4. The signal LCS+ is produced by a pulse amplifier, due to the DCD gate loading of seven flip-flops. Thi.s loading exceeds the driving capability of a single inverter stage. Residue Register Control The read, write, and clear signals for the checksum register are detailed in Figure 5. Note that there are three sets of control signals developed while there is only one residue register. The various signals are required to handle the gating and control which must be present for the byte and word modes of operation. The',1" suffixed group is responsible for controlling the low-order byte of the residue register during byte mode operations, while the "3" suffixed group is responsible for the high-order byte in the same mode. The "2" suffixed group is used during 12-bit word operations on the residue register. Since the word operations overlap both bytes of the residue register, some of the operations can be made common to both modes; thus the word mode clear

BIOP1 —... BCRDl+ CA N- BCRD1B08 Aii BIOP2 — U A S BCCLR1 PBIP4+ BCWR1+ BIOP4+ L A20 BCL- M A MSIX+ F BCE+ B09 B14 BIOP1- Rei BCRD2+ ntoB09 All F: IA BIOP2- 4 F J BIOP4- A BCWR2+ BCWR2.MSIX- i BC2E+ 2WISIX- BC2E+BC2EB09 Bll BI01 R N BCRD3B10 B11 BIOP2- BCCLR3 B10 BIOP4+ BCWR3+ Sy A20 BCHMSIX+ N M L B09 Bll Figure 5. Residlle Regi sttr lCrntrol.

-21enables both the BCCLR1 and BCCLR3 lines to clear the entire register. Since the four low-order bits of the residue register are not used by word mode operations, they can be cleared with no consequence. The MSIX+ and MSIX- signals appearing at the lefthand edge of the drawing are the outputs from the mode flipflop. When MSIX- is true (-3 volts) the CRG is operating in the 6- or 12-bit (word) mode. Recall that this flip-flop is set by the execution of the LCM (Load Character and set Mode) instruction. In order to conserve on module space, the residue register was constructed from R205 flip-flops, which consist of a pair of flip-flops on a single board. Due to the pin restrictions, however, there are only enough connections to allow three DCD gates per flip-flopo Since one pair is required for the shifting operation and the remaining gate is used for byte mode loading operations, another method must be used to load the register when operating in the word mode. Thus the 12 high-order bits of the register are loaded via a direct collector set through the gates shown in Figure 60 The other set of gates shown in this drawing are used to read the contents of the 12 high-order bits of the residue -register into the AC. These two sets of gates are enabled by the appropriate set of signals derived from Figure 5. The inputs and outputs are configured for a direct transfer between the AC and residue register.

-22CC00- D AACOO- K A ACOO+ M.A CCOO+ B15 B15 cco- E AACO L F A ACO01+ A A cc01+ B15.B1 D i CC02 — AAC02- F A AC02+ AAC- A CC02+ B16 B16 CC03- AAC0- CC0 F A i AC03+ AAC — M ACC03+ B16 B16 CC04- AAC04- - T A AC04+ M A CC04+ AlS MB1 CCOS- AACOS- - CT A AC05+ AAC A CCOS+ A15 B17 R R CC06- AAC06+ CCll- A A06+ AAC- T A CCO6+ U U A16 B15 CC07- AAC07T A AC0O7+ T A CC07+ V V A16 B15 CC08- R AAC08- R T A AC08+ T A CC08+ U U A17 B16 SF 6 CC09- AACO09 — ST A AC09+ V'CCO A17 B16 R R cCio- AAC10T A AC1O+ A1- T Al CC10+.U U Al18 B17 CC11S- AAC 11-. -T A AC11+ T CC..I+ BCRD2- VBCWR2- A18 B17 Figure 6. Residue Register IN/OUT Gating

-23Residue Register Mod 2 Adders The seven mod 2 adders required to implement the various checking polynomials are diagrammed in Figure 7. According to normal signal-naming conventions, the + or - sign following a circuit name indicates the respective voltage level which will be present when the associated lead is "true" or contains a logical "~I," Thus FBTP1- is at a negative (-3 volt) level when a logical 1 has been inputted through one of the 2-input gates. The adder in the upper left corner (CC02** outputs) is shared by both the CRC-12 and CRC-16 block check computation, and resides between the second and third stages of the residue register. The two 2-input NAND gates (FBTP1* outputs) provide the required gating into this adder. The MSIX signals, derived from the mode flip-flop, enable the appropriate gate with a negative level. When the generator is operating in the word (6/12-bit) mode, the MSIX- signal is at -3 volts. Since an enable signal, NANDed with a positive logic level from CRC12 or CRC15, produces a negative output (FBTP1-) for a "1" input, the other input to the adder, CC01-, is taken with a negative assertion level from the previous stage of the residue register. This results in a "1" on either adder input being represented by a minus level. This is done only for ease in logic understanding, since dissimilar levels on the inputs could be equally well used if the output leads from the adder were interchanged. Note that the FBTP1 signals also go to the

B 19 L CC01- N CC14+ V LB8 CC02S+ UI CC 15S+ B18 M A CRC15L B 2 8 2 B2 B 18 B19 S CC14-. V T V CRC12+ A N CRC15+ A MSIX.- B29 B30 B18 ~FBTPlB18 ~~~BT~ i CRC15+ U A N ~; FBTP1+MSIX+ v K B19 B19 ~~~~~~~~~~~~~~B28 B 28 CC2+29 C C 0+ EB3 E CC02+ CCoo+ F F F D A D A D CCllS+ B28 CC01S+ B29 CC03S+ B30 H ~~~~H K J1B281 K K 1B301 JA J ~~~~~~~~~~~A J A J All A29 2 B30 2 8 All ~~~~~CC03R+ CC01R+ N N NL A A M NLMA Iwp AN -- CRC12R A MSIX- FBTAP2 B28 B19 A30 D CC 11 - F CC15- F ~ EA J-.CRC12+ D CRC15+ Bl A30 -'F J15 B181 H E_____ F J, 1 K lJ1A301 B18 A30 A30 A30 H KT - N J At N CRC12- ~A N'CCRC15Cll-.... __1 V Figure 7. MOD 2 Adders.

-25first stage of the residue register. The bottom two adders on the figure have similar input conventions, while the middle three are just the complement with positive levels (ground) representing a logical "1" input. The upper right adder precedes the last stage of the residue register, and is used only when operating in the CRC-16 (byte) mode. It is a simple circuit which, although always active, does not interfere with word mode operation since the last (right-most) bits of the CRG are not used by this mode. The center three adders in Figure 7 are used only during word mode operation, and are thus disabled unless that is the current mode. Disabling is accomplished via the 2input NAND gate whose output is FBTAP2. When operating in the word mode, MSIX- is at a negative level and the gate feeds the output from the CRC-12 input adder through to the interstage adders on the FBTAP2 bus, with a logical "1" represented by a positive level. When the gate is disabled, FBTAP2 is held at a negative level (which corresponds to a logical "0" condition). Since an exclusive-or on two variables, where one is identically zero, results in an output which is equivalent to the other input variable, the interstage adders act as direct connections between stages when FBTAP2 is negative. This of course is what is required during byte mode operation. The bottom two adders form the summing junction for addition of the least significant bit of the residue register

-26with the incoming character bit. The results of this addition go to the appropriate feedback lines that drive the interstage adders. Residue Register Figure 8 is the actual residue register complete with shift connections and input/output gating for byte mode operation (word mode gating was documented in Figure 6). Note that the design of the register results in two essentially identical sections, each 8 bits wide. As mentioned before, the only line aside from the shift pulse that is common between the byte and word mode is the register clear, which is enabled for both prior to a word mode write~ The pulse line for this register is separated from the character buffer shift due to the driving capabilities of a pulse amplifier. A total of 29 flip-flops is a few more than can be comfortably driven. Shift Control and Mode Storage Figure 9 is the last figure for the CRG, and is composed of two sections. To the left appears the shift control circuitry which determines the number of shifts that will be produced to execute the checksum generator division. The RUN flip-flop is set by the occurrence of a CCC enable level and IOPl. When this FF is set, RUN- enables the R401 clock which then starts producing a pulse train of 100 nanosecond pulses at a 2MHz repetition rate. This clock output is buffered by

BCRD3F F F F F F F F H H J H B H J DA EBA DA C + EA DA H E DA E+ A ACO4+ ACO5+ ACO6 AC7+ 08+ AC09+ ACC A15 1A1l5 1A16 1A16. 1A17 1A17 1A18 1A18 E J R P R P E IJ R P E R pP E BCCLR3; F| CCO4 CCOS F CCO6' CCO7 B+C 2C — 1N 1E210 D 1 —B21 -- N 1B21+ D B;212- N 1lB22B2 —3 N 1lB2'3 SHIFT2 L K: U T 1 L K I I L K I U T -L UK U T F BTBlF BTp +CCO1R+CCO01$CC C03-2CC03 CC04-CC4CC -CC Cc6-CC06+ BCWR3+ tH Pts H Ps fH PS H S AAC04+ AAC05+ AAC06+ AAC07+ AAC08+ AAC09+ AAC10+ AAC1+ BCRD1MI, IM,,'M M T T T T, SHIFT2 | BCWR1+ _ _ K A. LA KA LsA R A s A sA AAC04+ AAC05+ AC06+ AAC07+ AAC08+ AAC09+ AAC10+ AAC11+ BCCLR1 L rK!U IT'L lK I'U T I IL'K U - L.K CC07-CC04+ +C08-CC08+ 0cd C 9+ CC101+'ACC11 ACC12-CC12+CC13 ACC1

All A12 E ND HOLD+, CLK D CLK RUN_- R401 r T | Al9 MSIX+ MSIXJ H B1 3 T s IT PA SHiFT2 RUN + f - RU PCLR+ I A13 K R 2'2 A1 A 19 R202 A13_D'M09 B14 F$,NtSV LC+ IOP4-C+ C02+ C03+ A -BC04+ C05+ C06+ C08+ C09+ B12 Figure 9. Run and Mode Control.

-29two pulse amplifiers which produce SHIFT1 going to the character buffer, and SHIFT2 which is routed to the residue registero As mentioned above, this is required due to the DCD gate loading on the shift lineo The total loading on that line exceeds the driving capability of one pulse amp. At each clock pulse the RUN flip-flop is strobed in order to stop the clock if the shifting operation is finished. The flip-flop will be reset though, only if the 11-input AND gate sampling C12S through C09 finds that those bits are all zero, Since a shift stop flag was set when the character buffer was loaded, we are guaranteed to have a non-zero value in that register until the loaded character is shifted far enough. Also since zeros are shifted into the left end of the register, we know that it must eventually assume a zero value. Note that the last (let us say n-th) shift required of this register results in the most significant bit of the character being transferred from the low-order position of the character buffer to the high-order position of the residue register. When this is done the shift stop flag will then be resident in the least significant bit (Cll) of the character buffer. Just prior to this (n-th) shift, the stop bit was in C10, and just prior to the n-l shift, it was in position C09. Thus, before the n-1 shift, C12S through C08 are equal to zero and C09 contains a one, On the n-l shift the flag bit moves to position C10 and leaves C12S to C09 all set to zero. This results in STOP+ going to ground, which enables the DCD gate on the reset

-30side of RUN FF. The next CLK pulse then resets RUN and the shifting process is halted. Note that the entire time that RUN was set the buffered output from RUN- holds the HOLD line to ground. This signal returns to the PDP-8 where it maintains the CPU in the PAUSE state until HOLD returns to -3 volts. The MSIX flip-flop is set by the same instruction that loads the character buffer, and serves as a 1-bit memory element to control the residue register I/O gating and feedback tapso Recall that IOP1 loads a 6-bit character while IOP1 and 2 load an 8-bit character, and IOP 1, 2, and 4 are required for a 12-bit character. The last IOP produced for an 8-bit character load is thus IOP2, which clears the MSIX flip-flop. If the character loaded is 6 or 12 bits in width, then IOP1 or 4 is the last produced and MSIX is set. PDP-8 Added Circuitry The circuit diagrammed in Figure 10 has been added to the PDP-8 processor used with the Data Concentrator and fulfills several functionso First it allows external devices to request a "long" (would you believe infinite) I/O cycle. The IO RESTART pulse is normally produced within the PDP-8 at the same time that the IOP4 pulse amplifier is strobed. This results in a T2 pulse being produced at the next CLK pulse and normal instruction execution is then resumed. The additional circuitry prevents the IO RESTART pulse amp from being enabled, however, if the HOLD line is at a ground level.

-31IOT- N BIOT (from PD31R) S R PF02V PD31 CLK+ Tf~~~~~~ ~ CF~ K- IO RESTART OLDT~~[~ N —-] ~ [ ~~PA29 HOI A Note: Clamped Load Provided T AN RA PF16 PF16 S T S T R11 Added at PF116 Figure 10. Additions to PDP-8 CPU. R203 at PE32. Used spare 1/3 of Module See also: I/O CONTROL DEC DRAWING D-8P-0-10J Figur-e I0. Additions to PDP-8 CPU.

-32To accomplish this, a R113 module was added at position PF16 and a left-over 1/3 of a R203 flip-flop at position PE32 was used. The HOLD line is inverted and the two signals are then run to two 2-input NAND gates which when strobed by CLKperform a jam-transfer of the contents of the HOLD line into the EX SYNC flip-flop. HOLD is thus sampled every 750 nanoseconds by the CLK line. If the HOLD line had been down when RESTART SYNC was set then EX SYNC- would be at ground and an IO RESTART pulse would not occur. The next clock pulse, after HOLD is released, sets EX SYNC and enables the DCD gate of the IO RESTART pulse amp since the RESTART SYNC FF is also set. The next clock pulse after that produces an IO RESTART and the processor is off and running again. The second circuit documented provides an external device with a positive signal that the processor is currently executing an IOT instruction. The IOT- signal is derived from an inverter which is driven directly from the output of the Instruction Register decoder in the PDP-8. This negative level is then buffered and inverted to form a positive assertion level signal called BIOT, which may be sensed by an external device to determine when the processor is actually executing an IOT instruction. This permits the use of the processor basic timing signals T1 and T2 which appear at the I/O interface but which normally may not be used with programmed data transfers due to the impossibility of determining whether

-33the contents of the Memory Buffer (from which device address decoding is obtained) contains a legal IOT instruction, or is actually a data word, or an external memory access operation (Data Break). The inverter shown on the diagram was acquired from an unused 1/7 of a R107 module at location PD31 in the PDP-8 mainframe.

APPENDIX A UTILIZATION MODULE LIST AND CIRCUIT NAME MAP

APPENDIX A UTILIZATION MODULE LIST AND CIRCUIT NAME MAP Wire-wrap output documentation is reproduced on the following pages. First is a circuit map of the DEC 1943 mounting panel upon which the checksum adapter has been built. Note that all module outputs are denoted by an asterisk on the drawingo The module types are noted at the top of each module position. Finally actual wire-wrap instructions are reproduced as an aid to device reproduction. The concatenated circuit list documents all pin connections for each circuit name. The connections are serially listed for each circuit in the order that they are wrapped. The output lists represent the order that each wire is actually wrapped on a bay. The shortest wires are put on first, followed by increasingly longer wires until the longest is finally placed. The five columns of the output list represent, in order: 1o The circuit name 2. The wrapping level, where 1 is the lowest (against the panel), and 2 the highest (a second-level wrap is placed above a one-level wrap on a pin)~ 3. The pin-to-pin length of the wire in quarters of an inch. If, however, a wire run is straight down a horizontal row of pins, then it may be connected via a solder-on bus strip rather than a series of wire-wraps. In this case the wire run is identified by BUS, and the run includes many rather than just two points. A-1

A- 2 4. The first pin location of the wire run. 5. The last pin location of the wire run.

A-4 8***.* CYCLIC CHECKSM C OEMPUT-ER ***' CONCATCNATEL C iRCUIT LISTS AACO0+ iA07E,14A__4E _1A _ AACGO- 1Ai4G, 1t15K.AAC 1+.. i A 7-,. i 1A4 A........................ AACO1- iAi4F, 1t15L AACO2+ IA. A7K, 1A.4 K,_1A24S _ AAC02- 1414J, IB16K AACO03+ 1.A07Mt JA i 4_AM, 1A2 IT AAC03- 1A21Ft lAl4L, 1B6bL AAC04+ IAJ7P,14AlPlb2OH, 124'H,iA25h_ AAC04- iA14N,1BI7K AAC_5_+ I. L.Z2 S.. I t.24_ _S I_.A2.._2_T_____14 S A O 7 _ AACO5- 1A22F, 1AiR, 1617L AAC06+ iA25S, i'25H, 12 1H,1A14U tl.AO7U AAC06- 1A4A T vi 1 5R AAC07+... 1.07 t, mibC, i2 1S, 182655.1A42h AACO7- 1Bi 4c, i. b AACO8+ iAc2ti i-,36 H, 1td22H ii1__4H _1B0 7 FAAC08- ii14Fti d1 k AACO9+ _l'_)7_i_.-i B i4 18 2 S,182t S, 1A27F AAC09- l8i1j, 11tcS AAC10+. 1A 2 7 S,id 1t7- 2 3H i _ 1 1.4M, 7 AAC1O- 1B14L, 17R A AC l I+.....B _! _...27S.,. A ZN H.... ACl1- 1 i3 14Nt 1i 7 5 ACOO+ 1A() c, iAC,6G 115Hi ACO1+ 1A05El iAO E,? i 15J AC02+ 1A05 h AO Ci t 1B i6 ___ ACO3+ 1AO iAC6Kt t1t J AC04+ i AO 5M, t 1 A C 6 M t.A 1 5h t i A 1 N. i A.1.. AC05+ 1AO P, 1ACtP A.1fP i A 1 J 1A15V AC06+ 1AiO5S,1AObS,1AiHiHiA1tN1Ai6tU AC07+ 1AO 5T, IA06T TiaPA16JiA16J iA16L... A.C. 08+.,, lA 0 c\ V i A 7i,1iA i. 7 N,i A1... ALO9+ 1 iH3, 16 U, 1A i7P, 1A1 7 J,iA1 7 AC1O+ i0 5E, BO6t E,iA 1 H IAe \N, iAll I ACIl+ 1idOH, 1oGO6H,1A18P P,1Ai8JiA1EV AC C+ I__ ~I__A.l J. ri B I Q _ ACCLR+ L:O5 P, i(Oc'P, 1AidF 3.ACOO+ A........._.A. C... BACO1+ 1AOiE, iAO2 1A07F.... ACO2 +_..A.i H,.i A.QOZ.k. Q....... BACO3+ iA01lAOi, AOZK, iAO7L 8ACQ'.._1.1'., LA_ 1 A 0 7 N BAC05+ iAOP,1P, 1A0L' 1AO7R 8 AC0.6+_ iA........___._.._ _ _OS_..,i:A 7_ BACO7+ 1Ai 1T, 1i02T1B07D............ B A_ C._ 8 _+....IA=Qi _ V__t -._ _V_-_.,_ 1 B0? F BAC09+ BOL, 1, 020, 11B007j BAClO9+ L3O IEs 0I 8O2E.,h i07L BAC11+ I1BO1lt iBO2H, 1i307N -.... +... __.: ___.....BO__.. ___..__!4 __,iA_ _..._... BCI1E- 1814R,18BO8tR,'iO8U......... 8:CE+ _.E_1......i........._'. i.Ki...................

A-S **** CYCLIC CHECKSLM COMPUTtL ****t bC3E+ 1 2CI S16,llM,1t09N BC3E- 1..B.i.Lt..... Q._...I__ ___ _____.___ UBCCLR t:e27F, 1 826F 25, 1t2M I1824F t,1171 t 18OiV BCCLR2 1A20P,IA20V 18O9V BCCL3 B 3 F, i B 22F, 1 2 F 1820 F 1817J B 1 CV BC H+_ _ AO 8J 0 I A09, 9 _M, A. O S- __ BCh- 1AOg9L, BO9H 1 BAOSL BCL+ 1A08Ki A09PiAlOV...... BCL- 1AOSN, 1809 BCRD1+ IAI1S 1BCbS B.CRD1- iA18E, 1A17Mi IA16M,1A15M,1Alll BCRD2+ -1Ai1U, 189S __ BCRD2- iA i T T A JT, A17 T,1A A16T,l 51',1 15F,1816F, 1AilT BCRD3+ 1l11,110S............ 1 l _ _. BCRD3- IA18F, A 17f,, A16F,11A1-F t,1811F BCWRI+ 1/A20Mt 1a27M,1 i626M,1 tI25 2 B245M, B 12 V B 125V,182V, 1827V BCWR2+ 181 E, t 0llN BCR2-........... l87T,1 lT, blST,11._Mil t,1i77Mt lB11D BCWR3+ IA20T,162.3M, 1622M, iB2 1M, 1B2O B OV, IB21 V, 1822V, 123V _BIOP1+_.i.2'E,1A2C6G, A13K, 1BOeFli3llP _ _ _ _ _._ BIOPl- iA"SE, 1C808p,1OSP,9 i81CP,1B11N BIOP2+ IA13N, BlO OK, iB1S. BIOP2- lAlOE,1817, lB17E,liBllR,ilCTI,ld09T,808T BIOP4+ 1..11!U,_10BN, A2OK, A20t,1A23t _ B IOP4- 1 AA' H, 1AlOJi 10E, 1B 8 1CL, i 1Bl.10T+ 1 5V.........._.,...06_V. 1A 1 1H IOT- LAl1F, 1810F, BLK+ 1AO 8 R), 1 A09 S BLK- 1AOSR, 1BiOJ, IB08b, iBOH 1BOSEL BMBOQ 1A0+ _D 1A0 4_____ _0_ __....._. BMBO1+ 1AO3 E,IAO4 BMBO02+ A_ 1_03H H AC4F _ _8M803+ 1A03M, 1A04 M M8B03- iA03K, 1 A04KlA08S BMB04+ 1 A03S 1A04S, 1A08T BMBO4- 1. 03p P A41A0P _ _ __-._..__ BM805+ 1.AJ3V.i A4V 8M_ 05- 1_ A0_ 3T lA 4T tlAO _ _ _ _S_ _u BMB06+ 1t803E3, iO4E BMB06- 180 3 18C40 lAO8 BMB07+ iACP, lAlOT, 804K, 1803K BB_7- 1$03 _ __ L 14-_1A_8M -— _A08E_ BMB08+ 1803P, 1804P, A1OUiAO6N......_6M B O 8- _.I. t3.._3.M 1. Q4_ _A._ _ R___AO F ___ __ _ __ __ BM809+ 1BO3S, 1O84S BM81O+ 1B03T,1804 T BMBI1+ l803V, 1804V.3.....8RU5N- 1 18065__S i 06 BT1- IBO1S, 102S,IAlO1M ~Z_ A _....BQE __0T_ 11__ ___ T__ _L COO+ 1A24K, 1A2.3R 18120 COO- A24L, I 23PA _ 3. COl+ IB1-E', A24E, 1A24T COL-_ 13t_. l4i IA __ _______ ____ _ __ __ C02+ 112ht 1A21R, 1A24R _C _ _ _0_2............_ _ _ _ __.___ _ 2 _ _ C03+ 1 A2K, 1A2iM, 1T1 2J

A-6 _** * YCLIC_ _ICKS LM COMPUiEf **** C03- 1A21L, 1Ai5L C....044+. A. 1A2E A2.2,__lB.12L C04- lA22J,1A25J C05+ _ L 12 M,1t 1A22M 1_A2 5 1 C05- IA22L,1A25U C06+ 1 A2K,1A25R, idl2P C06- 1A2eL,1A25P C07+ 1A26E, IA2..,_ 6132R C07- IA2tJ, A2'oU C08+. 1A2__ K 1___. I B12T C08- 1A27L, lAAcP C09+ 1A27E, iA27 T, 11812U C09- 1A27J,IA27U ClO+ iA2EK, A27k ClO- 1A2EL,IA27P Cll+ iA2E __ Cll- 1A3CJt 1AO M,. 1iA28J,i181EElBeIJ C12S+ iA3 A3, i3f1 4..... C12S- lA2'3J, i AzU CCOO+ il.5Nh,, lo2JE, 1B28E,12EH CCO0- iA15g,.ibSu,l1620J CCO1- IA1B5Ei dlE, 1,BL, 1L CF CCO1R+ IA1lL, 1B20U CQo1S+ 1 i i 31M, B T, iB28F, 1 26N CC02+ I itN, i1 64, i2 29t, 122 S.H CC02- iAlc, iBl6U, iB21J CC02R+ I__ I 2 L.1 l61S_ _ CCOZS+ 12 I1K,1 19N, b19PlP, B1 8 S CC03+ 1822K, 1B21R, 1116P CCO3- 1B2lL, 1821P, ib6E, A16E CC03R+ 1E2lS, 1821U CC03S+ 1b29F, ia9N, 1829P,1821. T _C_04 + t_ B i7 t_22E, 2 112 2 T CC04- lA17O, iAi5kR, B2J,1 8JB22 CC05+ 162.K, 1822R, 117P CC05- 1A17E, 1A15S, 1B23L, 1B22P CC06+ 115tU,1 823E, 182 3T CC06- 1A8D, IA16R,1 i23J, 1823U._... C. _7_........_.....B_. Kt_,_d_23.i_.r 81 5 V CC07- A i8E, 1A16S, 1b24L, 123P.......CC.0..+_................ I 16U, 1 0 2 _' E._.!._.B._24___! _............ CCO8- 1Al5K, 1 Ai 7, id2. 2,1824U... CCO9..+... 1e. 25K, l.4R., 1'6..6YV._.... CC09- I P15L, 1A17S, 125L, I24P CClO+ 1B7l 18 i5tk 1 t 3 0E, 3CH_ CClO- 1A.16K, I 18bR, 1825J _CC 1I+ 1 8i7 _ _ _ _ __2 CC11- AiL, 1AISS, Ibi8UOt,11S0,lt5f;,IB26L..... C _C 11.K+............_....53_C: S_,_. B__ -_ CCllS+.183CF, 13CN,l b3OP, 1b251 CC12+ 1821E,~ t1 826T _ C 1, +_.._._B 2 7 _K. 1,.. z_..'. 6...._.._...... _._........ CC13- 1A7L, 1527L, 1 82 2P CC14- 1At8K, 1B7zJ, 1B291

***** CYCLIC CHECKSUM CFMFLTER **** _ _ CC15+ 1827R.CC15-.A3c, A30H?P AIL.........L CC15R+ 1827U, 130V CC15S+ 1627T, b28V,!b2V9,li30T _ _ CCC+ 1AeC, 1AA13L CCLR+ A..... ON,A21K, lA2KlA iF,IIAi24f, lA5F, lA26F, IA27F,1 Pi8F CLK 113U0, iAI3,IA 1A 19P, A19V CRC12+......... iA3CTI, 19.F.,1B ll8K,118ET CRC12- 1A3CV, 128P CRC15+ 1A30 t,lA3CN, 1A30P, l20 L, I 1'T I CT__ CRC15- 1A3CS, i828U FETAP2 182S,18j29M,lB28M,I 182 O, ~2,, l d CJ,lB30M FETPI+ 1iiSK, 18ZOK FBTP1-.18B20L, ldlH,._3l sM, I3 1it, 118 V, 181V GIA191 IAlSC,1A19E G1A22 1A22V,1A21V, IA21C, 1A2 2C G1A23 IA23C,iA23L GECLR- iA08H, iBlOLC GND!AO- F 5FF, 1 F, lA04F, lAO3FrlAOf A'iF Jf,A0JAO, 1 03J, lAO4J, lA5J,1A J, AO6L,1ACL, 1AO4L A3L, 1A2L, lAO1L, 1AOl LAO2i.,A)3N, 1A04NA 1A O5N, 1A N, AO6R, AO 5N, iAC4R, IA03 A 1AA02U lA03l 1A4 1R, 1 AU, 1AAO 2U,1AO, 11A6U, 1 05F, 1O3 5J 1805L, 1B05N, 1BOOk, 1604N, iBC4L,,eC4J, 1O4F, 1fBC3F, 1F 03J, 1803L, 1BC3N, iB03R, 1d02N,1 B02L, IEC2J, 1802F,1801F, 1801J, 1801L B01 N, 1BOR, 1602R, 1O2U,l01,l, C3L, iBJO4U, 1C4, 1B05U,1B06U,180bR, 18306N, 1806L1B:06J,6 ___,_ 0OF HCLD+ 1O5T1,0iiBT, 1A DIC A12D INTRE. ieOQM,1 06M > IOPI- 1801K, 1B02K,1808E 10P2-.._. EOM,_2M.M., 1 08J IOP4- l'01F, 1B02P, lBO0M JiA291 1A iA2i9K __ _ __ _ JlA301 iA3CD lA30K,1A 30L J1813..11., I.T.J13U J1814 itlF, 1612K, 1 l 12Nt, ll2S,1812B L1814V J1B181.....l.SE,lBlEF, i818H J18182 IBiM, lbi8N,1B18P __J B12Z81__ 1 828L _ IB 28_L__ _ ___ __ J 18291 182SD, i629K, 1B29L J 1830.1....... 1. 30, 1B 3 OK,.3L 3L LC+ 1A299F,1A23H,IA20E,1A13V,IA3IF,1AC9K,lA0 8L LCCLR+ 1A.lS, 1A29. M LCE+ 1A25M, 1A22E, 1A22', lA21U,1AICF L... ICIO+ lAl it K _ _ __ ___ __ LCIO- 1A11J,1AOBP LC- _. A0iC,iA OH,!AO9J1jAOL LCS+ 1A20F,iA22, lA27V,1A26V,1A25,1lA26MlA27M,iA28M LCT+ A1 0K, 1A21S, iA21E.lAZ 414, 4 1 A23 t i A24V MSIX+ le19U,lA13S, IB3E, ibO0 M _M.SX- e182&R ___lIULA 13T, 0SJ _ _ MSIXS+ 1A09C,1AO9F, A13U PCLR+ A13F, 1A.. PWRCLR 1BO1V,1802V, 1AO9U RUN+ I 1 A. ___ RUN- 1AP11i,A3J, 1B1 3S _S._HI E_1..1 1 AL1 1AZ27N, i A26N, A2,N, 1A24A 1i23N, iA2t P, 1At I, 1A2 1H, 1A22H, 1A230, IA24O, 1A250,1A 26,1 t 270 1A280 SHIFT2 iAl 9T 13270 l 260Z1 1B 2 aC) 1824 c1820 22t l B 210, 10E200 1820N lB21N 1B 22N 1823N 1824N i 25N 1B26N, 1B27N SKIP 1 EG5K, iB 06K STOP+ 1i3E, 18a14T

OUTPUT LISTS C i i.+ AA2t 1 IN G L /C CR IT ~'S1 C C N\ C f I CL \ CC 1.5+ iBi7R S INLLL 1/U CK T tST LCCLINNECI'1\N RUN+ i/Al. j- SIN'uLE i/U OL TE'I CC N -TCIiCN

A-9 ***** CYCLIC CHELKSUM COMPuTER **_*** BAY 1 TO BAY 1, LEVEL 1 SHIFT1 1 bUS lA 230 IA 280 GND 1 BUS 1A 01F iA O0F 8CR"g_3- I B.US IA l15F 1A 18F CCLR+ I BUS 1A 23F 1A 26F GND,,...1.BUS,lA 0lJ 1A 06J__ GNU 1 BUS IA OIL 1A OLS BCRDi- I BUS 1A 15P1 1A 18M GNU 1 BUS IA 01N IA 06N SHIFT1 1 BUS iA 23N L. A27N GND 1 BUS iA 01 1kA 06C BCRD2- 1 BUS iA 51 T 1A 1_bT_ GND 1 BUS IA 01U 1A 06U SH.IFT2 1 BUS 18 20'3 i8 27C BCCLK3 1 BUS ItB 20F i8 23F BCCLR1 1 BUS,1_ 24F 18 27F BCWR3+ I BUS 1l 20I iS 23M dCWkI+ 1 bUS 1i 24M _ 16e 27M. SHIFT2 i bUS iB 20N 18 27N 8CWR3+ 1 BUS lB 20'V iB 2.3 BCWRI+ 1 BUS 18 24~ 18 27V "G1A191 1 001 IA 190 iA 19E MSIXS+ i 001 iA 09 LA 09F CC15- i.. 031 1A 3CE 1A 30H GND 1 001 1A 01f lA 01J GND 1 001 iA O6J iA 06L J1A291 i O01 1A4 29J A 29K GN........ Oi A 01L_ 1 _ 011\__ GND I 00i 1 IA OcN 1A O0R BLK+ I O0ji IA 08H iA 09S__ J18381 1 031 18 iSE iE 18F CCOO+ 1 001 IiB 28E i8 28H CCiO2+ 1 001 ib 29E 18 29H..CG 0.+ 1 001 iB 3CE 18 30H _ GND i 001 1 03 03F 08 03J GNU 00 i LB 04F 16 040 GND 1 001 It 010 B8' i1L GND 1 001 16 02 J 18 02L GNU 1 001 1i 05J lB 05L.... GNO_ _._001.__ l _060 18 06L_ GNU I 001 iB 03L 18 031 JlB182 1 001 1'6 19f 18 18N GND 1 001 lBI 011 i8 OIR GND i 00i lB 05N lB 05R.... __N_ lB.......... 1..................__........ _ _6., 1... 06_i. J1813 1 001 l 31 1 l8 13L..GiA2.2 00 __ 1 A 21C _ IA 22C BACO0+ i 002 IA 01 1 020 BMBO, 002 1A 03G 1A 040 ACO0+ 1 002 1A 05L 1'06...... 1Q. __..... _............_1 _...........O_ 14 lo A — 1 G HHO-D+ 1'32 1A 1i1 1A 120.... Cf 1._+..........Q..2..__. 1 A..... 0_.......... E _ A9. JZi &.._._ BMBOi1+ i 002 i1 03E 1A 04E

A- 10 ***r*8 CYCLIC.CHECKSLM COMPUTER ***** AC01+ 1 002 LA 05E - 1A 0eE 8AC02+ 1 002 1A 01H 1A 02H 8MB02'+ 1 002 IA 03H Ii 04I ACO2+.1 002 1A 05H LA 06H BCH+ 1 002 1A 08J iA 09M LC- 1 002 1A 09J _~A lOL Cl1- 1 002 1A.3CJ 1A 30M BAC03+ 1 002 1A 01K 1A 02K1 BMB03- 1 002 iA 03K 1A 04K AC03+ 1 002 LA 05K 1A 06K BAC04+ 1 002 1A 01M 1A 02M BMB803+ 1 002 IA 03M 1A 04 1 AC04+ 1 002 1A 051O 1A 061 LCS+ 1 002 1A 27M IA 28M BACO5+ 1 002 IA O1P 1P 02P BMB04- I 002 1A 03P 1A 04P ACO5+ 1 002 IA 05P LA 06P MB 07+ 1 00 _ 1A lOP 1A 10T GNU 1 00L 1A OiR 1A O1U eAC06+ 1 302 _A 01S IA 025 BMB04+ i 0o2 1A 03S 1A 04S AC06+ 1 002 1A 05S 1A 06S LCE+ 1 002 IA 22S iA 21L BAC07+ 1 002 1A CIT IA 02T BM805- 1 002 iA 031 1A 041 AC07+ 1 002 iA 05T 1A 061 BAC08+ 1 032 iA 01V 1A 02V 8MB05+ 1 002 1A 03V 1A 04V AC08+ 1 002 1A 05V 1A 06 G1A22 _ 1 002 A 21V 1A 22V LCT+ i 002 LA 23B LA 24V LCS+ 1 002. 1A_2. 1A 27 V BAC09+ 1 032 1B OlL LB 02C BMB06- 1 002 LB C3G 1 040 ACO9+ 1 002 LB 050 1B 06C BLK- 1 002 B- 081 1. 081CCi1- 1 002 1B 18g 1B 190 BAC.IO+ 1 002 L 01 E i_ 0 2E 8MB06+ 1 002 16 03E 1B 04E ACO1+ 1 002 1b OSE 18 06E GND i 002 iB Olf 1B 02F.JB4 1 002 LB 12F 18 12K BAC11+ i 002 lB OLH 18 02H __M30-_7_- _.0..........0.02 1B 03h 8_ 04H AC11+ 1 002 IB 05h L B 06H FBTAP2 1 002 iB 28J le 28M FBTAP2 1 002 lB 29J 18 3.0J o_IP 1-.1 002 Q2. _ iB 0iK IB 02K 8MB07+ 1 002 lB 03K IB 04K S__K P __ 1L 02 LB 05K O 06K FBTPI+ 1 002 lB 19K lB 20K CCO1- 1 002 1B 18L LB 19L 10P2- 1 002 lB 0tM iB 02M1 _MB.QS- i OQ02 lB 0314 18 04ML INTREQ 1 002 lb 05M b18 061M 8C._ 1 002. B 10M.LB s09s BCWR2- 1 002 1l 16M lB 1714

A-11 ***** CYCLIC CHECKSLM COMPUTE, 4**** FBTP1- 1 002 lB 18M.18 i8R.GNO1 _. A.1._..2 -_1....6..QO2_ _...._ _..i_0.. J1814 1 002 16 121 18 12S IOP4- 1 002 16 01P lB 02P BM808+ 1 002 1i 03P 18 04P ACCLR.. 1 002 _0-8 1O-._P0_5. P_......1'._O06. P BIOPI- 1 002 18 09P 1i lOP CC02S+ 1 002 18 1 9P 1_8_ 18__ _S_ GND 1 002 1B 02R 18 02L GND 1 002 10 04R 18 04U BT1- 1 0.2 1B 01S 1B 025 BMBO9+ 1 002 18 03S 18 04S'BRUN- i 002 1 05S 05 ie o 8T2A- i 002....T 18..0 02 BMB10+ 1 002 18 63T 18 04T ItOLU+ i 002 18 05T 18 06T BIOP2- i 002 16 091.i 1OT BCWRL- i 002 1B 16T 18 171 CC15S+ i 002 i8 27T 1B 28V CC 15+ 1 002 i 30T 18 29______ GND i 032 13 05U 18 06L PWRCLR 1 002 IB OiV 1B 02V BMBll+ 1 002 16 03V 1B 04V'Bl0T+ 1 i OO l 05V 18 036 Ft'TPi- 1 002 iB 18V 18 19V SHIFT, 1 003 1A 3.2IA 22F_ JlA301 I 00 A 30 1A 30K 8MB37- 1 0 3 1A 08t IA 08M CCLi<+ 1 00'3 1A 23F iA 22K CRC15+ 1 003 1A _3F_ _lA 30t\ 810P4- 1 003 1A 091- 1A 10J AC4+ 003..... 1A 15H.. _A_ 15N AL06+ 1 003 iA 16h 1A 16Nt AC08+ 1 003 iA 17h IA 17N AC10+ I 003 1A 18eh A I8N SI_. FT 1... 003 IA 21F.P 2___ L AC05+ 1 003 1 15J 1A 15P AC.07+. 0.03 IA itJ 1A 16P AC09+ 1 003 IA 170 IA 17P AC1I+ 1 003 1A 18J iA 18P BCL+ i 003 IA 08K iA 09P.L... 8_O_P4_ __~+ 1 003 1A 20K IA 20R COO+ i 003 IA 24K IA 23R 03__-__6 —.+ —— _ —.8.~. L. Q3...Q..0 __J.0 1A 26K. 1A 25R C08+ 1 003 IA 27K 1A 26R CIO+ i 003 1A 28K IA 27R COO- 1 003 1A 24L IA 23P CD_6_- __ - 1 O3.1 A 26 L 1A 25P CO8- 1 003 1A 27L 1IA 26P _CI_-.1_ 003 i A 28L IA 27P SHIFTI 1 003 iA 23N iA 22P CLK 1 003 IA 19P I 19V 8CCLR2 1 003 1A 20P 1A 20V.J_1._28_..L...1.. 003.____ 28G. _ 28K J18291 1 003 16 29C 16 29K.~11..3.011. 0 _.................... _ __3. C......._.3_O_K MSIX+ 1 O0.3 1B 09E 1 039M

A-12 *$***' CYCLIC CHECKSLM COMPUTER ***** BO1P4- 1 003 18 10E iB 10L CCO 1S+ 1 003 18 28F 18 28N CC03S+ I 003 iB 29F 18 29N CCllS+ I 003 1B 30F 18 30N FBTPi- 1 003 1B 19H 18 20L CCO2S+_ 1 003 1i 21K 18 19 N CC03+ 1 003 18 22K 18 21R CC05+ 1 003 1B 23K 18 22R CC07+ 1 003 18 24K 18 23R CC09+ 1 O0 1B 25K 18 24R CClI+ i 003 18 26K 18 25R CC13+ 1 003_ 18 2 7K 18 26R BC3E- 1 003 18 l L 18 1OR CCO3- i 003 18 22L 18 21P CC05- 1 003 18 23L 18 22P CCO7- 1 003 1 24L i8 23P CC09- 1 003 18 25L 18 24P CC 1- 1 003 1b 26L 1e 25P 8CWR2- 1 00.3 1 15 18 151 FBTAP2 1 0303 18 29M Ie 285 G1A23 I 004 IA 23C IA 23L CCO9- 1 004 1A 15L 1A 17S CC11- i 004 1A 16L 1A 18S LCS+ 1 004 1A 2.M 1A 25V 8MB08+ 1 004 lA 081N 1 10U SH.[FT2 1 004 18 1 20N 18 20N BCWR2+ 1 004 18 11E 1B 10N BC2E+ 1 004 18 09K 18 11K CRC12+ 1 004 18 18K e18 18 8CWR3+ 1 004 1B 20I 18 20V BCWi1+ 1 004 18 24M 18 24V GNU 1 004 _18 O01 1 8_03 J1814 1 004 18 12 1B 14V RUN- I 005 iA 11E 1A 13J C02- 1 005 1A 21J 1A 24P C12S_- 1 005 IA 23 J,i 23U CO1- 1 005 iA 24j 1A 24L C07- _1 005 iA 26J iA 2.6 C09- 1 005 IA 2'7J iA 27L CC08- 1 005 IA 15K A 17?R CC13- 1 005 iA 16K IA.18R._8_CR_. 3 + ___._o005 16 lt. 18 OS AACO9- 1 005 18 140 18 16S CCO_r __..__ _ 1__ 00..O......5 bi 22_J J-L8 228 CC06- 1 005 iB 23J- 1 23U CC08- 1 005 1B 24J. B 24U CCO2R+ 1 005 18 21L 18 19S __8IP4+ _1 005 1 08N \ 18e 11T AAC11- 1 005 18 14N 18 1i7S LCT+ 1 00Q 1IA 21E.1 241: LCE+ 1 00-6 1A 22E 1A 25P C12S+ 1 006 IA 23E iA 23T CO7+ 1 006 IA 26E IA 261...._ _L _O0__9J 28 0 lA 27E 1 7 8M808O- 1 006 1A 08F iA iLOR Q4__Q __I-,_ _ A ~ 22 _ 1A 250 C05- 1 006 1A 2zL lA 258

A-13 BCRD2- 1 006 1A 15T 18 15F._ GND.....1_ 00_ A _6_.1 _._ AACO7- 1 006.1 14L 18 15S CC12+ 1 006 18. 26E 18 26T AAC08- 1 00OO B 14F i B 6R BCCLR3..1 _006 id 20F 1 B i7J AACIO- 1 006 1B 14L 13 17R CC04- 1 007 A.... 17C 1A 15R CC06- 1 007 1A 180 1A 16R CC05- 1 007 1A 17 1A 15S CC07- 1 007 iA 1dE 1A 16S C04+ 1 007 IA 25E IA 22R LCS+ 1 007 iA 2OF iA 22-t LCIO- 1 007 IA 1IJ._ 1_08P BCRDi- 1 007 IA 151V A IlH 8CL- i 037 iA 09N lB 09L AACOo+ 1 007 IA 25 1d 25H AAC08+ i 007 IA 2c _. 18_ 26h AACI0+ 1 037 IA 27S 18 27H CC14+ 1 007 Io 27E 18 28T CC15R+ I O37 15 27U 18 J30 LC+ 1 0038 A 09K 1A 13P;_ C03+ 1 006 iA 25K IA 21M C03- 1 00j8 A 2iL IA -25L AAC04+ i 008 iB 20F 18 24H AACO5+ 1 008 lb 20S 138 24S AAC07+ 1 038 16' 21S 1e 25S AAC09+ 1 008 16 22S 1e z6s AACli+ 1 008 1B 23S 1 27S PCLR+. 309 iA 13.f 1A 09T BLK- 1 009 1A C0R 13 10J CC0-3+. i o09 1_i2.2...18 15N CC02+ 1 00 B13 21E N1 1c CC04+ 0i 09 18'22E 1e 171N BCIE+ i 009 1 09F 18a 14S CI.S +.1.00 1B 30P_ 18 25T CCC+ 1 010 1A 08C iA 13L 8C&H-_ _ 10iC 1A 09L 18 F0iCC1lR+ i 010 1B 30S 18 25L CLK 1 011 1A 13C 18 13C CCO0- 1 01i IA 15G IB 15 ___CS _2_- 1___0_ i__ 13 B 1 60 CCO1- i 011i A 15E 18 15E _C 0 _3-_ 1_............_....._l.IAE____Ei__18 16E BCR02- i Oil iA 11T 18 IbF MSIX- 1 011 1A 13T 1B 09J AAC06- I Oil iA 14T 18 15R — WR__ _.3+_ 1 11 ___ A 20 T 1 23M CRG12- 1 011 1A 30V iB 28P —._iB P-2_2 - O 011 B 17E 8 11 iR CCOl+ 1 011 i8 15P 18 20R GECLR- I 012 lA 08Fi 18 100 LCIo+ 1 012 1A IlK 1 I1ICK AAC0+_4_ _1.I.L2_.._A 14N!_ AB__ 17K 3CR.O2+ i 012 1A.l11 18 09$ _BZE':-._. _.... 12 __ _7 F B 11_LJ___ 8CIE- 1 012 lB 08H 18 i4R

A-14 ***'* CYCLIC CHCKSLM COMPUTER *~*** L~+ Pi 013 IA 20E IA 13V.....T-!_...i 013 A 11 18b 10ih. LC+ 013 IA 29F IA 23H AAC02- 1 013 1A 14J 1B icK AACO0- 1 014 1A 14g 1B 15K AACJO+ i 014 iA 07E IA i4E AACO1- 1 Oi4 IA 14 F 16 15L AAC)3- i 014 IA 2if iA 14L AACO1L+ i 014 iA 071- IA l1H AAC02+ 1 014 iA 07K IA 14K BIOPi - + 1 014 IA 13K IL 08F AAC03+ i 014 IA 071, iA I4j AAC04+ 1 014 1A 07P iA 14P CRC15+ 1 014 1A 30?P 18 293 BCR3I+ 1 0i4 iA liS 18 JtS LRC15- i 014 1A 3CS _ 8'16 AACOJ6+ i 01i4 IA14 11 2i1AACO7+ 1 01 07E iV 148 AAC09+ i 014 id 07K 18 14K AACii+ 1 014 i6 07F 16 14F BC'R'3- i 015 iA 15F 18 li 810P2+ i 015 iA 13N LB 08K 8CCLRI 1 015 10 24F i8 17h CCO3,+ 1 015 16 2IP 16 21T I0oP1- 1 0 i IA O"E iB 0'P AAC05- 1 016 iA ~2F iA 14R SHIFT2 i 016 iA i9'f 18 27L CCOo+ 1 016 lb 2.E 1B 15L CC08+ 1 016 2A+. 18 160 CCIO+ 1 01 1i 25E 18 17L AAC08+ 1 Ole 18 141- 18 22H CC03R+ 1 0i6 1I 29S 18 21L BIOPI+ 1 017 1A 20C t A 29E SHIFTi 1 017 iA 19V 1 27N AACO5+ 1 017 IA.14S IA 22T 8!0P2- 1 018 lA _OE.lB 170D_ STOP+ i 3018 A 13E 18 i4T BCR!+ 1.018 1A 20M 1_ 27M MSIX+ 1 018 1A 13S 18 19i BC.3E+ i 018 iA 205 18 I1I AACIO+ 1 018 lb 2k..I8 14I.. C L R I 319 _ i A 190 1A 29SI ACC+ 1 0i9 iA 19J i 10F....__2+..1..9..................... i. A "2_ 1.. _I!2H CC12- I 020 IA 17K 18 2tJ CC14- 1 020 iA 18K 18 27J Cli- 1 021 IA 28J 18 18E CCLR+ 021 ItA 21K IA ION CC13- 1 021 IA 17L 18 27L.... CC_1_-0__ __iA _18L.18 27P C05+ I 021 IA 2I 8t.12M MS iX- 1 021 i3 28R 18 i80 LCT+ 1 022 IA 10K IA 215 ___&C 1Z~~. 2 il 22_.Z2__Jk3A 3 T 1__LB___F CCO1R+ 1 023 IA IlL 18 200..-... C 0._.....__ -__ g3 1 A tX3C04$~ 1 M _. _8__z_ _L _2i0__ COI+ 1 024'iA 24L i8 12E

A- 15......... C*C I C.... C.Y. L L._L..CK..S_LU. MPAJJ E t,'.*.. BAY I TO EAY 1, LV-CL 2 LC-........2.... iA iOt, i 0SJ LC+ 2 Oi I A 09K IA 08L Jla 30 2 01,1 iA 30K lA.30L. CRCGi+ 2 00i 1A 3CN 1A 30P a o3I P 2- 2 0 Oi 10 17 lE ib.7E GND ) i lb 1F.1 i) l J GNO 2 01'i iB O2ZF it 02J GND 2 001i lb; 5F L, 05i GND 2 0i)l 1i O6F 15 oeJ_ J1di18 2- 01 lt- ItF 18 1i8k GND 2 01' 11 03j lB 03L GN 2 0<) i~t 04J 1 04t J182d1 Z 0-0i 16 lb 28L J182' 3 L i03 2. l 2 8 9L Jl3 1 0i 2 O91 io'30K 18 30L GN D 001 i13 ilL 1 i OIN GND 2 0'31 it 0"L lI 02N GND 2 001 116 03L l 051\ GNO 2 01 1 i8 OctL le 06N GNUO 2 i0 b 03N lB, 03R Jld182 2 O01 J 1 I1 1 1P CCO2S+ 2 001 o i91\ i l P CC03S+ 2 00)1 1i 29 N L 2l WF CCIS+ ~ Oi01 1 t 30c\ ld 30P SHIFT.. 2 0k2. i 2l r iA 2 2Ht CCL i+ 2 002 iA 21K iP 22K LCS+ 2 002 IA 26; 1A 27 tv SHIFTI 2 00`2 IA 21P 1A 22P LCS+ 2 002 1A 25 1V 2 C11- 2 0<)2 i.i BE ib 1J6..GND g 002 i 0.F d 04F BCLRD2- 2 002 lb 15f iB 1'F bLK- 2 002 1l.L.' i B )_b L 8CH- 2 02 1D O0Sh 11 09L F3:'LP 2. 002 2...... 29J FTAP 2 002 e 093J 0 1 30M 1.......,_tB_..4....0...0...2..1..2..! b. 2K.. 1 2N CCO:- 2 002 ib 19L id 2CP..... i.....0..... 2....1..........B b..........e FBTAP 2 02 0l 28: ib 2SM.G.. 2 002 __N.......4..._ _.........]0.... _.. __...5R BI OP.- 2 002 11 z.B 08b1 0o9P __-iN. _. l.2 02 IB OR 01 b 02R GNJ 2 002 1B 04R lb 05O.... _GN....0...u..................g_.....O._2 _. _. _ _ 0. _ _ __ 0 _ _ BCIE- 2 002 ib 088 18 08b i..B.....1 6_E._-__....... 02....l. 09.._.... _ _......___ __.._9U BC 3 E- 2 00~ is 10 R 18 10l 8IP,2- 2 002i 1- 1 1 iiR lb lOT FBTPI'- 2 002 lB l8R lb 18V BIOP2- 2 002'- 061 lb 09T GNU) 2 002 1B Ol;- 113 020

A- 16 ***** CYCLIC CHECKSLM COMPUTER ***'* GND 2 002 1B 03U 18 04U CC 1S..2 002 1 2'8V _L 29V C1l- 2 003 IA 28J 1A 30M BCH+ 2 003 1A 09M 1A 10S AC04+ 2 003 1A 15N IA 150 AC06+ 2 003 1A 161\ 1A 16U AC08+ 2 003 1A 17N 1A 17U AC10+ 2 003 A 18N _1A 18U LC+ 2 003 1A 13P 1A 13V CRC12+ 2 003 1 19F 18 18K FBTP1-' 2 00-3 1B 191- 18 18M BC2E- 2 003 1 1lJ 18 10M CC13- 2 003 1B 27L 18 2EP...... 8C_3E3+ 2 003 18 I1M 18 09N BIOP1- 2 003 i8 1LN 18 ICP LCT+ 2 004 1A 24M 1A 23v 8CL+ 2 004 1A 09F 1A 10V.8LK- 2 004 16 00 _o 18 l10J BIOP4- 2 004 1d 10L 18 11T L.CT+ 2 005 iA 21.E_ 1A 215S LCE+ 2 005 IA 22E 1A 22S AC05+ 2 005 1A 15J 1A 15V AC07+ 2 005 iA 16J 1A 16V AC09+ 2 005 iA 17J IA 17\ -AC 1+ 2 005 1A 18J 1A 18V BIOP4+ _2 005.A 23M...A 20R CC12- 2 005 l1 26J i 260 LC+ 2 006 1A 20E 1A 23F COl+ 2 006 IA 24E 1A 24T C02+ 2 006 1A 21R A_ 24R CCll- 2 006 IA 18S 18 180 CC04+ 2 006.._.122 18 22T CC06+ 2 006 1B 23E 18 23T CC08+ 2 006 1B 24E 18 24T BIOPI+ 2 006 18 08F 18 11 C4CC 4- 2 006 16 27J e 29T BIOP2+ 2 006 1B 08K Ia ilS C05+ 2 007 1A 22M 1A 25T BMB05- 2 007 1A 04T 1A 08U CCO1- 2 007 LB 15E 18 18L G1A22 2 008 IA 21C IA 21V BMB03- 2 008 1 A 04K LA 085 8MB06- 2 008 1A OBV 18 04L AAC06+ 2 008 1_ 1 13 - 1e -25tH AAC08+ 2 008 16 22ht 18 26H AAC10+ 2 008 18 23F LB 27H MSIXS+ 2 009 1A 09F 1A 13U BMBO0Q4+ 2 009... A 04S 1A 08T BACOO+ 2 010 LA 02L 1A 07C __ __LQ_.___...1A 18 10E MSIX+ 2 010 1A 13S le 09E BAC07+ 2 010 - A 027 1B 070 8AC08+ 2 010 iA 02V 18 07F _.BACO9i+ 2 010 l3_Z0_ — 1B 0T74 CCOO- 2 010 13 151 18 20J ____CL0_2Q _..L...__~QL0__i__0. 18 21 J CC03- 2 010 i 16E 18 21P

A-17 ***** CYCLIC CHECKSUM COMPUTER ***** CClO+ 2 010 18B 25E 1e 30E _ CLK _. 2 01 A)1 _] _ 1_ A IA9P. BACOI+ 2 011 IA 02E I A 07F 8AC02+ 2 011 LA 02H LA 07J BAC03+ 2 011 IA 02K 1A 07L __BAC~Q4~+... _2___ O __ l1 027N BAC05+ 2 O01 1A 02P 1A 07R 8AC06+ 2 011 1A 025 I A 07T LCS+ 2 011 1A 22U 1A 27V BCWR2- 2 011 1B 110 18 17M CCli- 2 011 18 19C 1B 25P BACIO+ 2 01i iB 02E 18 07L BAC11+ 2 011 i 8 02H 18 07N CCO3+ 2 011 18 16P 18 21R CC05+ 2 011 1B 17P 18 22R AAC04+ 2 012 iA 25H 1B 24H AAC05- 2 012 1A 14R 18 17L AAC05+ 2 012 1A 221 18 24S IOPL- 2 012 18 OE 18 02K IOP4- 2 012 1b 08M 1 B 02P AAC03- 2 013 iA 14L 18 16L 8MB07- 2 013 1A 08M 18 04H IOP2- 2 013 1B 08J 18 02M AAC04+ 2 014 1A 14P 18 20H AAC05+ 2 014 1A 07S 1A 14S BMB07+ 2 014 A 10iT 1_ 04K AAC06+ 2 014 1A 07U iA 14L AAC07+ 2 014 18 14E 1B 21S AAC08+ 2 014 18 07F 18e 14H 8CCLR3 _2 014 _ 1B 17J 1 t ov10 AAC10+ 2 014 18 07M 18 i441 BI OP1_+ 2. 015 1A 20C 1A 13K RUN- 2 015 IA 13J 18 13S AACO3+ 2 015 1A 14Y1 1A 2.11 CC04- 2 015 1A 15R 18 22J _CC_6-. 2 015 _.. _L__ _ __ 23_J_ CC08- 2 015 1A 17R 18 24J CC1O- 2_ 015 1A 18k 18 25J BM808+ 2 015 1A lOU 18 04P AACO7+ 2 016 iA 2teh IB 25S AACO9+ 2 016 1A 27H 18 26S..AAlII,+ __2 01_.. _ 1 A 28H 1_ 27S BMB08- 2 016 1A IOR 18 04M __MS I..__-_....._'?__ L0..1..1.E..0._ ___1A 8..T..18U CCOO+ 2 016 iB 2CE 18 28E CCQ2+ 2 016 18 21E 18 29E CCOlS+ 2 016 1B 28F 18 20O..-AAC _09 + _2_._ _ _ i B 14K 18 22 S CC07+ 2 Ol016 23R 18 159 _C0Q_.... _ 1__O B 2BR BI 8 16V CC 11+ 2 016 1B 25R 18 17\ CC15- 2 017 1A 30H 18 27P CC05- 2 017 1A 15S 18 23L 02__ _C __ 2.L....__0.. 1 7_A ~6S lB24L CC09- 2 017 1A 17S 18 25L.__GCLRI.......... _..2 _...._OL..... _ LB.. __-1. _.Q108 V AACOO+ 2 018 1A 148E P 235

A-18 Yc CYCLIt -ICiL L M ZS C0 Qu L& ~P A,04+ o s' -A.15. 14;':).C C 03 +.' 0 i i B 1A J AC05+ 5 2 O i A Ot-P LA 15P PwCLR A 0L iA 09u 9 02V AACi LI+ Z d ibi 1t4P.. 23S ACO 7+ O io ij 1A.1L u iA O'tT CRCi + I'0, 16 i l i8 d 2L AACO i+ I A)2 14 i 4'- A I, \ h AC O6+ 2,) 02 i A I h A1 )0t S AACJ2+')20 I 141S i A 2 -4 BCIP+ 2. 0)2J iA 2 0L d 14't C04+ 2 0L J iA i'd iZL ACGO+ Z O- ilA Ocu l3 15H LCE+ 2 02 i iA 10 iA 21i ACO2+ 2 02i1 i3 16 H IOT0T+ __ 02 __ iI, _ e J6 v ACOd+'02i i 17th iP OitV AC-i+ 2 02i iA Ol 8 0 1> d T1- 2 Oz i 1A 10t i iA O < AC09+ 2 0 IA 1P 17F 1d OC ClkS+ 2 ()l iA 2T 1i 14LU HULD+ 2 3.4 i LC i6 eT ACOI+ O2 1IA CeE ad 15J C::0Q+ Z' 2 1 A 1 2 i'i3 12C BC CLR2- Z iZ2 iA 20V id O9 V AC 1+ J 024 iA i dk 1d O-t LdIOP,+ 02i 4 iA 20 K iB eN ACii+ _ 024 iA 16P 1B OtF COo+ O2 07 1A 25R 16 1'P ACCL.R+ J -d; 1A ~1 d 1 0'P C08+ 2 Q2a.A 26 id1 i2T C07+ 2 02d iA 2t- 1 1 (09+ 2 031 iA 27 >3 120 520 w 1I E S.i. 52. OC,,.1 5, $. 7 O. _...... UNU.. "hE L....__...... _.:i_._._....._._.._._._................ _..,,UiMti~s8_6_ t;OF 6U T} S I T _PS...... 20 NUM.E3 O W'RP............. P 20 ~_lf~.T-Ag~h~~- ii~t~ ~Qj~.~ t-~i~(~_.__trr~~r ~ +_+_ ~ __ 2 2_ 2_5

APPENDIX B CONNECTOR MAPS

APPENDIX B CONNECTOR MAPS The following figures document the I/O cable connection locations and the I/O signal names as they appear on the checksum adapter side of the interface and on the PDP-8 side of the interface. The tables should be self-explanatory and are not further discussed. B- 1

CYCLIC CHECK COMPUTER MOUNTING PANEL 01/0 03/04 05/06 A BAC BMB Iivi 0-8 0-5 0-8 BAC BMB IM 9-11 6-11 9-11 BOP INTRE lv2P4 AC-CL BT1.%2 BRUNa FWRCLR HOLD Figure Bl. Cable Layout Map.

B-3 CYCLIC CHECK COMPUTER PDP-8 SIGNAL INTERFACE ASSERTION SIGNAL NAME CONNECTION LEVEL NAME BACOO+ AO1D,A02D <7> BACO(1) BACO1+ AO1E,A02E < BAC1(1) BAC02+ AO1H,A02H ~ BAC2(1) BAC03+ AO1K,A02K ~ BAC3(1) BAC04+ AO1M,A02M - BAC4(1) BAC05+ AO1P,A02P.> BAC5(1) BAC06+ AO1S,A02S, BAC6(1) BAC07+ AO1T,A02T ~ BAC7(1) BAC08+ AO1V,A02V BAC8(1) BAC09+ BO1D,B02D - o BAC9(1) BAC10+ BO1E,B02E,> BAC10(1) BAC11+,BO1H,B02H BAC(11) IOPl- BO1K,B02K I IOP1 IOP2- BO1M, BO2M --- IOP2 IOP4- BO1P,B02P — IOP4 BT1- BO1S,B02S -- BT1 BT2A- BOlT,B02T _ BT2A PWRCLR B01V,B02V - B POWER CLEAR Figure B2. Connector Map.

B-4 CYCLIC CHECK COMPUTER PDP-8 SIGNAL INTERFACE ASSERTION SIGNAL NAME CONNECTION LEVEL NAME BMBOO+ A03D,A04D - BMBO (l) BMBO1+ A03E,A04E --- > BMB1(1) BMB02+ A03H,A04H - BMB2(1) BMB03- A03K,A04K - BMB3 (O) BM B 03+ A03M,A04M - BMB3 (1) BMB04- A03P,A04P - K, BMB4 (O ) BMB04+ A03S,A04S - BMB4 (1) BMB05- A03T,A04T - BMB5(0) BMB05+ A03V,A04V - O BMB5 (1) BMB06- B03D, BO4D i BMB6(O) BMB06+ B03E,B04E ~ BMB6 (1) BMB07-. B03H B04H -o. BMB7(0) BMB07+ B03K, B04K > BMB7 (1) BMB08- B O 3M,BO4M - BMB8(O ) BMB08+ B03P,B04P - BMB8 (1) BMBO9+ B03S, B04S - BMB9(1) BMB 10+ B03T, B04T - Q BMB10(l) BMBll+ BO3V, BO4V - BMB1l (1) Figure B3. Connector Map.

B-5 CYCLIC CHECK COMPUTER PDP-8 SIGNAL INTERFACE ASSERTION SIGNAL NAME CONNECTION LEVEL NAME ACOO+ A05D,A06D - AC 0* ACO1+ A05E,A06E -. > AC 1 AC02+ A05H,A06H - AC 2 AC03+ AO5K,A06K - AC 3 AC04+ AO5M,AO6M - K AC 4 AC05+ A05P,A06P - o AC 5 AC06+ AOSS,A06S - $ AC 6 AC07+ A05T,A06T -,> AC 7 AC08+ A05V,A06V. AC 8 ACO9+ BO5D,B06D - AC 9 AC10+ BOSE,B06E - AC10 AC 11 B05H,BO6H -. AC11 SKIP** B05K, B06K - SKIP INTREQ** B05M, B06M -< INTERRUPT REQUEST ACCLR+ B05P, B06P -' CLEAR AC BRUN.-** BOSS,B06S -K B RUN(1) HOLD+ B05T,BO6T - HOLD BIOT+ B05V,B06V - BIOT * Some DEC Documents Refer to the AC Input Lines as the "IM"o ** Not Used by Interface. Figure B4. Connector Map.

APPENDIX C DIAGNOSTIC PROCEDURES

APPENDIX C DIAGNOSTIC PROCEDURES Included as part of the Data Concentrator support library is a binary tape for certifying the performance of the cyclic check adapter. The program tests the loading, clearing, and reading of all registers, as well as the clearing of the PDP-8 AC. The shifting facility of the character and residue registers is also checked under 6-, 8-, and 12-bit character modes. The mod 2 adders between stages are then checked along with the feedback tap control, with the generator operating in both the word and byte mode. Finally the generator is exercised by computing a checksum over 4096 characters using first the CRC-12 generator polynomial, then the CRC-16 polynomial. The results so obtained are compared against software-generated checksums for accuracy. If the test halts, the faulty register is normally displayed in the AC (plus MQ, depending on register length). See the program source listing for additional comments, especially with regard to the probable course of the error. After a halt, the program may be restarted with the processor CONTINUE key. Register clearing is taken care of by the routines. C- 1

201 CYCLIC CHECK CCMI'TTF - TEST PO1T IT!NFS * CYCLIC CHECK C:PFPUTITP - TF.ST ROUTINES -* 2? APO TL 6 * ~ 44J.S- * ~A. -4-,A*,,',it. r 4. 14 C414 -J -c J 4* *. J. -J -J.4 *i -C:$, -. Ar,5 *, * -Yt *4. Qi5 A * 4, - 4- $C41 ASSFNRLF.. nFF INITI.l.NS I 000! O,..3. 1P 000? CL.OP 2 0004 WR O P 4 6540 BCt L 6540 6550 BCH OPO 6550 61 iL f:.6 P I=51. 65:61 LCMP DPf 5 56 65.7 LCMt2 OPD 6567 - 6 71. CCC (PO 6571

C- 3 201 CYCLIC CHECK COMPUTFR - TEST PlOUTINES CYCLIC CHECK COMPUTER - TEST ROUTINES * ~* PAGE 1 * * *... PROGRAM STARTING ADDRESS * * --- O?00 —- * 0010 oRGp 10 0o1.0 AXPI OS 1 CO20 ORPG 20 -=* SAVE AREA 0020 TEMPI OS 1 0021 CHRCNT ns 1 002? CNT OS 1 COMMON CONSTANT POOL 0023 C040 K0040 DC 004C 0024 0100 KO100 DC 0100 0025 0200 K0200 DC 0200 0026 0240 K0240 DC C240 00-27 0377 K0377 DC 0377 0030 4000 K4000 DC 4000 0031 7401 K7401 DC 7401 0032 0377 M7401 DC 0377 0033 7540 M0240 DC 7540 0034 7-764 M001.20 DC 7764 0035'7770 M00080 DC 7770 * TH.ROUGHOUT THESF ROUTINES THE REGISTER BEING * TESTED WILL 1B DISPLAYED IN THE AC UPON A -'HALT. IF A REGISTER IS LONGER THAN 12 BITS, THEN'IT WILL BE DISPLAYED IN * BOTH THE AC AND MQ RFGISTERS. SEE CODE * FOR SPEC.IFIC DETAILS. 0200 ORG 200 * - PROGRAM INITIALIZATION 0200 7200 CLA 0201 1334 TAD CRLFP POINTER TO CKLF MESSAGE 0202 0o-10 D'CA AXR1 0203'7344 STA+CLL+R AL -2'TO AC 0204 3021 DCA CHRCNT

C-4 201 CYCLIC CHECK COMPUTER - TEST ROUTINES 0205 5733 JMP* CRLF INITIALIZE TTY REGISTER READ/WRITE CHECK CHECK BYTE MODE READ/WRITE 02C6 7200 START CLA 0207 3022 OCA CNT ZERO CNT (LOOP COUNTER) 0210 7040 CMA SET AC 0211 6563 LCM8 SET BYTE MODE. 377 TO CHAR BIJF 0212 7440 SZ7 LOAD SHOULD CLEAR AC 0213 7402 HLT ** AC CLEAR ERROR 0214 7240 STA 0215 6544 BCL+WR LOAD BCR-LO 02'16 7440 SZA AC SHOULD BE ZERO 0217 7402 HLT ** AC CLEAR ERROR 022-0 7200 CLA 0221 6541 BCL+RD 0222 7040 CMA 0223 0027 -4NO K0377 0224 7440 SZA AC SHOULD BE ALL ZERO 0225 7402 HLT ** BCL READ/WRITE ERROR? * ** FAULTY BIT POSITION(S) LIT 0226 7200 CLA 0227 6542 BCL+CLR 0230 6541 BCL+RD 0231 7440 SZA AC SHOULD EQUAL ZERO 0232 7402 HLT ** BCL CLEAR ERROR. ALSO POSSIBLE ** THAT READ IS IN ERROR. 0233 7240 STA 7777 TO' AC 0234 6554 BCH+WR 377 TO RCR-HI 0235 7440 SZA BCR LOAD SHOULD.ZERO AC 0236 7402 HLT ** AC CLEAR ERROR 0237 6551 BCH+RD DID ONES GET THERE 0240 7040 CMA 0241 0027 AND K0377 0242 7440 SZA AC SHOULD BE ZERO 0243 7402 HLT ** BCH READ/WRITE ERROR?'-:* ** FAULTY BIT POSITION(S) LIT 0244 7200 CLA 0245 6552 BCH+CLR CLEAR BCR-H't 0246 6551 BCH+RD 0247 7440 SZA DID IT WORK? 0250 740'2 HLT ** BCH CLEAR ERROR. ALSO POSSIBLE * *, THAT READ IS IN ERROR. -— * NOW CHECK WORD MODE READ/WR'ITE 0251 7200 CLA 0252 6567 LCM12 SET WORD MODE 0253 7240 STA 0254 6554 BCH+WR LOAD BCR THRU WORD GATES 0255 744/0 SZt.A AC SHOULD BE CLEARED 0256 7402 HLT ** AC CLEAR ERROR 0257 7200 CLA

C-S 201 CYCLIC CHECK COMPUTER - TEST POUTINES 0260 6551 BCH+RPD DID WORD GET THERE 0261 7040 C MA 0262 7440 SZ 7 AC SHgULD BF ZERO 0263 7402 HLT ** READ/WR[TE GATE OR LOAD ERROR.* *,F FAUJLTY BIT POSITION(S) LIT 0264 7200 CLA 0265 655? BCH+CLR 0266 655! BCH+RD 0267 7440 SZA DI1 REGISTEn CLEAR WORK 0270 74(0 HLT.** RCH CLEAR ERROR. ALSO POSSIBLE,*.*,.* THAT READ IS IN ERROR, NOW CHFCK THE SHIFTING CAPABILITIES ~~* SOF THE CHAR RUF AND BCR REGISTERS. SHIFT' CHECK 0271 7200 C..A 02?72 6561 LCt16 SET 6-9BT WC.R MODE 0273 1024 TAD K010 0274 6556 BCH+CLR+WR 0275 6571 CCC START CHECK SUM COMPUTATION. IF PROCESSOR STOPS HERE, THE POP-8'HOLnD' CIRCUITRY HAS MALFUNCTIONED OR THE CHECK ADAPTOR RUN FF HAS * NT RESET AT SHIFT-END CNT. =e* THIS IS TRlJE FOR ALL "CCC'S". 0276 6551 BCH+Rn 0277 7110 CLL+PAR FLAG SHOULD NOW BE IN LINK 0300 7440 S7A I ALL E. SF IS OK, AC SHOULD=0 0301 7402 t. T ** BATD SHTFT COUNTtJAMS, OR ADDERS 00,0? 7620 SNL+CLA NOsWl CHECK FCR FLAG BIT 0303 740? HLT t* PROBABLI.Y 3BAD ADDER OR CBUF SHIFT 8 CHECK 0304 6563 LtfM SET 8-BIT BYTE MODE 0305 7001 IAC 0306 6556 BCH+Cf..R+WR SET FLAG 0307 654? BCL.+CLR 0310 6571 fCC 031 t. 6541 BCL+RO FLAG SHOULD NOW BE IN L INK 0312 711.0 CLL+R AR FLAG SHOULD NOW BE IN LINK 031. 7440 SZA AC SHOULD = 0 031-4 7402 HLT *4 BAD SHIFT CNTJAMS,OR ADDERS 0315 7620 SNL+CL A NOW TEST FOR FLAG (LI}) 0316 740? H L'T *4 BAD SHIFT CNT,JAMS,OR ADDERS 0317. 7620 SNL+CLA NOW TEST FOR FLAG 0320 7402 HLT *4 NOT THERF.BAD ADDER OR CBUF? SHIFT 12 CHECK 0'321 1C30 TAD,. K4000 12TH BIT FLAG 0322 6567 LCM 12 0)3 2'3 63 52 BCH+CLR 0324 65'71 CCC

C-6.201 CY~CLI. C CHECK C,.MPU.JTFR - TEST ROlTINFS 0325 65'51 3C 4 + R O-? 2 6 1 032 Ta4 M'74!1 _0327 74 50 SNA C SH )OULf= 033 sj 5 73' J; MTAP f [K...CN T. ] NEXT PAGE 0'331 1031 TA.Q K7401 RFST.,RF AC 033. 7402? -l.7 T PtAD AAD)EP, OR CBUF?.. C O N S T A N T S 0333.100-.4 C, L ) PRNT! 0. 34 103. CL fP C C I -? 0. 3 5 04.0 f) M T T Dp CM. MTAC 0 W

C- 7 201 CYCLIC CHECK COMP!.JTFR - TEST ROUTINES * CYCLIC CHECK CCMPUTEP - TEST ROUTINES * * PAGE 2 * 4 * 0400 or07 400 * NOTF: * ADFR 1 IS BETWEEN BCR llCR(11)/BCR(15) CUF(11) * ADDER. IS BETWEEN RCR(Q) AND BCR(1) — 7c~ —--— * ADOER 3 IS B13TWEE!t RCR(l) AND SCR(2) ADDER 4 IS SETWEEN BCR(2) AND BCR(3) c* ADDEP 5 IS RFTWEFN RCR(10) AND BCR(11) ADODER 6 IS BFTWEN BCR(15) AND BCR(16) 4tt hjJNOW CHP:CK THF MOOf 2 ADDERS DERIVING THE FFECRACK FROM CRP(11 ). TFSTS AODFRS 1,t,?,4,AND 5 *0+0 M)? - WOQO MO.E 040')'7200 MTAOOW C.a 0401 6567 LCMI2 0 TO ADOPR INPUTS 040? 6552 RCH+CLR 0 TO F9 TAP 0401 6571 CCC 0404 6551 3CH+RF 0405 7440 SZ. A BC 0-1l SHOULD EQUAL 0 0406 740? HLT *4 AODEP FRRORS? 0+* MO 2 - WORD MODF 0407 7?00 MTAOIW CLA 0410 1030 TAO K4000 1 IN FOR LAST SHIFT 0411 6567 LCM1I? LAD CHAP B3UF AND SET MODE 0412 6552? 3H+CLR 0 OUT FOR 1 ON FBTAP -0413 6571 7,CC C 0414:6551. 3CH+PD BCR 0-11 SHOULD =- 7401 0415 1032 TAn M7401 (-K7401) 0416 7450 SNA DEF S I'T 0417 5?22 JMP MTAlOW YES.. 0420 1' 031 TAD K7401 NC...RECONS TRUCT AC 0421 7402 H I.T *4 ADDER FRPORS? * 4* CORRFCT AC = 7401 * 1+0 Mfn 2 - WORD MODE 0422 7200 MTA10W CLA INPUT 0 0423 6567 LC'1 2 0-424 71 30 STL-+RAR CUTPUT I FOR 1 ON FBTAP 0425 6556 RCH+CLR'+WR 0426 6571 CCC 0427 6551 BCH+RD 0430 1037 TA- M7401 RCR O-11 SHOULD EQUAL 7401 0431 7450 SNA DdES IT?

C-8 701 CYCLIC CHECK COMPITER - TEST RCUTINFS 0432 5235 JMP MTAIIW YES.. 0433 1031 TAD K7401 NO... RECONS TRUCT AC 0434 7402 HLT *4 ADODER PRRORS? * 4~**4 CORRECT AC - 7401 * 1+1 MOO.- WORD, MODE 0435 7200 MTAL1W CLA 0436 1030 TAD K14000 1 IN ON L AST SHIFT 0437 6567- LCM12 0440 71 30 STL+P R ] Ol.UT FOPR 0 ON ETAP 0441 6556 BCH+CIR+WR 0442 6571 CCC 0443 6551 qCH+Qn 8CR 0-11 SHOULD EQUAL 0 0444 7440 S __ 0445 7402 HLT - - ADOE-R ERRORS? - * ** CORRECT AC = 0 3*C N)NOW CHECK THE AODFRS DERIVING THE FEFFDR4CK FROM qCR(15). TEST S 4 1,ERS, 3 ANi) 6 * 0+0 *O).2 - PYTr MOnnF *, 0446 7200 MTAOO8 CLA 0447 6563 LC'4P SrT RYTF MOnE. 0450 655?. CH+CLR Oi'S FOR F3 TAP AND ADDER INPUTS 0451 654? RCL+CLR 0452 6571 CCC 0453 6551, CH.+P 0 SHflULO)=0 0454 7450 SNA 0455 5257 JMD MROC1 rK..THEN CHECK AODER 6 0456 7407 HLT ** n.ER 1 -ND/OOR 3 ERROPR? *:~ ~~*4 CORRECT AC = 0 045'7 7200 M001 CLA 0460 6541 B CL +P n, 0461 7110 CLL+RAR BCR(15) SHNiJLD HAVE BEEN 0 0-462 7620 SNL+CLA WAS IT? 0463 5266 j3MP MTAOI 3 YES.. 0464 6541 BCL+RD PUT LC-.CR TN AC 0465 7402 HIT * anER 6 ERROR * t*- CORRECT AC = 0 * _ -_____ 0+1 MOO 2 - PYTE MODE 0466 7?00 MTAOIB CLA0467 1025 TAD K0200 1 IN FOR LAST SHIFT 0470 6563 LCM8 0471 6552 BCH.+CLR 0 OU1T FOR 1 ON FBTAP 04'72 6542 BCL+CLR 0473 6571 CCC STOP THE WORLD I WANT TO GET OFF 0474 6551 8CH.+PR 0475 1033 TAD M0240 (-K024.0) 04.76 7450 SNA AC SHOULD EQUAL O 04'77 5302 IMn MBOl1l IT DIO, THEN CHECK AODER -6 0500 1026 TAD K0240 ** ERRnR RECUNSTRUCT AC 0501 7402 HLT *~ ADDFR 1 ANO/OR 3 ERRORS?

C-9 201. CYCLIC CHECK COMPUTER - TEST QOU.TTNFS * -,.*4ci CORRECT AC = 0 0.52 6541-. MB011 C! +PD ADoER 6 CI-HECK 0. 03 701.0]R)AR 0504 7430 57?.. RCR(I5) SHE)UJL ) E,QUJAL 1 050I 5310 J.Mp MTAIOR IT OFES 0506 7004 R AL.. OHDH. RECONSTRUCT AC 0507 7402 HI..T ADDER 6 FRROR,.. CnRRECT AC = 0001 *~ 1+0 t. 7Ci') 2 - PYTF MI- rF) F. 051.0 7200 MTAIOB CLA INPUT C FOR SHIFT 8 0511 6563 _, LC.R SET RYTE MODE 0512 655?2 8C+C.. 0 TO (DA P S 1 AND 3 0513 1.0?5 TAD' K?00 1 OUT FlPR 1 ON FBTAP 0514 6546 RCL.+CLP+WR 0515 6571 CCC 0516 655! RCH+RD 05 1 7 1 0- _ TAO MO-40 (-K0240) 0520 7450 SNA AC SHOULD FODAL, 0 09571 5324 j___ _ M.1 0I IT DOES, THFN CH-ECK ADDER 6 0522 1026 TK.KO40 FPREO C RECONSTP UCT AC I 9?5 74 0? H L T *c ADDFQ! AND/OR 3 ERRORS? *~ *.,4 ATC SHO!ULrD = 0 C0524 69541 M 9 R1 0 1 PiCL+90 AnODER 6 CHECK 025 7010A 0526 7430 SZ7L FQR(15) SHOULD FQUAL I -0527.-3'3-2' MTA 11 CK 0530 7004 RAt. PESTOPC AC 051 I 740? H L T 4 A' r)F 6 FRROR ~__ -,-*-,* A___ _-rtAHO!I. = O001 1+1. MONE? - YTF MOE _ - 0532 7200 TA1I.3 CLA 053'3 1025 TAD KO02 0 I fN FOR 14AST SHIFT 0534 6563 LC'_ _ 05.9 655? BCH+CLP 0536 1025 TAT KO?)O 1 OUT FOP 0 (IN FBTAP 053'7 6546 BCI. +CL +WR 0540 6571 CCC 054Al 6551 t CH+PD 0542 7 4 50 SNA AC SH.CULD FOUAL 0 0541 5345,IP R111 CK, TH.EN TFST ADDER 6 0544 740? HLT ___ _ _ ADOER 1 AND/OR 3 ERRORS? * *- CORRECT AC = 0 0545 7200 MIRI1.l C L A 0546 6541 3 C L+RD 0547 7450 SNA BCL SHOtlULO = 0 09'5590 5353 JiMP LOOP CK..THEN ON TO CHECK LOOP COUNNT 0 55 1 7402 HL..T * AD0FR 6 ERROR *,*-4 CORRECT AC = 0 0552 7200 CL.A 055'3 2022 L]OP I S7 CNT 0554 5757, IMP4 PTRI BACK AND O. IT AGAIN 0555 5756.JMp*'- COMDPl DONE, THEN ON TO NEXT PAGE 0556 0400 COMPI.P DC RCW.I

C- 10 201 CYCLIC CHECK COMPUTER - TEST ROUTINES 0557 C210 PTR1 DC START+2

C-li.'01 CYCL IC CHF'CK COMPtTTF F - TEST rO I.J'T NF..S t* ______ CYCLIC CHECK COMPUJTFR - TEST ROtJTI[NFES:* ~ PAGE 3 * *.~,QA:~ c' 0600 _ ORG 65O00 * NOW LFT'S CHECK OPE-RATION BY COMPUTING CHCCKS 1t?' B9Y SO.fFTlWARF ANID HARDWARE METHODS THN CC-MPARE THE RESULtS. RESI..JRttV CH-FCK - WORP Ml-.. E __GFNEPATOR PO,_. YNO T A. ~ X*1? + X**! + X1 *3 + X/*2 + X + 1 0600 3.37()? C.0 M,OCA WCNT -4qa0 TC COUNT 0601 3.5E5 DCA HGHI 7EPO -QA.DWAqE PESIDUtE SAVE AREA 060 2'57 r)c ^ C3 BI-JF LIKEWISE TSn SOFTWARE RESTOUE 6O'A 1 70 PCWM2 T!') WCNT USE THII.S AS INPUT CHARACTER 0'604 h667 Lfrvl? SeT 1?-RTT WOi, D M')DE 0605 1355 T) HOHI O60; A, k556. ir-4 + C R +WP 0607 CCC 0 0 7 A 71 13 _ _ C H_+_ _ _ _ _ 061.1 3355.DCf,A HGHI. SAVF'HAP. DWAE GENERATE1) RESIDUEJF *-' NOw LE T'rS C(1)MlJUTF IT BY SOFTWARF 961? 1034 T t M O12ql (-I!? fECT I M )'01 lq7l nfCqA SOeNT S T UP SHIFT. COLJNTER 0 1 4 1270 T Ar n WC NT INPUT CHARACTER 06 15 3_3 67 n CA CR!F _ PRSF RVE INPUT CHARACTER 306L6 1257 PRCW, W!3 TAn CHtUF FFTCH B3C RcSIDUJE 0617 71. 0 CLL+RAP SAVE LtSB N LINK 0620 33.57 OCA C BIF3 I F 0nA2 1 %67 TA!) CRUtf GET CHAQACTER 06?2 70!0 AqR CHAR LSR TO LINK;8CC LSB TO AC(O) 0623 7510 SPA THIS + NFXT FORMS xnR BETWFEN 06 4 7020 Cr L LSR''S F BCC AND CRUF 0625 3367 nDC CUF SAVF CHAR 0626 7420 SNL IS FFr.nACK BIT A 1 0627 524? JM R.CWM4 NO... 060Q 1'.57 TAD BC HJUF YES..MORF WftRK TO BE DONE 0631. 0031t. AND K740. XOR F3TAP I NTO BCC 0632 7041 C IA 063`3 7104' CLL+PAL 0634 1357 TAD BCHRUF 0635 c103! TAD K7401 0.6.36?37! S7r SCNT BUMP SHIFT COUNTER 063 7 5 9217 IMP RPCw M3+1 0640 33 57 OCA -BCHBUF SAVE FINAL RESIDUE 0641 5957 JM. RCW - 064? 2371 PCWM4 1SZ SCNT BUMP SHIFT COUNTER 0643 5216,jMIP RCWM3" BACK FOPn MORE SHIFTS 0644! 355 TAn HGH[I DONE..THEN LET'S COMPARE RESULTS 06'45 704i CI A 0646 J357 TAO BCHRUF

C-12 201 CYCLIC CHECK COMPUTER - TEST ROUTINES 0647 7650 SNA+CLA ARE THEY EQOAL? 0650 5257 JMP RCWMS Y.ES.. 0651 1357 TAD BCHBUF NC...THEN SET UP AC & MQ FOR HALT -0652 7421 MQL SOFTWARE FRESIOUE TO MQ 0653 1355 TA/. HGHI HARDWARE RFSIDUE TO AC 0654 7402 HLT ** ERROR IN RESIDUE COMPUTATION. 0655 7200 CLA 0656 5261.JMP RCBM1 4096 TI MS AROUND THE 065'7 213'70 RCWM. 5 I S WCNT PULBERPRY BUlSH. 0660 5203 JWMP RCWM? ~*~~~~~ * RESIDUE CHECK - BYTE MODE IF~* GE S GENERATOR PtOLYNMIAt.: X**16 + X**1'5 + X**2 + 1 0661 3355 RCBM1 DCA HGHI! ZERC ALL THE RES IDUE SAVE AREAS 0662 3356 DCA HGLO 0663 3357 DCA BCHRUF 0664 3360 OCA BCLBUF t NOTE: THF FIRST TIME THROUGH WCNT $c SINCE IT JUST OVERFLOWED. 0665'1.370 RPCBMR2 TAD WCN1T INPUT CHARACTER EMULATOR 0666 6-563 LCM8 SFT 8-BIT RYTE MODE 0667 1355 TAO HGHI LCAD RESIDUF REGISTERS 0670 6556 B(H+CLR+WR 0'671 1356 Tro HGLC 0672'6546.CL+CLR+WR 0673 6571 CCC 0674 6551 BCH+RD SAVE HAPDOWARE GENERATED CHECKSUM 0675 3355 DCA HGHI 0676 6541 BCL+RD 0677 3356 )CA HGLC ___ * NOW LFT'S COMPUTE IT BY SOFTWAR-E 0700 10(35 TAn 000OOOD (-8 DECIMAL ) 0 701 3371 DCA SCNT S TIFT FFOUNT ER 0702 13 70 TAO) WCNT 0703 3367 OCA CBUF 0704 1357 PCBM3 TAD BCHBUF FETCH LEFT-f3YTE 0'705 7110 CLL+RAR SAVE LSR TIN LINK 0706 3357, OCA BCHBUF 0707 7012 RTR 071 0 701.2 RTR 0711 1360 T.AD BCLRUF 0712 7110 CLL+RAR LSB OF RIGHT-BYTE TO LINK 0713 3360 DCA BCLBUF 0714 1367' TAD CBUF FETCH INPUT CHARACTER 07115 7010 RAR GET IT'S LSB 0716 7510 SPA THIS + NEXT FORMS XOR BETWEEN 0717 7020 CML LSB'S OF RCC AND CHAR 0720 3367 DCA CBUF SAVE CHARACTER 0721. 7420 SNL IS FEEDBACK BIT -= 1? 0722 5342 JM. RCBM4 NO,,.LIfF IS EASY 0'723 t360 TAD BCLBUF XOR FB LINE INTO BCR(t 15} 0 724 71 10: t CLL+RAR

C- 13 2'01 CYCLIC CHECK COMPUTER - TEST ROOUTINFS 07? 5'7020 C MLt 0776 7004 RAL 0727 3'350 ODCA BCIU. RUF 070 17tA7 TAD PCHBR!F NCOW GET HI'GH1-*:YTE.731 00?-6 AN9 KO?4C X.4. R FITAP TNTO H-IGH BCC 073? 704, C TA 07 3 71 04 C1(.- +PAl. 0734 l 57 TAD BCHBRU F 0735 1C,26 T Am KO?40 0'736 2.~7.2 I 57 SCNT HAVf THERE:EEN 8 SHIFTS? 0737 530.,imwp RCB3+1 N.. *'rTHN C, BiACK 0'740.,,O 3 57 OC.RCHf3UF YES..SAVE FINAL RESIDUE 0741. 5344 J _v. -C ___. 0742 2 71 R. BM4 I S. SCNT HAVE THFE EEN 8 S HI F T S? 0743 5'~304 d__'! R-fR.PCP3 N..."n "ACK. 7 4...'".'... _.0744 1R55 PC1RM5 TAn H GH1 CMD.ARF PR J S LTS'745 7041 C I A 074 6 1.. 357 TAn A BCHB FIJF 0747 1, 56 T HL t 075C 7041 C IA 0751 1 6) fTA R CLBI3F LIKF A [.IT POT OF HONEY 0D75 2 T7h,5 S1A,+Ct L AC SHtC..)L EQUAL 0 AT THIS OINT 07%3 536? Jr C ROK n754. 740:2 HLT ** ERRPIJ' IN RES I DUE COM PUTATION. * A FX. TXA,INE THE NEFXT FO UR LOC ATIO N'c, 0 JT.FC-OVER THF CONTENTS OF THE * ^- R niW tR E AND SOFTWARE C H CKSU M.....EG STERs. 075 5 HGH' 0756 HLt FC D 07L7 Bf CHUF DS 0760 BtLBUF 0S 1 0761, 5766 J!.P:*' C K 076?.2_.370 RPCMA 157!W4CNT HAVE7E f..ONF THIS 4096 TIME ES 07'3 7 52,5,j. R NOT YET. 0 764 5765 J P-* OUTPTR YES.. CONST.A:NTS 0765 1000 0tJTPTR DC ) UT P( R T 0766. 06 BACK )DC STAR T VARIABLES 0767 C5B tjF.q. _07 70 W CNT rS 1 0t77 1. SCNT OS

?01 CYCL Cr CrHECK CKCMOPUJTER - TFST QfIJTTNIFSq 4- - e J -,,,,; * JA - 4.. 4.t,4 41 4. 4. 4 *. J..4 4. 4* 4-.. 4.4*. J4 4.. 44 A. 4. 4* *4-.., r....:. t.._ ___ * CrYCLIC HFKC 1PU:,- T RT I NES 4. 4. 4,,,'LQ''. A,, Jr,,L, J. 4,.I. J.- la, J, _ r- -. Al.~,..k, JI rs w 8 * * t.. * J. 8 * * * t * * * t *, *A, * r 1_01 3 0 l.1. _; _ -'.. 1 nT~ R'RT ~1002~w 01A S~15~ TAn'~ ~. Cm,,1 (-'- S' —r~SF Lr\' TS 0 I Df7 A T T T p, i.. 1. 004 141.0t:?..t. JiP. NT I rTAYI F -.T.T.S f 4FACTER: 10 5 6 046- T_ TL S I'C6 7' -0 LA l l..5O'31 ( ~E I A. T'.0 I I~ r!,C FC R tC M N E R1012 6041, TcF 1 0 1 31. 5? 1?2 j IV:_ J M P, ~ - 1. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __. ~101iO 4 5204 JMP, PT. 5 C4 K Tl PP F rTx NfXT CHAR'ACTER 74- CO N- S O TAN1T S 1015 1.,7 CPf,'IP DC..M 105 3206 O FG IN 23C STA RT! 2! TVA IABLFS!. 0 ]. 3 5? 1..2,I

201 CYCLtC CHECK (COP1TFR - TES T ROI..JTIN.ES CYCL IC CHECK COMPUITFP - TEST ROU'TINES INfOIR-FCT STORAGE -~ LITERAL POOL * fc *3~ *t e? ~ P t A- =e 3t -P *r 4# f* t 4 ** * q' 6,8 * 4 4~ 5S'b ^ *S *t~ *e'j, * *'A Al J 641 14 11L. -A. 41 4* JI A. 4I Al 4 * A __ __ _M *ESSAGF I 01 7 7764 COmI DC COMI O CE, 1 (-L- E NGTH) ] 020 0325'3?5 "JNITT CHfECK" 1021 0316:316'1022 0311 3 11 1023 0324 324 1024 0240 240 1025 0303 303 1026 0310 3 1. 1027 0.3C0 305 L 0 3 03 03 0 3 30 1031 0313. 31. 3 103.2 01. 5 215 1 033 0?12 C C M.E 2 1

C- 16 201_ CYCl IC CHECK COMPf.ITER - TEST RO()tTINES 0700O EN')?00 5PFRAN:C- C-CSS —PFFEPFNCF. LISTING AX 1 0,1,0,O2?n? 11001 1CO4 ACK 0766 C76 1 RCHRtlF ('757 060? 061.6 0(t,20 063 C 0 634 0643 0646 0651 0O-63 0'704 0706 0730 0734 0740) 0746 fCl-UF.76' 0.66 071 —! -)7'1 -)7'-.23 0797 01 5 R F N 1016 1011 CRItJF 0767 061 0621 06?25 070 7 rC714'07?9 C 4.C NT 0'1'320? 4 1 0) 0 1 O007 CNT 007?? 207 055' CfcmP- 05%........- __.._ -!.-:. l-if:- 1 o 1 7 C.O'MIF 10 -3 0124 1).1.7 COMIP 1.01. I9 1000, O0? CRLF 0' 33? O?n__ CPLFP - 314 0201 HGHI T 1755 3601. 06 0 5 011 06:44 0) 65?.6)61. 0F, 67 067.5 0744 H G L 7% C.6,7,2 n,,71 0677 n1747 K0C4 C O0? "< 100 00,()4 0272 K-.000 2,?n,' 0467 051'3 053 0 __. _ _r_ K?024C O" n5o0 0G2 - 731 C73r5 1(.0377 00.?7 -O 2. 02_41 _ __. K4100 70 30 t03 2 F413 04.3 6 K7401( 00l1 Cil3. 0472 Q43. 061 063.19g 0553 3%F05 M0 1 0457 455 _ -MROl 050 4 7 7 MSlOl1, 52,4?1 _ ___ M II1 i 1 0545 I543 MTA'TA O 3r 5 0320 MrA009q 0446, MTAOC1 0406 0.35 M T A. ( I1 34k6 s 63.MrA I 0510'3.505 MTAIlW 043L? 04.217 TAI 045 0 _ ____ 0_ _ _ _ M) C.O 0031)5 C700:)0! 2.C 0,034 0.61 2 MO,?,4. 0 i03. 0475 05 17 M7401 0032 0)326 0415 04730 nO.)TPRT 1000 0765 O iiJTPTR T 0765 C764 PQRNT 1 1004 03- 3 1014 PT9!. 5 57 05. 54 RCB 1 0661l 0656 RCr 2 o665 0763:CB r'3 0704 C737 0743 RC.M4 074? 0722 Q 5 ~0744 0741 RCRb6 0762 53 _ __7_ __ __ RCWMi 0600 O06

201 CYCLIC CHECK COMPUTER TEST ROUTINES RCWM2 0603 0660 RCWP~ F~j Tf3 rIJ0616 0617 0643 RCWM4 064?2 0627' RC'WMWu5 0657 0641 0650 SCNT 077.1 0613 063"'A6 06 42'0701. 07-36 074'> START 0206 0557 076,6 1016'TEMP1 0020 WCNT 0770 0600 0603 0614 0657 0665 0,)70%? 0762 OPFRPATCR CROSS,-R-EFFFRFtNCE LISTING FCH 6550 0234 0237 -245 0?46 0?54 060 F0?65 0266 0?74 0276 0306 0323 032 5. 040? 040-4. 041? 01414 04 25.0 4 27 0441 0443 0450 0453 0471 0474 0512 C5i6 0535 0541 06 06 0610 0670 0674 8CL 6540 0215 0221 02 l?7 0 30 I 307 0311 041 0460 0464 0472 0502 0514 0524 0537 0546 067? 0676 C7CC 6 57 1 0275 03 10 0324 0403 0413 0 4?,S 0442 04592 0473 0515 0540 0607.0 -,,17 3 CLP 0002 0??7 0245 0265 0274 0306 0307 0323 0402 C412 04?5 0.441 0450i) _ 041 471 0472 05412 0514 0535 07007 06C6 0670 0672 LCM-12 6567 0252 03?? 0401 0411 0423 0 437 0604 LCM6 6561 0C272 LCMMR 6563 0211.0304 0447 047C 051 1 0534 06 66 RD 0001 0??! 0230 0237 0246 0260 0266 0276 0311 0325 0404 04'14 0427 0443 0453 0460 0464 0 474 050' 0516 0524 0541 0546 0610 0674 __ ~~0676, WR 0004 021. 5 0234 0254 0 27 4 0306 0425 1 0514 _453 0606 0670 06_72EPPORS 0 SCARDS 611 SPR, INT 6 94 SPUJNCH 8 STORAGE 9

Unclassified Security Classification DOCUMENT CONTROL DATA, R&D (Security classification of title, body of abstract and indexing annotation must be entered when the overall report is classified) 1. ORIGINATIN G ACTIVITY (Corporate author) "a. REPORT SECURITY C L.ASSIFICATION Unclassified THE UNIVERSITY OF MICHIGAN 2b. GROUP CONCOMP PROJECT 3. REPORT TITLE A CYCLIC CHECK COMPUTER FOR ERROR DETECTION 4. DESCRIPTIVE NOTES (Type of report and inclusive dates) Technical Report 5. AUTHOR(S) (Last name, first name, initial) Kenneth E. Burkhalter 6. REPORT DATE 7-. TOTAL NO. OF PAGES 7b. NO. OF REFS June 1968 77 8a. CONTRACT OR GRANT NO. 9a. ORIGINATOR'S REPORT NUMBER(S) DA-49-083 OSA-3050 b. PROJECT NO. Memorandum 19 |c. 9 b. OTHER REPORT NO(S) (Any other numbere that maybe assigned this report) 10. AVA ILABILITY/LIMITATION NOTICES Qualified requesters may obtain copies of this report from DDC. 11. SUPPLEMENTARY NOTES 12. SPONSORING MILITARY ACTIVITY Advanced Research Projects Agency 13. ABSTRACT This report discusses the design and use of equipment built to aid intercomputer communications via serial-synchronous data transmission techniques. The interface described computes on a character-by-character basis, a cyclic redundancy block checksum which is appended to outgoing or checked against incoming messages. This hardware technique reduces checksum computation on a small computer from several hundred microseconds per character to only several microseconds; a reduction that is necessary if more than several 201 type data modems are to be operated simultaneously under control of a single processor. Basic design objectives and decisions are described first. A brief overall system description with background information is then followed by programming considerations and detailed descriptions of the checksum computer logic. Finally diagnostic software and wirewrap documentation is provided for maintenance and/or reproduction purposes. D D 1JAN64 1473 Unclassi fi ed Security Classification

Unclassified Security Classification 14. K OLINK A LINK B LINK C l________________________ KE WRD |ROLE WT ROLE WT ROLE WT Cyclic Redundancy Check Block Check Computation Serial-Synchronous Data Transmission Logical Design Digital Computer Interface Maximal Linear Shift Register Sequence INSTRUCTIONS 1. ORIGINATING ACTIVITY: Enter the name and address imposed by security classification, using standard statements of the contractor, subcontractor, grantee, Department of De- such as: fense activity or other organization (corporate author) issuing (1) the report. | report from DDC." 2a. REPORT SECURITY CLASSIFICATION: Enter the over2a. REPORT SECUTY CLASSIFICATION: Enter the over-..(2) "Foreign announcement and dissemination of this all security classification of the report. Indicate whether "Restricted Data" is included. Marking is to be in accord- by D is not authorized " ance with appropriate security regulations. (3) "U. S. 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PROJECT NUMBER: Enter the appropriate ever, the suggested length is from 150 to 225 words. military department identification, such as project number, subproject number, system numbestsk number, et14. KEY WORDS: Key words are technically meaningful terms subproject number, system numbers, task number, etc. or short phrases that characterize a report and may be used as 9a. ORIGINATOR'S REPORT NUMBER(S): Enter the offi- index entries for cataloging the report. Key words must be cial report number by which the document will be identified selected so that no security classification is required. Identiand controlled by the originating activity. This number must fiers, such as equipment model designation, trade name, military be unique to this report. project code name, geographic location, may be used as key 9b.. OTHER REPORT NUMER(S): If the report has been words but will be followed by an indication of technical conassigned any other report numbers (either by the originator text. The assignment of links, rules, and weights is optional. or by the sponsor), also enter this number(s). 10. AVAILABILITY/LIMITATION NOTICES: Enter any limitations on further dissemination of the report, other than those Unclassified Security Classification

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