ERRATA Figure 3. 5(b'} caption: "Ir/T" should read "T/To " 74 Figure 3., 209 bottom curve: "K=10DB" should read "K=- IODB." 83 Figure 3, 27, drawings on right side: "G( )=..1 "shoilld read "fGt). o o "," two places~ 84 line 12:'oo automatic-phase controlO~ " should read automatic phase-controlo.".37 line 6: "If in" should read "If an." 4 *c,

THE UNIVERSITY OF MICHIGAN OFFICE OF RESEARCH ADMINISTRATION ANN ARBOR PRECISE FREQUENCY SYNTHESIS USING NONPRECISE TUNING COMPONENTS Technical Report No. 120 2899-52-T Cooley Electronics Laboratory Department of Electrical Engineering By: T. W. Butler, Jr. Approved by: aZ B. F. Barton Project 2899 TASK ORDER NO. EDG-4 CONTRACT NO. DA-36-039 sc-78283 SIGNAL CORPS, DEPARTMENT OF THE ARMY DEPARTMENT OF ARMY PROJECT NO. 3A99-06-001-01 Submitted in partial fulfillment of the requirements for the Degree of Doctor of Philosophy in The University of Michigan June 1961

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ACKNOWLEDGMENTS The author wishes to express sincere appreciation to all members of his committee for their encouragement and helpful criticism in the preparation of this work. The technical guidance of the Chairman, Professor J. A. Boyd and members Professor H. W. Fjrris and Dr. L. W. Orr was particularly helpful. The author wishes also to thank Mr. Robert E. Graham and Mrs. Alice Brockus for their intensive efforts in preparing the material for publication. ii

TABLE OF CONTENTS Page ACKNOWLEDGMENTS ii LIST OF FIGURES V ABSTRACT x CHAPTER I. INTRODUCTION 1 1.1 Statement of the Problem 1 1.2 Survey of Other Methods of Precision Frequency Synthesis 3 1.2.1 Tunable LC Oscillator 4 1.2.2 Crystal Oscillator 4 1.2.3 Multiple Crystal Frequency Synthesizer 4 1.2.4 Single Crystal Frequency Synthesizer 5 1.3 Stabilized Master Oscillator Frequency Synthesizer 6 1.3.1 Servo System 6 1.3.2 Sampled Data System 7 1.4 The Status of Current Work —Summary 9 CHAPTER II. HISTORICAL BACKGROUND ON THE STUDY OF ELECTRONIC TUNING METHODS USING SOLID-STATE DEVICES 11;.1 Electronic Tuning 11 2.2 Magnetic Tuning 12 2.3 Electric Tuning 20 2.3.1 Ferroelectric Capacitors 20 2.3.2 Voltage Variable Diode Capacitor 32 2.4 Conclusion 38 CHAPTER III. ANALYSIS OF THE GENERALIZED DISCRETE FREQUENCY SYNTHESIZER 40 3.1 System Concept 40 3.2 Discrete-Frequency Reference 46 3.2.1 Definition of Peak Factor 46 3.2.2 Methods of Generating a Discrete-Frequency Reference 54 3.2.3 Summary 83 3.3 Phase-Lock Oscillator 84 3.3.1 Theory of Operation 85 3.3.2 Design Procedure 109 3.4 Analysis of Frequency Choices for the Frequency Synthesizer 119 CHAPTER IV. SYNTHESIZER DESIGN CONSIDERATIONS 125 4.1 Design Philosophy 125 4.1.1 Discrete-Frequency Reference 127 4.1.2 Phase-Lock Oscillator 127 4.1.2.1 Voltage-Controlled Oscillator 128 4.1.4 Control Network 132 4.1.5 Measurements 134 iii

TABLE OF CONTENTS (Cont.) Page 4.1.5.1 Discrete-Frequency Reference Measurements 135 4.1.5.2 Phase-Lock Oscillator Measurements 136 CHAPTER V SUMMARY AND CONCLUSIONS 152 5.1 Introduction 152 5.2 Summary of Results 152 5.3 Suggestions for Further Research 155 APPENDIX A COMPARISON OF ELECTRONIC TUNING DEVICES 158 APPENDIX B LIMITATIONS ON SRG USED FOR DECADE SPECTRAL DIVISION 159 LIST OF REFERENCES 161 DISTRIBUTION LIST 163 iv

LIST OF FIGURES Figure Page 1.1 Block diagram of a multiple crystal frequency synthesizer 4 1.2 Block diagram of a single crystal frequency synthesizer 5 1.3 Block diagram of a stabilized master oscillator frequency synthesizer (Servo System) 6 1.4 Block diagram of a stabilized master oscillator frequency synthesizer (Sampled Data System) 8 2.1 Schematic diagram of a typical controllable inductor 13 2.2 Definitions of magnetic paranmeters 14 Lc max 2.3 L of typical magnetic tuning unit vs. frequency 16 c min 2.4 Q of typical magnetic tuning units vs. frequency 17 2.5 Basic circuit for application of a controllable inductance Lc in a tuned circuit 17 2.6 Ferroelectric capacitor hysteresis loop 22 2.7 The static capacity-field butterfly loop for a typical ferroelectric ceramic 26 2.8 Ratio of capacitance, CJC vs. temperature in degrees centigrade x 40 v 27 Cc max 2.9 Cc a of typical ferroelectric capacitor vs. frequency 28 c min 2.10 Q of a typical ferroelectric capacitor versus frequency 29 2.11 Basic circuit for application of a ferroelectric capacitor in a tuned circuit 30 2.12 Voltage sensitivity of capacitance 33 2.13 Q of a typical voltage variable diode capacitor vs. frequency 35 2.14 Basic circuit for application of a voltage variable capacitance diode in a tuned circuit 36 v

LIST OF FIGURES (Cont.) Figiure Page 2.15 Alternate method of increasing circuit Q 37 3.1 Discrete frequency reference (DFR) 40 3.2 Phase-lock oscillator (PLO) 41 3.3 Discrete frequency generator (DFG) 42 3.4 Generalized discrete frequency synthesizer 43 3.5 (a) Rectangular function e(t) (b) Peak factor (pf) and average power (P ) of e(t) versus the ratio r/T avg 49 3.6 Repetitive impulse (f = clock frequency) 54 3.7 Repetitive finite pulse 55 3.8 Peak factor (pf) and average power (Pavg) in the band of interest vs. the location of the 1st zero (Z) in Mc for N = 11 spectral components 58 3.9 Peak factor (pf) and average power (Pavg) in the band of interest vs. the location of the lst zero (Z) in Mc for N = 26 spectral components 59 3.10 Peak factor (pf) and average power (Pavg) in the band of interest vs. the location of the lst zero (Z) in Mc for N = 51 spectral components 60 3.11 Location of 1st zero (Z) in Mc vs. the number of spectral components (N) for maximum power in the band of interest 61 3.12 Digitally-generated linear maximal sequence 62 3.13 Digitally-generated linear maximal sequence where r < 1/fc 63 3.14 Peak factor vs. pulse width (X) for fixed clock frequency (fc) 64 3.15 Modulo-two addition table 65 3.16 A simple shift-register generator 66 3.17 An equivalent lumped circuit for the two-tank variableparameter system 69 vi

LIST OF FIGURES (Cont.) Figure 3.18 Theoretical model of a single-resonance parametric amplifier 71 3.19 Frequency spectrum of a single-resonance lower-sideband up-converter 71 3.20 Plot of BJC/BT vs. amplifier gain for a given K 74 3.21 Sideband suppression in output tank before (solid curve) and after (dotted curve) application of pump 75 3.22 Block diagram of error-correcting circuit for a single-resonance lower-sideband up-converter 77 3.23 Spectrum of an AM wave 79 3.24 Comparison of the repetitive finite pulse and the amplitude-modulation technique 80 3.25 Linear FM waveform 81 3.26 Frequency spectrum of the linear FM waveform 82 3.27 Examples of useful spectra and their associated time waveforms 83 3.28 Block diagram of phase-lock loop 86 3.29 Circuit and vector diagrams of phase-detector circuit 88 3.30 First order loop pull-in behavior (n even integer) 91 3-31 Transient response plot of o (t) = l-eKt 93 Jail eo 3.32 Frequency response plot of Oi (Wj) = 1 94 i l+jE 3.33 Open-loop gain of system 99 3.34 Proportional plus integral control networks 101 3.35 Transient response of system 103 3.36 Frequency response of system 105 vii

LIST OF FIGURES (Cont.) FigurePage 3.37 Capture range of system 108 3.38 Equivalent circuit of a typical oscillator tank circuit 112 3.39 Capacitance of ferroelectric capacitor vs. tuning voltage 113 3.40 Elementary frequency combining network 120 3.41 Frequency spectrum for case N = 1, G = 20 kc 122 4.1 Two-digit synthesizer 126 4.2 Discrete-frequency reference 127 4.3 Phase-lock oscillator 128 4.4 Schematic diagram of PLO-1 129 4.5 Characteristic curve of the phase detector 130 4.6 Oscillator and reference amplitude at the phase detector coil as a function of frequency 131 4.7 Phase-detector frequency response 132 4.8 Dc amplifier gain-frequency characteristic 133 4.9 Low-pass filter attenuation vs. frequency characteristics 134 4.10 Discrete-frequency reference amplitude vs. frequency 135 4.11 Lock range vs. reference input of PLO-1 136 4.12 Lock range vs. frequency of PLO-1 with a reference input of 2 mv 137 4.13 Frequency stability vs. temperature for PLO-1 138 4.14 Frequency in Mc vs. supply voltage changes (&E) in volts of PLO-1 139 4.15 Block diagram of VCO tuning circuit 140 4.16 Simplified diagram of VCO tuning circuit 140 4.17 Circuit of simplified drive network 141 viii

LIST OF FIGURES (Cont.) Figure Page 4.18 Step response of simplified drive shown in Fig. 4.17 141 4.19 Circuit diagram of a more complex drive network 142 4.20 Expected drive and control circuit operation under switching conditions 144 4.21 Expected frequency variation under switching conditions 145 4.22 Actual drive and control circuit operation under switching conditions 145 4.23 Amplitude of spurious sidebands relative to DFG-1 output signal versus frequency 148 4.24 A relative measure of the noise output of the system 149 4.25 10 Mc output signal of DFG-1 150 ix

ABSTRACT This dissertation treats the effective utilization of nonprecise tuning components in unique techniques for precise frequency synthesis. Frequency synthesis is the generation of sinusoidal RF signals of precisely-controlled and accurately-known arbitrary frequencies. Nonprecise components which are examined in detail under the several limiting conditions of operation are solid-state devices, such as variable capacitance diodes, ferroelectric capacitors, and controllable inductors. The significance of combining a discrete-frequency reference and an electronically-tuned phase-lock oscillator in the generation of precise frequencies is that it is possible to construct a unit whose output frequency can have certain discrete values. This unit, called a discrete-frequency generator, has an output frequency which is precisely one of the harmonics of the discrete-frequency reference. By using several discrete-frequency generators, each with different incremental steps, combining,and taking the mixed output, it is possible to cover a wide over-all range in small incremental steps. The design and construction of a discrete-frequency synthesizer which tunes over a 1-Mc range in 10-kc steps (two significant figures) is carried out to demonstrate the practicability of the proposed technique. The discrete-frequency reference is provided by a five-stage shift-register generator. The shift-register generator is synchronized by a cry~tal clock which has a long-term frequency stability of one part in 10. The spurious output of the synthesizer is at least 55 db below the desired output. The significant consequences of this investigation result from the extreme flexibility afforded by completely electronic tuning methods. The incorporation of the nonprecise components through the use of phaselock circuitry has made it possible to develop a technique of frequency synthesis which permits the rapid selection of precise frequencies, is adaptable to remote control, may be readily programmed, and theoretically is unlimited in frequency range of operation. x

CHAPTER I INTRODUCTION 1.1 Statement of the Problem Frequency synthesis is the generation of sinusoidal RF signals of precisely-controlled and accurately-known arbitrary frequencies. This study treats the effective utilization of nonprecise tuning components in unique techniques for precise frequency synthesis. Nonprecise components which are examined in detail under the several limiting conditions of operation are solid-state devices such as variable capacitance diodes, ferroelectric capacitors, and controllable inductors. The significant consequences of this investigation result from the extreme flexibility afforded by completely electronic tuning methods. The incorporation of the nonprecise components through the use of phaselock circuitry has made it possible to develop a technique of frequency synthesis which permits the rapid selection of precise frequencies, is adaptable to both remote control and electronic prograrmming using analog or digital methods, and theoretically is unlimited in frequency range of operation. This paper is divided into five chapters. The statement of the problem and a discussion of current techniques for providing precisely-controlled frequencies are presented in Chapter I. A study of various electronic tuning methods using solid-state devices is carried out in Chapter II. This study formulates basic decisions regarding the limitations of tuning elements and voltage-controlled oscillator circuit parameters. 1

2 The system concept of a generalized discrete frequency synthesizer is presented in Chapter III. The significant contribution of combining a discrete frequency reference and an electronically-tuned phase-lock oscillator in the generation of precise frequencies is that it is possible to construct a unit whose output frequency can have certain discrete values. This unit, called a discrete-frequency generator, has an output frequency which is precisely one of the harmonics of the discrete-frequency reference. By using several discrete-frequency generators, each with different incremental steps, combining and taking the mixed output, it is possible to cover a wide over-all range in small incremental steps. The question of how to minimize for a given power spectrum the peak-to-peak amplitude of a signal is presented. A term peak factor is defined and a relationship which can be effectively used as a figure of merit in the design of an appropriate frequency spectrum is developed. In addition, a study and evaluation of various methods for the efficient production of high-order harmonics with balanced energy in the frequency band of interest is carried out. Of the various methods presented for generating a discretefrequency reference, the shift register generator method is particularly interesting. The digitally-generated linear maximal sequence fulfills the condition of minimum peak factor while providing a reasonably uniform amplitude spectrum over a given band of interest. From a practical point of view, the shift register generator is simple to implement. Logic modules can be taken off the shelf and put together to form a discrete frequency reference. In addition, by using clock dividers and coincidence gates in conjunction with the shift register generator, it is possible to obtain any number of discrete frequency references

3 each with different incremental steps. Also in Chapter III an analysis of the problem of combining two signal frequencies to obtain a single signal frequency in the form of their sum or difference while using phase-lock oscillators of a practical design is carried out. Many authors have attempted to describe the various performance characteristics of the phase-lock oscillator loop but no one of these has treated the aspect in a manner sufficiently complete for the present purposes. Therefore, the basic operating principles of a phaselock loop are presented and analyses are made in instances where the literature is not complete. For example, an analysis is carried out to determine frequency sensitivity, loading effects, and other characteristics of voltage variable capacitors when used as the tuning element in an oscillator tank circuit. Based on this analysis a figure of merit is developed which is defined as the product of the frequency sensitivity S and the Q of the oscillator tank circuit. In addition, equations for the convergence time of a phase-lock oscillator loop are developed. In Chapter IV the design, construction, and testing of a two-digit synthesizer are carried out to demonstrate the practicability of the system. Chapter V is devoted to a summary and conclusions. Suggestions for further research are presented and specific applications in which the proposed technique for precise frequency synthesis would be particularly useful are given. 1.2 Survey of Other Methods of Precision Frequency Synthesis The development of frequency control circuits will be traced briefly and the technical forces causing their evolution will be discussed.

1.2.1 Tunable LC Oscillator. The simple tunable LC oscillator was a practical way of generating channel frequencies when crowding of the spectrum was not a problem and frequency inaccuracies could be tolerated. 1.2.2 Crystal Oscillator. Crowding of the spectrum necessitated closer channel spacing and increased frequency accuracy. The increased frequency accuracy was provided by the crystal oscillator. 1.2.3 Multiple Crystal Frequency Synthesizer. As it became apparent in multi-channel equipment design that a choice of one of hundreds of channels was required, the multiple crystal synthesizer was developed (Ref. 1). The principle is illustrated in Fig. 1.1. The F1S F, X | FIRST'F +F. (f,+f,+Af,) MIXER SYNTHESIZED f f,+AfI+2 f,+nf, OUTPUT IN RANGE (f' + f,)-(f, + f2+ n Af2+ n Af, ) SEZN XTAL OSC I" I I I f f+2f f+f 2Af f+ nf2 Fig. 1.1. Block diagram of a multiple crystal frequency synthesizer.

frequencies of several crystal oscillators were mixed to produce the desired output frequencies. Each oscillator was provided a means of selecting one of ten or more crystals so that a large number of channel frequencies could be synthesized. 1.2.4 Single Crystal Frequency Synthesizer. To accommodate additional channels the channel spacing was reduced. This, however, necessitated maintaining channel frequencies within a tolerance as small as -2 part per million. A system proposed by H. J. Finden (Ref. 2) retains the advantages of the multiple crystal synthesizer but eliminates the problem of maintaining a large number of crystals to the same accuracy. The accuracy and stability of the output signal are esentially equal to that of the reference oscillator. The principle is illustrated in Fig. 1.2. BAND m _ IER m IXER, PASS.~+,FILTER SYNTHESIZE R Io0m K OUTPUT 100 [L+ ]K.C. REF, OSC. l00 K.C. IOOL KC Fig. 1.2. Block diagram of a single crystal frequency synthesizer.

6 Basically, the single crystal frequency synthesizer is a circuit in which harmonics and subharmonics of a single standard reference oscillator are combined to form a multiplicity of output signals which are all harmonically related to a subharmonic of the standard reference oscillator. 1.5 Stabilized Master Oscillator Frequency Synthesizer 1.3.1 Servo System. A system proposed by E. W. Pappenfus (Ref. 3) and G. J. Camfield (Ref. 4) uses an indirect technique in which the output frequencies are obtained from a variable oscillator, which in turn is controlled by reference crystal oscillators. The principle is illustrated in Fig. 1.3. The control is both mechanical OSCILLATOR MOTOR RELAYS REACTANCE MOTOR DIRECTION CONTROL F VALVE RACTANC M DIRECT CURRENT FREQOUENCY FREUENC PHASE FILTER FILTER CHANGER r -CHANGER- IDNATOR _-f, F-f, f2 F-f,-f2 t f3 REFERENCE REFERNC REFERENCE CRYSTAL CRYSTAL CRYSTAL OSCILLATOR OSCILLATORI OSCILLATOR Fig. 1.3. Block diagram of a stabilized master oscillator frequency synthesizer. (Servo System)

7 by means of a tuning motor and electronic by means of a reactance tube. The frequency F1 of the variable oscillator is varied until the output from the second filter reaches the frequency fr, at which time the phase discriminator operates and the tuning motor automatically stops. When the motor stops, F = fl + f2 + f3' F may be changed by altering any of the reference crystals. If the system used twenty crystals in two groups of ten each to control the first two reference oscillators (so that fl and f2 could each have any one of ten values), then F could have any one of a hundred values. Admittedly, if ten harmonics of a single crystal-oscillator had been used for each group a hundred frequencies for only two crystals could be obtained. It was felt, however, that high-order harmonic selection involves the use of precision circuits which must be maintained accurately on tune and which may offer the possibility of being tuned to an incorrect harmonic. In addition, a unit comprising one crystal plus harmonicselection circuits tends, if anything, to be larger and to require more power than a unit using a number of crystals. For the system to operate satisfactorily, the open loop set-on accuracy of the master oscillator must be within +5 kc. This is accomplished by constructing a very stable mechanically-tuned oscillator with a reactance tube in the tank circuit for lock-on purposes when the oscillator is brought within the +5 kc limitation. The stability of the system described above depends upon the stability of the frequencies used at the translating mixers. 1.3.2 Sampled Data System. A system proposed by N. G. Alexakis (Ref. 5) uses an entirely different principle, i.e., a preset frequency counter, to tune and stabilize a master oscillator. The

8 basic elements as shown in the block diagram of Fig. 1.4 are a voltage-.OUTPUT VOLTAGE TUNED PRESET MASTER|RRORROR DET. TIME ERROR SIGNAL _ SYSTEM TIMING SIGNALS TIME REF. OSC. Fig. 1.4. Block diagram of a stabilized master oscillator frequency synthesizer. (Sampled Data System) controlled oscillator, preset counter, timing signal and error detector. The fixed reference time interval is compared with the variable interval required by the counter. If the variable time is less than the one-second fixed interval, then the master oscillator frequency is too high. If the variable time is greater than the reference interval, the master oscillator frequency is too low. The error signal thus developed is a constant-amplitude pulse of varying duration and either

positive or negative polarity. The voltage-controlled master oscillator requires a proper dc voltage to reduce the error to zero. This voltage is derived from the time-varying error signal by an integrating circuit. 1.4 The Status of Current Work —Summary As indicated in previous sections, several direct approaches to frequency synthesizers have been made. Using multiple decks of crystals and mixing the outputs of several crystal oscillators is one method. A second method uses only one crystal oscillator of high precision which is fed to multiplier-divider chains and harmonic generators. The desired harmonic in each decade bank is selected by mechanicallytuned high Q filters, and the outputs of the various filters are suitably mixed to furnish the desired output frequency. A further refinement in this area is the use of a variable frequency master oscillator to obtain the desired frequency. The master oscillator is in turn controlled by reference to crystal oscillators. The control in this case is both mechanical and electronic. The final system described which uses a voltage-controlled oscillator and a preset counter to obtain the desired frequency output has much to recommend it since it is a straightforward and quite simple technique. The significant consequences of the proposed technique result from the extreme flexibility afforded by completely electronic tuning methods. The incorporation of the nonprecise components through the use of phase-lock circuitry has made it possible to develop a technique of frequency synthesis which permits the rapid selection of

10 precise frequencies and is adaptable to both remote control and electronic programming, using analog or digital methods. Theoretically, this technique is unlimited in frequency range of operation.

CHAPTER II HISTORICAL BACKGROUND ON THE STUDY OF ELECTRONIC TUNING METHODS USING SOLID-STATE DEVICES 2.1 Electronic Tuni Electronic frequency control is flexible, versatile, and in many instances essential where fast frequency selection and low tuning power are required. During the past few years, two methods of electronic tuning using solid-state elements have evolved: (1) Magnetic tuning which uses the principle that the inductance in a resonance circuit may be varied by means of a magnetic bias field, and (2) Electric tuning which uses the principle that the capacitance of the resonant circuit may be varied by an electric bias field. The ideal tuning element for frequency synthesis applications, whether it uses the principle of magnetic or electric tuning, should have the following characteristics: (1) RF loss is negligibly small. (2) Tuning capabilities should extend to at least 1000 megacycles with little change in Q. (3) The temperature coefficient of frequency should be zero from minus 50 degrees centigrade to plus 100 degrees centigrade. (4) Frequency ratios should be at least 10 to 1 with relatively small control power. In 11

12 addition, the operating frequency should extend to 1000 megacycles with this ratio. (5) Frequency selection should be rapid, using step or continuous control. (6) Tuning elements should be small, compact and capable of large scale manufacture with only a small fraction of rejects. (7) Isolation of controlled and controlling signals should be possible. Since this ideal does not exist and it is unlikely that it will be developed within the next few years, the present choice for a particular tuning method and tuning element must be a compromise to obtain a close approach to the ideal in those properties most important for a specific application. 2.2 Magnetic Tuning During the past fifty years, attempts have been made to construct controllable inductors without moving parts and cover as much of the frequency spectrum as possible at a reasonable expense of control power. A controllable inductor is a device comprising a number of windings. Some of these windings carry alternating current; others, carrying direct or slowly varying current, are used to determine the magnetic state of the core and thus to control the alternating current in the winding first mentioned. The usefulness of these earlier results was limited to very low radio frequencies. Although the laminated core technique used at that time was considerably improved by the use of nickel-iron alloys and etching processes to reduce the lamination thickness, difficult production methods and low Q's prevented any

13 significant use of these tuning units. From 1930 to 1945 attempts were made to develop an RF tuning element using powdered iron materials. Those efforts did not produce units which could be called practical. A representative example was developed by W. J. Polydorff (Ref. 6) in 1944. The unit described produced a change of inductance of approximately 4 to 1 and had a Q of 50 in the frequency range of 200 to 400 kilocycles with a control power requirement of 25 watts. The weight of the unit was in excess of 25 pounds. Since 1945, a new class of magnetic core materials called ferrites has been developed (Ref. 7). These materials, which have a wide variation of permeability with applied field, have enjoyed prominence in the magnetic tuning field because of their high resistivity and freedom from eddy-current losses at high frequency. Fig. 2.1 shows a schematic representation of a controllable inductor having one signal winding and two control windings. The signal winding is drawn in two sections, shown orthogonal to the control winding, to indicate that inductive coupling between the control and signal windings MAGNETIC SHIELD 7 1 CONTROL I WINDING NO. I I (A.F. C.)_n jO 4 I I SIGNAL o |8 5:WINDING CONTROL I WINDING NO.21 2 3 1 I I I CL cnrlae inducoJ Fig. 2.1. Schematic diagram of a typical controllable inductor.

14 has been cancelled. A magnetic shield surrounds the ensemble to prevent stray fields from influencing its behavior. Ferrites used as magnetic core materials consist of oxides of metals and are formed at high temperatures. All materials that exhibit ferromagnetism are paramagnetic when heated above the Curie temperature.i Permeability ([) of a magnetic material is defined as the ratio of B/H where B is the flux density in lines per square centimeter (gauss) and H the magnetizing force in gilberts per centimeter (oersteds). The permeability of the magnetic material is low at low flux density, maximum at some moderate flux density, and quite small when the core is saturated. The permeability at low magnetizing force (the limit as B and H approach zero) is called the initial permeability (so). In addition to the previous terms there is another term called incremental permeability (do) which is a function of LH and H The magnetic quantities involved are shown in Fig. 2.2. The dotted +8 / I IOI I IA / aH - H3- HH /~~~~~Ho _- 1I/2(H3+HI) __-_ -- 11 -A Fig. 2.2. Definitions of magnetic parameters. Curie temperature —point below which the material ceases to be paramagnetic.

15 curve represents a B/H or hysteresis loop for some magnetic material. The solid curve shows the change in magnetic flux density B under the influence of a small cyclical variation in magnetic field. Although B is a double-valued function of H, it is possible to define incremental permeability as ~& = ~B//AH as the material is cycled around the path 1-2-3-4-1. Ho is the mean value or dc component of the magnetic field. Incremental permeability is also defined as the permeability offered to an ac magnetizing force superimposed on a dc magnetizing force. In describing a ferrite material we must know its history, Ho, AH and the frequency of operation. The initial permeability o0 for very small or zero flux densities is an inherent property of the material under consideration. For various ferrite materials in which we are interested the,io lies between 2 and 1500. The incremental permeability (M,,) of a ferrite material decreases monotonically with increasing H for a constant AH. The maximum theoretical change in permeability is 0,/,c where.Lc is the permeability at saturation. Since p c approaches unity, the maximum change in inductance is proportional to io. The maximum change in frequency we can expect due to the permeability change is max fmin From a practical point of view the hysteresis effect simply means that if the control current is raised from zero to a given value, one signal inductance is obtained. If the same control current value is approached from a high current setting, a different value of signal inductance will occur.

16 Magnetic tuning units are now being produced with very good stability. By a suitable choice of core material there is generally a value of control current for which the temperature coefficient over a broad temperature range is substantially zero, with coezficients of opposite sign on either side of this current setting. Signal winding coefficients of 0.5%/0C are encountered, although more typical values are 0.1% to 0.2*. At frequencies up to 10 megacycles, inductance change ratios in the hundreds are feasible. Typical units designed for applications between 10 and 50 megacycles have ratios in the order of 30 to 100. In the 50 to 100 megacycles range, this drops to between 3 and 6; and above 100 megacycles to less than 2. The curve of Fig. 2.3 shows the l00 Lcmx. Lcmin 50 0 50 100 200 FREQ., IN MC: L max Fig. 2.3. L m- of typical magnetic tuning unit vs. frequency. c ratio of maximum to minimum inductance plotted versus frequency. Representative Q values are in the low hundreds for frequencies up to several megacycles. They range between 40 and 100 for frequencies up to 50 megacycles, dropping to between 10 and 50 at 100 megacycles and perhaps 5 to 10 at 200 megacycles. The curve of

17 Fig. 2.4 shows the typical values of Q plotted versus frequency. 100 50 00L I I I 0 50 100 200 FREQ. IN MC: Fig. 2.4. Q of typical magnetic tuning units vs. frequency. Figure 2.5a illustrates the basic circuit for application of c) t r C -L'C Lc I Lc (a) (b) L = controllable inductance c r = loss associated with controllable inductance L = loss free inductance C = total capacitance in tank circuit Fig. 2.5. Basic circuit for application of a controllable inductance L in a tuned circuit.

18 a controllable inductance in a typical tank circuit. It may frequently be true that the tuning ratio (TR) may be greater than necessary but the circuit Q may be unacceptable due to inherent losses in the controllable inductance. Fig. 2.5b depicts a method of increasing the tuned circuit Q by including a small loss-free coil in shunt with the controllable inductance. AL c (2.1) Qcoil r L max TR c coil L min c The Q of the controllable inductance with the loss-free coil in shunt is Qcircuit Qcoil L (2.3) while the tuning ratio becomes L min + L 2 T circuit TRcoil L maxx + L (2.4) If L > > L then the frequency range will be determined by the available inductance range of the controllable inductance. However, if Lc > > L then a definite gain in Q may be achieved only through a loss in effective inductance variation range. The control power required to obtain the full inductance variation of low level units is approximately 1 watt. Some commercially available inductors, however, have been made to operate at a level of about 0.1 watt. The control power is interrelated with the required

19 L max Lc ratio and frequency and will vary somewhat. The relationship L min C between control current and signal inductance is nonlinear, the percentage change in inductance per unit control current being greatest for small control current values. Since this is undesirable, appropriate compensation circuitry has been developed. Since step frequency control of the proposed synthesizer is envisioned, the problem of furnishing the electronic means for magnetic tuning may become quite difficult. The following typical example serves to illustrate the seriousness of the problem. In the frequency range 1 to 3 Mc, it is desired to step from 1 to 2 Mc in 1 microsecond. The circuit has the following properties: Control inductance = 3 henries Required control current shift = 10 ma lo6 Control voltage e = L = 3 x.01 x 10= 30,000 volts Peak control power p = 300 watts A voltage of 30,000 volts presents not only a serious problem in control circuit design, especially in transistor circuits, but also in voltage insulation in the design of the control winding itself. The voltage across the control winding may be reduced at the expense of a larger control current. Since the magnetic field is proportional to the number of ampere turns (NI) and since the inductance of the control winding is proportional to N2, then by reducing N by a factor 10 the control circuit has the following properties: Control inductance =.03 henries Required control current shift = 100 ma

20 Control voltage = L di =.03 x.1 x 10 = 3,000 volts dt Peak control power = 300 watts An improvement is achieved in the voltage across the control winding but at the expense of increased control current. In both cases the power calculation of 300 watts is an instantaneous or peak demand lasting only 1 microsecond. In conclusion, the study and development of ferrite material has resulted in a controllable inductance having a volume less than one cubic inch, weighing slightly over one ounce, and being capable of tuning a frequency range of 7 to 1 at 1 Mc to 1.5 to 1 at over 200 Mc. Q's of the order of 100 - 10 are obtained over this frequency range and the average temperature coefficient of the elements is below.03%/0C. 2.3 Electric Tuning Increasing interest in the use of voltage-variable capacitors for electronic frequency control has resulted in the development of two different classes of capacitors: (a) The ferroelectric capacitor and (b) The voltage variable diode capacitor. A clarification of the distinction between the ferroelectric capacitor and the voltage variable diode capacitor appears desirable and will be carried out in the following brief discussion. 2.3.1 Ferroelectric Capacitors. In the past decade there has been a considerable development of a new group of nonlinear dielectric materials called "ferroelectrics." These materials, although the name stems from the Latin word for iron, do not contain appreciable amounts of iron. Rather, the name indicates the close resemblance the mechanism of electrical polarization to that of the magnetization

21 of ferromagnetic materials discussed under Section 1.1. Ferroelectricity can be described as a spontaneous polarization. Polarization in dielectric materials may be due to: (1) Alignment of permanent electric dipoles, (2) Displacement of the + and - ions relative to one another (e.g., Na+ and Cl in NaCl) or (3) Displacement, relative to the positive nucleus of the negative charge of the electrons. Ferroelectricity will occur if any one of these mechanisms, either singly or in combination occurs spontaneously, i.e., without the application of an external electric field. A number of materials exhibit ferroelectricity, but on the whole the phenomenon is rather rare. Ferroelectric materials are always piezoelectric but the converse is not always true, e.g., quartz. Barium titanate (BaTiO3) is, from a practical point of view, the most important ferroelectric and, when mixed with a nonferroelectric buffer material, such as strontium titanate, becomes a suitable material for many practical applications. In a conventional capacitor a graph of Q vs. V is essentially linear, i.e., a straight line with slope (C) proportional to the dielectric constant (e). The relationship of these quantities is expressed as Q = cv (2.5) where Q is the charge stored, C is the capacitance and V is the applied voltage. In a ferroelectric capacitor the plot of charge versus voltage is not a straight line; i.e., it is nonlinear. If a complete

22 cycle of positive and negative voltages is applied, the result is a hysteresis loop as shown in Fig. 2.6. Although the hysteresis loop Ps:A STARTING POINT, UNPOLARIZED Pr. PS SPONTANEOUS POLARIZATION Pr REMANENT POLARIZATION EC COERCIVE FORCE (FIELD) P POLARIZATION - DIPOLE MOMENTS/UNIT VOLUME - COUL/ IN2 E / / / E E FIELD STRENGTH IN VOLTS/MIL: C E DIELECTRIC CONSTANT = dP/dE Fig. 2.6. Ferroelectric capacitor hysteresis loop. is not included in the definition on nonlinearity, it is exhibited by all nonlinear dielectrics and thus may be considered an inherent property. The hysteresis loop can be explained by considering the behavior of the barium titanate crystal (Ref. 8). At room temperature this crystal has a tetragonal form which is similar to a distorted cube in which one axis, the "c" axis, is elongated by a spontaneously occurring electric dipole along that direction, while the other two axes, both "a" axes, since they are identical in every respect, are shortened. The dielectric constant along the "a" axes is at least several times greater than that along the "tc" axis.

23 Along the "c" axis the polarization may have two directions, oppositely oriented, which may be called positive and negative. When the voltage along the "c" axis is varied in sign, the dipole flips from one stable position to the other. Since a finite field is necessary to reorient the dipole, there is little change in polarization until a critical field level is reached. A rapid change in crystal polarization occurs when this level is reached, and subsequent increases in field strength produce little further change in polarization. When the field is reversed, this process is repeated, with opposite polarity conditions prevailing. In the ceramic of which practical capacitors are formed, the barium titanate forms into a multitude of tiny crystallites whose spontaneous dipoles are randomly oriented. Therefore, there is no favored "c" direction, and the statistical average of the elemental orientations cancels to zero. With no biasing electric field applied to the dielectric the observed dielectric constant lies between that characteristic of the "c" direction and that of the "a" directions. It is somewhat closer to the "a" value since "a" axes are more abundant. Referring to Fig. 2.6 and beginning at point A, there is initially no net polarization before voltage is applied. When a dc bias is applied tc! the material, some of the dipoles originally oriented randomly will align themselves with the field, and a partial "c" axis is induced perpendicular to the electrode faces. As a consequence, the dielectric constant decreases. As the biasing voltage (applied field) is increased, more and more dipoles are reoriented, and the dielectric constant continues to decrease as the polarization in the new "c" direction increases. This proceeds until a further increase

24 in bias fails to yield a proportionate increase in polarization. This presumably occurs as a result of the supply of randomly oriented dipoles becoming exhausted. In the polycrystalline ceramic many of the elemental dipoles are incapable of being oriented perpendicularly to the electrode faces due to their position in the ceramic matrix. At best they can be elastically strained in the direction of the field. When the field is reduced, these strains relax and some polarization is lost. However, since a large number of dipoles are oriented into a stable condition, they remain so and the charge stored in this manner is not recovered. This makes up the remanent polarization, Pr. When the field is reversed, a certain field strength, E, is required to reduce the polarization to zero and further increase in field switches the dipoles to the reverse direction. When the field is again reversed, the plot of polarization versus field duplicates the upper path. It is seen, therefore, that the point A is not traversed again and that the process is not reversible. The behavior of a given capacitor can be shown graphically since its capacitance is proportional to the dielectric constant, c, which is the slope of the hysteresis loop. The shape of the loop is affected by the peak field strength applied, temperature and frequency as well as the material of which the dielectric is composed. In general, the sides of the loop become more vertical and the saturation region flattens out with higher peak fields. The dipole switching occurs at a very fast rate. It has been known to follow pulses of the order of 1 microsecond and smaller. The zero bias dielectric constant does fall off somewhat above the region

25 of about 700 Mc/s, and it is to be expected that the hysteresis loop will change at the higher frequencies. Another effect described by W. J. Merz (Ref. 9) which may be observed in certain ferroelectric ceramic materials is the double hysteresis loop phenomena. In this case the double hysteresis loop occurs over a rather large temperature range and is caused by a transition from a nonferroelectric state via a shift in the Curie temperature with applied field. The double hysteresis loop phenomena may be demonstrated very graphically as shown in Fig. 2.7 by means of a butterfly plot (Ref. 10). For convenience, the incremental capacity, which is proportional to the eA of the sample is plotted against the applied field. From a practical point of view the hysteresis effect means that if the control voltage is raised from zero to a given value, one signal capacitance is obtained. If the same value of control voltage is arrived at from a high voltage setting, a different value of signal capacitance will occur. Presently available ferroelectric capacitors have relatively poor temperature stability (Ref. 11). There is no value of control voltage that gives a zero temperature coefficient over a wide temperature range as was the case in ferrite tuning. The design of circuits using ferroelectric tuning which must operate over a wide range of ambient temperatures must therefore include temperature control of the capacitors. This is not a serious peoblem, however, because of the very small volume occupied by the capacitors. It is not difficult to build a capacitor tuning unit and a olow-watt thermostatically-controlled heater in a miniature oven having a volume of.01 cubic inch.

400 o o ~~390 ~~~ —- o O~0 380 200 150 0 50 150 200 250 o 350 2_50 200 150 1 00 50 50 00VLTS 150 200 LS VOLTS PER I0 MILS Fig. 2.7. The static capacity-field butterfly loop for a typical ferroelectric ceramic.

27 Figure 2.8 demonstrates the stability of a typical ferroelectric capacitor with and without the use of the thermostating techniques. The temperature of the environment was varied from +400C down to -200C. In both cases, the ratio of the value of capacity at various temperatures to that at 400C was plotted as a function of temperature in degrees C. 14 I 0 0 12 A 0 I 0 07 ~x 0 - 0 8 - -o THERMOSTATICGALLY CONTROLLED 0_ A- NOT THERMOSTATICALLY CONTROLLED 07 0 06040 30 20 10 0 210 -20 4- TEMPERATURE, C ~ Fig. 2.8. Ratio of capacitance, C /C, vs. temperature x0 40~' in degrees centigrade.

28 At frequencies up to 100 Mc ferroelectrics are available with capacitance change ratios in the order of 10:1 at a field strength of about 100 volts/mil. The capacitance tuning ratio drops to perhaps 8:1 at 1000 Mc and to about 2:1 at 3000 Mc for the same field strength. The curve of Fig. 2.9 shows the ratio of maximum to minimum capacitance plotted versus frequency. 10c max Cc min 5. I,,,,,, I I 0 500 1000 FREQ. IN MC C max Fig. 2.9. c of typical ferroelectric C min capacitor vs. frequency. Representative Q values in the order of 100 are available for frequencies up to about 10 Mc. The Q values are in the order of 50 at 100 Mc, 10 at 1000 Mc, and about 3 to 6 at 3000 Mc. The curve of Fig. 2.10 shows typical values of Q plotted versus frequency. Since in a tuned tank circuit both Q and frequency increase with an increasing bias field, a reasonable Q is maintained over the tuning range.

29 1000 50 0oo 500 1000 FREQ. IN MC Fig. 2.10. Q of a typical ferroelectric capacitor versus frequency. Figure 2.11a illustrates the basic circuit for application of a voltage variable capacitance in a tuned circuit. In many cases, the circuit Q may be satisfactorily high when this simple circuit is used, and if C0 is chosen much larger than the maximum capacitance of the ferroelectric, the frequency range will be determined by the available capacitance range of the ferroelectric. However, it may often be true that the losses in the ferroelectric material cause an unacceptable decrease in circuit Q. Fig. 2.11b depicts a method of increasing the tuned circuit Q by including a small loss-free capacitor (C) in series with the ferroelectric.

30 DECOUPLING L ffLC L c L CAPACITOR SIRESISTOR BIAS (a) (b) L = total inductance in tank circuit r = loss associated with ferroelectric capacitance C = loss-free capacitance C = controllable capacitance (ferroelectric) Fig. 2.11. Basic circuit for application of a ferroelectric capacitor in a tuned circuit. cap = rC( The Q of the ferroelectric capacitor with the loss-free capacitor (C) in series is Qcircuit = Qcap C C] (2.8) while the tuning ratio becomes CAPACITO R RESISTOR =loss-free capacita min + ce cirui ca Ox+ J(2.9) C max I~omin

31 If C > > CC)the frequency range will be determined by the available capacitance range of the ferroelectric. However, if Cc > > C,then a definite gain in Q may be achieved but only through a loss in effective capacitance variation range. The energy required to obtain the full capacitance variation is V max E f I C(V) ~ v dV (2.10) This energy generally results in a power demand of a few milliwatts for most low frequency-swept devices. The relationship between control voltage and signal capacitance is nonlinear, the percentage change in capacitance per unit control voltage being greatest for small control voltage values. Since in many cases this is undesirable, shaping of the control voltage must be done to compensate for the nonlinearity. The problem of furnishing the electronic means for tuning a ferroelectric capacitor is not serious. An example of step frequency control is shown below: In the frequency range 1 to 3 Mc, it is desired to step from 1 to 2 Mc in 1 microsecond. The circuit has the following properties: Control capacitance = 200 >Sif Required control voltage shift = 50 volts de -12 6 Control current i = C = 200 x 10 x 50 x 10= 10 ma dt Peak control power P =.010 x 50 =.5 watt for 1 microsecond A control current of 10 ma may be easily obtained from transistor circuits, so the design problem is reasonably simple.

32 In conclusion the study and development of ferroelectric material has resulted in a controllable capacitance having a volume less than.001 cubic inch, weighing a few grams, and being capable of tuning a frequency range of 10 to 1 at 100 Mc to 3 to 1 at over 3000 Mc. Q's of the order of 100 - 3 are obtained over this frequency range. Coefficient of capacitor drift with temperature depends upon bias voltage and for a nominal bias voltage is about l%/0C. 2.3.2 Voltage Variable Diode Capacitor. The voltage sensitivity of semiconductor junction capacitance was understood prior to 1940. Not until recently, however, has this property been exploited for broad use in electronic circuitry (Ref. 12). The reverse voltage on a semiconductor junction is supported by a region which is depleted of mobile carriers, as shown by Fig. 2.12. As the applied reverse voltage is changed, the depletion width (Wd) necessary to support the voltage changes. This depleted region acts as an insulator, resulting in a capacitance which varies in an inverse manner with applied voltage. Voltage sensitivity of capacitance depends on the impurity distribution in the junction region. The more abrupt the Junction, the greater the depletion width depends on applied voltage, resulting in a higher voltage sensitivity of capacitance. For a parallel plate arrangement, the p-n junction has a capacitance equal to: C (2.11) Wd

GRADED ABRUPT HYPER ABRUPT P N P P N IMPURITY AND CARRIER DISTRIBUTION No - NI n N-N I p-n ND NA NET CHARGE DENSITY A POTENTIAL Wd Wd Wd K Wd cc V 3 Wd Cc V2 Wd cc V 2) C: 4-rWd C cc V C C: V C V-(>) Fig. 2.12. Voltage sensitivity of capacitance.

34 = permittivity of the dielectric A = junction area Wd = width of the depletion region For the case of an abrupt junction, the depletion width is given by: Wd = 1 = K1 + (2.12) combining Eqs. (2.11) and (2.12) for an abrupt junction C = K eA (2.13) K1Vo where K = a constant V, = applied bias voltage V = internal contact potential (0.3 to 0.9 volts) When V is small with respect to V an abrupt junction exhibits a capacitance which varies with the inverse square root of voltage. Other capacitance voltage functions may be obtained across differently graded p-n Junctions. If, for example, the semiconductor changes from p to n in a linear manner the capacitance varies as the inverse cube root of the applied voltage. Voltage variable capacitance diodes have relatively good temperature stability (Ref. 13). The capacitance is fairly independent of temperature at the higher bias levels and becomes increasingly more sensitive with decreasing bias levels. This agrees quite closely with theory since the major uncompensated temperature effect is the internal contact voltage, VO, term in Eq. (2.13). For silicon, VO is approximately V V~~~~~~~~~~

35.08 volts at 25 C and decreases to.04 volts at 150 C. The result is an approximately linear temperature sensitivity of about.15%/~C at 0.5 volts,.025*/OC at -4 volts, becoming negligible at higher voltages. At frequencies up to 50 Mc voltage variable capacitance diodes are available with capacitance change ratios in the order of 5:1 with a voltage change of -2 volts to 100 volts. Using special fabrication techniques capacitance change ratios of 5:1 may be maintained up to several hundred megacycles. Representative Q values in the order of 100 at 50 Mc can be obtained commercially. The value of Q drops to about 10 at 500 Mc and to about 5 at 1000 Mc. The curve of Fig. 2.13 shows typical values of Q plotted versus frequency. Since the Q of the capacitor equals C and r remains practically constant over a wide frequency range, c the product Qf remains practically constant, giving a curve which is a rectangular hyperbola. 100 0 500 1Q00 FREQ. IN MC Fig. 2.13. Q of a typical voltage variable diode capacitor vs. frequency.

Figure 2.14 illustrates the basic circuit for application of a voltage variable capacitance diode in a tuned circuit. In many cases, BLOCKING CAPACITOR r L C ACIT O r L Cc DECOUPLING II PI PI ~~~~~~~~~~~~RESISTOR Co L BIAS 0 BIAS Fig. 2.14. Basic circuit for application of a voltage variable capacitance diode in a tuned circuit. the circuit Q may be satisfactorily high when this simple circuit is used, and if Co is chosen much larger than the maximum capacitance of the diode, then the frequency range will be determined by the available capacitance range of the diode. However, it may often be true that the diode's reverse losses cause an unacceptable decrease in circuit Q. The same method of increasing the tuned circuit Q as described on pages 29-30. for the ferroelectric capacitor may also be used for the diode. Although the gain in Q is offset by loss in effective variation capacitance range, it does reduce the amount of ac across the diode —a desirable feature, because if the ac were an appreciable fraction of the lowest bias voltage applied, there would be modulation of the capacitance of the diode by the signal. Figure 2.15 presents a suggested arrangement of two diodes in such a way as to increase the circuit Q (if this is found to be

37 seriously reduced by losses in a single diode), while retaining a relatively large available capacitance sweep. |r 4BLOCKING CAP Cc c DECOUPLING r 4 RESISTOR BIAS Fig. 2.15. Alternate method of increasing circuit Q. The energy required to obtain the full capacitance variation generally results in a power demand of a few milliwatts for most low frequency-swept devices. As in the case of the ferroelectric capacitor the relationship between control voltage and signal capacitance is nonlinear, the percentage change in capacitance per unit control voltage being greatest for small control voltage values. Since in many cases this is undesirable, shaping of the control voltage must be done to compensate for the nonlinearity. The problem of furnishing the electronic means for tuning a voltage variable capacitance diode is not serious,and as in the case of the ferroelectric capacitance the control current may be easily obtained using transistor circuits. In conclusion the study and development of voltage variable capacitance diodes has resulted in a controllable capacitance having a

38 volume less than.01 cubic inches, weighing a few grams and being capable of tuning a frequency range of 5 to 1 up to several hundred Mc. Q's of 100 at 50 Mc dropping to a value of 10 at 500 Me are readily available. The coefficient of capacitor drift with temperature depends upon bias voltage, and for a nominal bias voltage of -4 volts is about.025%/~C. 2.4 Conclusion From the foregoing discussion it is evident that the choice of a tuning element for frequency synthesis applications depends upon many factors such as frequency range of operation, tuning ratio, rapidity of frequency selection, temperature stability, control power, and environment in which the device is to be operated. No one tuning element possesses all the characteristics of the ideal tuning element discussed in Section 1.1. The controllable inductor,for example, has a high tuning ratio and Q, particularly in the lower frequency ranges with relatively small control power and good temperature stability. In addition, isolation of the controlled and controlling signals is possible. The controllable inductor presents some problems in control circuit design when step frequency operation is required and might create some difficulty if microminiaturization of the circuitry were a necessity. The ferroelectric capacitor has a substantial tuning ratio and Q over a wide frequency range with almost negligible control power. The ferroelectric capacitor does not present any problems in control circuit design when step frequency operation is required and due to its very small size is well suited to microminiaturization. It has, however, rather poor temperature stability and in most cases would require a thermostatically controlled oven for proper operation. Since the controlling signal is nearly always at a lower frequency compared

39 to the controlled signal, isolation is easily accomplished using decoupling circuits. The voltage variable capacitor diode has an adequate tuning ratio and Q for many applications over a wide tuning range and with negligible control power. It does not present any problems in control circuit design when step frequency operation is required and due to its small size is well suited to microminiaturization. It has good temperature stability and does not demonstrate any hysteresis effects. However, where high RF voltage may be developed across them, the junction must be back-biased far enough so that no part of the signal voltage swing causes the net voltage applied to the junction to go positive, or clipping will result. As in the case of the ferroelectric capacitor, isolation of the controlled and controlling signals is easily achieved by using a decoupling circuit. The self-heating of ferroelectric and back-biased diode capacitors is considerably less than that of a controllable inductor for the same type of service. In addition, lead inductance limits controllable inductor operation at high frequencies whereas lead inductance does not necessarily dilute the tuning range of ferroelectrics and diodes. In general it can be said that the present choice for a particular tuning element must be a compromise in order to obtain a close approach to the ideal in those properties most important for a specific application. A comprehensive tabulated comparison of electronic tuning devices is carried out in Appendix A.

CHAPTER III ANALYSIS OF THE GENERALIZED DISCRETE FREQUENCY SYNTHESIZER 3.1 System Concept The analysis of the generalized discrete frequency synthesizer may be better understood by first considering the building blocks. The system is essentially comprised of two basic units: (1) A crystal (or other high precision frequency standard) controlled discrete-frequency reference (DFR). (2) A wideband phase-lock oscillator (PLO). As shown in Fig. 3.1, the DFR consists of a crystal-controlled clock oscillator, multiplier or divider chains, a harmonic generator having an output rich in harmonics, and a band-pass filter. LLA LiliL AJLLL KiK\ |MULTIPLIER | HARMONIC | [BAND-PASS C~L. OCK OI -oR GENERATOR FILTER. Fig. 3.1. Discrete frequency reference (DFR). Ideally, the filter output consists of a limited set of harmonics of approximately equal amplitude. For example, the filter output could contain components every kilocycle in the band from 110 to 120 kc. Thus the output of the DFR is the equivalent of many crystal oscillators, all with a precise harmonic relationship. 40

The PLO shown in Fig. 3.2 has the function of reproducing A itI11ILO DC A CONTROL VOLTAGE f f- f, VOLTAGE DET OSC. OUTPUT FREQ, PHASE LOCK FEEDBACK PATH Fig. 3.2. Phase-lock oscillator (PLO). cleanly one of a number of frequency components applied to its input. It thus acts as a tunable narrowband filter. The voltage-tuned oscillator has its output frequency and phase compared in the phase detector with the desired harmonic of the input waveform. If these are of the same frequency, the output of the phase detector will be a dc voltage dependent upon the phase difference of the oscillator and the reference. This dc voltage is amplified and fed to the control element in the oscillator. If the oscillator frequency tends to drift or change in any way, this attempted change is first sensed as a phasedifference change in the phase detector. This produces a change in phase detector output voltage which acts to hold the oscillator frequency constant. In short, if the oscillator tends to drift, its output phase relative to that of the reference will change but its average frequency (fl) will remain fixed. Note that in automatic frequency control systems the frequency

42 of the oscillator is compared to a reference frequency, e.g., the resonant frequency of a passive circuit, and the frequency difference — not phase difference —is used to generate a signal which tends to reduce the frequency difference. Such a system requires a small but finite error of the controlled variable (the output frequency) in order to operate. The phase-lock system, on the other hand, requires no steady-state error of the controlled variable but instead utilizes an error in the integral of the controlled variable, i.e., an error in phase difference. When not in phase-lock the oscillator frequency may be brought within the capture range of the desired harmonic by means of the externally applied dc voltage. By combining the discrete-frequency reference, Fig. 3.1, and the phase-lock oscillator, Fig. 3.2, it is possible to construct a unit whose output frequency can have certain discrete values. This unit, called a discrete-frequency generator (DFG), (Fig. 3.3) has an output }A AI f --- fI K C\ ( DISCRETE PH ASE CLOCK so FREQ LOCK P REF ~DFR- OSC (PLO) OUTPUTFREQ DC CONTROL VOLTAGE Fig. 3.3. Discrete-frequency generator (DFG).

43 frequency which is precisely one of the harmonics of the discrete-frequency reference. The number of different frequencies that can be selected is a function of the voltage-tuned oscillator set-on accuracy. If, for example, it is desired to tune the DFG over a 10 Mc range and, in addition, if it is assumed that the relatively unprecise tuning elements will not allow open-loop set-on accuracies greater than about t 5 percent, then the DFG can only cover the 10 Mc range accurately in 1 Mc steps. This, in effect, means that the discrete-frequency reference can not have components spaced any closer than 1 Me over the 10 Me band. Starting with this as a basic unit to produce one digit of the desired frequency, decade units are added to furnish the desired number of significant figures. Operations and details of a proposed generalized discretefrequency synthesizer may be understood with the aid of the example shown in Fig. 3.4. 10 f, + I Aaf, A-O r- DFG - I |f+ 3Af, e m [fi+ 3Af] + n [f2+ 5Af ] DC CONTROL [f, ] 3f [f, 5Af |+AIVOLTAGE i"A M C -ex DFG - 2 DC DCCONTROL MC OER PLO* 2 IT 0 VOLTAGE M-2 g +C a A d AO DFG - - DC CONTROL VOLTAGE Fig. 3.4. Generalized discrete-frequency synthesizer.

44 A single clock oscillator and suitable multiplier divider chains furnish the basic frequency Afi (i = 1, 2,..., k, for DFG-i; i = 1, 2,..., k, where Af.i is the harmonic spacing of DFG-i). The range of DFG-i is fi to (fi + 9Afi) in Afi steps, and if it is assumed that Zf1 > 6Af2 >... > Afk then the total range of the k-digit synthesizer is lO6fl in Afk steps. For example, if ZfI = 5 Mc and fk = 100 kc, the range of the synthesizer is 50 Mc in 100-kc steps. As indicated in Fig. 3.4, the range of DFG-1 is fl to (fl + 9I fl) in f1 steps, and of DFG-2 is f2 to (f2 + 9Af2) in Laf2 steps. Single output frequencies, e.g., fl + A~fl from DFG-1 and f2 + Baf2 from DFG-2, are fed to mixer (M-l). The output of the mixer contains components m(fl + AZfl) + n(f2 + Bmf2), where m and n are positive or negative integers. The output of the mixer is fed to the phase-lock oscillator (PLO-1), whose operating range is confined to the frequency range (fl + AZfl) +/(f2 + BhAf2), where +/- means either + or -. Higher-order harmonics in the mixer output which happen to fall within this band are of such low amplitude that they are ignored by PLO-1. The voltage-tuned oscillators in DFG-1 and DFG-2 are brought to the approximate vicinity of the selected reference components by means of rough tuning dc voltages V1 and V2. The phase-lock loops then take over and bring the oscillators into precise frequency alignment with the selected components. The same rough tuning voltages V1 which are applied to DFG-1 are also applied to PLO-1. This brings the frequency of the voltage-tuned oscillator of PLO-1 within the capture range of the desired (fl + Af1) +/' (f2 + B/f2) frequency, where its phase-lock loop takres over and brings the oscillator into precise frequency alignment. The capture range of PLO-1 must be at

least 9Af2 wider than the capture range of DFG-1, so the same tuning voltage can effect capture at any frequency (fl + Akfl) +/- (f2 + Bf 2). Additional decades operate in a similar manner producing a final output frequency of (fl + Afl) +/- (f2 + B2f) +/..' (fk + jAfk) which has the desired range of 10 afl in Afk steps. This example shows a generalized discrete-frequency synthesizer capable of producing frequencies to k digit accuracy with high precision, since the whole system is crystal-controlled by a single clock oscillator. The synthesizer system may be further modified to give any desired frequency between the steps of the lowest order digit. This may be done by furnishing a vernier oscillator at the low frequency tuning range of Skfk. The operating range of the synthesizer may be placed in any desired position in the frequency spectrum up to approximately 300 Mc with presently available transistors and solid-state tuning elements. As indicated in Chapter I, to achieve an efficient synthesis technique basic research in a number of problem areas is required. For example: (1) A study and evaluation of the various methods for the efficient production of high-order harmonics with balanced energy distribution over the frequency band of interest is required. (2) Basic research in phase-lock oscillator design with particular attention directed toward operation at higher frequencies and toward such dynamic characteristics as capture range, capture stability, rapid frequency convergence, and purity of the output signal is needed.

(3) An analysis of the problem of combining two signal frequencies to obtain a single signal frequency in the form of their sum or difference while using tunable narrowband filters, i.e., PLO's of a practical design with arbitrarily-limited frequency discrimination characteristics, is required. These problem areas will be considered in detail in the following sections. 3.2 Discrete Frequency Reference To initiate the study and evaluation of the various methods for the efficient production of high-order harmonics with balanced energy distribution over the frequency band of interest, a generalized statement of the problem is in order: (1) What class of time functions will produce a given frequency spectrum? (2) Of this class which functions will have the maximum amount of the total available spectrum energy in the band of interest and at the same time have a minimum peak-to-average voltage characteristic? (3) What practical methods are available for generating these desirable functions? 3.2.1 Definition of Peak Factor. Any periodic function with period T which may be represented by a Fourier Series has the form E c e(t) = + nl En cos (rxo t + e ) (3.1) where Eo,, ek (k =, 2, 3,...)are all real and co = -.

47 The average power of e(t) across a 1-ohm resistor is defined as follows: T2 Pavg 1 T [e(t)] dt (3.2) avg T Parseval's theorem states that whenever e(t) is bounded and integrable over the period then 1 T 2 1 2 T Of [e(t)] dt 1 [E2 + E 2] (3.3) Let f(t) = A cos (wt + e) (3.4) where f(t) is a single frequency function with peak value A. The average power of this single frequency function is 1 2 T A avg [A. = (3.5) and is completely independent of both frequency and phase. If the average power of the single frequency function f(t) is equated to that of the arbitrary periodic function e(t), one finds that 2 2 1E E 2 _ n (3.6) 2 2 n or E 2 ^ - A n1 + n En (3.7) A term "peak factor" may now be defined as the ratio of the peak-to-peak value of any function e(t) to the peak-to-peak value of

48 a sine wave function f(t) of equivalent average power. P-P value of e (t), Peak factor = pf = P-P value of sine wave ft (38) of equivalent average power From Eq. (3.8) it iE clear that the pf of a sine wave function is unity. To determine the absolute upper and lower limits over which the peak factor may be expected to range, consider the pf of a function e(t) under the following conditions: Let e(t) = E e(t)mi = E. etmax max min min O<t<T O<t <T where: E > OB E <0 max - mn - The above requirements merely state that functions with large dc values are excluded. The peak factor of such a function may be written as E - E pf = max min (3.9) 2 f [e(t)]2 dt For fixed values of E and Emin the pf is determined solely by the max in value of the integral T 2 of [e(t)] dt. The value of this integral is a maximum when E max = JE in| and e(t) is always equal to EB or EB. The pf under these conditions reaches max min its minimum

2 E Pfi. max 1 =.707 (3.10) min 2 /T E dt To max The upper bound of pf is quickly found from Eq. (3.9); indeed, as the value of the integral goes to zero the pf goes to infinity. From the above analysis it may be concluded that the absolute range of the peak factor is from a minimum value of.707 to a maximum value of infinity. To demonstrate this fact somewhat more graphically consider the peak factor of the function e(t) shown in Fig. 3.5(a). 40 eo(t) E2 E max. TPf 1ePfa Pavg. Pavg. (T) 1 2 20 -T/2 T / 2 +T/2 E min I0.707 0 12 25 5 IO Fig. 35.. (a) Rectangular function e(t) (b) Peak factor (pf) and average power ag) of e(t) versus the ratio ~/T. Let -E 2E max rmin max The average power of the function is P,,e(t) = 2fE 2 dt 2 E 2t O avg T max max 2T (5.11)

50 The equivalent power of a sine wave as given in Eq. (3.5) is P = (3.12) Equating these two functions gives 2 _ 2 E 2 T (3.13) 2 max 2T or 2E max (3.14) max T The peak factor becomes E E pf max min (3.15) 2A pf 1 1 2 (3.16) 2 T 2T If E is held constant, then pf goes to infinity as ~ goes to zero and max pf goes to.707 as T goes to T. As the pf goes to infinity, the power in the spectrum goes to zero; and as the peak factor goes to its minimum value of.707, the power in the spectrum reaches a maximum. The results of pf and Pavg plotted vs. the ratio of T are shown in Fig. 3.5(b). In the particular case discussed above, i.e., the rectangular wave, one might conclude that operation at the point of maximum power in the spectrum and minimum pf would be ideal, but it must be remembered that although the spectrum power is a maximum it is predominantly rich in low frequency content while the power in the desired band of interest

51 may be very low. From the above analysis one can see that the peak factor is a necessary but not sufficient condition to be effectively used as a figure of merit in the design of an appropriate frequency spectrum. In general, a relationship is needed which takes into consideration both peak factor and the ratio of power in the band of interest to the total available spectrum power. Such a relationship can be defined as: pf* = pf P T (3.17) I where pf is the peak factor as defined in Eq. (3.8), PT is the average power of e(t) and PI is that average power of e(t) contained in the band of interest. Clearly / p ~~> ~1 ~(3.18) > I Using the relationship in Eq. (3.3) it can be shown that E 2 E - E 2 [ + n=i En ] 2E 2 E k j E 2 n n n=j n Where it is assumed that the dc term is not included in the term k 2 the eqtion reduces t n2] the equation reduces to

52 E - E f* max min (3.20) k 2 2 L.E n=j n where j and k represent the desired harmonics to be included in the band of interest. k 2 Admittedly, the sum nL 2 is not always easy to calculate n=0 n given e(t), but it can be done using straightforward techniques. On the other hand, given En rather than e(t) it is not routine to obtain the set of e(t), thus making the determination of Emax - E. very difficult. The question of how to adjust the phases of a multicomponent signal, having a given power spectrum, to minimize its "peak factor" has been a long-standing problem in multi-carrier telegraphy, radar, and many other applications in which it is desired to minimize, for a given power, the peak-to-peak amplitude of a signal. This problem has not yet yielded to a closed form of solution. An approximate solution has been suggested (Ref. 14) which considers frequency modulated signals. It was found that for a certain class of FM signals a simple approximate relationship exists between the phase angles and the power spectrum. By adjusting the phase angles of a signal with a given power spectrum,one is able to obtain a waveform which resembles an FM signal and has a peak factor nearly as low. The questions might be asked, what is the maximum peak factor of a function with N spectral components and what advantage may be obtained by adjusting the phases of the various components. 1This set En of amplitude components does not uniquely determine the n time function e(t). A different time function exists for each set of phase angles en n

53 Let E N e(t) = +- + E cos (nw t + ) (3.21) 2 n o n where N is so chosen that all L En cos (now t + en) may be neglected. The average power as defined in Eq. (3.3) is T EE 2 N Pav To f [e(t)]2 dt e + _ i E 2 (3.22) Again, equating Eq. (3.22) to the average power of a sine wave, one finds that E N 2 A 2 + E (3.23) 2 n n The peak-to-peak excursion of e(t) is defined as 2 e ax The peak factor then becomes 2e e 2 max max (3.24) A 2A E N 2 2 + n N For the particular case where e(t) = E n_ cos (now t + en) (3.25) the maximum peak factor becomes Npf = -= (3.26) Equation (3.26) proves that the maximum peak factor is equal to the square root of the number of desired spectral components and occurs only when the cos (ixnut + en) of Eq. (3.25) is equal to unity for

54 each component. If one assumes that by proper adjustment of the phases of the function a minimum peak factor of 1 could be achieved,then the ratio of maximum to minimum peak factor is pf max = (3.27) pf(3.27) min It follows that for a small number of spectral components there is little to be gained by adjusting the phases. However, as the number of spectral components increases, e.g., N = 10, there may be a considerable advantage in phase adjustment. 3.2.2 Methods of Generating a Discrete-Frequency Reference. Four methods of generating a discrete-frequency reference are analyzed. These methods are (a) the Repetitive-Impulse method, (b) the ShiftRegister-Generator method, (c) the Parametric method, and (d) the Modulation method. (a) The Repetitive Impulse Method. The ideal frequency spectrum would consist of spectral components of balanced amplitude with the desired harmonic spacing over the frequency range of interest. The ideal spectrum and its time function are shown in Fig. 3.6. le j j _ _AI l _ _ _ _ _ _ _' fc t- fc 2fc 3fc f (a) Time function. (b) Frequency spectrum. Fig. 3.6. Repetitive impulse (fC = clock frequency).

55 Although the frequency spectrum shown in Fig. 3.6(b) is desirable, it is impossible to generate a repetitive impulse as shown in Fig. 3.6(a). Generation of pulses approaching the ideal, i.e., nanosecond pulses with repetition frequencies greater than 50 Mc,is possible using the recovery effect of certain types of pn junction diodes (Ref. 15). Perhaps the most straightforward method for providing a uniform amplitude spectrum is to utilize a clock oscillator frequency equal to the required separation of the harmonics. The clock output is used as a trigger signal for a blocking oscillator or diode harmonic generator which has an output waveform very rich in harmonics. The desired harmonics are selected by means of a filter and amplified to obtain the energy required for proper operation of the phase-lock loop. A time function which is realizable and its associated frequency spectrum are shown in Fig. 3.7. The relationships among the parameters of the pulse f = I/T Er T tt A E } Z -T/2 0 +T/2 t I T - T (a) Time Function (b) Frequency Spectrum Fig. 3.7. Repetitive finite pulse. of Fig. 3.7(a) and the frequency spectrum of Fig. 35.7(b) may be summarized as follows: (a) The repetition frequency f determines the spacing of the lines representing the ourier components but hs no effect on the envelope curve drawn through the ends of the lines.

56 (b) The pulse shape determines the shape of the envelope curve; for a rectangular pulse the envelope always has the form of s X where x = 2 ok. (c) The pulse duration T determines the spacing of the zeros of the envelope curve. (d) Since the spacing of the zeros is 1/T and that of the lines is f = - the number of spectral components within each loop of the envelope is T. Although the time function shown in Fig. 3.7 is realizable and may be used to provide a reasonably uniform amplitude spectrau over a given band of interest, a more detailed examination of the repetitive finite pulse and its associated frequency spectrum must be carried out to determine how to optimize its use in a synthesizer. The question might be stated as follows: For the case of the repetitive finite pulse how does the peak factor and average power in the band of interest vary as a function of the pulse width X and the number of spectral components N? Referring to Fig. 3.7 assume the pulse height E and the period T of the time function remain constant. From the frequency spectrum select a given number of spectral components N, all of the same sign and in the desired range, by means of an ideal band-pass filter.1 Under the above conditions examine both peak factor and the average power contained in the band of interest as a function of the pulse width. An ideal band-pass filter as defined here will pass all frequencies within its pass band without amplitude distortion while rejecting all other frequencies. At the same time the phase shift across the pass band will remain constant or at most change linearly.

57 The Fourier Series for the time function e(t) out of the bandpass filter takes the form k e(t) = E cos not (3.28) n=j n where ~t = 27rf sin nn E = 2 * iT (3.29) From Eq. (3.28) it can be seen that the peak value of the function e(t) occurs at t = O, T, 2T,.., etc, At these points cos ilt = 1 for all n, and e(t) has the value k e(t) =. En} t = O, T, 2T, n=j n' The average power in the band of interest can be obtained with the use of Eq. (3.3) and is k P = E2 (3.31) avg 2 n=j n Under these conditions pf* = Pf (3.32) where pf = =J (3.33) ~ E n= n

58 To obtain useful results the following conditions were imposed and the problem programmed for the IBM-704 computer. Let T = 10'5 sec E = 1 volt 10-6 10 where Z is the value in Mc of the first zero in the frequency spectrum and is varied in discrete steps in the range 1 to 40 Mc. N = 11 components where the components are in the range from n = 100 to n = 110. Peak factor and average power as functions of the position of the first zero (Z) are shown in Fig. 3.8. For the first zero locations below the band of interest both power and peak factor vary 4 5 03 - 14 3~ ~ 0 2 X-1 < ~ ~ ~ 231 1 IP. AVG. - tu 0 I I I * I * I, I, I, I, I 0 2 4 6 8 12 16 20 24 28 32 36 40 LOCATION OF FIRST ZERO(Z) IN MC Fig. 3.8. Peak factor (pf) and average power (P ) in the band avg of interest vs. the location of the 1st zero (Z) in Mc for N = 11 spectral components.

59 wildly. For first zero locations above the band of interest the peak factor becomes a constant independent of the first zero location. The power in the band of interest on the other hand rises from a minimum at Z = 11 Mc to a maximum in the range Z = 20 to 22 Mc and falls off as Z increases. Under the given conditions then, a pulse width T should be chosen such that the first zero of the frequency spectrum will fall in the range 20 to 22 Mc. The question might now be asked, what happens if the number of spectral components is increased? The results of increasing the number of spectral components while holding all other conditions the same are shown in Figs. 3.9 and 3.10. 5 6 4 - - 5 o 3 - P AVG. -4:: _ O0 I- 2- 3 93 O- I, I, I I, I, I, I, I I 0 4 8 12 16 20 24 28 32 36 40 LOCATION OF FIRST ZERO (Z) IN MC Fig. 3.9. Peak factor (pf) and average power (P ) in the band avg of interest vs. the location of the 1st zero (Z) in Mc for N = 26 spectral components. In Fig. 3.9 N = 26 and the spectral components are selected in the range n = 100 to n = 125. The general behavior of the peak factor and average power as a function of the position of the first zero is very similar to the case where N = 11. The regions where the peak factor

6o becomes independent of first zero position and the power in the band reaches a maximum, however, have both moved out in frequency. The peak 7.. 8 ~~~~~~~6 7~~~PF 6-5-7 0 U) HP AVG 4 8 12 16 20 24 28 32 o 40 4 8 12 16 20 24 28 32 36 40 LOCATION OF FIRST ZERO (Z) IN MC Fig. 3.10. Peak factor (pf) and average power (P ) in the band of avg interest vs. the location of the 1st zero (Z) in Mc for N = 51 spectral components. factor becomes independent of first zero location beyond about 16 Me while the maximum power in the band of interest occurs when the first zero is located in the range 22-24 Mc. In Fig. 3.10 N = 51 and the spectral components are selected in the range n = 100 to n = 150. Again, the general behavior of the peak factor and average power as a function of the first zero is quite similar to the previous two cases with the exception that the peak factor becomes independent of the first zero location beyond about 20 Mc and the power in the band of interest reaches a maximum when the location of the first zero occurs in the range 24-26 Mc. It is interesting to note that if the points of the first zero which give maximum power are plotted vs. N, the number of spectral

61 components, their locus will approximate a straight line of the form, 10 Z = N + 199 (3.34) This equation is plotted in Fig. 3.11. 26 (21,25) 24 -(26,22) (II 21) 23 (1,20) (1121) 20 _X —— 0 IOZ: N+199 M12 Z 13 N8 2 0 2 4 6 8 10 12 14 16 18 20 N * 28 30 40 50 Fig. 3.11. Location of 1st zero (Z) in Mc vs. the number of spectral components (N) for maximum power in the band of interest. From the results of the analysis of the repetitive finite pulse, one can conclude that the expected peak factor is approximately equal to ~j as predicted in Eq. (3.26) and verified in the curves of Figs. 3.8, 3.9, and 3.10. Also the peak factor is independent of the location of the first zero of the frequency spectrum when the first zero is placed somewhat above the desired band of interest. In addition, the average power in the band of interest reaches a maximum when the location of the first zero occurs at some point above the band of interest. This point of maximum power can be found with the

62 aid of the curve of Fig. 3.11. In general, to achieve optimum utilization of a repetitive finite pulse in generating a discrete-frequency reference, it is only necessary to derive the location of the first zero above the band of interest which will give the maximum amount of power. (b) The Shift-Register Generator Method. As indicated in Eq. 3.9, the minimum attainable value of peak factor occurs when the function e(t) is always equal to Ema or Emin where E =. The peak factor under these conditions is found to be.707. It is interesting to consider the possibility of generating time functions which fulfill the above conditions while providing a reasonably uniform amplitude spectrum over a given band of interest. The digitally-generated linear maximal sequence (Ref. 16) shown in Fig. 3.12(a) will produce a line spectrum which has a sin x x envelope and has the spacings as shown in Fig. 3.12(b). A digital L = Number of clocked pulses per period fc = Clock freq. T = Pulse width T = Period et - lfc or T f = I/T E max. 2V'/Ti L EM Emin I O /r rle T (a) Time Function (b) Frequency Spectrum Fig. 3.12. Digitally-generated linear maximal sequence.

sequence refers to a succession of binary states which in this case are regarded as consisting of E's and E mins where Em I = IE I. max min max mi From Eq. 3.2 the average power is found to be T Pavg = O [e(t)I2 dt = T E (3.35) avg -T max max The peak factor can be found from Eq. (3.10) to be 2 E pf = --.707 (3.36) 2 dT 2 2 2/2T.orE max dt From Eq. (3.36) it may be observed that the peak factor of the digitally-generated linear maximal sequence is a constant independent of the fundamental period T. At this point it might prove interesting to investigate peak factor (pf) as a function of pulse width (T) when the clock frequency (fc) is held constant. The time function and frequency spectrum for this case are shown in Fig. 3.13. From the standpoint of increasing T L Emoax. i e1 _, / 0 fL f 2'E I/T E /I I Pulse width min. fc = Clock freq - T - L = Number of clock pulses per period r (a) Time function (b) Frequency Spectrum Fig. 3.13. Digitally-generated linear maximal sequence where X < f.

the amount of energy in the high-frequency components one must decrease the pulse width T. The graph of Fig. 3.14 is a plot of peak factor vs. 2.3 pft,707 T T - T — I f 2 fc fc Fig. 3.14. Peak factor vs. pulse width (T) for fixed clock frequency (f ). the pulse width. The peak factor ranges from a minimum value of.707 (point where T = ) to a maximum value of infinity (point where T = O). f C From the graph a reasonable range for fc is.25 < tf < 1 (3.37) In particular, for a peak factor of unity Tfc 1 (3.38) A basic shift register to which modulo-two adders have been added can be used to generate digital sequences (Ref. 16).1 In 1Brief excerpts on the fundamental properties of shift-register-generator sequences have been taken from Ref. 16 and presented here.

65 the past the major use of a shift register was in the arithmetic unit of a digital computer. A shift register consists of a series of bistable elements with the capability of moving the contents in each element to the next element by means of a "shift" pulse. A shift register is thus a storage unit which moves its stored contents one position for each shift pulse. To form a shift-register generator, modulo-two adders are added to form feedback loops. The addition table for modulo-two addition is shown in Fig. 3.15; circuits which operate according to this 0 i I I O Fig. 3.15. Modulo-two addition table. table are often referred to as "exclusive-or" circuits. There is no output when the inputs are alike, and there is an output whenever the inputs are different. Modulo-two addition can be viewed as ordinary addition written to the base two, where only the least significant digit is recorded. A simple generator consisting of one adder along with the basic shift-register is shown in Fig. 3.16, where the numbers in the blocks refer to the bistable elements of the basic shift-register. To see that this is truly a generator and not just a storage device, consider an initial storage of six ones. The next five inputs will all be zeros since the initial ones will continue to be shifted into both the fifth and sixth stages for five shifts. The total

66 MOD ULO-TWO + ADDER SHIFT REGISTER I I' 2 3 4 5 6 OUTPUT i l Fig. 3.16. A simple shift-register generator. sequence has a period of sixty-three digits (compared to six for storage) and is repeated over and over. When one connects a shift-register as a sequence generator, it is found that the output sequence is a function of the particular feedback connections made. Also, for some connections, the output sequence depends on the initial loading of the register. This has led to the grouping of the output sequences into two types: maximal seTuences and nonmaximal sequences. This grouping is based on the "length" or "period" of the output sequence. For a given number of stages in a register, there exists a maximum to the number of digits which occur before the sequence begins to repeat itself. It is quite easy to establish this number. Consider a simple generator of n stages; if, as it is shifted, the register successively contains every combination of n zero-and-ones, the output sequence will be the largest possible. Since there are 2 different ndigit binary numbers, this would seem to be the maximum period possible. However, the sequence generator cannot possess all zeros in its stages (if it did, the generator would remain in this state and produce

67 the all-zero sequence); for this reason the largest possible period for a linear n-stage shift register is 2n-1. Thus if a given output sequence has a period equal to 2 -1, then that sequence is called a maximal length sequence. L = 2n 1 (3.39) where: L = length of maximal length sequence n = number of stages in the shift-register generator Consider the six-stage generator shown in Fig. 3.16. With this connection, a sequence 63 long is obtained; since 2 - 1 = 63, this is a maximal sequence. If a given output sequence has a period shorter than L, that sequence is termed a nonmaximal length sequence. The feedback connections of a generator determine whether the output sequence will be maximal or nonmaximal. Maximal sequences can be obtained from a generator with any number of stages (n). In this particular study interest will be in maximal sequences only, although nonmaximal ones could conceivably prove useful. Returning to Eq. (3.38) where for unit pf, f = and assuming that clock frequencies (fc) in the order of 108 cycles are obtainable, then X becomes 1 -8 -9 v = 2 f- 5 x 10 5 x 10 c ~ = 5 nsec

68 Pulse widths of 5 nsec are well within the state-of-the-art. Of the various methods presented for generating a discretefrequency reference the shift-register-generator method is particularly interesting. The digitally-generated linear maximal sequence not only fulfills the condition of minimum peak factor while providing a reasonably uniform amplitude spectrum over a given band of interest, but is independent of the fundamental period T. From a practical point of view, the shift-register generator is simple to implement. Logic modules can be taken off the shelf and put together to form a discrete-frequency reference. At the present state-of-the-art, clock frequencies of 20 Mc are available which means that first zero locations of approximately 40 Mc in the ix frequency spectrum are achievable with a unity peak factor. By using clock dividers and coincidence gates in conjunction with the shift-register generator, it is possible to obtain any number of discrete-frequency references, each with different incremental step. In order to explain the method and the relevant properties of numbers considerations, the following example of dividing down by successive factors of 10 is developed. The basic idea is that if one periodically samples a linear maximal sequence properly one obtains another linear maximal sequence with the same number of digits per period. The term "properly" means the sampling rate k and the number of digits L = a -1 have no common factors. In the example of dividing down by successive steps of 10 one must arrange that the period contains no factor of 5 or 2. Obviously, it contains no factor of 2 since L is an odd number. One must now choose the proper number of stage n so that 5 is not a factor

69 of L. This is not very restrictive since one may use any number of stages so long as they are not multiples of 4. The proof of this is given in Appendix B. Under these conditions then it is possible to divide down the original sequence by a factor of 10 obtaining a second sequence with a spectral spacing O as great. Dividing again by the same facP ~10'A"~ ~1 tor, a third sequence may be obtained with a spectral spacing OO of the original sequence. This simply means that if one were to start with a discrete-frequency reference of 10 components spaced 100 kc apart, additional sets of 10 spectral components could be derived spaced 10 kc, 1 kc, etc. (c) The Parametric Method. A promising technique is discussed which is capable of presenting a uniform amplitude spectrum, one component at a time (as opposed to the entire reference spectrum), to the input of the phase-lock oscillator. In essence, this type of discrete-frequency reference can be thought of as a comb from which a single tooth can be selected at will. The principle component in this circuit is a parametric amplifier (Ref. 17). The equivalent circuit of a typical two-tank frequency converter is shown in Fig. 3.17. This model has tuned w3= n3+ nJ2 Ct = C3 SIN (W3t +, 3) TANK I __ TANK 2 FREQENCY C=TIME VARYING CAPACITNCE F LREQUENCY o2 Fig. 3.17. An equivalent lumped circuit for the two-tank variable-parameter system.

70 circuits at both the signal frequency and at the "idler" or lower sideband frequency. (In the case of the lower-sideband up-converter, the idler frequency becomes the output frequency.) The variable capacitance Ct serves to couple together the two high Q tank circuits of resonant frequencies 1l and a2' respectively. The variable capacitance is driven sinusoidally at a rate (3 = a1 + Q2. If a voltage exists across one of the tanks at its resonant frequency, a second voltage is developed across the second tank at its resonant frequency by the mixing action in the variable capacitance. The phase of the second voltage is automatically adjusted so that net energy flows into the tank circuits from the pumped capacitor. Consider now the conditions for amplification. A signal generator, tuned to' A- a1 is coupled into tank 1 and an output load GL2 is coupled into tank 2. The magnitude of the capacitor variation (Ct) is reduced to a value just below the point where oscillations occur. The signal generator is then responsible for the existence of V(w1) across tank 1. The mixing action in the variable capacitor will then result in producing V(w ) across tank 2. The converted signal, as is the case in mixer circuits where the local-oscillator frequency is higher than the input frequency, exhibits a modulation inversion since a signal w1 + ZLko applied to the first tank gives rise to a signal 2 - ko in the second tank. In the practical operation of this system as a discrete frequency reference from which a single component may be selected at will, the input circuit would have to tune over a large frequency range, perhaps 10 to 1. The necessary adjustment of the amplifier in this case would be very difficult. Consequently, being limited by the present

71 state-of-the-art, operation with an untuned input is almost mandatory. As described by Fisher (Ref. 18), the tuned circuit at the input may be eliminated to allow the design of a simple-to-adjust, tunable amplifier. The equivalent circuit of a single-resonance lower sideband up-converter is shown in Fig. 3.18. The parameters are the same as in Fig. 3.19. C t =C3 SIN(wJ3t +3) TANK ~ G I GL ig ~ GT C Cz L2 2 G L UNTUNED LOAD SOURCE RESONANT fREQUENCY.A Fig. 3.18. Theoretical model of a single-resonance parametric amplifier. Consider, as shown in Fig. 3.19, that the output of the O f, nfI fp nf, fp FREQ. Fig. 3.19. Frequency spectrum of a single-resonance lower-sideband up-converter. harmonic generator is a very low level frequency spectrum with components of nfl (where n is an integer). A lower sideband up-converter is used to convert a selected component of this spectrum to the frequency

72 fp - nfl. Even though the converter is untuned at the input, tuning at the difference frequency produces large regenerative gain at its low frequency image, and high rejection of unwanted mixing products or comb components is obtained. The gain of the single-resonance lower-sideband up-converter is G.G 1 (3.41) 1 + o2 (W _ wr)2 o for G > > 10 where or = resonant frequency of the output tank after the pump (or local oscillator) frequency has been applied w~ = output frequency 0 Go = midband gain of the output tank 0 BT = bandwidth of the output tank before the pump is applied. Let G 2 + ~o ( - Or) = K (3.42) 2 o r BT for K > 10 G 2 ~2 ( O)> > (3.43) BT? 0 r

73 Thus from Eq. (3.42) G (w or)2 B T2 K -a -~ —~ — (3.44) Define a term BK 2o 2(w - wr) (3.45) where BK is twice the spectral spacing of the discrete-frequency reference. Substituting Eq. (3.45) into Eq. (3.44) and solving for the BK ratio of the B one obtains T BK 4K B =11G (5.46) BT - BK If the ratio of B = 1, then T db = G - 6 db (3.47) db Odb Figure 3.20 is a plot of the ratio of the BK/BT versus the amplifier gain with K as the variable parameter. For a given ratio B B,K shows the amount of spectral component suppression one would reT ceive for a given value of gain. To clarify this discussion somewhat, consider the example shown in Fig. 3.21. The solid curve is the pass-band of the output tank before the pump is applied. Assume the output frequency w is at the resonant frequency or and the adjacent two spectral components coa and ~b are at the 3 db points (i.e., B = 1). Turn on the pump and adjust

I00 80 6040 200-GAIN 8 BK 6 BT,~~~~~~BT 4 - /O0 8 100O 20DB 30DB 40DB 50DB 6 -~~~~~~~ T~~~~~O

75 I' I \ SIDEBAND I \ SUPPRESSION BEFORE 40DB 1I\ APPLICATION OF PUMP ___I_________ I SIDEBAND | | /i 1 \\ 3DB SUPPRESSION AFTER X Xl *1D\ t APPLICATION OF PUMP EQUALS 34 DB WA Wr (s FREQUENCY — o o Fig. 3.21. Sideband suppression in output tank before (solid curve) and after (dotted curve) application of pump. the power level until the gain of the amplifier is 40 db as indicated by the dotted curve. At this point it can be found from the chart of Fig. 3.20 that the gains of the two adjacent spectral components are suppressed by a factor of approximately 34 db. It is an inherent characteristic of a single resonance parametric amplifier that as pump power is increased the pass-band of the output tank not only narrows down but will actually shift in frequency; (this shift in frequency of the output tank reflects an inductive reactance into the input circuit which in effect peaks up the input signal at the desired frequency). In the final analysis then what was originally an untuned input (before pumping) becomes a wide range tuned input (with pumping). In the practical application of the device if it is desired

to tune from one value of n to another the pump is first disabled and a coarse tuning voltage applied to center the output pass-band over the desired value of n. The resonant frequency of the output tank will shift away from the desired value of n as the pump power is brought up to the level which will give the required suppression of adjacent spectral components. To correct for this shift a fine tuning voltage may be introduced by means of error-correcting circuits as shown in Fig. 3.22. For either of the two above types the error-sensing circuit works in the same manner. The output of the comb generator (a low frequency, wideband spectrum) is applied to a buffer stage as well as the phase detector. Since the output of a buffer stage is the input to the low frequency tank at the reactive mixer, the signal at this point (also in or near lock) is essentially a sine wave with a frequency equal to one of the harmonics of the comb. The particular harmonic depends on the rough tuning voltage. The phase of this sine wave depends on the tuning of the idler tank in Type 1 and the pump in Type 2. It is desirable to make the phase angle as small as possible in order to maximize the Q of the reactive mixer circuits. This is done by comparing the phase of the appropriate comb component and buffer amplifier output. This "error" signal is detected and amplified and then applied to either the pump or output tank respectively. In conclusion, it should be noted that the technique of presenting a uniform amplitude spectrum, one component at a time, will simplify the design problems of the phase-lock loop. The adjacent spectral components of the discrete-frequency reference, if not attenuated, will appear as modulation at the output of the phase detector to modulate the VCO and produce undesirable FM components. The design of sharply

77 A A f nf fl nf \ ORO~~~~~~~~ I PHASE PUMP REACTIVE PHAET AND PUM f MIXER FILTER AMP DC CONTROL VOLTAGE TYPE I FIXED TUINED OUTPUT TANK. HARMONIC BUFFER OT GENERATOR AMP I I DC AMP PHASE ANDPUMP TYPE 2 VARIABLE TUNED OUTPUT TANK, FIXE TUNED TUNED PUMP OSCILLATOR. Fig. 3.22. Block diagram of error-correcting circuit for a single-resonance lower-sideband up-converter.

78 tuned rejection filters with little envelope phase delay (phase delay in the pass band results in a reduction of the capture and lock range of the system) is difficult to achieve, thus any prefiltering of the discrete-frequency reference will certainly lessen the design problems of the phase-lock loop. (d) The Modulation Method. Both amplitude and frequency modulation techniques may be used to generate a given set of spectral components in the desired band of interest. The amplitude modulation technique relies upon the fact that the spectrum of any periodic time function, e.g., the repetitive finite pulse, is symmetric about zero frequency. By multiplying the time function of a desired spectrum,centered about zero by some carrier frequency which is centered in the band of interest, the spectrum is effectively translated to the band of interest and the required number of spectral components which are evenly distributed on either side of the carrier frequency may be selected by means of a band-pass filter. Consider the following amplitude-modulated wave jw t v = M (t) Ve 0 (3.48) a where M (t) the modulating function is the time function of the desired o spectrum centered about zero and Ve represents the carrier frequency centered in the band of interest. If the nth frequency component of the modulating wave has the magnitude Cn, the modulating waveform can be represented as jnolt M (t) = cn~ ne (3.49) aw n= - n where t = the period of the modulating wave. CD1

79 The Fourier Series expansion of the modulated wave is 00 jw t jnclt v =v = L C e e (3.50) n -co n or j(wo + n d)t v = V L c e (3.51) n= —~ n Thus the spectrum of the amplitude-modulated wave is a symmetrical spectrum centered about w as pictured in the sequences of Fig. 3.23 shown below. LU 0 o V (A) SPECTRUM OF UNMODULATED WAVE 0 I J.I D V,.7 I I t I I I I 1. 1 1 1 1 1w -7 w, -51, -3w, -w, O w, 3w, 7~ (B) SPECTRUM OF MODULATING WAVE w0-7w S T-3wU Mo F M 3U)U wO +7w~ (B) SPECTRUM OF MODULATED WAVE Fig. 3.23. Spectrum of an AM wave.

60 If the band of interest is small compared to the carrier frequency, it would seem advantageous to use a pulse wide enough to generate a spectrum where the first zero occurs at a point somewhat beyond the frequency equal to the half-bandwidth desired. If this pulse were then used to amplitude-modulate a carrier centered in the band of interest, a relatively large amount of the total energy would be concentrated in the band of interest and the time waveform would have a much lower peak factor than if the repetitive impulse method (method a) were used. A comparison of the repetitive impulse method (method a) and the amplitude modulation method (method d) are shown in Fig. 3.24 below. V w if n n t E - w -ot BAND OF INTEREST MA (t) w Wo ~-lmt <z L — BAND OF INTEREST Fig. 3.24. Comparison of the repetitive finite pulse and the amplitude-modulation techniques.

The frequency modulation technique relies upon a rule which can be used intuitively as a general principle. The principle may be stated as follows: The spectral contributions of an FM wave are functions of the rate of change of frequency during the entire cycle; the longer the frequency of an FM wave remains in a certain range of frequencies, the greater will be the spectral contributions in that frequency range. Based on the above principle, the only FM waveform that will generate a spectrum of uniform amplitude components is a linear function of time. Consider a modulating function of the type Mf(t) = wo + Lk - T t (3 52) A sketch of this function is shown in Fig. 3.25. Mf(t)t WO T T1 -4" Fig. 3.25. Linear FM waveform. The modulated waveform is given by 2Lxo 2 v = V cos[(W + ) t — ) t (3.53) o T The amplitude of the spectral components is therefore T -j 2nt 2 t2 Cn " e x cos[(w0 + w)t t - ]dt (3.54) 0 T'

82 This integral is in general quite difficult to evaluate; however,by means of numerical methods and with the aid of the computer it can be evaluated. The spectrum of the frequency modulated wave is sketched below in Fig. 3.26. (0 -AS @0 Aw Fig. 3.26. Frequency spectrum of the linear FM waveforms. The sawtooth wave would yield an even flatter spectrum if the corners of the time function were rounded off. In conclusion, both AM and FM techniques would be quite simple to implement. The FM wave, although somewhat more difficult to analyze, does have a very low peak factor. In fact, the peak factor is unity, the same as that of a sine wave. Although the major part of the section has dealt with the spectra of easily generated time functions such as rectangular pulses, triangular waveforms, etc., other time waveforms may yield very interesting spectra. One possible technique for finding useful time waveforms is to determine the inverse Fourier transform of the envelope of the desired spectrum. The resulting time waveform is aperiodic but it can be made periodic by cutting the waveform off at some time and repeating the wave. Where one should cut depends upon the waveform and upon the requirements of the desired spectrum. Two possible transforms and sketches of both frequency and time functions are shown.

83 G IIGw 0 t -a a - - G(t) = 2 SINat G( ) = I Iwl < a -irS r Str =0 Iwl>a -r< r 7r Gt IG I( t_ G= —-*4 SNw G( )=-4jSIN wi (I- O2 )(4-W1) G(t) = 2/3 S.27N t + 1/3Examples of useful spectra and theiN2t Fig. 3.27. Examples of useful spectra and their associated time waveforms. It is interesting to note that in the sketch of Fig. 3.27(a) the time function is made periodic by cutting off the wave at the point where the 3rd zero occurs and repeating the waves. In Fig. 3.27(b) it is not necessary to cut off the wave since the time function is already periodic. 3.2.3 Summary. A study and evaluation of the various methods for the efficient production of high-order harmonics with balanced energy distribution in the frequency band of interest has been carried out. The concept of peak factor has been analyzed and a relationship which can be effectively used as a figure of merit in the design of an appropriate frequency spectrum has been developed. The method used to generate the discrete-frequency reference will, in general,

84 depend upon the final design conditions imposed. For example, if the desired number of spectral components is not large and the band of interest is high in frequency, it is advantageous to use AM or FM modulation techniques. If the band of interest is high in frequency and a number of very closely spaced spectral components are required, the parametric method may prove very useful since it provides a high degree of adjacent spectral component suppression. The shift-register generator method provides a good general technique which reduces to practice very easily and can be used under a wide variety of conditions. 3.3 Phase-Lock Oscillator A vital element of the discrete-frequency generator (DFG) is the phase-lock oscillator (PLO) or automatic-phase control (APC) system as it is sometimes called. There are varied and sometimes conflicting uses for a phase-lock oscillator, e.g., a PLO system can be used to reduce the jitter or frequency noise of a high power oscillator such as a klystron or with somewhat different design parameters, it can be used in a receiver to increase the power level and attenuate the noise of a weak FM signal. In the frequency synthesis field which involves the generation and selection of a single frequency signal, a poor signal-tonoise ratio may result —the noise in this case taking the form of adjacent frequency components of the reference generator and small deviation FM or phase jitter of the desired component. A PLO can be used as a high-Q filter to select a desired signal, attenuate unwanted components, and reduce phase jitter. In addition, a PLO can be used to track input frequency changes, e.g., Doppler shift of satellites, for sweep synchronization of the color sub carrier in the color-television system and for FMs discriminators.

85 In the case of the generalized discrete frequency synthesizer the PLO would ideally have a wide acquisition and lock range, a very rapid lock-in capability and small noise bandwidth. These features, as it will be shown, are not fully compatible. Many articles have attempted to describe the various performance factors of the PLO loop but no one of these articles is sufficiently complete for our present purposes (Refs. 19 and 20). In the following sections, an analysis will be made of those properties which determine acquisition and lock range. convergence times, output spectral purity and frequency range of operation. Acquisition range is the largest unlocked frequency difference at which synchronization will occur. The lock range is the total drift in the unlocked oscillator which can be exactly compensated by the locked system. Convergence time is the total time it takes to go from one locked frequency to another. The output spectral purity depends upon the filter bandwidth of the system which in turn expresses the performance of the system as a low-pass filter with respect to FM noise components existing in the input to the system and as a high-pass filter with respect to FM noise components generated within the output oscillator. In addition, techniques for optimizing PLO loop performance to allow their use in a synthesizer satisfying a specific need and an evaluation of the limits of operation subject to the present state-of-the-art will be presented. 3.3.1 Theory of Operation. The elements of a typical phase-lock loop are shown in Fig. 3.28. Reference signal input to such a loop may be assumed to be Ei sin ei(t). The output of the voltage-controlled oscillator (VCO) is given

86 e. ed e e PHASE LOW-PASS o eo Fig. 3.28. Block diagram of phase -lock loop. eo(t) = Eo sin eo(t) (3.55) where eo(t) = wC(t) + e(t) (3.56) Substituting Eq. (3.56) into Eq. (3.55) one obtains eo(t) = Eo sin [wct + e(t)] (3.57) The voltage eo(t) has a frequency associated with it given by eo(t) = wot C= C+ e(t) (3.58) and this frequency is observed to consist of a constant determined by the rough-tuned or free-running frequency of the oscillator Wc plus a time-varying term proportional to the actuating signal. Briefly, the operating principles of such a loop are as follows: The phase detector can be mathematically represented as a multiplier and operates in this system to give ed = ei(t) x eo(t) (3.59)

87 [Ei sin ei(t)] x [Eo sin eo(t)] (3.60) EiE r = 2 cos [ei(t) - e(t)] - cos (3.61) [ei(t) + eo(t)] Since the filter following the multiplier is low-pass it rill not pass the sum frequency term, thus the multiplier output ed is proportional to the cosine of the difference phase. ed = K1 Ei E~ cos e(t) (3.62) where e(t) = ei(t) - eo(t) (3.63) and K1 is the sensitivity of the phase detector (rad Volts)1 If it is assumed that the multiplier is a balanced phase detector composed of peak-detecting diodes, and if the VCO output voltage Eo is much greater than the reference signal voltage Ei,then a simplified form of the multiplier output voltage can be derived. As shown in the vector diagram of Fig. 3.29 one of the detector diodes is fed with Ei the sum of E~ and 2, the other is fed with the difference of these two vectors. The resulting rectified voltages Ed and Ed can be established 1 2 by trignometric relations. E 2 E 2 i+ E 2 (3.65) d 4 + E0 + i Eo cos0 (3 2.

88 ed _ d Fig. 3.29. Circuit and vector diagrams of phase-detector circuit. The phase-detector voltage is equal to the difference of the rectified voltages, i.e., ed Ed - Ed (3.66 ) 2 Subtracting Eq. (3.65) from Eq. (3.64) one obtains -2 Ei E cos e ed Ed - = E + E (3.67) 1 2 dl d2 If Eo >> Ei Ed + Ed 2Eo (3.68) 1 2

89 Substituting Eq. (3.68) into Eq. (3.67) one obtains ed Ed - Ei cos e (3.69) 1 2 Sinc e i = ee + A/2, Eq. (3.69) becomes ed = Ei sin ee (3.70) One can see that due to the balanced nature of the phase detector the dc voltage due to the VCO has been removed. In addition, for a large VCO output voltage the multiplier output voltage ed is independent of the output level of the VCO. Denoting the linear transfer function of the loop filter as F(p) the VCO control voltage becomes, in the general case, ec = F(p) K1 Ei Eo sin ee(t) (3.71) Assuming the frequency of the output of the VCO consists of a constant equal to the free-running frequency of the oscillator Wc, plus a time-varying term proportional to the actuating signal, and assuming furthermore that the VCO has a linear control characteristic K (rad ), then the oscillator output frequency becomes Wo(t) = c + K2 ec (3.72) o(t) w eC + F(p) K1K2 Ei Eo sin ee(t) (3q73) The output phase eo(t) becomes t t e0(t) = f wo(t)dt = t + f K1 K2 F(p) Ei E sin ee(t) dt o o (3-74) Substituting ee(t) = 8e(t) - e0(t) -,t/2 into Eq. (3.74) one obtains

90 t ee(t) = ei(t) - wct - I KlK2F(p) EiEo cos ee(t) dt - n/2 Differentiating both sides of the equation (3.75) yields Pee =P ei - tc - KlK2F(p) Ei Eo sin Be (3.76) rearranging gives Pee + KlK2F(p) Ei Eo sin ee = Pei - c (3*77) The product K1K2 Ei E0 may be defined as K, the gain constant, and has the dimensions of radians per second. K represents the maximum frequency shift at the output of the system per radian phase shift at the input. The equation may now be written P ee + KF(p) cos ee = P ei - Wc (3.78) This equation represents the general differential equation of the PLO loop. P 8e is the instantaneous difference frequency between the reference signal and the VCO signal. P ei is the instantaneous frequency of the reference signal while wc is the free-running VCO frequency. The simplest loop is one in which the loop filter has no energy storage elements (i.e., produces a constant transfer ratio F(p) 1). If the difference frequency between the reference signal and the free-running VCO signal is defined as = P ei - c = i - Wc (3-79) and is constant, the steady-state solution cose - K (3.80)

91 This means the system has a steady-state phase error which is proportional to the initial set-on error Axw and inversely proportional to the gain constant K. Since the maximum value of cos e = + 1,. the system will acquire and stay in lock over a frequency range I| lock range < K (3.81) Figure 3.30 is a plot of P ee vs. ee for a given constant seton error of Aw and describes the operation of the system. For lockon to occur, the error frequency curve must intersect the abscissa —at the point where the VCO output frequency equals the reference frequency. There are two possible intersections, but only one of these is stable, the other corresponds to a condition of positive rather than negative feedback. If the frequency error P ee is positive, the phase error ee tends to increase; for negative frequency error, ie decreases. The stable intersection is called the locked operating point and indicates the t nlTnr + SIN K ] F..- en +b1)er (SIN K n AS K (n-l) r n 7r (n + O)r (n+2)Tr. Aa-K Fig. 3.30. First-order loop pull-in behavior (n even integer).

92 phase error 8e required to maintain lock. If the frequency of the VCO drifts, it will remain locked but the operating point will move toward one end of the stable region. At IAwl > K the VCO will unlock and continuous frequency modulation of the oscillator will result. Under the assumption that the phase error is small, Eq. (3.78) may be linearized by substituting ee ~ sin 8e for 2 < e <(382) Using the linearizing assumption and letting the transfer ratio F(p) = 1,Eq. (3.78) becomes P(8i - eo) + K(ei - 80) = P ii (3.83) P e0 + Keo = K ei (3.84) This leads to a transfer function e K 0 (P) = K (3.85) Using LaPlace transforms the transient response of the loop to a sudden step of input phase leil becomes o (P) K =p(p+ K) (3.86) which in the time domain becomes 8 (t) -Kt (3.87) 2 (t) = lA plot of the transient response of the system for F(p) = 1, i.e., a direct connection between the phase detector output and the oscillator control stage is shown in Fig. 3.31. It should be noted that

93 o00 ei I / //I K -Kt Fig. 3.31. Transient response plot of - (t) = 1-e leil for large error angles the transient response will be slower than shown on Fig. 3.31 because of the error in the approximation ee = sin ee. The frequency response of the system is found by comparing the steady-state sinusoidal waveform of eo with that of 8i for a sinusoidal ei input i(~ (3.88) The simple loop behaves like an RC filter and has a cut-off frequency of Cut-off frequency Wc is defined as that frequency where the loop gain is down by a factor of 3 db

94 WC = K (3.89) The complete frequency response locus of the system is shown in Fig. 3.32. 9o~ z 1800 = P w=O REAL AXIS.5 O W-K 270~ Fig. 3.32. Frequency response plot of O- (jw) = i l+jK The mean-square phase fluctuation at the output of the locked oscillator loop will be equal to the input noise-to-signal ratio times the ratio of power gain for noise and signal. Since the signal has an infinitesimal bandwidth, and since the noise power may reasonably be expected to be spread uniformly over a wide band, the output noise-tosignal ratio or mean-square phase fluctuation as shown by George (Ref. 21)

95 will be equal to the ratio of input noise spectral density to signal power ratio times the noise bandwidth of the closed-locked oscillator loop. The noise bandwidth of the system is the integral with respect to frequency of the magnitude of the gain transfer function of the loop. This gain transfer function is given in Eq. (3.88). The noise bandwidth is then found to be: eo 2 B = If 0(jw) d6i (3.90) 0 i Note that the integral is taken only from zero to infinity because of the low-pass output of the phase detector. Alternatively, we might say that only half the noise gets to the phase detector, that is, that half which is in phase with the reference signal. Equation (3.88) can be substituted into Eq. (3.90) and the integration carried out to yield B = 2 K rad/sec (3-91) This means the system has a noise bandwidth (B) which is proportional to the gain constant K. Pull-in time may be determined for the first-order loop by use of Eq. (3.78) in the following manner. Let F(P) = 1 and P ei - c =AU Equation (3.78) then becomes P ee + k sin ee = (3.92) where e is the instantaneous phase error between the reference signal

96 and the VCO signal. Since dee Pe dt Equation (3.92) can be rewritten as dt 1 (3.93) dOe w K sin e3 whence the pull-in time is given by ee final de t = i - Ksin O (3.94) e initial Since e fiin - 1 -K- it is observed that the pull-in time (t) will be infinite. This is to be expected since the Lipschlitz condition as described by Rauch (Ref. 22) is not violated at the singular point. Actually we are interested in the time required to obtain a zero difference frequency. A reasonable approximation to this time may be obtained by integrating Eq. (3.94) to a value of Be such that a one cycle difference frequency exists. This is given by Ao- K sin el 1 (3.95) or eel =sin (O - (3.96) el K Define a zero difference frequency time tZDF such that - K sin - W+ K sin.el= K Isin e - sin e'j< cje - e where C > K.

97 eel de tZDF = e i a K si e where K2 > 2 (3 tZDF - K sin -ee97 ee initiale 1 -K + K/DK sin ee - K2- W2 cose el I - sin K (3.98) -/ KI _ /\,A K e e init. -K + to sin el - K2 2 cos e A1 ml- K sin 8e in A / K 2 - zn2 -K + Am sin 8e- -2 A2 cose init..e init. e init.. K'- K sin Ke init. (3.99) K K - A~ -K + Aw sin e n;ocinit. e e cit. e init.... - K sin e'.. e mnit. t(3.100) now j8?-AwU2 \K2_-(A-l1) = (K-22) 1)1+ 2 (3.101)'2 _ 2 (3-101) (2 _, 2) + (2 a,- 1) (3.102) In all instances except at the extreme limits of the capture range (2 n:- 1) << K2 - 2 (3-103) Thus Eq. (3.100) reduces to K2F 2/ —-? -.22 2 tZDF' - =. In2 L _K + Zos in 8 iit._ - _D icos 8 i it( (3.10o4)

98 As a typical example let 8e init. = -90~, thus sin e init. = -1 and cos 8 = 0. e init. Equation (3.104) becomes tZDF1 I [n (K2 _aw2 ) (t.+K)] (3~ 105) When K >> A( n n 2 K tZDF - K (3.107) For K = 10' tZDF 10 l n 2 x 105 10 sec (3.108) tZDF As indicated in Eq. (3.104) the pull-in time for a simple loop depends upon the initial phase error 8e init. the gain constant K and the initial frequency offset Aw. Since the noise bandwidth of the loop is directly proportional to the gain constant, then an increase in bandwidth will decrease the pull-in time, other factors remaining constant. The open-loop gain of the system is defined as - and may be obtained as follows: From Eq. (3.88) o 1

99 while from Eq. (3.63) ei = ee + eo eo By substituting Eq. (3.63) into Eq. (3.88) and solving for - (jw), the e open-loop gain becomes: 8 1 e (jW) (3.109) e Figure 3.33 shows a plot of the open-loop gain of the system. Co 6 DB/OCTAVE O db C FREQUENCY (LOG w) - Fig. 3.33. Open-loop gain of system. The loop gain decreases with frequency, intersecting the zero db (unity gain) line at a frequency wC = K. This frequency was previously defined as the cutoff frequency (Eq. 3.89) of the closed-loop system. This simply means that the transfer characteristic of the system equals unity under locked conditions (Wi = W0) for input variations with rates below Wc and falls off for rates above wc' It should be noted that due to the single integration term the loop gain decreases at a rate of 6 db per octave. 1 Since the control of the oscillator adjusts its frequency while the error signal is detected in a phase detector (which detects the integral of frequency with respect to time), the servo loop contains one ideal integration.

100 Since the open-loop gain-frequency curve completely defines the characteristics of the system, it is easily seen that the lock range and acquisition range are equal to each other and proportional to the gain constant K. In addition the cutoff frequency Wc is equal to the gain constant K. The conclusions to be drawn regarding the first-order loop are: (a) The loop will acquire lock within one cycle provided the frequency error is less than the cutoff frequency wc' (b) The lock-in time is governed by the initial phase error Oe init the initial frequency offset Lw and the gain constant K. (c) The lock range, capture range, cutoff frequency, and noise bandwidth are all proportional to the gain constant K. (d) The steady-state phase error of the system is proportional to the initial detuning and inversely proportional to the gain constant K. It was shown in Eq. (3.80) that for small steady-state phase errors due to average frequency drift the gain constant has to be made as large as possible. If it is desired to reduce the effects of noise attendant with the input reference signal, the gain constant should be made as small as possible as shown in Eq. (3.91). A proper compromise of gain must then be found to insure adequate performance of the system for all requirements. In other words, the system capability should include independent control of bandwidth and gain constant at least over a limited range of operation. Independent control of the bandwidth and gain constant can be achieved by the use of a more elaborate control networks as shown in Fig.

101 3.34. Networks of this type are called proportional plus integralcontrol networks (Ref. 23). R2 R R R ed ed CI I 7 CC 2 ~1 = R1C 1l = RC1'2 - (R1 + R2)C T2 = R(C1 + C2) ec 1+ F(p) = (p) =..p ed 1 +r 2p Fig. 3.34. Proportional plus integral control networks. If one prescribes the transfer function of the control network to be i + 1P F(p) = + p (3.110) then by substituting Eqs. (3.63), (3.82), and (3.110) into Eq. (3.78) one obtains 2 K1 r\ K K K p0 T T+ -pe0 0 Pei Te i (3.111) 2 2 2 2 2 where e0 and ei are again relative phase angles. To simplify Eq. (3.111) it is convenient to introduce the following parameters 2 K 2=.K (3.112) n 2 and

102 2w = - -+ K (3-113) n 2 2 where On is the resonant frequency of the system in the absence of any damping and t is the damping ratio. In terms of the new parameters the time constants of the control network are T 2t 1 (3.114) 1 uw K n and K 2 2 (3.115) n With these definitions Eq. (3.111) becomes Using LaPlace transforms the transient response of the loop to a sudden step of input phase Ie | becomes 22 which in the time domain becomes co =~(t) =1 -e gnt Cos 2 t t sin2 ti e +l +' =2 n - sin 1 2 8n (3.118) For e < 1 the system is underdamped, for i = 1 critically damped and for i > 1 overdamped. In order to avoid sluggishness of the system, a rule of thumb may be followed (Ref. 24) making.4 < g < 1. The

103 transient response (Eq. 3.118) can be plotted in dimensionless form if certain specifications are made for the ratio wn/K. Since the time constant T1 of the control network must be positive or at most equal to zero, the maximum value for w /K can be found from Eq. (3.114), and is n = 2(3.119) max In this case the control network is reduced to a single time constant network (1 = 0). On the other hand, if for a fixed value of Lun the gain of the system is increased towards infinity, the minimum value for Un/K becomes nj = 0 (3.120) min Plots of the transient response of the system for these two limits assuming a damping ratio of g = 0.5 are shown in Fig. 3.35. 1.4 W- n /K =O e(Wnt,) 1.02 5 2 4 6 8 10 Fig. 335 Transient Fig. 3-*35. Transient re sponse of system.

104 The frequency response of the system may be found from Eq. (3.111) and is 1 + j2n n 1 - eo 1=1 + j2w) ( 2D) (3.121) ei W ( 2 1 + j2% Plots of the frequency response of the system for the two limit values and assuming a damping ratio of e = 0.5 are shown in Fig. 3.36. The curves show that the cut-off frequency of the system for e = 0.5 is approximately 0c = wn rad/sec (3.122) The noise bandwidth of the system may be obtained by substituting Eq. (3.107) into Eq. (3.90). This substitution results in the following equation. 2 2 B = f n d (3.109) n 0 2 (2 ) ( 0) The integration can be carried out by means of partial fractions and yields 4t2 - 4 K +( + 1 B = 2 K wi (3.110) For small values of G)n/K it can be shown that Eq. (3.110) reaches a minimum when e = 0.5. Thus the noise bandwidths for the limit values of un/K and e = 0.5 become

105 n t rad B K n = 2 sec (3.111) and n rad (3.112) K,On fsec I_(jw) +6 - - O \\ \ -6 K-= o -12 K = 05.1 1 10 0 Wn Fig. 3.36. Frequency response of system. The response curves of Figs. 3.35 and 3.36, as well as the above derivations, show that the gain constant and the bandwidth of the system can be adjusted independently if a double time constant control network is employed. In the study of the synchronized system it was permissible to assume small phase angles, thus linearizing the differential equation (Eq. 3.78). This simplification cannot be made for the evaluation of the pull-in performance of the system. The.pull-in or capture range is defined as the range of difference frequencies, between the input sigmnal and the free-running VCO signal, over which the system can reach synchronism.

106 Assuming that the difference frequency between the reference signal and the free-running VCO signal is constant as defined by Eq. (3.79), Eq. (3.78) may be written Pee + KF(p) sin e = A (3.127) Mathematically then, the capture range is the maximum value of AW for which, irrespective of the initial condition of the system, the phase difference 8e reaches a steady-state value. As indicated in Eq. (3.81) with F(p) = 1, solution of the nonlinear equation is straightforward (integration may be carried out using separation of variables). In this special case which has been treated in detail by Labin (Ref. 25), the capture range is found to be equal to the lock range, i.e., {a lcapture range < K (3-128) In the case of the more elaborate control network where F(p) = 1 + l1p/l + 2P, Eq. (3.127) becomes 2 1 1 K s nW P e + K — cos e pe + -sin n (3.129) e 72 2 e e 2 e 2 This equation can be simplified by inserting the coefficients defined in Eqs. (3.112) and (3.113), and by dividing the resulting equation by 2n' This leads to the dimensionless equation 1 p + + (2 - )cos e j pe + sine = 2 P I K W e e = onn (3. 130) A further simplification is possible by defining a dimensionless frequency

107 de 1 1 e Y pee = dt (3-131) n n and one obtains a first-order differential equation from which the dimensionless time wot has been eliminated. Substituting Eq. (3.131) into (3.130) one obtains sin e W. dy _ T2S e - nn cos e (3-132) de y K Ky There is presently no analytical method to solve this equation. The equation completely defines the slope of the solution curve y(ee) at all points of aee - y plane, except for the points of stable and unstable equilibrium, y = O, o/K = sin ee. The limit of synchronization can thus be found graphically by starting the system with an infinitesimal velocity Ay at a point of unstable equilibrium, y = 0, ee = A - sin- Aw/K, and finding the value of LAK for which the solution curve just reaches the next point of unstable equilibrium located at y = O; e = 3ir - sin l LA~/k. The method is discussed by Stoker (Ref. 26) and has been used by Tellier and Preston (Ref. 27) to determine the capture range for a single time constant control network. To establish the limit curve of synchronization for given values of e and wn/K, a number of solution curves must be plotted with AW/K as a parameter. These solution curves can best be obtained by means of an analog computer. The limit of capture range in terms of AU/K then can be interpolated to any desired degree of accuracy. The result obtained in this manner by Gruen (Ref. 28) is shown in the dimensionless graph of Fig. 3.37, where AD/K is plotted as a function of wn/K for a damping ratio 5 =.5. Since this curve represents the stability

108 I,0 t.8.8.6.4 p 0 I.2 -, @nK.2.4.6.8 1.0 Fig. 3.37. Capture range of system. limit of synchronization for the system, the time required to reach synchronization is infinite when starting from any point on the limit curve. The same applies to any point on the AcL/K axis with exception of the point Aw/K = 0. Since this axis describes a system having either infinite gain or zero bandwidth neither of which has any real practical significance any discussion concerning this axis is meaningless. The practical capture range therefore lies inside the solid boundary. The individual points on the figure represent the measured pull-in curve of a particular system for which the damping ratio was maintained at e = 0.5. For small values of Cn/K this pull-in curve can be approximated by its circle of curvature which, as indicated by the dotted line, is tangent to the - A/K axis and whose center lies on the an/K axis. The capture range thus can be expressed analytically by the equation of the circle of curvature. If its radius is denoted by R, the circle is given

109 2 2 n(i _R) + (-P) = R2 (3.133) Thus, for (wn/K) -0, the capture range is approximately i(|' n'() C<URDn K - w2RnK (3.134) capture n n n R can be interpreted as a constant of proportionality which depends on the particular design of the system, and which increases as the system gets closer to the theoretical limit of synchronization. Equation (3.134) shows that the capture range for small values of cwn/K is proportional to the square root of the product of the cutoff frequency cun and the gain constant K. Since the bandwidth of a second order APC system can be adjusted independently of the gain constant, the pull-in range of such a system can exceed the noise bandwidth by any desired amount. The pull-in or capture time as shown by Richman (Ref. 29) depends upon the initial frequency offset, af cycles per sec, and the noise bandwidth, B cycles per sec, in the following manner: nf2 t 4 3f (3.135) B Equation (3.135) is valid except near the limit of the capture range where capture time approaches infinity. 3.3.2 Design Procedure. The theory discussed above is best illustrated by means of the following example. Suppose a phase lock loop is to be designed in which the total phase Jitter must not exceed 50 In addition the noise bandwidth is to be 1 kc/s and the voltage

110 tuned oscillator drift 2 kc/s. The required gain constant is found from Eq. (3.80) yielding __K = i 2A 2000 144,000 radians/sec (3.136) sin ee.087 Since IZW lock-in| < K the system will hold synchronism over a frequency range of 144,000 radians/sec. K is large compared to the required bandwidth; therefore the resonance frequency of the system is established from (3.112) n = = 2 * 1000 = 2000 radians/sec (3.137) The time constants of the control network, assuming a damping ratio of 0.5,are determined from (3.114) and (3.115) respectively =, 1 -4 TK 200 144 000 ~ 5 x 10-4 sec (3138) K 144,000.144 K 144000 = -- 4=.036 sec 2 W 2 20002 (3.139) The capture range of the system is determined from (3.134) ~ ~o capture < n K < 2 x 103 144 x 103 (3.140) < 17 x 103 rad/sec A proper choice of gain distribution and control network impedances still has to be made to fit a particular design. For example, if the peak amplitude of the reference voltage is.01 volt and the peak amplitude of the output voltage is 1 volt, then the sensitivity of the

ill oscillator control stage must be K2 = 14.4 x 106 radians/sec/volt. If the capacitor is assumed to be.01 lf for the control network of Fig. 3.34, the resistors R1 and R2 become respectively 50 x 103 ohms and 4 x 106 ohms to yield the desired time constants. For an initial frequency offset of Lf = 1 kc/sec, the capture time as given by (3.135) becomes f2 4 6 -3 B 10 In the design of the phase-lock oscillator a great deal of subjective experimentation is required. The procedure is to first design the best oscillator possible to produce the desired output frequency. To develop a suitable oscillator design,an analysis has been carried out to determine loading effects, frequency sensitivity, and other characteristics of voltage variable capacitors when used as the control element in the oscillator tank circuit. Based on this analysis the practical limits of both the tuning element and oscillator circuit parameters may be proposed. Assume the simple circuit of Fig. 3.38 where L is the total circuit inductance, Cc is the circuit capacitance including stray but not the tuning element capacitance, C* is the capacitance of the tuning element, rc represents the circuit. losses while r* represents the loss associated with the tuning element. R is merely a decoupling resistor. The frequency sensitivity of the circuit shown in Fig. 3.38 may be expressed as Af kc nS - Ev volt (3.142) =e a nv~~~~.(3.143)

112 Cc R TUNING VOLTAGE C Fig. 3.38. Equivalent circuit of a typical oscillator tank circuit. where C*C = + (3.144) c Taking the differential of Eq. (3.144) with respect to voltage yields 1 c Q * Ccc* + 6C* c c c c+ For sm*ll this becoC*mesC* For IC* small this becomes C2 ~UC'c AC*e (3-146) v = (c + c*)2 V (3 A plot of the capacitance of the tuning element (in this case a ferroelectric capacitance) versus the control voltage is shown in Fig. 3.39. The solid line shows the actual dependence of capacitance on control voltage while the dotted curve indicates that a rectangular hyperbola provides a good approximation to the solid curve over a large portion of the tuning range.

130 120 110 100 90 \: 80 70 50 40 -,) PLOT OF TYPICAL FERROELECTRIC CAPACITOR C= f(v) 30 _ (2)RECTANGULAR HYPERBOLA APPROXIMATION TO (I) C= 20 10 i I I 210 240 270 30 60 90 120 150 180 210 240 270 V (VOLTS) Fig. 3.39. Capacitance of ferroelectric capacitor vs. tuning voltage.

114 Thus K C* (3.147) where: K1 is a constant for a given ferroelectric capacitance, and V is the control voltage. If the tuning element is a back-biased diode then the dependence of C* on V may be given by K2 C* =. (3.148) V - V 0o where K2 is a constant for a given diode, VO is the contact potential, which varies slightly for different diodes, and V is the control voltage. In the case of the ferroelectric capacitor Ev 1 v2 (3.149) V and since from Eq. (3.147) K1 C*v (3.150) then nv 0V (3.151) Substituting Eq. (3.151) into (3.146) gives v (C C*)2 V (3.12)

115 The resonant frequency of the circuit of Fig. 3.38 is 1 2 f = C (3-13) The ratio df/&Nc for small Lc is LCf = C-1 1 (3.154) 2C f Substituting Eq. (3.153) into (3.154) yields Af f( IZAC~~ f~ 2C (3.155) To obtain an expression for the frequency sensitivity of the circuit, substitute Eqs. (3.155) and (3.152) into (3.143) A_ f Af C S =,W Z SnV (3.156) C 2 f C C* 2C (Cc V (3157) f 1 c From Eq. (3-158) it can be seen that the sensitivity varies directly as the oscillator frequency and inversely as the control voltage. For a fixed value of control voltage a small value of C* is desirable. A second factor which has a decided effect on the loading of the tuned circuit is the loss factor (r*) associated with the tunable element. The Q of the tunable element may be represented as

116 Q* = *r * (3.159) The total Q of the circuit can be written as (* CC) (r* + r) (3.160) C r* t + rc C* + Cc The Q of the circuit,if the tunable element does not have any loss associated with it,may be represented as 1 QC w C rC (3.161) From Eq. (3.144) C* C C* + C (3.162) C or Q = C _ (3.163) The ratio of the circuit Q with loss in the tunable element (QT) to the Q without loss (Qc) is %T r QC r* + rC (3164) From Eq. (3.159)

117 r* Qcu- (3.165) 1 wli-ile from Eq. (313) C = C* C.. (3 166) K, c 0 C~ C) Substituting Eqs. (3.165) and (3.166) into (3.164) we have the following, %r 1 Q =1 cc (3.167) C _ _ _ _C c Q(* (C*+ C For C* > > C c %T 1 - 1 Q (3.168) Q* C* Since the product of Q*C* is reasonably constant over a given range the loading of the oscillator tank does not change radically with changes in control voltage. To minimize loading use a large Q*C* product. For maximum sensitivity it was found that a small C* was desirable. It appears then that the conditions for minimum loading and maximum sensitivity counter one another and a compromise must be made. It is possible to define a figure of merit which takes into consideration both the sensitivity and loading. This figure of merit may be defined as the product of the frequency sensitivity, S, and the QT of the oscillator tank circuit. Comribining Eqs. (3.158) and (3.164) one has

118 Qc 1 Q=T v PV) CC* ( (3.169) Equation (3.169) reduces to S~ = fQ* (3.170) +rc The interesting case, i.e., r* > > r occurs at the higher frequencies. Thus, Eq. (3.170) becomes S% - 2V (3 171) To maximize Eq. (3.171) for a given frequency the ferroelectric capacitor should possess a high Q* at the control voltage. In addition the control voltage should be maintained at as low a level as possible. To get at the case where rc > > r* (low frequency case), reduce Eq. (3.169) to the form Q f C r - c c c 1 (3.172) SQ~ = 2V CJ~ * r + r* (3.172) or for r > > r* SQT = 4VC* (3.173) It is seen then for the low frequency case where the circuit losses are fairly high, the tunable element loading effect becomes negligibleand the S3T product is determined mainly by the expression for the sensitivity S. Thus a small tunable element C* is desirable.

119 The conclusions regarding the performance of an APC system can be summed up as follows: Three parameters, which are (1) the gain constant k, (2) the damping ratio i, and (3) the resonance or cutoff frequency wn' completely describe the performance of the system. These parameters are specified by the requirements of the particular application and define the overall design of the system. It has been shown that among the systems with zero, single, and double time-constant control networks, only the latter fulfills the requirement for achieving good noise immunity, small steady-state phase error, and large capture range. 3.4 Analysis of Frequency Choices for the Frequency Synthesizer In the development of the frequency synthesizer system the combining of two-signal frequencies to obtain a single frequency signal in the form of their sum or difference is one of the most basic operations. When the ratio between the two frequencies to be combined is low the method is quite straightforward, since the desired result can be arrived at by using a mixer and a filter. When the ratio between the two frequencies increases, the problem of separating the desired sideband from the undesired cross-modulation products becomes progressively difficult and eventually impractical. Two signal sources cl and w2 applied to a nonlinear element (mixer) produce a spectrum of modulation products of the general form m a2 + n w1o where m and n are integers and + or - indicates the upper or lower sideband spectra. An elemental frequency-combining circuit is shown in the block diagram of Fig. 3.40. Two signal frequencies,D1 and,,are connected to a nonlinear element or mixer ml,while the phase

120 DFG- I DESIRED PLO-3 M-1 OUTPUT DFG-2 Fig. 3.40. Elementary frequency-combining network. lock oscillator PLO-3 selects and locks to the desired sum or difference frequency and suppresses to a desirable degree the other modulation products, in particular the other sideband product and the carrier frequency (the higher of the two primary frequencies). The frequency differences between a desired modulation product (o~2 + Ol) and the nearest unwanted modulation products are equal to the lower of the two frequencies to be combined. Thus the higher the ratio between w2 and w1 frequencies, the more difficult are the frequency-discrimination requirements that must be met by the PLO-3 design. An example of the technique which may be employed to determine the proper frequency choices in the present synthesizer design is presented below. Assume the desired condition is to have the range of DFG-l cover 10 kc in l-kc steps, the range of DFG-2 cover 90 kc in 10-kc steps, and thus the mixer (M-l) output will cover 100 kc in 1 step. If the lock-in range of PLO-3 is limited to a range of 150 kc, then by a suitable choice of l and 2 the unwanted mixer components which fall in the

121 desired band (w2 + ~1l) are sufficiently low in amplitude that the oscillator will lock on only the desired component. The order of mixed harmonics such as m 2 + n l is defined as Imj + Inl,and the value of Iml + Inl is selected to be some arbitrarily large number (e.g., 8 to 10). A systematic treatment was suggested by L. W. Orr and is as follows: Let w1 range from a to a + 10 kc andw2 range from b to b + 90 kc; Let the guard band have a width G kc The desired output wc2 - Wl will range from b-a-lO0 to b-a+90. There are to be no low-order harmonics between b-a-lO0-G and b-a+90+G. Let the desired band fall between the Nth and (N+l)th harmonic of w1' Based on the above assumptions the following equations can be set up. N(a+10) = b-a-10-G (3.174) (N+l)a = b-a+90+G (3-175) which reduces to a = 100 + 10ON + 2G (3.176) b = (N+2)a-G-90 (3.177) Assume the guard band is 20 kc wide and let N = 1. a = 100+10+40 = 150 (3.178) b = 450-20-90 = 340 (3.179) The desired output,w2 -'ranges from b-a-10 to b-a+90 or from 180 to 280 kc. The case for N = 1 is plotted in Fig. 3.41. Table I indicates the harmonics which fall in the desired band mo - ol. It

122 should be noted that harmonics below order 8 do fall in the operating region. DE SIRED LuJ L -,__I I W _ _ I II - -:a) C cN a) + -,+ + +.O O O 0.1.2.3.4.5 FREQUENCY (MC) Fig. 3.41. Frequency spectrum for case N = 1, G = 20 kc. Additional cases have been calculated and the tabulated results appear in Table II. The two numbers in the columns of harmonics are the values of m and n which result in a harmonic of m 2 - n w1 or -m w2 + n 1 falling in the useful output band. It appears from these calculations that to obtain a harmonicfree desired band up through order 8, the desired band must be placed between the 5th and 6th harmonic of ol (i.e., N = 5) regardless of the width of the guard band. The first undesired harmonics will then be 2 w2 - 8 WVU The design of PLX-3 is such that although many of these higher-order harmonics may fall in the operating range they will not fall within the set-on limits of the PLO-3 thus giving additional discrimination against unwanted harmonics in the system. The harmonics which do fall within the set-on limits will be ignored by PLa)-3 since they will not contain sufficient energy to permit capture.

123 N= 1 G = 20 kc 0)2 -el = 180 to 280 kc Harmonic Order Frequency Range (m+n) 2w2 - 31 5 200-410 kc 2t2 - 4I 6 40-260 -2wa + 6w 8 40-280 -W2 + 7X1 9 190-440 3a~2 - 5nDol 8 220-540 3W-2 - 6w 9 60-390 aW2 - 7CU1U 10 0-240 -3w2 + 8l 11 0-240 I D2 + 9w1 12 70-420 -3o2 + 100ol 13 210-580 Table I. Order of harmonics falling in desired operating range 180-280 kc.

G = 2Okc Hamonic (Amn cos (m% + nu)t tof order (6 + n) N a kc b kc (w2 -1)kc 5 6 7 8 9 10 11 2 13 14 1 150 340 180-280 2,3 2,6 2, 7 _3, 5 3,6 3,7 3,8 3,9 3,10 2 160 530 360-460 C,4 ~,5 -,9 2,10 3, L7,8 39 etc.~ 3 170 74o 560-660 2, 5 2,6 2,12 C3,9 3,10o 4 180 970 780-880 2,6 2,7 6 - - etc. 5 190 1220 1220-1120 2,-7 i, - - etc. G 50 kc 1 210 490 270-370 2,3 2,4 2,6 6,7 3 230 1010 770-870 2,5 6 - - - - etc. 5 250 i6io 1350-1450 _ _ - - 2j 2 - - - etc. Table II. Order of harmonics (m + n) falling in desired operating range -w 2

CHAPTER IV SYNTHESIZER DESIGN CONSIDERATIONS 4.1 Design Philosophy An experimental synthesizer which embodies the arrangement shown in Fig. 3.4 was designed, constructed, and tested for the purpose of demonstrating the practicability of the system. In the interest of facilitating construction and testing, some compromises were made. These were as follows: (a) Transistor circuitry would be employed throughout but no attempt would be made to minimize the number of components and the package size. In a finalized version of a synthesizer some redesign, utilizing smaller cases and printed circuit techniques coupled with a reduction in the required number of components, would permit a much smaller package size. (b) Commercial power supplies would be used for all control and operating voltages. Agairn, some redesign of the system incorporating less critical voltages and single battery operation could effect a considerable reduction in both the size of the overall system and the power requirements. (c) The synthesizer would be designed to tune over a 1 Mc range in 10 kc steps (two significant figures). If additional significant figures are desired or a larger range is required for a specific application, additional modules may be added. (d) Decade tuning would be used (10 steps per significant figure) although for certain applications where the synthesizer might be remotely programmed, a different number of steps per significant figure 125

126 might be more appropriate. (e) The primary reference would be a standard crystal with a stability of approximately one part in 105. If more stability is desired, a primary reference of greater stability may be employed. (f) Push-button tuning would be used, however the synthesizer would lend itself well to a number of different methods of programming. As a result of these considerations, a two-digit synthesizer was constructed as shown in Fig. 4.1. The discrete-frequency reference DFG- I,10.0 - 10.9 MC X 3.1 MC IN IOOKC STEPS CLOCK - DFR - I PLO- I s OSC ll 1 1.60 - 12.59 MC ) IN IOKC STEPS VI (DC CONTROL ) MIXER PLO - 3.' -VOLTAGE I V DF R-2 4 PLO- | DC CONTROL in 100 kcseps. h1.60 - 1.69 MC nVOLTAGE IN IOKC STEPS V2 DCC CONTROL ) \ VOLTAGE Fig. 4.1. Two-digit synthesizer. is provided by a five-stage shift-register generator which is synchronized by a 3.1 Me crystal clock. The output of DFG-1 is in the range 10.0-10.9 Me in 100 kc steps. The output of DFG-2 is in the range 1.50-1.69 Me in 10 kc steps. The outputs of DFG-1 and DFG-2 are combined in the mixer which in turn has an output in the range 11.50-12.59 Me in 10 kc steps.

127 4.1.1 Discrete-Frequency Reference. The discrete-frequency reference is a digital waveform generator utilizing commercially available logic modules. As shown in Fig. 4.2, it consists of a master clock, a basic five-stage shift-register generator, a clock divider and coincidence circuits. Two sequences are generated; one with a period of 10 usec DFR - I MASTER BeASIC 5 STAGE MC_.9 a 10CLOCK SHIFT REGISTER 100 KC REFERENCE O TPUT 3,1 MC GENERATOR 4.1.2 haseLck cllar Te phaslo 1.65 1.69 I CLOCK 310 KC COINCIDENCE / 1 MCCOM DIVIDER - CIRCUITS 10 SC REFERENCE OUTPUT DFR - 2 ADDI T I ONAL STAGES Fig. 4.2. Discrete-frequency reference, and one with a period of 100 psec. These sequences yield harmonics spaced at 100 kc in the tuning range of PLO-1 and harmonics spaced at 10 kc in the tuning range of PLO-2. 4.1.2 Phase-Lock Oscillator. The phase-lock oscillator in its elementary form consists of (1) a voltage-tuned oscillator, (2) a phase detector and (3) a control network, composed of a low-pass filter and dc

128 amplifier combination, as shown in the block diagram of Fig. 4.3. The REFERENCE INPUT PHASE LTER DC DETECTOR AMP VOLTAGE OUTPUT TUNED OSC TUNING VOLTAGE Fig. 4.3. Phase-lock Oscillator. schematic diagram of PLO-1 is shown in Fig. 4.4 and will be described in some detail. Since the operation of PLO-2 and PLO-3 are very similar, they will receive only brief comment. 4.1.2.1 Voltage-Controlled Oscillator. The oscillator is a straightforward adaptation of the Hartley oscillator circuit to transistors. The oscillator tunes the range from 10 to 11 Mc upon application of O to +10 volts at the tune connection and has an open-loop set-on accuracy of better than 10 kc throughout its tuning range. This means that tuning to the vicinity of any one of 10 discrete frequencies in the range 10 to 11 Mc is easily accomplished. Oscillator output is taken from the unbypassed emitter, since this provides good isolation in addition to a low impedance source. The output amplifier is included only for experimental convenience. It feeds a 50-ohm coaxial cable at a level of a few hundred millivolts.

VOLTAGE TUNABLE OSC. BALANCED PHASE DET. 0.1 470 TP 20 L_ _AA-15 TUNE1 1 K ( ( ( ( I~fj7A 4GNW 10K~IOK IN67A Io I I I, - ---- - P.001 L50MH.001 I~~~~~~~~~~~~OOK I' _ ~5M — 00 1 V-720K1 I0K J22K 60 --- - o 2N370 CAPACITOR 2 ~~~~~~~~~uLrLWPS I L. C.01 100.00 1 I~~~~~~~~~~~~~~~~~~OK I10IK 390K v ~~~BUFFER AMPS. 2.2K.001 0.1 I lK,REFERENCE 100K 20 SIGNAL 2N 370 INPUT.001 4.7 K I N759 4.7 K I K o.001 100 K o 22K 2N 1 381 2N 1381 2N 1381 PLO-I OUTPUT 2.2K.01 DC2AMP 22K I 2.2K.0220K 4.7K OOK BUFFER AMR DC AMP r-. — TUNING VOLTAGE Fig. 4.4 Schematic diagram of PLO-i.

130 4.1.3 Phase Detector. The phase detector is a balanced type constructed for wideband operation and adequate isolation between inputs. The electrostatic shield between primary and secondary windings of the oscillator signal coil was found necessary to preserve good balance characteristics. The advantage of this type of detector is that variations in input signal levels do not seriously affect the detector output. For experimental purposes both the oscillator and reference inputs are provided with buffer amplifiers. The output of the phase detector is a function of the phase difference between the oscillator and reference inputs as shown in Fig. 4.5. The voltage across the balanced coil in 0.6 U 0.4 H 0 0.2 H 0 o -0.2 -0.4 -0.6 0 90 180 -0.8 I I I PHASE DIFFERENCE (DEG.) Fig. 4.5. Characteristic curve of the phase detector. from the reference signal is presented in Fig. 4.6(b). In these measure

131 ments the reference signal was maintained at 350 Av or about the level required for a 30 kc capture range. The coils are peaked on the high 400300 C) 200"_ 1PHASE DETECTOR: I00_ OSC. AMPL. (350 OV REFERENCE INPUT) (A) 0 - 2.5 2.0 1.5 U PHASE DETECTOR REF, AMPL.,.a J (350F/v REFERENCE INPUT) 0.5 (B) I I I i-0 I...O 9.8 10.0 10.2 10.4 10.6 10.8 11.0 11.2 11.4 Fig. 4.6. Oscillator and reference amplitude at the phase detector coil as a function of frequency. frequency side of the 10-11 Me range for the reason that the oscillator sensitivity falls off at high tuning voltages. The frequency response of the phase detector is shown in Fig. 4.7.

132 +5 w z o 0o -5 w -IO z D c 10K 20K 50K 100lK 200K 500K I M FREQUENCY (CPS) Fig. 4.7. Phase-detector frequency response. 4.1.4 Control Network. The use of the control network at the phase detector output enables one to make the overall gain constant (K) as large as desirable and at the same time restrict the loop bandwidth for good noise immunity (i.e., noise which arises from adjacent spectrum point modulation of the output). In the PLO, the control network takes the form of a dc amplifier followed by a low-pass filter. Goals for the control network include: (1) Maintain a phase shift from dc to the maximum expected pull-in requirement (in this case 30 kc) as low as possible. (2) Attenuate frequencies above the maximum expected pull-in range as rapidly as possible in order that unfiltered adjacent spectrum modulation be minimized. (3) Provide adequate gain up to the maximum pull-in

133 requirement expected. An unstable mode of operation exists in a feedback amplifier when the open-loop gain is equal to unity and the open-loop phase shift around the loop is 180 degrees. The design problem that exists in any closed-loop system, then, is to insure that open-loop gain is much less than one when the open-loop phase shift is 180 degrees. Due to the three control network requirements not being mutually compatible, some design compromises were necessary to insure an adequate stability margin. The dc amplifier whose frequency response is shown in Fig. 4.8 provides a convenient means for experimenting with loop gain. It has a 40 30 z 20 1K 10 K 100 K IM FREQUENCY (CPS) Fig. 4.8. Dc amplifier gain-frequency characteristic. bandwidth in excess of 600 kc, a gain of up to 40 db, a high input impedance and low output impedance. The dc amplifier is more complex than would be necessary in a nonexperimental circuit and in fact its use may be unnecessary in a final model of the phase-lock loop.

134 The low-pass filter is an m-derived type which cuts off about 40 kc. To reduce adjacent spectrum point modulation of the output, an infinite attenuation point at 100 kc was included. In some cases it may be necessary to include infinite attenuation points at 200 kc, 300 kc and etc., as well as at 100 kc. The phase shift is such as to permit operation out to a capture range of 30 kc without loop oscillation. The amplitude characteristics of this filter are shown in Fig. 4.9. 60 50 400 20 z 10_ O0K lOOK IM FREQUENCY (CPS) Fig. 4.9. Low-pass filter attenuation vs. frequency characteristics. 4.1.5 Measurements. Measurements were made on the basic units, i.e., the discrete-frequency reference and the phase-lock oscillators, to determine their individual operating characteristics. The basic units were then assembled and measurements were made to determine over-all system performance.

135 4.1.5.1 Discrete-Frequency Reference Measurements. The amplitude spectrum of DFR-1 is shown in Fig. 4.10. The spectrum of DFR-l has the form of a sin x/x distribution with the 1st zero at the master clock frequency, in this case 3.1 Mc. As shown in the figure, DFR-1 has a relatively uniform distribution of spectral components, spaced 100 kc apart, in the desired operating range of 10 to 11 Mc. The output of DFR-2 28 24 - 2016 12 8 D Id 6 l g0.2 4 6 8 10 12 14 FREQUENCY (MC) Fig. 4.10. Discrete-frequency reference amplitude vs. frequency. also has a relatively uniform distribution of spectral components, spaced 10 kc apart, in the desired operating range of 1.60 to 1.69 Mc. Since the capture range of each PLO is a function of the energy in the reference signal and, since it is desirable to have the same capture range at each

136 reference point, it is important that a uniform distribution of spectral components be obtained throughout the desired operating range. 4.1.5.2 Phase-Lock Oscillator Measurements. The measurements of such dynamic characteristics as capture range, lock range, convergence time, stability, and spectral purity have been obtained and are described in the following text. The capture and lock ranges, which were found to be approximately equal, vary as a function of the input reference amplitude as shown in the example of Fig. 4.11. It can be seen from the figure that for any 80 70- 0 60 50C.) 40 30 20 0 10.J O I 2 3 INPUT REFERENCE(MV) Fig. 4.11. Lock range vs. reference input of PLO-1. given frequency the capture and lock ranges are linear functions of the

137 reference amplitude. For a given constant input reference amplitude of 2 my, it was found that the capture and lock ranges of PLO-1 varied between the limits of 40 and 50 kc over the desired operating range. While in the case of PLO-2, the capture and lock range varied between the limits of 4 and 5 kc over the desired operating range. A plot of lock range versus frequency for PLO-1 is shown in Fig. 4.12. If in 50 45z A 40o 9.9 10 10.1 10.2 10 10.4 10.5 10.6 10.7 10.8 10.9 FREQUENCY (MC) Fig. 4.12. Lock range vs. frequency of PLO-1 with a reference input of 2 myv. average lock range of PLO-1 is assumed to be - 45 kc/sec over the operating range, then from the expression for gain constant K K 6Lw/sin ee, it is found that K < L~/1 for e = x/2 = 2n ~ 45,000 = 264,000. e PLO stability may be broken down into two cases, namely, locked and unlocked. Lock stability depends on the stability of the primary reference which in this case is aproximately 1 part on 105.

138 Unlocked stability depends on many factors such as temperature variations, supply voltages variations, and component variations. The seriousness of the temperature problem may be demonstrated by the curves of Fig. 4.13. Curve 1 shows the frequency drift versus temperature of PLO-1 with the dc amplifier in the circuit. Curve 2 shows 200KC NOTE: CURVES NORMALIZED TO 400 C. 0OOKCCURVE 3 croz CURVE 2 -IOOKC IL -2 00KC-300KC U VE I 0~ -15 -10 -5 0 +50 +10o +15 +20 TEMPERATURE WDEGREES CENTIGRADE) Fig. 4.13. Frequency stability vs. temperature for PLO-1. the frequency drift versus temperature of PLO-1 with the dc amplifier out of the circuit. It can be deternined from the curves that with the dc amplifier in the circuit, the drift at 30~ C is approximately 10 kc/C,

139 while without the dc amplifier the drift is approximately 3 kc/CK. From these results it is obvious that some type of temperature compensation or control must be incorporated, if the system is to perform properly. Curve 3 is a plot of a typical PLO without dc amplifier after some redesign work had been done on the loop. In the redesign of the loop the oscillator was changed from an adaptation of a Hartley to a Colpitts circuit with the tank circuit between base and ground rather than between base and emitter. In addition, a more rigid mechanical structure and better electrical shielding all contributed to bring the temperature drift down to approximately 1 kc/C~. Figure 4.14 is a plot of the unlocked stability of PLO-1 as a function of power supply voltages. In the case of both the +10 volt supply and the -15 volt supply, a change of approximately 200 millivolts will cause a variation in frequency of about 40 kc. Although frequency instability due to supply voltage variations is a serious limitation in II.2 11.1+10 VOLT SUPPLY 110I 10.9 o 1J -15 VOLT SUPPLY D10.8 10.6 I I I I 0.1.2.3.4.5.6,7.8.9 1.0 A E (VOLTS) Fig. 4.14. Frequency in Mc vs. supply voltage changes (AE) in volts of PLO-1.

140 the laboratory model, the problem can be overcome to a large extent by including voltage regulation with Zener diodes as references in a final model. Convergence time has been defined as the total time it takes to go from one locked frequency to another. The pull-in time of the loop itself was discussed in Chapter III, where a reasonable approximation to the time required to obtain a zero difference frequency was developed for the simple case (Eq. 3.104) and stated for the general case (Eq. 3.135). In any practical application the tuning voltage must be applied to the tuning diode through some drive network. From the standpoint of tuning, the VCO appears as shown in the circuit arrangement of Fig. 4.15 ROUGH DRiVE LOOP TUNING NETWORK VA RV8 FILTER ERROR LOW "" LOW FREQUENCY VCO FREQUENCY Fig. 4.15. Block diagram of VCO tuning circuit. eet ed D(P[ F(,) Fig. 4.16. Simplified diagram of VCO tuning circuit. or more simply the low frequency circuit is given by Fig. 4.16, where ed is the phase-detector output voltage, F(p) is the transfer function

141 of the loop filter, et is the tuning voltage and D(p) is the transfer function of the drive network. Assuming F(p) has been designed to meet certain basic loop requirements and is a known function, then the pullin time for the loop itself may be estimated quite closely. For example, a 100 kc loop will take approximately 10 4sec, and a 1 kc loop 1 Cisec to pull-in if the voltage applied to the diode places the frequency of the VCO well within the capture limits of the loop. Typical pull-in and escape times will be less than indicated by the example due to greater accuracy in set-on voltages and the use of large withdraw voltages. At this point close attention to the design of a drive network D(p) must be given so that the over-all convergence time is not appreciably lengthened. For example, assume that D(p) is the transfer function of the circuit shown in Fig. 4.17. R e(i) c e(o) Fig. 4.17. Circuit of simplified drive network. Hence D(p) = 1 +. The step response to this function is shown in Fig. 4.18. e(i) e TIME INPUT VOLTGE STEP TIME OUTPUT VOLTAGE STEP Fig. 4.18. Step response of simplified drive shown in Fig. 4.17.

142 For a 100 kc loop,unless the RC time constant is sufficiently small, a major part of the convergence time will be associated with the response of the drive circuit. In the case of a 100 kc loop one would pick RC < 10 usec. Usually this condition leads to a resistor which is so small as to load the tuned circuit significantly. To obtain a more rapid response than is possible with this simple network, consider the drive circuit shown in Fig. 4.19. L R ei c i e__ Fig. 4.19. Circuit diagram of a more complex drive network. The transfer impedance for this network is given by: e0 1 1 - = Z(p) = - 2 4R2 ei LC 2 R 1 4. P +L P L 1 2 = c2 4.3 and = ~J i 4.4 Thus, 2 Co Z(p) = 2 0 2 4.5 p + 2 OP + W O O The step response of this two-pole network is given in many texts, e.g., Truxel (Ref. 30) and will not be repeated here. Since it is desirable to minimize the convergence time, a fast-rise time in the drive network is required. A fast-rise time is provided by small i. However, a small e

143 also implies large overshoot. A compromise choice of A =.7 gives an overshoot of approximately 5 percent and provides rise time less than 3.2n/wo sec. If one requires the minimum convergence time for a system which has a loop pull-in time of 10 Lsec, the following condition should be imposed 3. 2r < 10,usec 0o As an example, select = 3 isec thus f = 1 Mc Hence, -12 1 10 - = L C X2 412 x 10-6 Thus, for C =.0025 of, L = 10 Ah and R = 1.4 = = 1.4 -9 90 Q. 2.5 x 10 If it is necessary to have an even more rapid response than can be provided with the two-pole network, more complex circuits with finite zeros and additional poles can be considered. A sketch indicating the performance of the voltage Vb on the control side of the tuning diode for a prescribed voltage Va on the drive side of the tuning diode is shown in Fig. 4.20. The input step voltage is arbitrarily shown as 1 percent below the required voltage for some desired frequency fl and 5 percent below the required voltage for a second desired frequency f2. This simply means that for a given frequency the voltage across the diode must be a constant. Thus, there must be a dc correction voltage on the control side of the diode proportional to the error in set-on accuracy of the drive voltage. It should be noted that

5% LOW VOLTAGE ON DRIVE SIDE OF TUNING Ct 10/0 V0 DIODE LOW t t ---- INPUT VOLTAGE TO DRIVE NETWORK VOLTAGE ON CONTROL ~~Vb l |SIDE OF TUNING DIODE Fig. 4.20. Expected drive and control circuit operation under switching conditions. as the voltage Va on the drive side of the diode begins to rise the voltage Vb on the control side begins to drop in an effort to maintain the voltage across the diode constant. As Va pulls further away, however, the lock range of the system is exceeded and a voltage proportional to the beat frequency between the VCO and the reference is obtained. As the frequency of the VCO is driven further from the reference frequency, the beat frequency increases and its amplitude decreases until the output of the phase detector drops to essentially zero. As the voltage V a takes the VCO closer to the new reference frequency,a high frequency low amplitude beat is observed. This beat decreases in frequency and grows in amplitude until the capture range is reached and thae system falls into synchronism. At this point a dc correction voltage is obtained which is

145 proportional to the error in set-on accuracy. If the above analysis is correct, then the output frequency of the VCO should change as a function of time as shown in Fig. 4.21. Lii f t - Fig. 4.21. Expected frequency variation under switching conditions. An actual measurement of the convergence time of PLO-1 was made by applying a repetitive square wave in series with the rough-tuning voltage and of such a magnitude as to carry it from one locked state to another. The results of this measurement are shown in the photo of Fig. 4.22 NOTE: Sweep rate is 20 isec per cm. Fig. 4.22. Actual drive and control circuit operation undter switching conditions. It should be noted that the photograph consists of many sweeps and, since

146 the capture time is a function of the starting phase or phase between the reference and VC;, when it, the VCO, is brought within the capture limits, the capture time will vary. The maximum convergence time for PLO-1 appears to be approximately 100 usec. Since PLO-1 has a bandwidth of about 40 kc, the pull-in time of the loop itself should be about 25 isec. The drive circuit of PLO-1 is a simple RC network with a time constant of approximately 50-60 isec. Thus, the convergence time is made up of the sum of these two or approximately 100 4sec. No attempt was made to minimize the convergence time of PLO-1 by utilizing a fastdrive voltage. If rapid switching is a requirement, then a more complex network as discussed earlier in this section could be used as the drive network. In summary it should be reemphasized that drive circuit considerations only become important when the bandwidths are large. For example, a bandwidth of 100 kc has a pull-in time of approximately 10 4sec,thus the time constant of the drive network should be kept as small as possible to maximize convergence times. In the case of a 1 kc bandwidth, the pull-in time is approximately 1 msec, thus reducing the time constant of the drive circuit to a value much below 100 Lsec will not alter the total convergence time appreciably. Spectral purity of the discrete-frequency generator is simply a measure of the purity of the output signal. In other words, how closely does the output signal approach a sine wave? The purity of the output signal will be examined under steady-state conditions since this is the mode of operation. The first factor is intermodulation of adjacent harmonics in the detector of the phase-lock loop. This intermodulation produces

147 spurious sidebands at multiples of the reference generator repetition rate. These amplitudes may be obtained from a spectrum analyzer, calibrated receiver, or indirectly through an observation of the waveform at the tuning diode. The amplitudes of these spurious sidebands were measured with respect to the desired output signal using a calibrated receiver and are presented in Fig. 4.23. A second factor is loop noise itself. Primarily due to the dc amplifier and discrete-frequency reference, the noise is confined to frequencies below approximately 1 kc/sec. Since spectrum analyzers are presently unavailable in this region, a simple narrowband discriminator was constructed having a bandwidth of approximately 1 kc at 10 Mc. The series of photographs shown in Fig. 4.24 indicate the relative noise in the system. Photograph A shows the output of the narrowband test discriminator without an input signalwhile Photograph B shows the output of the test discriminator with a sine wave input from the HP 606 Signal Generator. Note the trace of 60 cycle line frequency leaking through. Photograph C is the output of the discriminator with PLO-1 in the system and the HP 606 Signal Generator used as a sine wave reference. Photograph D is the same setup as Photograph C with the exception that the discrete frequency reference has bean substituted for the HP 606. The difference between Photographs B and C is a relative indication of the noise contributed by the loop itself. It is felt that the major part of this noise is contributed by the dc amplifier and transistor power supplies. Since Photograph D is not greatly different from Photograph C, it is assumed that the discrete-frequency reference contributes little additional noise to the over-all system. A third factor causing deterioration of the DFG-1 output results

H 0 -10 L. I -20 H OUTPUT FREQUENCY OF w -30- DFG-i (AMPLITUDE O DB) -40 I cr z -50 w a0 -7 -80I 0 6 O -90 a.z ~V) 2 23 -100 < (n 8.5 9 9.5 10 10.5 1 111.5 FREQUENCY (MC) Fig. 4.23. Amplitude of spurious sidebands relative to DFG-1 output signal versus frequency.

149 NO TEST TO INPUT DISC SCOPE Te st Setup (A) TEST TO HP 606 DISC SCOPE Test:.';etup (B) TEST TO HP 606 PLO1- I 0 DISC SCOPE Test Setup (C) ~I~TEST TO, " DFR- PLO- IR DISC SCOPE Test Setup (D) Fig. 4.24. A relative measure of the noise output of the system.

150 from clipping and distortion of the DFG signal itself. This distortion generates harmonics of the DFG frequency which, however, are easily removed through more careful design of the oscillator and buffer stages in the DFG unit. In addition, much of the distortion is removed when the synthesizer is connected to other equipment such as transmitters or receivers which have additional tuned stages. A plot of the actual 10 Mc output signal of DFG-1 is shown in Fig. 4.25. Measurements made on the operating characteristics of PLO-2 and PLO-3 shown in Fig. 4.1 (page 126) indicate that their performance meets design requirements. In addition, the output of DFR-2 is somewhat cleaner and has a more uniform amplitude distribution than DFR-1. Measurements made on the over-all system indicate that the twodigit synthesizer does perform as predicted. In a practical design, however, several considerations deserve attention. The unit should be mechanically rugged, and electrically well-shielded. The system should incorporate less critical operating voltages and single battery operation Fig. 4.25. 10 Me output signal of DFG-l.

151 and lastly, a different number of steps per significant figure might be more appropriate, especially if remote programming is anticipated.

CHAPTER V SUMMARY AND CONCLUSIONS 5.1 Introduction In the preceding chapters it has been demonstrated that effective use can be made of nonprecise tuning components in unique techniques for precise frequency synthesis. The nonprecise components which are examined in detail under the several limiting conditions of operation are solid-state devices such as controllable inductors, ferroelectric capacitors, and variable capacitance diodes. 5.2 Summary of Results The significant consequences of this investigation result from the extreme flexibility afforded by completely electronic tuning methods. The incorporation of the nonprecise components through the use of phaselock circuitry has made it possible to develop a technique of frequency synthesis which permits rapid selection of precise frequencies, is adaptable to both remote control and electronic programming, and theoretically, is unlimited in frequency range of operation. A study of various electronic tuning methods using solid-state devices is carried out in Chapter II. This study formulates basic decisions regarding the limitations of tuning elements and voltage controlled oscillator parameters. The system concept of a generalized discrete-frequency synthesizer is presented in Chapter III. The significant contribution of combining a discrete-frequency reference and an electronically-tuned phase-lock oscillator in the generation of precise frequencies is that it is possible 152

153 to construct a unit whose output frequency can have certain discrete values. This unit, called a discrete-frequency generator, has an output frequency which is precisely one of the harmonics of the discrete-frequency reference. By using several discrete frequency generators, each with different incremental steps, combining and taking the mixed output, it is possible to cover a wide over-all range in small incremental steps. The question of how to minimize for a given power spectrum the peak-to-peak amplitude of a signal is presented. A term'"eak factor" is defined and a relationship which can be effectively used as a figure of merit in the design of an appropriate frequency spectrum is developed. In addition,a study and evaluation of various methods for the efficient production of high-order harmonics with balanced energy in the frequency band of interest is carried out. Of the various methods presented for generating a discretefrequency reference,the shift register generator method is particularly interesting. The digitally-generated linear maximal sequence fulfills the condition of minimum peak factor while providing a reasonably uniform amplitude spectrum over a given band of interest. From a practical point of view the shift-register generator is simple to implement. Logic modules can be taken off the shelf and put together to form a discrete frequency reference. In addition, by using clock dividers and coincidence gates in conjunction with the shift-register generator, it is possible to obtain any number of discrete-frequency references each with different incremental steps. The basic operating principles of a phase-lock loop are presented and analyses are made in instances where the literature is not complete. In particular, a figure of merit is developed which determines the effects

154 of frequency sensitivity and loading of the tuning element on the controlled oscillator. In addition, equations for the convergence time of a phase-lock loop are developed. An analysis of the problem of combining two signal frequencies to obtain a single frequency in the form of their sum or difference while using phase-lock oscillators of a practical design is carried out. In Chapter IV the design, construction, and testing of a twodigit synthesizer was carried out to demonstrate the practicability of the system. The synthesizer was designed to tune over a 1 Mc range in 10 kc steps (two significant figures). If additional significant figures are desired or a larger operating range is required for a specific application, additional modules may be added. The discrete-frequency reference is provided by a five-stage shift-register generator. The primary reference is a standard crystal which has a long-term frequency stability of one part in 105. Over-all system stability may be increased by increasing the stability of the primary reference. The purity of the output signal was examined under steady-state conditions and it was found that the greatest contribution of noise was due to intermodulation of adjacent reference harmonics in the detector of the phase-lock loop. This intermodulation produces spurious sidebands at multiples of the reference generator repetition rate. In this particular synthesizer the spurious output is 50 db below the desired output. Additional sideband suppression may be obtained by improving the low-pass filter characteristics or using a prefiltering technique between the discrete-frequency reference and the phase-lock oscillator. Loop noise primarily due to the dc amplifier and discrete-frequency reference is confined to frequencies below approximately 1 kc/sec and was found to be

155 too low to degrade the output signal significantly. The convergence time of the over-all system is less than 250,usec in 10 kc steps. In 100 kc steps the convergence time is less than 100 isec and could be reduced to -20 4sec by reducing the time constant of the drive network. 5.3 Suggestions for Further Research The results of this investigation suggest several problems which seem worthy of study: (a) An investigation of basic techniques associated with generating a uniform amplitude frequency spectrum with the maximum amount of the total available spectrum energy in the band of interest and with a minimum peak-to-average energy ratio is recommended. An approximate approach to the problem is presented in Chapter III, Section 3.1. (b) While it is permissible to assume small phase angles for the study of the synchronized system thereby linearizing the differential equation, this simplification cannot be made for the evaluation of the pull-in performance of the system. The solutions to nonlinear differential equations are necessary if one is to establish the limit of synchronization. With lst- and 2nd-order nonlinear differential equations the limit of synchronization can be found graphically as indicated in Chapter III. However, the solutions to higher order nonlinear

156 differential equations (as would be the case if more complex control networks were used) become very unwieldy. It is suggested that a detailed investigation of high-order systems employing generalized nonlinear techniques would allow one to describe the pull-in behavior of an APC system more completely and to derive the optimum system parameters required for any particular application. (c) To date, the analyses of phase-lock oscillators have been restricted to sinusoidal reference signals. In some cases the analyses have included the effects of white Gaussian noise along with the reference signal. Since the analyses of phaselock oscillators with arbitrary periodic reference signals have not appeared in the literature, and since this problem is pertinent to synthesizer design, additional study should perhaps be undertaken, (d) Since only one of the reference components of the discrete-frequency reference need be available to the VCO at one time, improved stability and efficiency result if the unwanted components are suppressed. A promising technique (as described in Chapter III, Section 3.2.2) for implementing spectral sorting arises through the properties of reactive mixers. With further research in this area, it might be possible to employ this technique

157 directly as a frequency synthesizer, thus eliminating the need of an additional output oscillator. (e) The availability of a means of precise tuning and rapid frequency selection at remote locations suggests further work on, and exploitation of the discrete-frequency synthesizer. Since the synthesizer may be readily programmed using analog or digital techniques, it is applicable to frequencyhopping communication systems where precise tuning and rapid frequency selection are requirements. In addition, it may be used to advantage where several slave receivers at remote locations must be tuned to precisely the same frequency as required in remote-controlled direction finding nets. A further application is in airborne navigation systems requiring fast selection of predetermined channels, as required by high performance aircraft.

APPENDIX A COMPARISON OF ELECTRONIC TUNING DEVICES Mlagnetic Ferroelectric Variable Tuning Units Capacitors Capacitance Diodes Size ~ 1 cu. in..001 cu. in..003 cu. in. Weight 1 oz. < 10 ginms. < 10 gms Temp. Sensitivity.04%/C~ @ 10 ma 1%/CC @ 20 v.025%/C~ @ 4 v Hysteresis Yes Yes io Available Frequency Tuning Ratio at 1 Mc 12:1 3:1 2:1 100 Mc 2:1 3:1 2:1 500 Mc 1.3:1 1000 Mc 1.5:1 1.3:1 Maximum Useful Frequency < 500 Mc 1 kMc 10 k34c Q for f = 10 Mc 7200 - 200 > 200 100 Mc 50 75O 750 1000 Mc 10 @ 500 Mc ~ 5 @ 3 kMc ~ 10 @ 10 kMc Open Loop Set-on Accuracy (% of range) 3 - 5% - 10% 1 - 2 Tuning Power Requirement ~ 1 watt Negligible Negligible Control Cirrent or Voltage Range 0 - 50 ma 0 - 200 volts 0 - 60 volts Restriction in Amplitude of RF Peak RF voltage must not exceed back bias value Remarks Rugged construction Cheap to manufacture Fairly cheap to Fairly expensive Matched pairs are manufacture Matched pairs are cheap Matched pairs are expensive expensive 158

APPENDIX B LIMITATIONS ON SRG USED FOR DECADE SPECTRAL DIVISION The following is proof that the only limitations on the shiftregister generator used for decade spectral division are that: (1) It be a maximal sequence, and (2) The number of stages is not a multiple of 4. Lemma 512n - 1 — 512n-4 - 1 Proof 21 = 24(2n-4) 1 16(2n-4) - 16 + 15 16(2n4 - 1) + 15 If 512n-4 - 1 and since 5115, then 5 divides the right hand side. This means 5 divides the left hand side which is 2n _ 1. --'(2 ) -15 = 16(2n-4 1) If 512n - 1 and since 5115, then 5 divides the left hand side. This means 5 divides the right hand side which is 51 2n4 - 1. Note 5 and 16 have no common factors; therefore, the only way 5 can divide the right hand side is for 512n-4 - 1. Theorem 512n - 1 41n Proof F:-. 41n Note that 5124 - 1. By induction using that part of the lemma dealing with increasing index, i.e., (512n - 1 j 512n - 1)implies 5124m - 1. 159

If one were to assume that 512 - 1 where k is not a multiple of 4, then applying the lemma with the finite number of steps in direction of decreasing index (i.e., 512n-l), implies 512n-4 - 1. We find that 5 divides one of the numbers 2 - 1, 22- 1, or 23 - 1, but since 5 divides none of these the assumption that 512k - where k is not a multiple of 4 is absurd. 160

LIST OF REFERENCES 1. R. L. Craiglow and E. L. Martin, "Frequency Control Techniques for Single Sideband," Proc. IRE, Vol. 44, pp. 1697-1702, December 1956. 2. H. J. Finden, "The Frequency Synthesizer," J. IEE, Vol. 90, Part III, pp. 165-167, December 1943. 3. E. W. Poppenfus, "Stabilized Master Oscillator for Multichannel Operation," Electronics, Vol. 23, pp. 108-113, December 1950. 4. G. J. Camfield, "A Frequency Generating System for VHF Communication Equipment," J. IEE, Vol. 101, Part III, pp. 85-90, April 1954. 5. N. G. Alexakis, "Digital Input for Precision, Variable Oscillators," Electronics, pp. 56-57, October 50, 1959. 6. W. J. Polydoroff, "Incremental Permeability Tuning," Radio, October 1944. 7. C. G. Sontheimer, "Applications of High Frequency Saturable Reactors," Proc. NEC, Vol. IX, 1953. 8. T. W. Butler, Jr., "An Introduction to the Practical Application of Ferroelectrics," Cooley Electronics Laboratory Technical Memorandum No. 61, University of Michigan, pp. 2-5, October 1958. 9. W. J. Merz, "Double Hysteresis Loop of BaTiO at the Curie Point," Phys. Rev., Vol. 91, p. 513, August 1, 1953.3 10. H. Diamond and L. W. Orr, "Interim Report on Ferroelectric Materials and Their Applications," Cooley Electronics Laboratory Technical Report No. 31, University of Michigan, pp. 41-47, July 1954. 11. T. W. Butler, Jr., "Electric Tuned Capacitance-Modulated VHF Oscillator," Cooley Electronics Laboratory Technical Memorandum No. 59, University of Michigan, pp. 15-19, September 1958. 12. L. J. Giacoletto, "Junction Capacitance and Related Characteristics Using Graded Impurity Semiconductors," IRE Transactions on Electron Devices, pp. 207-14, July 1957. 13. G. F. Straube, "A Voltage Variable Capacitor," Electronic Industries, (2 parts), pp. 69-73, May 1958, and pp. 77-80, July 1958. 14. M. R. Schroeder, "Amplitude and Phase Spectra of Certain Frequency Modulated Signals," Internal Memorandum, Bell Telephone Laboratories, April 29, 1960.

LIST OF REFERENCES (Cont.) 15. A. F. Boff, et al., "A New High-Speed Effect in Solid-State Diodes," Digest of Technical Papers, 1960 International Solid-State Circuits Con.ference. 16. T. G. Birdsall, M. P. Ristenbatt, "Introduction to Linear ShiftRegister Generated Sequences," Cooley Electronics Laboratory Technical Report No. 90, University of Michigan, pp. 3-10, October 1958. 17. H. Heffner, G. Wade, "Gain, Bandwidth and Noise Characteristics of the Variable-Parameter Amplifier," Technical Report No. 28, Electron Tube Laboratory, Stanford Electronics Laboratories, p. 5. 18. S. T. Fisher, "Theory of Single-Resonance Parametric Amplifiers," Proc. IRE, Vol. 48, pp. 1227-1232, July 1960. 19. P. Leek, "Phase-Lock AFC Loop, Tracking Signals of Changing Frequency," Electronic and Radio Engineering, Vol. 34, pp. 114 and 177, April and May 1957. 20. R. Ley, "Phase Synchronization of an Oscillator, Application to a Continuously Variable Oscillator of High Stability," Ann. Radioelec. (Paris), Vol. 13, pp. 212-233, July 1958. 21. T. S. George, "Synchronizing Systems For Dot Interlaced Color TV," Proc. IRE, February 1951. 22. L. L. Rauch, "Automatic Control Course Notes," Summer 1957. 23. G. S. Brown and D. P. Campbell, Principles of Servomechanisms, John Wiley and Sons Publishing Co., New York, N. Y., 1948* 24. H. T. McAleer, "A New Look at the Phase-Locked Oscillator," Proc. IRE, Vol. 47, pp. 1137-1143, June 1959. 25. E. Labin, "Theorie de la Synchronization par Controle de Phase," Philips Res. Rep. (in French), August 1941. 26. J. J. Stokes, "Non-Linear Vibrations," Interscience, New York, 1950. 27. G. W. Preston and J. C. Tellier, "The Lock-In Performance of an AFC Circuit," Proc. IRE, February 1955. 28. W. J. Gruen, "Theory of AFC Synchronization," Proc. IRE, pp. 10431049, August 1953. 29. D. Richman, "Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television," Proc. IRE, Vol. 42, p. 106, January 1954. 30. J. G. Truxal, Automatic Feedback Control System Synthesis, McGrawHill Book Company, Inc., New York, 1955. 162

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