TiHE'iV-RSITY OF MICHIGAN INDUSTRY PROGIRAM OF TIr COLLEGE OF ENGNEEHING LOGICAL OPERATIONS ON ELECTRONIC DPN'~iT-AL ANAL-ZERS Robert N. Linebarger Instrunentation Engineering Program September, 1960

PFKFACE This work was performed by Robert N. Linebarger as a research project in partial fulf illm ent of the requirements for the Professional Degree., Instrumentation Engineer, at The University of Michigan, Ann Arbor, Michigan, August, 196O0 ii

ACKNOWIEDGMENTS The author wishes to acknowledge his appreciation for the guidance and encouragement of Professors R. Mo Howe and D, T. Greenwood of The University of Michigan in the preparation of this study, In addition, sincere appreciation is extended to the faculty of the Instrumentation Engineering Program, The University of Michigan, for the Henry E. Riggs Fellowship which has made possible this study and the professional degree program during the past year. In particular, special thanks go to my wife, Joyce, without whose helpful encouragement and many patient hours of effort this thesis would not have been possible. iii

TABLE OF CONTENTS Page PREFACE o... a o *o o D0 0 o * o 4 i AIn.\TOWILEDGIAENTS. o o 0o o 0 o 0 o * * 0 f * 0 0 0 0 o 4 * 0 0 * 0 * 0 0 t 0 0 n 0 o 0 0 0 0 0 iii S?d4MARY0 0 0 6 0 0 0 f 0 0 0 0 a 0 00 0 0 0 * a 0 0 0 0 0 0 0 0 0 0 0 0 a i LJ'ST 01F S~m3OBX66hofehouva4*oooe~o~ovoj*Xoo~*X~eoX#~oo*4bo~vvfff ~v ii LIST OAP MBOLS1 INTROD7 0 ON o a a 0 a a o I s 0 C e0 a a * a 00 a 0 0 0 0 o o a 0 0 0 0 o 0 0 vi 1 CITAPTE3~1 1 General OD CTION...... a. a. O e Oo.ooDO. 1 1.1 General......0000*00 000000..000,.....0 oo.o............. 1 12 Basic Logical Properties of Operational Amplifiers with Diode Input Circuitry~0..0..ooo 1 1o3 Operation Modes........e..o.........O........*...... 5 C HAPER 2. C01fOiENTIONAL "AND" "TR" LOGICAL OPERATIONS..0 00 0 0 6 C2RAPPIER 3. LOGICAL OPERATIONS INV-OLVING ORDERING RiELATIONS....... 11 3,1 Basic Circuits00., of 11 3.2 Canonical Formse.. o.. *...O.........................*,.. 13 3 3 Corlplementation0*.0e..00>........ o oo eO0 C o......... 16 3.4 Mixed Expressions Containing Continuous Variables and Boolean Functions.~. O.... * a................... O o o.... 21 3.5 Simplification of Ordering Relation Logical Expressions. 23 CHAPTER 4. LOGICAL OPERATIONS WITH CONTIIFJOUTS SIGNAL INPUTSO..00 26 CPAP!PXER 5o PRACfTICAL LMITATIONS OF OPERATIONAL AMPLIFIER LOGICAL CIRCUITSO, O........o....0o o o.. 31 5.1 Conventional Switching0.0 00.00......*....b0.........O0. 31 5 o 2 Continuous Signal Logic Circuits..0.,, n o... 0..... 34 GAAPTlR 6, AN APPLICATION OF ORDERING RELATION LOGIC TO AN OPTIMALIZING AULOMATIC CONTROL SYSTEMO.0...........,, 000o 35 6.1 Problem Description.. *... 0.0..0.0. 0...... * 35 6.2 Basic Logical Circuits...........00..0.0...*. o37 CHAPTER 7, AN APPLICATION OF ORDERING RELATION LOGIC TO A DUTY CYCLE OPTIMIZER................................... 43 CHIAPER 8. MISCELLAN'EOJS APPLICATIONS.*.OO*O... *.O.o.oOoo a oo. 46 iv

TA3BLI OF CONTENTfS CONT"D Page CHAPTER 9 EAMPIRICAL RESULTS AND CONCLUSIONS', I..O.n o,.o.o.o. O. 48 91 Threshold Switching Effects. 48 9,2 Optimalizing Control System Logic with Adjustable Delay. 48 9~3 TIypical Flip-Flop Response Using Operational Amplifiers~ 52 9~4 Basic Circuit Operation for Continuous Signal Logic~.... 60 9o5 Conclusionso e o *..o * O o * 4..65 APPEiNDX 1o BOOLEAN ALGEBRA TECENIQUESo...6........0...a 67 A.1 Fundamental Derivations.................. * a 0 a 00 a....... *. 67 AD 2 Canonical Forms........o.... o 0..... *.. 0 0 70 Ao3 Theorems and Canonical Transformations... o. *.o o * o 73 APPENDIX 2, ALGEBRAIC EIATMEAT OF CONTI1JOUJS INPUT SIGNAL LOGIC~ 75 CNF ES f f a a 0 a 0 a O D o a * GOa * * a 0 * 0 ~ 0 0 a ~ o 0. v 0 to c a 0 0 * 0 0 78 00T.* o~ 0O ~ o~o o o 7

SUMMARY Circuits for perfolrming logic can be easily implemented using diode circuitry on differential analyzers. Conventional "and", "or", "':egate" logical circuitry can be realized using three basic modes of binary signal inputs and outputs. Logical expressions involving ordering relations can also be corneniently implemented by using operational amplifiers, In particular, is is possible to implement expressions involving both continuous inputs for ordering relations and boolean variable inputs within a single amplifier circuito Standard Boolean Algebra reduction techniques are available for simplifying these logical expressions, in addition to set theory class incluas ingexclusion principles, It is also possible to implement a logical system, described by a modified Boolean Algebra, which operates with the maximum and minimum of a set of continuous input signals, A sumnary of rules for reduction of logical expressions is given, and the circuitry for realizing any of the valid boolean identities is shown to be derived from a basic operational amplif ier circuit o Applications of the above ordering logic are made to an optic malizing control system and a duty cycle optimizing controller~ vi

LIST OF SYMBOLS A, B, C, o.. Continuous Signal Constants X, Y, Z,. o. Continuous Input Signals to Logic Network e, t, o.. Binary output signals from operational amplifier X, y, Z, X Binary input signals to logic network t, e, Boolean Algebra complement of input signal t, e, _f Class inclusion operator Logical "and' operator +, V Logical inclusive "or" operator vii

CHAPTER 1 JINTRODUCTION 1o 1 General In the past, applications of differential analyzer equipment have in general been restricted to systems involving continuous signals, It is the purpose of this paper, however, to demonstrate that computer amplifiers, with associated non-linear circuitry, possess very effective logical prop. erties. This is particularly tIrue when dealing with logical operations on continuous signals, such as comparisons, maximization, or minimization~ Three basic logical operations on differential analyzer equipment are described: (1) Conventional "and"1, "or", "negate" logic, (2) ordering relation logic, and (3) continuous signal logic. In addition, applications of the above logical operations to an optimalizing control system and a duty cycle optimizing system are described, including logical implementation and resultso 1 2 Basic Logical Propexties of Operational Amplifiers with Diode Input C ireuitLry Operational amplifiers as used on conventional differential analyzer equipment are primarily used for linear operations upon computed. vaxiables. They possess four basic characteristics, however, that allow effective logical operations to be performed. These characteristics are: (1) Power gain through system (2) Linear input-output,relationship (3) High sensitivity to input polarity when operated with no external feedback impedance (4) Continuous signal inputs of either positive or negative polarity

Because of their high gain, conventional operational amplifiers, with no external feedback impedances can be used as binary devices. Figure 1-1 shows a conventional amplifier systen used for binary output. +eo +Sat ~-J\ _ +ei ei:e~ eo -Sat (a) (b) Figure 1-1 (a) Conventional System for Binary Output (b) Input-Output Voltage Relationships The grid voltage point, eg, becomes highly sensitive to input polarity and. magnitude, Thus, with either binary or.continuous input signals having two possible polarities, a binary amplifier output can be obtained.* The amplifier binary output can be amplitude limited by using a matched zener diode pair shunting circuit shown in Figure 1-2o ~ [-Vs +eo ei -o — e+e -Vs (a) (b) Figure 1-2 (a) Zner Diode Limited Amplifier (b) put-Output Voltage Relationships. IV i controlled by zener diode breakdown voltage,

Assuming no grid current drawn and the existance of a virtual ground at point eg for all time, the amplifier output will drive to either of its zener diode saturating levels depending upon the polarity of the input voltage. Note that for the above type of element, the polarity of the input signal represents the binary nature of the signal. Thus, input signals may be continuous, multileveled discrete, or binary. The binary output of the element will be controlled strictly by the polarity of the input. Typical binary inputs then become as shown in Figure 13,o ei ei 0 state 1 state; I I I time I time 1 state 0 state Figure 1-3 Typical Notation for Binary Input Signals. By placing a small bias signal on the input, the binary output may be made sensitive to amplitudies of the input, as shown in Figure 1-4, +Vs ei eo: ei Bias (a) (b) Bias point Figure 1-4 (a) Anplitude sensitive binary element (b) Input-output voltage relationships

In this case, depending upon the polarity of the bias signal, only a single polarity signal with two levels need be used, Note that the response of the element, Figure 1-4(b), is equivalent to that of Figunre 1l2 with the switching point moved by the bias value, allowing single polarity inputs to give a binary output depending upon their magnitude By shunting the amplifier with a conventional diode, one of the sat~uration levels may be reduced to near ground. potential, Figure 1-5 shows two such circuits and the binary outputs generated, Note that the zero level voltage will have a slight bias due to the voltage drop through the diodes Zener, Zener e io >~ = —~ 0eO ei e b ia.a-~F-~n bias (a) (b) $s7\ -'eo Figure 1-5 Circuits for' Generating Zero Voltage Binary Output Level~

1.3 Operation Modes In conventional switching systems using operational amplifiers, three possible operating modes are available for binary input signals, Figure 16 shows these operating modes for a conventional binary output, e0 eO e0 1 state 1 state 0 state ei., ei -- ei 0 state 1 state 0 state mode 1 mode 2 mode 3 Figure 1-6 Typical Input Output Relations for Conventional Binary Signal Operating Modes Note that each of the modes of operation may have their O and 1 state notation reversed, giving six possible combinations of binary signal notation.

CHAPTER 2 CONVENTIONAL "AND"Y, "OR" LOGICAL OPERATIONS Using the three possible modes shown in Figure 1-6, conventional "and", "orIt, lnegate" logic may be implemented using operational amplifiers with diode circuits. These logic circuits are directly analogous to conventional active circuitry used for digital computer logic. When operating in modes 1 and 2, however, additional bias inputs must be used to guarantee proper circuit performance for zero level signal inputs, Figure 2-1 shows the ixnclusive'"or", x or y or both, ftunctioi implementation for the three modes of inputs. Thus, in Figure 2-1 (a) for example, if the x input is 021 x + + eO (a) Mode 1 e =(x + y) y 0 NOTE: This notation implies a matched z ener diode b bias pair-see Figure 1-4(a) x o-~ — -B eO (b) Mode 2 e -(x + y) NOTE: The top polarity indicates 0" l 1 amplifier output under in+ bias put controls. The bottom polarity is output when the bias controls. 0.1 x 0 - eO (c) Mode 5 eo = -(x + y) - bias Figure 2-1 Inclusive "or" Circuits for Three Modes of Operation. -6

-7positive or the y input positive or if they are both positive, the amplifier output is negative~ Only when both inputs are negative are both input diodes blocked, In this condition the negative bias takes controls and the amplifier output becomes positive, Hence, the negative amplifier output represents an input of x or y or both, the inclusive "or" function0 The operation of the two other circuits of Figure 2-1 are directly analogous. Note that all three modes of operation require zener shunting diodes to control the limiting saturation values. In addition, a slight bias voltage is applied to insure the amplifier output going to the opposite state when both diodes are cut off, In all three modes, it is assumed that the 1 state voltage is of sufficient magnitude to avoid a threshold effect from either the input diodes or bias input. Because of the sign reversal in the operational amplifier, the outputs appear in the dual form of the mode being used, ioeo, having opposite polarity0 This characteristic will later be shown to be a definite advantage in simplifying logic implementationo Figure 2-2 shows the "and" circuit implementation for all 3 modes of inputs. Thus, in Figure 2-2 (a) for example, if both the x input and the y input are simultaneously positive, both diodes are blocked. In this condition, the negative bias takes control and the output becomes positive0 The negative amplifier output then represents the input of both x and y together, the logical "and" function, Again, the operation of the other two circuits of Figure a-2 are directly analogous,

+100 x +0-~~t-nd ~ > eo (a) Mode 1 eo -(x y) Y~q. +.. bias -100 x + eo (b) Mode 2 eo -(x y) + bias X cr - " —"h —k —le —— o eg (c) Mode 3 e0 = (x~ y) 1 bias Figure 2-2 "and" Circuit Implementation of 3 Operating Modes. Note that for implementing the "and" operation in'Figure 2-2, two bias signals must be aed, the first to control the input grid when the logical condition is met and the second. to takee control when the condition fails. Mode 3 operation displays the simplest implementation technique,

.-9 Figure 2-3 shows the implementation for complementation elements in the three modes of operation. 0*1 x- Dd~gg~~-l~e- (a) Model e0 = x - bias X eo (b) Mode 2 eO = 1 0 I + bias 1 "xcbJ l-e, (c) Mode 3 eo = X = T Figure 2-3 Complementation Circuits for 3 Operating Modes. Complementation using modes 1 and 2 are directly analogous to signal inversion except for the limiting effect upon the output, Again note that mode 3 allows the simplest implementation a simple inverter becomes the complementation device with no diodes required. It is of interest to note the resemblenace of the circuits of Figures 2-1(a), 2-2(a) and 2-3(a) to the operational circuits of conventional digital logic elements for binary inputs, as shown in Figure 2-4.

01 r " w ^ 1 1 J e \1R2 { 2 if -- x \ 3 I II x3 3 Pulse Pulse Pulse Amplifier Amplifier (a) (b) Figure 2-4 Conventional Pulsed Signal Logical Circuitry (a) Inclusive'tor?? (b) "and" Circuit. The analogy between the two systems, pulse circuit logic and operational amplifier logic, carries over completely since the operational amplifier acts only as a power gain device for its logic. For binary input signals, th4 linear ch&racteristics of the amplifier are not needed, However, for ordering logic operations, and maximum-minimum signal logic to be described later, the ltinear characteristics of operational amplifier equipment provide convenient logical outputs, Using binary input signals of mode 1, 2, and 3 operation, it has been shown that logical elmaents can be constructed from operational amplifier equipment in a very straightforward fashion, Hence, logical expressions in canonical form (see Appendix 1) can be implemented quite quicekly for experimentation on analog equipment,

GEAPTER 3 LOGICAL OPERATIONS INVOLVING OBRDERIG RELITIONS 3,1 Basic Circuits The existance of a virtrual ground at the input to an operational amplifier allows effective ordering relation logical operations to be performed~ By means of diode circuitry, the complete logical system, as derived in Appendix 1, can be implemented using operational amplifiers. The pprevious chapter has shown that operational amnplifier circuits can operate effectively as binary logical elements, summarized in Figures 2-1, 2.2, and 2.35 If a modification is now made in the diode placement, an interesting logical element involving ordering relations is created as shown in Figure 5.1l X,Y Continuous X Signals t t Binary Signal -Y 0ol -b ias Figure 3.1 Basic Logic C';ircuit.ry for Ordering RelationS $ Assmning the inpats X, Y to be continuous variables sucha that O < X < ~ref O < Y < E " +ref Then frM Figure 3-1, the following boolean expression can be written

for the output: t t (x > Y) (3-1) Where: t Binary output of amplifier operating in mode 1, 2, or 3 depending tpon validity of boolean expression on right hand side of equation () = Denotes a boolean ~epression involving ordering relations and continuous input variables. Lilkwise, by either reve rsing input variable polarities or diode direction, the dual operation may be generated. as showun in Figare 3-2~ 01( 0 1o bas bias (a) t (X < Y:x ) (b) t (Xg Y) Figue 3-2 IRal 0Ordg ri elation Circuitry, (a) by reversing input signal polarities (b) by reversing diode direction and bias Hlme, bese of -the virtual ground existing at point eg (Figure 3>2), the operational amrplifier eontinuorusly compares the tvo input signais and gene.ra tes a binary output accerdwing to the larger of the two inputso The action is a special case of the response of an open feedbak amplifier to multiple inputs, as shown in Figure 3-3

x v X7 t ~t [(X1 + 2 + X3 + X4) > 0] 3 NOTE: For this circuit only, AR4 + operation denotes conX4 / V ventional arithmetic summation~ Figure 3-3 Ordering Relation of Conventional Open Loop Amplifier Operation With Multiple Inputso The action of the diodes in Figure 3-2 serve to eliminate any coupling between two or more pairs of inputs to the same amplifier. The basic ordering relation logic may be implemented using the principle of logical duality, As discussed in Appendix 1, for each unique circiuit configuration there are two possible outputs, each the dual of the others For the basic ordering relation, a smwmary of the possible circuit configurations is presented. in Figure 3-4o 3.2 Canonical Forms As discussed in Appendaix. 1, the canonical forms of ordering relat;ionships may be implemented using a single operational amplifier. First consider the disjunction noirmal form (Msaterm) given by Equation (3-2) tt_- (X > A) + (Y > B) +t (Z > C) — o-d (3-2)

t x>Y) bias t (x<) Y) bias t= (x<)Y+b (a) t t (x Y) (b ) 32 0,) From Figure 5, i azy one of th diods condut, the amplifier t den hard. into negative satation, lited y the zener iode reak o voltage This eleentas tt i Y) bias using ( )orrin t+re (x Y)l output becomes negatively saturated. Hence. if the relations (X > A) or (Y > B) or (Z > C) or any combination of them are true, the amplifier is usi ng ordering relat iOnS.

15 t x > A)+ ( > B)+ (Z > C) X Ov -A bias *WB Figure 3-5 Implementation for Maxtermn Form of Ordering Relation Logical Expression. Likewise consider the conjunctive nQrnal form expression (Minterm) given by Equation (3-3) below: t (X > A)~ (Y > B)' (Z > C).... (3-3) Figure 3-6 shows the implementation for the first three terms of EquatiOn (3-3). t~ (X >A) (Y>B) >, (z> C) 0,1 -A t -B O- - Figure 3-6 Implementation for Mintermn Form of Ordering Relation Logical Expression~

16Emaining Figure 3-6, only when all diodes are not conducting does the output become negatively saturated, due to the small bias voltage present on the grid, Hence, (X > A) and (Y > B) and (Z > C) are simultaneously required to be true in order to block the diodes and give a negative outputS This element then generates the logical "and" function for ordering relations in minterm form0 303 Complementation As was mentioned in Chapter 2, mode 3 operation of the abowe circuit outputs (Figures 3-5, 356) allows camplementation to be easily performed by either one of the following two methods: (a) Polarity reversal of inputs (b) Diode direction reversal and reversal of output notation and bias voltage Treating the ttor" circuit first, using Equation (3-2) t (X > A) + (Y > B) + (Z > C) (3-2) Teorem 7 of Appendix 1 (DeMorgants laws) generates the following camplementary function from Equation (3-2) t+ = t e(X> A) + (Y >:) + (Z > C) (3-4) =(X > A) (y > B) X (Z > C) (3-5) Now using Equation (Ah4) from Appendix 1 -X > A) (X < A) (Y > B) (Y < B) (3-6) (Z > C) (Z < C) Substituting the above expressions into Equation (3-5) t= a (x < A) o (Y < B) o (z < C)

-17Hence, the positive output froom the ampl;ifier of Figure 35 generates the conjunctive fOLn for the complements if the individual relations. For many cases, the disjunctive form involves the dual ordering relation of Equation (3-2), as given in Equation (3-7). t - (X A) + (Y < B) + (Z < C) (3-7) = (X >A) + (Y >B) + (Z> C) This equation can be implemented in two forms: (1) By reversing the polarity of the continuous inputs or (2) reversing the diode direction, bias voltage, and output notation. Figure 3-7(a) shows the implementation using the first method while 3-7(b) shows the second method.6 t - (X < A) + (Y < B) + (Z < C) t+ = (X < A) + (Y < B) + (Z < C). _=- t t 0.1 1 Figure 7 lementatin Circuits for Odeing Relations (a) Polarity reversal method (b) Diodie direction mnd notation reversal method

-18In a similar fashion, the conjunctive normal form for the complements of the inputp relations may also be easily implemented as shown in F igure 3-8 o HIence, rollowing conrrventional Boolean Algebra rules as outlivd in Appendix 1, the dual structure of ordering relation logic is seen to be + iOnt a — tO t A -BA' 0 - 1 0 1 (a) (b) Figure 3-8 Implementgtion for Conjunctive F6rm of Order Relations., (a) Reversed input signal poarity method (b) Reversed diode -and notation methodanalogous to the dual form of conventional "and", "for" logic. As exp-ected, the.ordering relations, "t";" together with the "'+T", "1-"y operations

-19TABLE 3-1 DUAL FORM OF ORDERING RELATION LOGIC SYSTEM Operation Dual + a o + < > > < Following general Boolean Algebra techniques, if an ordering relation expression S is given, its complement S may be found by the following set of rules(1): (1) Substitute + for v and - for + everywhere in the original expression, keeping the same parenthesis notation, (2) Substitute > for < and < for > within each set of ordering relation parentheses. The dual nature of the two basic circuits, "or", "and" are smwnarized in Figures 3-9(a) through 539(d.) It is interesting to note that mixtures of ordering relations may also be used within expressions such as Equation (3-8), t = (X > A) + (Y < B) + (Z < C) (3-8) Equation (3-8) is implemented by reversing the polarity of the input signals for the second and third terms, as shown in Figure 3-10, The rules of complementation previously discussed apply to mixed systems of expressions also, as in Equation (3-8),

-20x 0 unless noted) (a) (b) -xo /' -xA +, ot A.~" - B.= as _Y O+bias Z Z -C (c) (d) t = (X < A) + (Y < B) + (Z < C) t+ = (X > A) + (Y > B) + (Z > C) t = (X > A) ~ (Y > B) ~ (Z > C) t 5 (X < A)' (Y < 3) ~ (Z < C) Figure 3-9 S ary o Duality Principle in Basic Circuits for Ordering Relation Logic

-A A -bias +bias -Y 0//',Im.Y Reltins ihiAll resistors 0.1 meg unless noted AZ 0 ZONE \W ~~~~~-C (a) (b) t - (X > A)+ (Y < B) +(Z < C) t ( (X > A)+ (Y < B)+ (Z < C) Figure 3-10 Implementation for itures of Ordering Relatiguns Within the Same Expresslono 3.4 Mixed eScpression Staining Continuous Variables and Boolean Functions Ordering relation logic may also be used with conpentional Boolean funcetions in canonical form. For expressions of the foromn: t = [(X > A) + (Y > B) + (Z < C)] + w + r +. (3-9) wherei X, A, Y s Bt ZI C o Cntinuous variables wI r o oo = Boolean varaiables in mode 3 the circuit is shown in Figre 3-11, Similarly, conjunctive expressions may also be implemented of the form: t [(X > A) + L(Y > B) + (Z < C)]Ow Or o (3-10) The circuit for this type of expression is shown in Figure 3-1~o

~22X -A 1 All resistors 0.5 t meg unless noted Y + -B -bias -Z Co —/~ —" tt [(X > A) + (Y > B) + (Z < C)] + w + r.1_ Ool s1 |t+ = [(X < A) ~ (Y < B) - (Z > C)] ~ w 01 Figure 5311 Circuit for Mixed Continuous-Boolean Inputs in Disjunctive Form,. X j All resistors 0.5 -A l l meg unless noted k"B}~~ - ~~-bias Z t [(X > A) + (Y > B) + (Z < C)] * w r C t =[(XA) (Y< B) (Z > C)] + w + w, r O / Figure 3-12 Circuit for Mixed Continuus-Boolean InpUtts in Conjunctive Form.

.235 The one limitation of mixed -expressions is that mixed "and.", "or" boolean functions may not be used, Only single boolean variables connected by the * operator or the + operator, but not both, may be mixed with continuous ordering relation expressions, It should be noted at this point that the summing junction input currents caused by the boolean functions should be larger than the maximm possible input current from the ordering relations, This can be insured by proper choice of the binary input resistor magnitudes, Note in Figures 3-LL and 312, the binary variable input resistors give a 5 to 1 cEurrent ratio for identical input amplitudes of the continuous and binary signals, Hence, if the boolean signal inputs are gain boosted to the maximum level of any of the continuous inputs, the resistor ratio will insure proper operation, Thus, it is possible to implement logical expressions involving both binary and continuous inputs with a single operational amplifier, The circuit operation follows all the rules of Boolean Algebra applied to ordering relations and binary functions, 3,5 Simpliffication of Ordering Relation Logical Expressions In addition to the normal operational rules of Boolean Algebra as outlined in Appendix 1, an additional principle of set theory class inclusion-exclusion may be applied to simplify ordering relation logic expressions, From consistenoy relations(2), the statements X < Y, X * Y = X, X + Y Y are all equivalent. In addition, set theory operations may be utilized

to reduce ordering relation expressions. For example, if (Y > A) and (Y > B) where (A < B) then (Y > B) C (Y > A) Hence, statement of (Y > B) automatically implies (Y > A). If both expressions appear in an ordering expression, one may be eliminated since it is autmaticall ly implied by the validity of the otrkh term. EVlaple 3-1: Given the expression: t = [(Y < 6) + (Y > 4) ~ w] (3-11) note that (Y < 6) = (Y > 6) g (Y > 4) (312) Hence, if (Y > 6) is true, then it must follow that (Y > 4) is also true. The set (Y > 6) may then be substituted for the set (Y > 4) providing the subset (4 < Y < 6) is contained in some other set term in the expression. Since (Y < 6) satisfies this condition, the following substitution may be mad.e: (Y > 6) < (Y > 4) (3-13) (The reader should be cautioned to carefully examine the conditions allowing this substitutiono This reduction technique is valid only when the subset eliminated is contained in one of the sets of the bracketed portion of the expression), Equation (3-13) then becomes: t = (~ < 6) + (Y > 6) ~ w (3-14) The substitution can be made since the term (Y < 6) makes the expression true regardless of the validity of the second term for 4 < Y < 6, Hence, the second term is of importance only for (Y > 6). Rewriting Equation (3-14) by using complementation: t. (Y < 6) + (Y < 6) w (3-15)

- 25 This is of the form a + a ~ w, and from theorem T8 of Appendix 1, a + a w = a + w (3-16) Hence: t =; (Y < 6) + (Y > 6) w (Y < 6) + w (3-17) Example 3-2: Given the expression t (Y > o) + (Y > 4) w (3-18) note that (Y > 4) C (Y > 0) (3-19) Since (Y > 0) is an independent term in the expression, t (Y > O) + (Y > 4) o w-= ( > o) + (Y > 0) W (3-20) This is of the form a + a * w, and from theorem T4a of Appendix 1, a + a * w= a, Hence [(Y > O) + (Y > 0)' w] = (Y > O) (3-21) Thus, in addition to the normal simplification techniques of Boolean Algebra, ordering relation logical expressions can be further simplified by using set theory relations, particularly class inclusion-exclusion together with the principle of logical implication, The cornventional mapping methods for binary function simplification are all applicable to ordering logic expressions or to mixed groups of binary variables and ordering relations, In addition, it is anticipated by the author that mapping methods using comrbined Boolean Algebra-set theory relations can be developed to handle both binary variables and continuous variables inputs to logic systems~ At this stage of the investigation, however, the exact form of these mappings is not indicated.

CHAPTER 4 LOGTCAL OPERATIONS WITH CONTINUOUS SIGNAL INPUTS An interesting application of Muller's work(6) can be made by using operational amplifiers as logical summers~ Using the derivations of Appendix 2, the following operations are defined: A - B Minimum [A, B] A V B Maximum [A, B] Where: A, B, *,,, X are continuous voltages such that: -Eref < X < +Eref'This cQondition is illustrated by the Venn diagram of Figure 4t1 for two voltages A, B where A < B. A C B A B B=A A VB=B Figure 4.1 Venn Diagram for Two Voltages in a Continuous Signal Logic System. From an examination of conventional digital circuitry, analogous continuous input signal circuits may be found for the above logical operations~ Figure 2-4 displays conventional digital circuitry for the inclusive or operation and the "and" operation, Examining Figure 2.4, the junction point, el, will always assume the highest voltage of any of the binary inputs. If the inputs vary between zero and scme small positive voltage, the output becomes the logical "or" function~ -26

This techniques can be used to implement a circuit for selecting the maximum continuous input signal (7). Figure 4-2 shows such a circuit using diode inputs to an operational amplifier. Since a -100 volt bias voltage will be impressed on point el, any input magnitude between +100 and -100 volts is allowable, As the diode conducts, the voltage of the input signal is impressed on point eL, changing the current in resistor R2 from the -200 volt bias, For proper circuit operation, it must be assumed that the voltage inputs have a very low output impedance, or essentially act as a constant voltage source, Hence, point el will rise to the maximus voltage available from the inputs, where the input mode may be analogous to 1, 2, or 3O This circuit then becomes a continuous "V" gate for use in the logic system described in Appendix 2, -200 Rf R2 x cay F | el / > Loe X.2 aMode X3 | (1) eo -Max [X1, X2, X3,... Xn] Xn O H | (2) eo =-Min [X1X, X2 X3, o. Xn] Figure 4-2 Circuit for Maximum Signal Selection. In a similar fashion, a circuit for selecting the minimum input signal frit a set conatiuous inputs may also be easily implemented using diode circuitr with operational amplifiers, ixamning Figure 24(b),

~28the junction point el will always assume the lowest of the binary voltages placed on the circuit, Again, if the inputs vary between zero and some positive voltage, point el will assume the higher binary voltage only if all three inputs are simultaneously positive, thus creating the logical "and" operation. This technique can be adapted for continuous inputs as shown in Figure 4-3, Again, using a +100 volt bias at point el, any input magnitude between +100 and -100 volts is allowable, As the diode conducts, the voltage of the input is impressed upon point el, Heneqe, point el will continue to fall until the minimum input voltage is impressed on el. As in the maximizer circuit described abmore, the same assumptions on voltage sources must be made, This circuit then becomes a continuous "*" gate for use with the "V" gate previously discussed. +200 RS x eo X2 (1) eo'-Min [X12 X2, oo Xn] 0XnO - |(2) eo o -Max [X1, X2, o oo Xn] Figure 4"3 Circuit for Minimum Signal Selection, It is interesting to note the dual operation of the circuits depending upon the mode of input signals being used~ Figures 4-2 and 4-3

show that either configuration can be used. as a miaxmizing circuit or as a minimizing circuit, by the choice of operating modes 1 or 2, In adaition, mode 3 may also be used together with its dual of operation to form dual circuit responses as above. Thus, any one of the three operating modes allows use of the duality principle in implementation4 Operation of the input signals analogous to mode 1 appears to offer the greatest flexibility in logical implementation since the negative values of input signals allow a dual logical function to be implemented using opposite amplifier output polarity. This condition was also found in Chapter 2 for binary operation, Thus the ability to handle both positive and negative input signals as circuit inputs considerably increases the number of logical functions possible on a single amplifier. The operation of complementation is quite simply performed using this type of logic. From Appendix 2, Equation (A-47), the complement is defined as: A (1 - A) Since the reference used for the circuits described in this chapter is +Eref, the complement of any continuous variable is found from X (Eref X) This can be implemented by simply summing both -Ef and. +X in a conventional summer as shown in Figure 4-4. Note again that mode 1 are assumed for this complementation. Simple polarity changes modify this complementation unit for use in mode 2 operation.

130x s Crcu e = (+Eref n X) = X ref Figure 4.4 Basic Circuit for Goplemenrtationo

CHAPTER 5 PRACTICAL LIMITATIONS OF OPERATIONAL AMPLIFERt LOGICAL CIRCUITS 5o1 Conventional Switching Two definite problems exist in attempting to implement logical expressions using diod.e circuitry with operational amplifiers -First, solid state diode operation with low voltage inputs create a type of threshold effect which places a limit upon the accuracy of low level voltage comparison. Figure 5-1 shows typical diode current-voltage forward conducting characteristics at room temperature(8) By placing the diodes in a constant temperature environmen:t of about 120'C, this threshold drop can be reduced to about Ool 100 ma 10 ma 100 tia 10. Pa, o3 4 4 5 o6 D7 o8.9 1 aO Voltage across the diode (Eb) Figure 5-1 Typical Curre4-Voltage Characteristic of a Silicon Juncti6n Diode at Room Temperature.

-352 or 0.2 volts. However, with higher operating temperatures, there is a significant deterioration of the diode back resistance which may affect circuit operation. Another solution to this problem lies in new semiconductor techniques which indicate that diodes applicable to this type of switching will soon be available with threshold levels of 1 ma. at less than 0.1 volto It is felt that this latter figure is sufficiently low for switching applications, taking into account the inherent error in the input signals to the operational amplifier logic circuits. Second, it will be noted from Figures 3-1 through 3-12 that a small bias signal input is required to insure correct amplifier output when all diodes are blocked0 The magnitude of bias voltage needed is less than 01ol volt, well within the accuracy limitation imposed by the switching diodes, However, depending upan the magnitude of the D. C. amplifier offset voltage referred to the input, the switching speed of the operational amplifier may be slowed by such a low level input, and hence, the amplifier may experience uneven switching rates for positive and negative inputs. For the frequencies of continuous signals operated upon by most real-time analog computer elements, the switching speeds are entirely adequate0 This problem places a limitation, however, on the type of inputs allowed, Because of threshold effects, slowly varying comparison signals cause a "soft switch" to occur, and hence, there are both lower and upper limits on the frequencies of inputs not involving disc continuous changes. * Personal communication with.Mr George MacRoberts, Semiconductor Division, Texas Instruments Co., Cleveland, Ohio.

-335 The "soft switch"t threshold effect can be reduced somewhat by minimizing the signal dwell time in the threshold region as shown in Figures 5-2(a) and (b), Since the comparison circuit need be linearly voltage voltage Ein Ein I threshold region e ref Er \\\S \gEref I threshold i | region - ~ - time l ime soft switch soft switch region region (a) (b) Figure 5-2 Effect of Scaling of Input Variable Magnitude Upon Threshold Effect. (a) Slowly varying low level signal (b) Same signal with increased scaling operating only in the region of the threshold, the input signal may be scaled up in magnitude and the comparison made at a high level. This serves to minimize the time during which the input signal lies within the threshold band. Since binary outputs are desired, scaling problems due to large magnitude input signals are not involved. Note, however that this scaling technique may be used only when the scaled inputs do not exceed the limits of the analog reference voltages, as per conven. tional analog computer scaling. If both inputs to an ordering logic

input, are variables, it may be necessary to form the sum of the inputs in a previous summing amplifier before applying to a logic circuit. Only when both scaled variables can be kept within linear operation limits does the scaling method apply. 5 2 Continuous Signal Logic Circuits In considering the logical operations of Chapter 4 and Appendix 2, one important point must not be overlooked. The input voltages to maximum or minimum signal selection circuits should not be altered by loading effects. Thus, a constant voltage source is demanded. If the voltage source output impedance is high, significant loading errors will appear in the output~ Since it is assumed that most input voltages used will be computer generated, the low output impedance of operational amplifiers will essentially eliminate loading effects. It should also be noted that a small input bias current to the anmplifier summing junction can be used to correct for the average diode voltage drop~ When all binary inputs are being used, the bias signal may be increased in magnitude to switch sharply the amplifier when the input logic fails. Since the input signals are daiscontinuous binary voltages, the threshold effect does not enter into the operation,

CH-TAPTER. 6 AN APPLICATION OF ORIDEING RELATION LOGIC TO AN OPT:MALIZING AXUOICMATIC CONTROL SYST:E 6.1 P!roblem De:ec;ription Givren a system to b; controlled with an output variable as a function of a primary con0trol variable as shown in Figre 61 (611) For optimum system y) Cmax I-.. yo Fgig;re 61i System OuCtput Variable Wi'th Optimum Peak operaton~, E ooi rol system iLs to maxifrize the \alie of 0ry) at all t~im.e;o S inec,9't!e yo ytale will shift with t:hne and operating conditions, only the y,' -valhe and it-s d.er<ivrat-Ave are available for cont.irol pziotpo s,. enee, te f ollowing logLe system may be w-itten to de,:s ribe tlehe action of oohe peak. seeking cont rol systemo:Th.e controller will be assumed to be a bang. bang type with te positve ou:tput incu. asing the valua of y and the negative O'.'jtp-ut decreasing yo 315 15

(C > 0) and (Y > 0): Drive + (C < 0) and (Y < 0): Drive + (C > 0) and (Y < 0): Drive - (C < 0) and (Y > 0): Drive The logical expression for the control system output can then be written as: T = (c > 0) (Y > 0) + (c < 0) (Y < o) (6-1) Thus, any initial velocity displacement will return the system to the peak of the C (y) relations However, there exists a hazard in -the switching for Equation (6-1)o Since there are two control signals of two values each, there exist four possible signal combinations for the logic circuit. The proper operation of the control system depends upon how the changes of logic state are made in going from one state to another. For example, assume that (y < yO) initially. If (Y > 0) and (C > 0), a positive drive signal moves the system toward the peak, As the peak is passed, C becomes negative, giving (Y > O) ~ (C < 0). This results in a negative drive signal from the control system. The physical system will lag the control signal by a certain amount, resulting in the possibility of having Y < 0 while C < 0. This condition of dynamic lag is not shown by the functional relationship, Figuure 6-1, since it is only a static relationship curre. Hence, at the time of switching from + to - control signals, there will be a portion of time in which (Y < 0) (C < 0) will occur. This condition will cause a + control signal, driving the system away from the peak. The result is an oscillation about the switching point P3o

Note that the same condition is true when driving in the opposite direction at point P1i Keeping this hazard point in mind, the logic system can be easily implemented. 6.2 Basic Logical Circuits Since the basic control signals are ordering relations, the logic is most easily implemented using direct ordering relation logic on an operational amplifiers The circuit for Equation (6l1) is shown in Figure 6.2, l,~ o~ ~- I - 1. = A Ao b ias Figure 6-2 Implementation of Logical Expression of 6-1i The dual logic circuit is shoaw in Figure 6-j35 This implementation will be shown to have advantages for eliminating the hazard switching condition.

-38=01 L 0 +bias / AFinue po otht th r- > a)pi (ie > o)+ (F < 0) ( 0).Figure 6-3 Dual Circuit for Implementation of Equation (6-1)o A time plot of the three amplifier outputs of Figure 6-3 versus typical Y, C inputs is given in Figure 6-4 to demonstrate the problem of asynchronous switching. Note t.at. amplifier 3 gives the correct output signals with the exception of the short pulses occurring at times t2 to t3 and t5 to t6, This is caused by the delay in the C switching signal.'What is desired then, is a circuit logic which delays the Y switch point -until C has switched, The operation can be implemented rather simply in ordering logic circuitry. Using the same logic circuit as shown in Figure 6-3, a modification is made to the Y comparison input of amplifier 20 Instead of the Y comparison reference being zero, a voltage K(T) is fed back fromi amplifier 3 and used as a reference, The value of K (0 < K < 1) is adjusted to control the reference voltage, Figure 6-5 shows the modified circuit~ Examining Figure 6-4, it is noted that the

Y time J I I I + amp ~4 _ I A +t T T i + T 3t r t t2 t3 t4 t5 t6 Figure 6~4 Time Plot of Typical Logic System Signals, output of amplifier 35, +T or i-T, will always be of opposite polarity to that of the Y input, JUST B;FORE TEE HAZARD SWITCHING POINT OCCURS, Hence, by feeding back voltage from amplifier 3 to amplifier 2, a variable bias

voltage for the Y switching reference is created whose polarity is 6 always opposite to Y. Hence, the Y switching point can be properly biased in magnitude to jMch the time lag in the C switch. +b ias 0 1 effect That is, the lag is always opposite to The direction of switching, ol +bias +bias TC~rs > 0) (Y < 0) a (Y< < 0 I I) * (C > 0) o Figure 6-5 Modified Logic Qircuitry with Delay Fator to can be easily implemenate for C Switchi ng Delay o Fic must be asynchro-6ous, dilays thcan switching curves for the moified delaby changing tme sys+,em. Notiice that the delay in the ~ switch takes the foxm of a hysteresis effect.. That is, the lag is always opposite to the direction of switching, either Y > 0 or Y < Oo Hence, using the normal logical expression T+ - (~ > o)' (C > o) + (Y < o) - (C < o) (6-2) T+ can be easily implemented if synchronized switching occurSo If the logic must be asynchronous, delays can be implemented by changing the

-41.reference bias for one of the variables to be sensed. This creates an ordering relation logical expression of the form: (Y < wKT) D ( < O) + (Y > +K2T) 4 (C O) (6-3) where K1 K2 if the switching curves are symmetrical. Y I I ~ I I|i FK2SLH switching bias | | ampK1p1i | ~I~ t~tDelay I IIDelay1 amp.' _III1~~ t IJ i I I I ie 6 Tet o, o t t1 t2'13 3 i t 6 t! Figrrpe 6-6 Time Plot-o;f Modified Switehing System Re-sponseo

jp42All of the logic necessary to implement such a nonlinear controlling dewice can be achieved on conventional operational amplifiers with diode input circuitry~ It is interesting to note that the same logic as implemented above may also be used for driving a system to a minimum value of C(y)o The only changes required are to reverse the polarity notation for a positive y drivre signal and readjustment for asynchronous switching problems.

CHAPTER 7 AN APPLICATION OF ORDERING BELATION LOGIC TO A DUTY CYCLE OPTIMIZER Given a set of N machines with different power requirements, all connected to a common power source bus as shown in Figure 7-1. 1 225 3 Power Bus bar Source.S.~l~u.6 5 3F. >'&1 Duty Cycle System with Common Power Bus. the power source capacity-4e-c-iusufficient to carry all machine loadings in parallel, but it is desired to match the loading as closely as possible to the manimum rated capacity of the source. The problem is complicated by each machine having a different power requirement, online time, and operation cycle,'Thus the total load power required changes abruptly and somewhat randomly as different machines are brought onto and dropped off of the common bus line. A logic system to allow optimum loading matching, under random conditions, to a given source capacity can be implemented using combinations of ordering relations and binary inputs to an operational amplifier as follows.

Each machine has four stable states of operation as listed below: lo Off-line, not ready 2. Off-line, ready 30 Coming on-line 4, On-line In order to allow a machine to came onto the bus line, the following three statements must be simultaneously true: (a) Machine off-line, ready (b) Power required by the machine < power remaining in the source (c) No other machine has come on line within the previous 2 cycles. Note that decisions (a) and (c) are binary in form while decision (b) involves a comparison. It is assued that a continuous voltage is available for the value of the remaining power in the source (before capacity is exceeded), denoted by Pro Also, each machine presently has "off line, ready" binary signal output circuitso Assuming a transient blocking signal is available for 2 cycles after any machine comes on line, denoted as B, the logical expression for a single machine can be written as Xi - ri ~(Pi < Pr) * (B) # (Si) (7-1) where: ri ith machine ready (mode 3 binary) Si ith machine on line (mode 3 binary) B transient blocking signal (mode 3 binary) P ith machine power requirements (mode 1 continuous) Pr > available source power remaining (mode 1 continuous) Wi = ith machine on line (mode 3 binary)

j45The logical implementation of Equation (7-1) is shown in Figure 7.2, Pr — ~ Wi ~NOTE: All resistors 1 -i l / meg. unless noted Lid A +bias ri q -S e Wi- o'i (Pi < P E) u (ri) ~ (B ) ( Si ) 25 Figure 7.2 Logical Implementation of Equation (7-1) Note that by feeding back an input signal, Si, to the amplifier through a 0,25 megohm resistor, once the machine is turned on Si controls the amplifier outputt regazrdless of the other inputs signals:Hence, the logical circ-uit acts as a special type of flip-flop circuit, being reset only when the machine goes off line, Because of the ri input, the circuit is capable of being rsetr" only when the machine is off line and ready to come on line, This latter condition will depend upon the recovery time necessary asfte each machine operation and the rate at which material becomes available to the machine,

CHAPTER 8 MISCELLAEOTUS APPLICATIONS It is interesting to note that logical operations on operational amplifiers may also be extended to flip-flop actions Specifically, both minterm and. maxterm formn expressions may be used to "set" and equivalent flip-flopo Figure 8.1 shows a flip-flop circuit with mintera type input express ion1 Again, as in Appendix 2 and, C1hapter 3, note that both ozdiering relations and binary inputs can be combined as inputs to the same amplifier. Since a two amplifier circuit is used with feedback, the ouiput of amplifier 1 will be driven hard to its positive or negative saturation valbue, depending upon the zener diode limiting iAmpalifier 2 serres as an inverter-reset circuit~ Examining Figure 8.1, the logical expression noted must be met for ail the diodes to be blocked, When -l T| I('X > A) (Y > B] e w + v NOTE: All resistors 1 ATv -+ bias mego unless noted Figure 8-1 Imnplementtion of a Flip-Flop Cirilit Using 0rderting Relationship and Bihary Variab les o

amplifier 1 has a positive output, the system will be denoted as in the "set" mode. Whenever the logical expression is met, the output is driven negative. The feedback from amplifier 2 reinforces the input, and amplifier 1 remains saturated in the negative polarity state, If the input "set" conditions are removed, amplifier 1 will return to the positive state whenever a positive reset pulse is applied to amplifier 2. If the input conditions are still in effect when the reset is applied, the circuit returns to the "set" state immediately after removal of the reset pulse~ Note that all binary inputs operate in mode 3 while the continuous inputs operate analogously to mode 1. The total expression shown in Figure 8-1 should include a term for the reset value as follows; T [(X > A) * (Y > B) + w + v] * R(81) Thus, the expression is dependent upon the reset signal remaining off d.uring the set phase of operation,

CHAPSUER 9 EMPIRICAL RESULTS AND CONCLUSIONS 91 Thnreshold Switching Effects As discussed in Chapter 5, the dwell time in the comparison threshold region determines the speed of switching, Figure 9-3 through 9-6 display this effect for three different dwell times. Note from Figure 9-3 the "soft" switch occurring especially as T goes from T- to T+, requiring almost one full second, Also note that actual switching occurs at the value (X - A) = 0.5 volts which would be expected for conventional diode drops of approximately 0~5 volts, Figures 9J4 and 9-5 show improved switching response for input rates of change approximately 7 times that for Figure 993. Again note the 0.5 volt diode drop. Finally, Figure 9-6 shows the much improved switching speed when the input signal is scaled up even higher, showing full switching in less than 0.03 seconds, 9,2 Optimalizing Control System Logic with Adjustable Delay In order -to test the action of the control logic circuitry shown in Figure 6-5, a typical physical system with dynamic delays of the form of Figure 9-1 was implemented, The static optimization curve was approximated by the expression: C = K1 (Y- 2)2 (91) from which C 2Y + 2K2 (9-2)

In orier- to simulate the dynamic delays between Y and C, the general system of Figure 9-2 was implemented, Cortrolled System Surce System Parameter |Source | |Dynamics Dynamics I QI Quantizers Q2 Figure 9-1 Optimalizing Control System, T ---- C 1lp + 1 T2p + 1 P calco Physical Parameter Dynamics Dynamics siggn of Y Figure 9-2 Simulated Optimalizing Control Systemo An adjustable amorkt of dfelay may be placed into the control logic network by feedback methodso Figure 9-7 shows the actions of the optimalizing contol system with a hazard switching ef~ect shown in the bottom

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trace. This response duplicates the predicted hazard switching response of Figure 6-4~ Figure 9-7 is the response for a system hazard delay that is not sufficient to cause a limit cycle away from the optimum point Figure 9-8 shows the control system action when a small amount of switching delay is placed in the logic network. Note the improvement in the Y signal trace as the hazard switching duration is decreased. Figure 9-9 shows the system response when sufficient switching delay is provided to eliminate the hazard effect~ The Y response trace shows definite improvement. The above figures may be compared with Figures 9-10(a) and 9-10(b) to evaluate system action. Figure 9-10 shows the limit cycle behavior of the control system when no switching delay is provided to overcome a high degree of hazard switching effect. Note from Figure o 0 910(a) that the hazard occurs when the Y signal becomes zero. The Y output correctly tracks toward the optimum point until the Y condition is met, thereafter oscillating about the hazard point. Figure 911(a) and 9-11(b) display proper logic element response with switching delay provided, Note the absence of any ambiguous switching signal in the control output, T, as compared to Figure 9-7(b), Also note the smooth tracking of the Y value until the optimum point is reached., thereafter oscillating about the point. 9o3 T.pical Flip-Flop Response Using Operational Amplifiers Flip-flop action with logical inputs is shown to be possible in Chapter 9. Figures 9-12 and 9-13 confirm this response for a conventional "or" circuit and a logical "and" circuit0 Figure 9-12 shows

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the response for an input expressions of the form: t+ + (X > A) + w (9-3) Note the action of the reset pulse in Figure 9-12(b) in which R does not effect the circuit output if the input expression is still valid. Figure 9-13 shows the response for the analogous expression to Equation (9-3) above, t = (X < A) w (9-4) Note in Figure 9~13(b) the relatively low value of the reset pulse R required to reset the flip-flop action, Also, as expected, once the circuit has been set, the variation in either of the variable inputs, continuous or binary, does not affect the flip-flop outputo Figure 9-13(a) displays this effect quite sharply0 9 4 Basic Circuit Operation for Continuous Signal Logic I4ogical operations using continuous input signals have already been described in Chapter 4, Figures 9-14 through 9-17 display the dual form of the basic circuits, as predicted in Figure 4-2 and 4-3o Figure 9-14(c) shows the operation of a maximizer circuit for two inputs, shown in Figure 9.14(a) and 9-14(b)o Note from the polarity being used that the input signals operate in a continuous mode analogous to mode 1 already described. Hence, the output correctly follows the maximum of the two positive input signalso The basic circuit configuration used for the data of Figures 9l14 and 9%15 is that of Figure 4-3~ When the input mode is changed to operation analogous to mode 2, this same configuration becomes a minimization circuit. Figure 9-15(c) dispplays the circuit output for continuous negative inputs shown in

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D65Figure 9-15(a) and (b)o The operation is as expected, the output constantly following the minimum of the two input signals, Thus, the same circuit configuration can be used as a signal maximizer or minimizer by proper choice of the mode.of operation~ Similar to above, Figures 9-16 and 9-17 display the duality of logical operations for the second configuration used, that of Figure 4-2. Figure 9~16(c) shows the output correctly following the maximum of the two negative inputs, thus performing signal maximization for mode 2 operations. Figure 9-17(c) likewise shows the dual operation when mode 1 input signals are used. Note that (c) correctly follows the minimum signal input as expected. One additional point should be mentioned concerning operation of the two configirationso Either configuration can be used for maximum or minimum signal selection when mode 3 operation is specified.0 Similar to the dual form seen aboave, the maximum or minimum signal will be selected depending upon which maximum voltage, +100 or -100 volts, is chosen as the zero or one reference0 Since a ffull 200 volt bias signal is used, the entire voltage range of the — variable available on the computer, -100 to +100 volts, may be used as inputs, However, there is a definite disad.vantage in forming the complement of a logical expression if the full voltage range is used for inputs, Thus, operation analogous to mode 1 or mode 2 will permit ease of complementation by simple inversiono 9o5 Conclusions It has been shown in the derivations of previous chapters, and in the empirical data of this chapter, that rather effective logical operations may be carried out using operational amplifiers on analog computing

-66equipment, In particular, some forms of logical circuitry involving comparisons and ordering relationships can be implemented quite simply by using operational amplifiers in diode networkso It is not the purpose of this study to suggest that static logic networks be implemented on computer equipment for permanent control applications. Rather, it is suggested that conventional analog computer equipment can be used quite conrveniently for checking out the logical circuitry0 Since most control systems are simulated on analog computer equipment for design purposes, the input signals, either binary or continuous in form, are readily available for logical operations. It is interesting to note from Figures 9-7 through 913 that basic logical qTuantities such as delays are also available from this type of logical circuitry. In effect, what has been done in this study is to investigate the basic logical operations available on analog computing equipment and to simulate those operations using conventional operational amplifier circui ts Chapters 6 and 7 show that this type of logical simulation does have application to some control systemso In particular, the logical control for the optimalizing system of Chapter 6 requires only 3 amplifiers, including the adjustable delay circuitry, Reference (12) indicates conventional logical implementation requires a great deal more equipment, Although it is not within the scope of this study, the author wishes to point out the implications of control logic simulation to applications involving process control and Industrial automation, Chapter 7 shows the ease with which an application involving ordering relationas can be implemented,

APPENDIX 1 BOOLEAN ALGEBRA TECHNIQUES To illustrate the application of Boolean Algebra to logical expressions involving operational amplifiers, the basic derivation of the algebra will be given together with a summary of pertinent theorems, stated without proof. For a complete discussion of theorems and proofs, the reader lsJi referred to references (1), (2) and (5) in which rigorous derivations and complete proofs are given for the system, A-1 Fundamental Derivations We begin by defining a set K of elements a, b, c,o.. which are combinable under two operations designated as logical addition "+" and logical product "o" The postulates of the system may then be stated as follows: Pla: For every a,b in K, a + b is also in K Plb: For every a,b in K, a * b is also in K P2a: For every a in K, there exists an element 0 such that a + 0 = a P2b: For every a in K, there exists an element 1 such that a o 1 = a P3a: For every a,b in K, a + I = b + a ) (commutative law) P3bo For every a,b in K, a o b = b - a P4a: For every a,b,c in K, a + (b + c) = (a + b) + (assc iative) P4b: For every a,b,c in K, (a b) c = a (b c) P5a: For every a,b,c in K, a + (b& c) = (a + b) -(a + )) a (distributive P5b: For every a,b,c in K, a o (b+ c) = (a - b)+ (a c)J P6: For every element a of K, there exists an element a in K such that a a (ca (omplementaation) -67y

-68From the above postulates, the following theorems are stated without proof. Tla: The element 0 is unique Tlb: The element 1 is unique T2a: a + a =a t (idempotent) T2b: a - a - a T3a: a + 1 1 T3b: a 0=0 T4a: a + a b= a T4b: a - (a + b)= a + a - b = a T5: a is uniquely determined T6: (a ) a T7a~ (a + b) = a' b T7b' h a.-h) = a V S I (DeMor gan s Laws) T7b: (a b) aV'J T8: a + a o b a + b T9: a ~ (a + b)= a b T10: (a + b) - (a + c) = (a ~ c) + (a o b) Tlla: (a - c + b c) (a c ) + (b C) Tllb: (a + c) (b ) a + c) (b + c) Note the interesting dual nature of the + and. operations. Duality is a result of Boolean Algebra laws and provides symmetry to the logical operationso Given one equation as valid, its dual is also then valid as well as its complement and the dual of the complement. For example, from postulate P5a: a + (b - c) - (a + b) ~ (a + c) (A-l)

.69The dual is formed by replacing all + by * and all * by + as follows a o (b + c) = (a * b) + (a o c) P5b The complement of the first expression is by theorem 8: a. ( + ~) (a )+ (a. c) (A-2) Using the substitution technique, the dual of Equation (A-2) then becomes: a + c) = (a' + b) X (a''c ) (A,3) Thus, by proving the validity of one expression, four dual relations have been proven valid. Ordering relations involving continuous variables, such as (A > B) and (A < B), may also be considered as statements for which the validity is a binary quantity, true or false, represented by the usual binary system values 1 or 0 respectively. Also, from set theory -conditions, which also form a Boolean Algebra, the principle of set complements may be used such that (A > B) = (A < B) (A-4) Thus, the ordering relationship within parenthesis effectively be. comes a binary variable with a defined complement in terms of the compler ment of the ordering relation, All of the previous rules of Boolean Algebra hold when working with ordering functions. In addition, the complement of any ordering variable is easily expressed by reversing the ordering relationship. As an example, using postullate P5b and

-70O Equation (AJ4) above, (A > B) {(c < D) + (X >Y)) (A-5) may be expressed as(A > B). (C < D) + (A > B). (X > y) (A.6) (A > B) (C < D) + (A > B) o (X < Y) (A-7) Since ~ordering relationships form boolean variables, they may be logically combined with any other boolean variable, permitting mixed variables in the same expression. To eliminate any confusion due to notation, capital letters will be used for continuous variables while loVer case letters will designate binary variables, For example, T = (A >:B) A (x + -: r) + z. (w < 5) (A,8) forms a perfectly valid boolean expression0 A,2 Canonical Fonrms Boolean Algebra operations require a standard. form for coarison of expressions. The two most common forms are the minterm canonical form and the ma:;,ennrm canonical form, both applicable to ordering relation logical expressions~ nThe minter form is obtained by expanding a given expression, using postulate P6., until all combinations of the given fumnction variables are obtained, Each combination occurs in conjunctive form (logical product, ) with the sets of combinations connected by disjuctiorn (logical sum)

For an expression imnvolving n variables, each of which have 2 possible states, there are 2n possible unique combinations. Example A-iL Expand (x z y) + (x - z) = T into minterm form, Using postulate P6, (e, o y) + (+ z + ( Z) O (yY) T T (A-9) (xo y z)+ (: y o:) + (". y o z? + ( y y z) (A-10) For ease of notation, each minterrm will be denoted by its binary number equivalent, found by writing 0 for a complemented variable and 1 for an uncomplemented variable. Thus, the simplified minterm notation for the example A-1 above becomes: (1 1 1) + (1 1 0) + (O 1 1) + (O 0 1) T (A-ll) 7 6 3 1 The decmal equaivalents of the binary numbers are known below each minterm and serve as a convenient notation, Thus, the above example can be written as T ml + m + m6 + m7 (A-12) where the lower case m denotes a mintemn form, In a dual fashion expressions may be expanded -until all disjuyctive combinations of the input variables are obtained, Each combination is connected by conjunction. Again, for n input variables, thfere are 2n possible maxterm combinationso Example A-2: Ex:pand. T (x y) ( z) into maxterm form. Using theorem T8 (DeMorgan's law) and postulate P5 (X ):)+ { ~ Y ) + (X ~:) (A (4)

-72Again using theorem T8 T ( = (x + z) (X + z) ( (y + z) (A-15) Now adding 0 to the first term of (A-15) (x + z) + (y e y) = (x + z) + (x + z) ~ (1) + (y o ) (x + z) + (x + z)' (y + y) + (y e y) (A-16) {(x: + Z) + y} o {x + z + y} (A-17) (x + y + z) ~ (x + y + z) (A-18) Similarly for the second term of (A-15) (+y) =+y+ (z () )= ( + y z) -(+y+ ) (A-x9) For the third term (y + z) = (y + z) + (x -) = (x y + z)- ( + y + z) (A-2o) As in the case of minterm expressions, each maxterm will be denoted by the decimal equivalent of the binary number represented, Thus for example A-2, I = (x + y + z). (x + y + z). (x + y + z)* (2 + y + z). (x + y + z) ( + y + z) (A-21) is denoted as: (:1::)'(l0 ). (0 1 1) (0 1 0)' ( 1 1 ) 5 0 1 ) (A-22) 7 5 3 2 7 3 Note fram theorem T2b, Mj ~ Mj Mj Hence, T M2 * M3 M5 M7 (A-23) Where the capital letter M denotes a maxterm formo

=73Ao3 Theoremas and Canonical Transformations Basic relationships exist between minterm and maxterm forms which allow for convenient transformations~ It can be easily verified that the proper relationship is as follows (l) Mii Ml;2n_.i (A-24a) Mi m2n_,_i (A-24b) Where n= n = mber -of binary variables i = particular terni considered The following basic theorems aire stated without proofo 2nl M mi 1 (A-25) i=O 2n"1 i 0 T(A-26) i 0 Mi 1 mj tO10 (Ai27) J i~tj M. M. ~ 1 J (A-28) Now denoting by fi. Oy1 t;:e presence or absence of the ith tem, ffunctions may be conm.niently e.-ressed in either minterm or maxterm form by the following notations, 2"-12n-l f, fi mi Tii (fi + M2n.l-i) (A-29) imO~i=0 The basic theorems (A2.4) through (A-29) are important because they show that any boolean fianction may be writtenl in both mintem and max-tetrm form.

M74. Using the above canonical notation, ordering relation variables may also be denoted as being in mintenrm or maxterm form for simplicationo (Y > 3) - (Z < 5) + () * (.R > K) is in mintei. fozrm while [d > 3) +2 (z K 5)] [ (w) + (R > K:] is in ma'term form, Standard boolean reduction techniques, including mapping methlods, mnay be applied to all of the above canonical forms. These teciques are particularly well covered in references (1), (2), and. 3 9

APPENDIX 2 ALGEBRAIC TREATMENT OF CONTIN'JOS INPUT SIGNAL LOGIC Given a sys~tem involving variables A, B, C,,o., X which may be normaalized. to lie in the range 0 < X < 1, an interesting logic system may be derived. From the abovre system, the following operations are defined: Logical And: A o B Minimum [A, BJ (A-30) Logical Or: A V B Ma~ximam [A,B] Applying lattice theory to such a system(6), it can be shown that any boolean ident-ity, using the o, V relations, is valid if complementation is not involved. in the identityo These identities are summarized below: AA A A (A-31) A - B A (A-32) A o (B ) (A B) C (A-3 o 3) A.(BV) (A B V \A C) (A-34) A (A VB) A (A-35) 1 ~ A A (A-36) O o A 0 (A-37) A V A A (A-358) A V B BVA (A-39) A \ WBV C, (A V B) V/C (A-4O) A V o C j = (A VB) ~ (A VC) (A-41) A VI3B A A (A-42) -75

A V 0 A (A-43) A ~V = 1 (A-44) The inclusion relation A C B may also be used and appears as A o B = A (A-45) AV B = B (A-46) Where A < B If the complement relation is defined as: A 1 -,A (A-47) DeMorgan s laws, theorem T7, may also be used, Hence, A - B A V. (A-48) A VB A o B (A-49) Also, the rule of involution directly follows from DeMorgan's law: ( A ) 1 - ( - A) A (A-50) Not all the rules of Boolean Algebra follow however. In particular, a a =0 P6 a+ a 1 must be replaced for continuous variable logic by the expression A o A CB VB (A-51) Where A < B For questionable identities, the validity of an expression may be checked by substitution of the continuous values into both sides of the expression. The following example demonstrates this technique.

-77Example A —: Show that the boolean iden'tity (a + b) (a + c)= (a - c) a - b) (b ) c) does not hold for continuous signal logic. Let A = ~, B = 1, C = 1l A = 1 SubstitLuting into both sides of the identity (A V B) ~ (A V - 1) (~ V 1~ (V 1 2 whlile (A - C)V (A o B~1( VB c) = (~ 1)v(~' )V(1 1) 1 T5Thts the -two sides are not equivalent and the identity failso sing the formal re.duction ruals of Equation (A531) through (A-50), logical expressions involving the "V~ and. "o" relations between continuous signals may be reduced by algebraic methodso However, the systematic re. duction methods of Boolean Algebra in general are not allowed since they depend upon the expansion of the function into canonical form~, Because of the limitation of complement operations, expressed by Equation (A-51), a canonical fo:rm expanssion eqnivalent to that of Boolean Algebra cannot be obtained~ It is the authors opinion, howyever, that a mapping method, analogous to Karnaugh.(" mapping methods can be de.'ive.d Although such mappings are riot now de-vteloped., to the authors kn.owledge, the amount of researchu being conduted on many valte logic systems indicates that analogous reduction methods s:ould soon be available0

REFERENCES (1) Phister,, Jro, Montgomery0 Logical Design of Digital Computers. New York: John Wiley & Sons, Inc,, (1958), Chapters 2, 3, 4. (2) Humphrey, Jro, Watts SO Switching Circuits with Computer Applications. New York: McGraw-Hill. Book Co,, (1.958), Chapters 2, 5, 6 (3) Caldwell, Samu.el H. Switching Circuits and Logical Design. New York: John Wiley & Sons, Inc,, (1958), Chapters 3, 5o (4) Stabler, E Ro An Introduction to Mathematical. Thought. Reading, Massachusetts: Addison-Wesley Pub' Co,, (1953), Chapter 10, 45-48, 193-210 (5) Nelson5 E. Co "An Algebraic Theory for Use in. Digital. Computer Design," IRE Trans0 on Electronic Computers, EC-3, No 3, (September, 1954), 12-21l (6) Muller, Do Eo "Treatment of Transition Signals in Electronic Switching Circuits by Algebraic Methods." IRE Trans. on Electronic Computers, EC-8, No, 3, (September, 1959), 401. (7) Jackson, Albert So Analog Computation. New York: McGraw-Hill Book Co,, (1960). 194-199o (8) Notes for 1960 Summer Intensive Course in Automatic Control, Lecture Demonstration on Diode Circuits for Function Generation. Instrumentation Engro Program, University of Michigan College of Engineering, Ann Arbor, Michigano (9) Britton, J. Ro and Snively, LO C. Algebra for College Students. New York: Rinehart & Company, (1959), 334-3360 (10) Pressman, Ao I. Design of Transistorized Circuits for Digital Computers. New York: John Ro Rider Pub.o Co,, (1959), 931130 (11) Cosgriff, Robert L, Nonlinear Control. Systems0 New York: McGraw-Hill Book Co0, (1958), 304 306o (12) Cosgriff, Robert Lo'"Seros that Use Logic Can Optimize, " Control Engineering, (September, 1955), 133-1.350 (13) Ledley, Robert SO Digital Computer and Control Engineering, New York: McGraw-Hill Book Co., (1960), 295-315O (14) Culbertson, James T, Mathematics and Logic for Digital Devices. New York: DO Van Nostrand Coa, Incr, (1958) Chapters 5, 6, 8(15) Korn,'G. Ao and Korn, To Mo Electronic Analog Computers0 2nd edo New York: McGraw-Hill Book Co, (1956), 1 47-15.