T H E U N I V E R S I T Y OF M I C H I GAN Memorandum ENGINEERING DESIGN REPORT: PDP-7/MODIFIED 338 DISPLAY INTERFACE Stephen F. Lundstrom CONCOMP: Research in Conversational Use of Computers ORA Project 07449 Fo Ho Westervelt, Director supported by: DEPARTMENT OF DEFENSE ADVANCED RESEARCH PROJECTS AGENCY WASHINGTON, D.C. CONTRACT NOo DA-49-083 OSA-3050 ARPA ORDER NO. 716 administered through: OFFICE OF RESEARCH ADMINISTRATION ANN ARBOR August 1967

ENGINEERING DESIGN REPORT: PDP-7/MODIFIED 338 DISPLAY INTERFACE The purpose of the interface to the PDP-7 described below is to allow the modified DEC 338 display control (a DEC 338 display without a PDP-8 processor) to operate with the PDP-7 as its processor. The resulting interface will accept any device that will interface to a PDP-8 except those using the extended data-break facility (three-cycle data break). The addition of such a feature would be a logical extension of the design of this interface but was not attempted because no need existed for it at the time of the original design, and thus it was not economically attractive. This report will serve as a progress report for those interested in technical progress on the project, and as a maintenance manual for those responsible for system maintenance in the future. Basic design objectives and decisions will be described first. A brief discussion of programming objectives will be followed by a detailed description of the logic involved. An appendix includes a comparison of corresponding interface logic signals on the PDP-8 and the PDP-7. The only major design decision was to decide what part of the 18-bit PDP-7 word to use to provide the 12-bit PDP-8 data. It was decided to have the data bits associated with the PDP-8 data be the low-order 12 bits. This decision allows the programmer of the modified 338 display to use the high-order bits of core as special flag bits so that the 338 display program may be imbedded in a larger data structure. It also allows use of the LAW (Load Address Word) instruction of the PDP-7 to set up initialization of the display with the programmed accumulator transfer instructions with a minimum of storage requirements. Arguments concerning the instruction field being high-order bits and the sign-bit being the highorder bit were not considered to be overriding because of the different order codes of the two computers and because the PDP-7 generally uses diminished-radix-complement (one's complement) arithmetic while the PDP-8 uses radix complement - -

-2 - (two's complement) arithmetic. Thus representations of negative numbers are different in the two machines. High-order signbits are not advantageous as far as the display is concerned, since no data formats have the high-order bit set for negative moves. Logic is provided in the interface to gate the PDP-7 device address (bits 6-11) into the corresponding PDP-8 device address location when not in a data-break cycle. Figure 1 shows the correspondence of accumulator data bits,and Figure 2 shows the correspondence of memory buffer data bits. PROGRAMMING CONSIDERATIONS The same device addresses and input-output pulse (IOP) numbers that the 338 system uses are effective in the PDP-7/modified 338 display system except for the locations of the bits in the PDP-7 instructions. PDP-7 subdevice addresses are not used, but the clear-accumulator bit remains effective. As mentioned above, the modified 338 display considers its instructions to be in the low-order 12 bits of memory words. It ignores the contents of the high-order six bits except when storing into the PDP-7 memory on pushjump instructions. In such a case, the high-order bits get set to zeros. This is only in the push-down stack, of course. GENERAL TECHNICAL SUMMARY The middle six bits of the twelve-bit PDP-8 buffered memory buffer output are derived as follows. (Bit 3 is shown as typical.)

ro l 2! 3i4 g5 6 7 |8l9| O ll l2!13 14 l 15 6 1 71 - 7T lk T I- t L-I _...... --- -Ia I I 1 o 2 3 4,5..6!7 8 9 10 I l PDP-7 ACCUMULATOR PDP-8 ACCUMULATOR Figure 1 ACCUMULATOR DATA TRANSFER PDP-8 (PDP-7 IOT) MEMORY BUFFER VALID WHEN NOT IN A PDP-7 BREAK CYCLE PDP-7 MEMORY BUFFER VALID DURING PDP-7 BREAK CYCLE PDP-8 MEMORY BUFFER SAME BUFFER Figure 2. MEMORY BUFFER DATA TRANSFER

-4 - o-!> IBMB3(1) BREAK(l) (0) MB3) B ]-~ BREAK(0) 4AuMm..m.... J MBB6 (1) MBB9 (1) Figure 3. Typical Memory Buffer Bit. A slight amount of propagation delay is introduced here. The delay is approximately 3x40 nsec = 120 nsec. The time between the loading of the Instruction Register (IR) and the generation of the IOP1 (Input-Output Pulse 1) is 120 nsec minimum. The IR is loaded during T3, which begins 150 nsec after the memory strobe; T3 is 270 nsec long. The setting of the IR should take about 100 nsec. The generation of IOP1 actually takes about 60 to 80 nsec after T5. T5 starts 120 nsec after the end of T3 (or beginning of T4). Thus there is probably about 350 nsec for the worst case of 120 nsec settling. It should be noted that the PDP-7 IOTs are normally generated with different timing than with the PDP-8. The relative times are PDP-8 PDP-7 IOP1 to IOP2 1.0 vpsec.450 psec IOP2 to IOP4 1o0 psec.150 psec The difference in timing would not normally cause problems. However, the 338 display control uses IOP2 for an I/O skip instruction. The time required to propagate IOP2, generate the appropriate skip logic, and increment the PDP-7 program counter is longer than 150 nsec. The memory address register of the PDP-7 is set with the contents of the program counter at the

-5 - same time that IOP4 is generated. Thus, the skip does not occur at the correct time. To avoid this problem, the Slow Cycle is requested for any such devices. The PDP-7 I/O Slow Cycle has a minimum delay of 1 sec between I/O pulses. Currently the Slow Cycle is forced for all devices, but once the 338 display control can provide its own request, the forced Slow Cycle for all devices can be deleted. LOGIC DESCRIPTION The basic problem in the logic was to transform the PDP-7 I/O interface signals to the corresponding PDP-8 I/O interface signals. These are summarized in the Appendix. Accumulator outputs, accumulator inputs, and programmed I/O control signals are all directly compatible signals. The IOP pulses IOP1, IOP2, and IOP4 are all buffered to give cleaner pulses and more driving power. The first IOP pulse, IOP1, is delayed to allow memory buffer and accumulator outputs a chance to settle, since those signals are not buffered and are driving longer lines than usual. It may be wise at some future time to buffer these signals with R650 modules. If this is done, the delay of IOP1 can probably be deleted. The memory address and data input lines to data break have to be complemented. The memory buffer output lines would normally only be complemented, but because of the bit assignments described previously, the middle six bits of the PDP-8 memory buffer output are generated by gating the appropriate PDP-7 MB bits. The data break control signals basically have the same polarities. Some of the signals expected are not the normal PDP-7 interface signals provided. Thus, one connector has been added to the standard PDP-7 I/O interface connectors to provide these signals. The timing pulses are brought via the high-order PDP-7 data break address lines. When the PDP-7 data break multiplexer is used, the timing pulses are brought

-6 - via the same lines as described above, but only on channel zero of the multiplexer. The interface constructed uses two of the multiplexer channels, one for the modified 338 display control and one for the 201A dataphone interface (to be described in a forthcoming report). Some of the data-break control timing on the PDP-7 is slightly different than that on the PDP-8. Basically, on the PDP-7, Break Request must be dropped after the AddressAccepted pulse. On the PDP-8 the Break Request must be dropped at the beginning of Address Accepted. Besides the difference in basic timing requirements, the PDP-8 Address-Accepted pulse is only 70 nsec long, while the standard PDP-8 pulse is 100 nsec. The PDP-7 does not generate an appropriate Buffered-Break signal. To solve the above problems, a flip-flop which generates the Break signal and gates the memory buffer lines has been added. This flip-flop is set by the PDP-7 Address-Accepted pulse delayed by a W640 pulse amplifier. It is cleared on every PDP-7 clock cycle. The delayed PDP-7 Address-Accepted pulse also generates the corresponding PDP-8 Address-Accepted pulse. On the following logic diagrams, the connectors on the right-hand side of the drawings correspond to the standard PDP-8 interface connectors. The connectors on the left-hand side of the drawings connect to the appropriate points in the PDP-7. Logic Diagram 1.1 The low-order 12 bits of the PDP-7 accumulator (buffered) outputs are used to drive the PDP-8 buffered accumulator lines. The IOP1, IOP2, and IOP4 programmed I/O pulses are buffered in W640 pulse amplifiers (see Logic Diagram 1.7) as are the BT1, BT2A and B Power Clear pulses (see Logic Drawings 1o7 and 1.8)o

-7 - Logic Diagrams 1,2 and 1.3 The circuits shown develop the PDP-8 buffered memory buffer outputs. Note that the low-order 12 bits of the PDP-7 memory buffer are used. Of those, the low-order three bits and the high-order three bits are simply inverted. The middle six bits, which correspond to the I/O device address during programmed I/O instructions are developed in the circuit shown in Logic Diagram 1.3. Basically, this gate takes the PDP-7 device address when the break cycle is not in effect, and the low-order twelve bits of the PDP-7 memory buffer when the break cycle is in effect, Note that this allows standard PDP-7 programmed I/O programming to be usedo The third connector to the PDP-7 shown in Logic Diagram 1.2 is the connector carrying almost all of the required signals which are not normally provided at the PDP-7 interface and are necessary to generate the required functions at the PDP-8 interface. Logic Diagram 1.4 The low-order twelve bits of the PDP-7 accumulator are loaded from the PDP-8 accumulator input interface. The Skip, Interrupt Request, and B Run (1) signals drive the appropriate points in the PDP-7 interface directly. The Clear AC signal is not provided. Note that the functions normally provided by this signal in clearing the accumulator during programmed I/O transfers can be assumed by the programmer of the PDP-7 I/O sequence by microprogramming the Clear AC bit in the IOT instruction. The TT INST and Line (1) signals are associated with the PDP-8 line-adapter interface option and are not supported. Logic Diagrams 1o5, 1l6, and 1.7 correspond to Logic Diagrams lc8, 1.9, and 1,10 respectively. These logic diagrams describe that part of the interface involved with the multiplexed data-break facility, If the multiplexer is not used or needed, the circuits shown on Logic Diagrams 1.8, 1.9, and 1.10 may be deleted.

-8 - Logic Diagrams 1.5 and 1.8 The circuit shown on this logic diagram develops the necessary logic signals for addressing PDP-7 core addresses during data-break cycle-steals. Note that this interface is currently connected to the Type 173 multiplexer, but may be connected to the corresponding points in the I/O package. The proper PDP-7 addressing logic is developed by logically inverting the PDP-8 data-address inputs to the interface, Break Request is inverted and the transfer direction is used to drive the corresponding REQ IN line on the PDP-7. Address Accepted and B Break are generated in Logic Diagrams 1l7 and 1o8o The Increment MB signal is not supported. Logic Diagrams 1l6 and 1,o9 This circuit develops the necessary signals for input of data to the PDP-7 during input data-break cycles. Each of the twelve PDP-8 data-bit inputs are inverted and used to set the low-order twelve bits of the appropriate PDP-7 word. Cycle Select, Increment CA, and WC Overflow are signals involved in the PDP-8 three-cycle extended data-break facility. This facility is not supported in this interface. Such support would be a logical extension of this interface. Logic Diagrams 1,7 and lo10 Address Accepted is delayed slightly and buffered through the W640. The leading edge of the pulse sets the break flip-flop which generates the Buffered Break signal for the PDP-8 side of the interface. The break flip-flop is cleared by PWR CLR (see Logic Diagram 1.12) and BTP6 from the PDP-7. BTP6 is used by the multiplexer for a similar function. It should be noted that the break flip-flop is required for two reasons. First, the PDP-7 Break (B) is generated at TP6 time of the cycle before the break cycle, while

-9 - in the PDP-8, B Break is not logically set until the AddressAccepted pulse starts the data-break cycle. Second, Break (B) in the PDP-7 is logically true for any data break, clock break, or program break. Logic Diagram 1.11 The two break flip-flops on Diagrams 1o7 and 1.10 are ORed together to provide the gating signal used to gate the memory buffer bits. Logic Diagram 112 The I/O pulses,, IOP IOP2, and IOP4 are buffered solely to provide more power to drive cables. PWR CLR is generated whenever a PDP-7 BEGIN (B) or a PWR CLR NEG signal occurs. Begin (B) is generated whenever the START key is activated. The PWR CLR NEG is generated when the Clear All Flags IOT is executed and during the poweron sequence. BT1 and BT2, which correspond to core write and core read times in the PDP-8, are generated with the corresponding pulses in the PDP-7, TP6, and TP4 respectively. Note that IOP1 is delayed to allow the unbuffered signals (BAC, BMB, etc.) to settle before having to decode any lOTs.

-10 - I/0 Pk H15 |A01i 18( ACS 0 D ACB. *E ACB2 'H ACB3 *K ACB4,M ACB S -P ACB ( os — ACB 7 T — ACB8.1/0 PkJt5 IA024 1B02 ACB 9 ' AcBtO -. - ACSil b-o AC612 is-K AC134. GO ACB5 J -- ACBi7 --- Di lA13 -*E* F. *K --- — " ~IC~III, lop 1 'S OT,V (ME 34) BAC a BACi BACZ EAC3 BAC4 BAC5S BAC 6 SAC7 BAC 8 (MF34) a Irrmr I Ln - '. kiA L ori T I G0D *. -- -— I *' *P -C BAC9 =<;> SAcio -c> BAC it -. I0Pi -. I0P2 - I0P4 - +BTi _R BT2A -* PNR CLR —.s I mIOT PDPo7 DISPLkY INTERFACE LoGcc. DIAGRAM 1il

T/0 Pk HOZ 1AO3 ~ iB03 MBBO(i) D MBB l, SE MB83(i) ', MBB4(i) 'M MBB585(1i *P M887() ' - MB (1 ).... -11 - IAI! i _ %'.A p el"A -. a l. %-pvw E RiO7 0. F _'A II a I (O R i07 J__ __ C_ 1181 RiO7 K AL 1916 C,,am I w I oK: OP OT Ov 5 (ME35) -— BMB 0 (4) — ~BMB 1 (1) -— > BMB z ({) -B8MB 3 (o) - BBMB4(0) c-BMB 4 (1) a BMBs 5 I/O Pka J02 IA04 < B04 M859(i) A MBB 1i() O MBBi 2($ MBBaG (~.D I. MB817(i_{ MBB17(1' *V -- ------ IAI( (MF35) p -0 BMB ( (0) *S BMBsC (1) OH BMB7 (0).a4 BMB 8(0) 4p OMB 8(i) bS- BMHBQS ). J I I PAOitz17 L - 1621 BM8 O(l) 8 MS11(ID BTi INT REQ PwR CL NEG 1/0 PI I/0 P2 1/0 P4 PDP- 7: DISPLAY INTERFACE LoGic -D AGRAM. 2.

-12 - BMB 3(U) BMB (0D) BREAK () - MBB iO(i)BRFAKi (i MBB 1ii (I) ~ 0 BMB 5(i) 0 B50 No P UH R41 t t-i- > BM8e 7(1) BRE)AKi () +B2.... I..1 7 MBB1( 1)^ - E_ IB20 a 1 I1:: IB2I ~~ 0 (MB ~(I) PDP- 7 DISPLAY [I-FRFACF Lo/y- D~AiPAr J f "3

-13-,klI C ACtN ACIN d ACI~N, ACINd ACIN ACIN I/0 Pk1 (A05? ) L &E a & * 3 *< 5 ~M 4. *M E13 BOS (PE2) kw 7 'S I ----,- -A17 03 --- —- I --- ~D 5j - AC I s t —.- ACO I.,-E, Act __ __ K ---- AC3 I _. - AC4 I/ Pkg Fi3 IAO4 oIBO8 ACIN 9.D AcINiO * — AC ii 9 — - AClN i2 -- ACI N 3 — ' ACIN 14 GP ACI L5.SACIN Ai __ ACI N7 NV. ii F,, ' -1I.S,'1 *I Ac, -4 — AC( --- ACT -3 —AC8 _ _ _ a II - - -,,,I ' G iAI8s (PF2) -D --- AC9 --— IE --- Aci --— O. ACli — *K SKIP - ---- tNT REQ I --- — CLEAR AC --- --- B RUN (i).a1- NTT INST *VW LINE (i) Emt I rnit Fr sis-roo PDP- 7 % DISPLAY IN7r~rqACE La m ic D t skrw;R km s

-14 - MPLX DOto D IA: IP4.rp' ODA03 ODA04 0DA09 0DA10 0DAi4 0DA13 0DAi4 0 DA 14 0DA17 IA23 (ME 30).r 0 ADDR EXT 1 0ADDR E<XT3 H ~>-0-0 ADDR FXT3 *K- O DPFO (i) ~M 0- i (1) "p 0DF2 (1) *T AI19 (PE 3) 0D 0 DATA ADDR 0 E 0 0 DATA ADDR 1 - ' -4 ---0 DATA ADDR 2 0 DATA ADDR 3 ~ -0 —0 DATA ADDR 6 T0 ODATA ADDR 7 st-0 --- DATA ADDR g IA20 (PF3) DATA ADDR 9 *E DATA ADDR 10 OH t> ----40 DATA ADtR il K ---4 ---0 BREAK REQ HPLY 0 DATA INCRr.MENT Mb45 1 L0 CN(C RE 0 ATA PDP-7: DISPLAY INTERFACE * NOTE: COLLECTOR OF GROUNOE)- EMI(TTER 1R'Nc.t$TOLr1 Loc~ic DIAGRAM 1. 5

-15 - ODI 0DI 0D] 0DI 0DI 0DI 0DI 0DI 0DI MPLX D04 IA08 o *D --- j I i [2.. -- 3 K — 4 M —: p _______________ J (PE4) 7.,.V.,. B Rio7,,DA 8AT0 *'TLK p0ATABITI 7-KT E.........____~-,- -----— 0 DATA BIT 2 PLY 005 0DATA BIT3 2 IA09 - r I a.M. 2-t. ---M- -0DATA BIT4 *A9 [5- D 1 i5T u S I —.0 0 DATA ~IT S _..,,.T --- 0 DATA BIT 7 R17 - H l — ^ ----^o7p IA22 (PF4) O[ ' ' = —'" DAlT A BIT 1 i Lt-* —o-r --- - - - DATA BI 4i ---— 0 CYCLE SELECT 0WC0E SERLW T 0 DI ODI OD] PDP-7: DISPLkY INTERF'ACE LOGIC DlAC-RM 1.4

^6ADD W(t40 - 0 ADDRESS ACC 0 BREAK(l) OADDR. ACC 1830 a — C\ ACC 1810 IB30 PDP- 7: DISPLAY INTERFACE LoGic DIAGRAM n17

-17 - D EXTt J.DAO31 -iDAO4 IDAO6& I bAO7 iDAO9 I PA10 IDAII IDA13 IDAI4 4DA15 IDA14 IDAV7 1A24 IDATA ADbR O IDATA ADDlI 1DATA ADD 2 1 DATA ADDR 3 1 DATA ADDR4 I DATA ADDRS I D"TA ADDR 6 DATA ADDR 7 I DATA ADDR $ REQ iAt)DD Acc I DATA ANCC #tNOTF-: COLLEXTOR OF GRUNDED-rMIITOR T1RA*51S'TOf -I INCREMElN'T PDP-1: DiSPLIX INTE;FACE LtvcDiAc-RAmA to?

PDP-P7: DISPLAY INTERFACE,BOS LOGtc DIAGRAM 1..9 - 1 DATA BIT O -- i DATA IT 2 - DATA 8tT3 -i DTA aAT 4 - i DATA 81T 5 1 DATA BIT o -~ DATA 8IT 7r 00 - i DATA BIT 9 -i DAXTA BIT 11 - 1 CYCLE SELECT e-V REMERWT CA 0VERFLOW

-19 - I') 'I) hii cct oui I 0 u xi t 04. to %P 4E bMoo I a a I I I Lt,-o 40i $ A2 ce) 4(4

-20 - BREAO i BRAK of BREAK(0) < a) n Rai7 isgw4 122 PDp-7? Dm6PLY IHT??F LOG, c DiA, iRik

-21 - W^O40 CLR NEG B301 " "1 P R. DELAY -D 1814 4 E_ -_ aB32 W640 N F PA.+ I/0P2 --- 4Ri 814 - Bi3 4W&40 u B P 4 0P4 PA v J FPWRCut BEGIN(B^ i3 r W,40 - N ETi ^82a S Ts'R0 4 eI W640 _, A BTP4 I BT2 TP4D- 10. 1 PDP-7v' DISPLY INTER1ACE Los tc DiAt eRm i.l I

-22 -Ir I/0O Device Mlodiy connectiorns to connector sLot at H25 to be as foLLowsH25 BT i E B BEG 35KIP M TNNT REQ PWR CLR NEG -I/0Pi:-I/P4 ADD J06K-H82D TP4 ADD J06P -H32E TP& t, T'ype i73 MuiLtipLexoro ADD BOiD- DOD ~p4 ADD BOiE- DO.E rP6(

A B MODULE LAYOUT (page 1 of 3) 1 2 3 4 5 6 7 8 9 10 11 W021 W021 W021 W021 W021 W021 W021 W021 W021 W021 W021 PDP-7 PD7 P PD7 P PD7 P PD7 P PDP-7 MISC PDP-7 PDP-7 PDP-7 PDP-7 ACC ACC MBB MBB ACC ACC I/O DATA DATA DATA DATA OUT OUT 0-8 9-17 IN IN SIGNALS IN IN ADD ADD 0-8 9-17 0-8 9-17 0-8 9-17 0-8 9-17 CH0 CH0 CH0 CH0 to to to to to to to to to to H15 Ji1 H02 J02 E13 F13 MLPX MLPX MLPX MLPX D04 DOS D06 D07 W021 W021 W021 W021 W021 WQ21 W021 W021 W021 W021 PDP-7 PDP-7 PDP-7 PDP- 7 DATA DATA DATA DATA PDP-7 PDP-7 PDP-7 PDP-7 PDP-7 PDP-7 IN IN ADD ADD ACC ACC MBB MBB ACC ACC 0-8 9-17 0-8 9-17 OUT OUT 0-8 9-17 IN IN CH1 CH1 CH1 CH1 0-8 9-17 0-8 9-17 to to to to I _ I _ _ _ _ _I I!i

MODULE LAYOUT (page 2 of 3) 12 W021 PDP-7 DATA BRK CNTL CH0 to MLPX D08' 13 W021 1 PDP-8 BAC 0-8 OUT 14 W021 2 PDP-8 BAC 9-11 OUT IOPs 15 W021 3 PDP-8 BMB 0-5 OUT 16 17 18 19 W021 4 PDP-8 BMB 6-11 | OUT W021 5 PDP-8 AC 0-8 IN W021 6 PDP-8 AC 9-11 IN W021 7 PDP-8 DATA ADD 0-8 IN CH0 I i I i I 1 W021 8 PDP-8 DATA ADD 9-11 IN ADD ACC CH0 21 W021 9 PDP-8 DATA BIT 0-8 IN CH0 W021 10 PDP-8 DATA BIT 9-11 IN CH0 22 A B I I I I . 1...,. i. -. i f. i - I I I I I --- I - -!I I I W021 PDP-7 DATA BRK CNTL CH1 to R107 BIOP1 BIOP2 BIOP4 BTP6 BTP4 BBEG W640 IOP1 IOP2 IOP4 W640 PWR CLR BT1 BT2 R107 BMB0 BMB1 BMB2 BMB3 BMB4 BMBS BMB6 Rill BMB3 BMB4 BMB3 BMB3 BMB4 Rill BMB5 BMB4 BMB5 BMB5 Rill BMB6 BMB7 BMB6 BMB6 BMB7 I II I I t_ Rill BMB8 SLO CYC BMB7 REQ R107 BMB7 BMB8 BMB9 BMB10 BMB11 BREAK BREAK(1) Rill BREAK (0) OBREAK REQ 1BREAK REQ BREAK (0) BMB8 BMB8 -1

MODULE LAYOUT (page 3 of 3) 23 W021 11 PDP-8 ADD EXT 1,2,3 CHO 24 W021 7 PDP-8 DATA ADD 0-8 IN CH1 25 W021 8 PDP-8 DATA ADD 9-11 IN ADD ACC CH1 26 W021 9 PDP-8 DATA BIT 0-8 IN CH1 27 W021 10 PDP-8 DATA BIT 9-11 IN CH1 28 W021 11 PDP-8 ADD EXT 1,2,3 CH1 29 R107 1DA05S 1DA04 1DA03 1DA06 1DA07 1DA08 1DA09 30 R107 1DA10 1DAll 1DA12 1DA13 1DA14 1DA15 1DA16 31 R107 1DA17 1DATA REQ 1DI6 11DI7 1DI8 1DI9 1DI10 32 R107 1DIll 1DI12 1DI13 1DI14 1DI15 1DI16 1DI17 A B Un R107 0DA05 0DA04 0DA03 0DA06 0DA07 0DA08 0DA09 R107 ODA10 ODA11 ODA12 ODA13 0DA14 ODAS1 0DA16 R107 0DA17 0DATA REQ 0DI6 0DI7 0DI8 0DI9 0DI10 R107 0DI11 0DI12 0DI13 0DI14 0DI15 0DI16 0DI17 R202 0BREAK 1BREAK W640 OADDRESS ACC 1ADDRESS ACC R107 0ADDACC OADDRESS ACC 1ADD ACC 1ADDRESS ACC B301 BIOP1

APPENDIX INTERFACE LOGIC SIGNALS PDP-7A AND PDP-8 References: PDP-7 Interface and Installation Manual PDP-7A Logic Diagrams PDP-8 Interface and Installation Manual

-28 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION E13S EIC6 |*->* ACO PE2D E13T EIC7 L->* >* AC1 PE2E E13V EIC8 * ___ * AC2 PE2H F13D EIC9 --- * I* AC3 PE2K F13E EIC10 |* * AC4 PE2M F13H EIC1l ------ AC5 PE2P F13K EIC12 |* -— >* AC6 PE2S F13M EIC13 * ||, * AC7 PE2T F13P EIC14 _ * _* AC8 PE2V F13S EIC15 * __ * AC9 PF2D F13T EIC16 --- * AC10 PF2E F13V EIC17 * ACl 1PF2H ____ ---_ *_AC 1_____ 1 --- —-_ ----_ PF2H (In PDP-7A I/O Device) ACCUMULATOR INPUTS *Note: Collector of Grounded-Emitter Transistor

November 1967 To Whom It May Concern: The attached pages 28 to 34 are corrected pages, superseding those of the same number in the Concomp Memorandum, Engineering Design Report: PDP-7/Modified 338 Display Interface, by Stephen Fo Lundstrom, August 1967. Concomp Project: Research in Conversational Use of Computers 231 West Engineering Building Ann Arbor, Michigan 48104

-28 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION E13S EIC6 |* _* ACO PE2D E13T EIC7 ___ * * ACl PE2E E13V EIC8 __p* AC2 PE2H F13E EIC10- ---— >*4PE2M F13D EIC9 ____ >* * AC3 PE2K F13E AEIC10 * | * C4 PE2M F13H EICll _.._ * b* AC5 PE2P F13K EIC12 |____ * * AC6 PE2S F13M EIC13 * * AC7 PE2T F13P EIC14 * ___* AC8 PE2V F13S EIC15 __ AC9 PF2D F13T EIC16 _ * || * AC10 PF2E F13V EIC17 | *>* ACll PF2H (In PDP-7A I/O Device) ACCUMULATOR INPUTS Corrected page 28. Stephen F. Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967. *Note: Collector of Grounded-Emitter Transistor

-29 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION HiSS ACB6 - 0 -- BACO ME34D H15T ACB7 -.- BAC1 ME34E H15V ACB8 --- - 0C BAC2 ME34H J15D ACB9 ------ BAC3 ME34K J15E ACB10 -— _ -- BAC4 ME34M J15H ACBll - -C BAC5 ME34P J15K ACB12 ----— BAC6 ME34S J15M ACB13 -- > -- BAC7 ME34T J15P ACB14 -0 -4> BAC8 ME34V J15S ACB15 -- - 0BAC9 MF34D J15T ACB16 - > -— BAC10 MF34E Jl5V ACB17 - - 0BACll MF34H (In PDP-7A I/O Device) ACCUMULATOR OUTPUTS Corrected page 29. Stephen F. Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967.

-30 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL { INTERFACE CONNECTION I NAME SYMBOL SYMBOL NAME CONNECTION *2 PROGRAM *1 INTERRUPT PF2M INTERRUPT - -<> REQUEST D27E REQUEST *2 * _ *1 D30D I/O SKIP --— > D SKIP PF2K *2 { J08D I/O PI -4 -- IOPl MF34K *2 { JO8E I/O P2 i -— 4 - IOP2 MF34M *2 |:! J08H I/O P4 - -! - IOP4 MF34P (In PDP-7A I/O Device) PROGRAMMED INPUT-OUTPUT SLOW CYCLE CONTROL Corrected page 30. Stephen F. Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967. *Note 1: Collector of Grounded-Emitter Transistor *Note 2: These points not available on normal PDP-7A I/O Interface

-31 - PDP-7A PDP-8 --- -, -,-, INTERFACE SIGNAL I LOGIC LOGIC SIGNAL INTERFACE CONNECTIONi NAME SYMBOL.! SYMBOL NAME I CONNECTION DO6K ADDR-BIT 03 -— c ADDR EXT 3 ME30H D06M ADDR-BIT 04, -—! 0 ADDR EXT 2 ME30E D06P ADDR-BIT 05 -— Q0 ADDR EXT 1 ME30D D06S ADDR-BIT 06 - --- > DATA ADDR 0 PE3D D06T ADDR-BIT 07 -— 0 - DATA ADDR 1 PE3E D06V ADDR-BIT 08 ---- DATA ADDR 2' PE3H D07D ADDR-BIT 09 *| --- DATA ADDR 31 PE3K D07E ADDR-BIT 10 — 0 | DATA ADDR 4 PE3M D07H ADDR-BIT 11 -— <>- DATA ADDR 5j PE3P D07K ADDR-BIT 12 - -— 0 DATA ADDR 6. PE3S D07M ADDR-BIT 13 -— '0 DATA ADDR 7 PE3T D07P ADDR-BIT 14 - -— <> DATA ADDR 8J PE3V D07S ADDR-BIT 15 - -— <> DATA ADDR 9 PF3D D07T ADDR-BIT 16 4 -— <> DATA ADDR10 PF3E D07V ADDR-BIT 17 -4 — C> DATA ADDR11 PF3H -.. (CHO-TYPE 173 MULTIPLEXER) DATA BREAK ADDRESS LINES Corrected page 31. Stephen F. Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967.

-32 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION D04S DATA-BIT 06 — * --- DATA-BIT 0 PE4D D04T DATA-BIT 07 -4 -- DATA-BIT 1 PE4E D04V DATA-BIT 08 - -- DATA-BIT 2 PE4H D05D DATA-BIT 09 < - - DATA-BIT 3 PE4K D05E DATA-BIT 10 -| --- DATA-BIT 4 PE4M D05H DATA-BIT 11 - - - DATA-BIT 5 PE4P D05K DATA-BIT 12 - - -< DATA-BIT 6 PE4S D05M DATA-BIT 13 -— 0 DATA-BIT 7 PE4T D05P DATA-BIT 14 - -$ DATA-BIT 8 PE4V D5OSS DATA-BIT 15 - - -— DATA-BIT 9 PF4D DOST DATA-BIT 16 ---- - DATA-BIT 10 PF4E D05V DATA-BIT 17 - -— DATA-BIT 11 PF4H (CHO-TYPE 173 MULTIPLEXER) DATA BREAK INPUT LINES Corrected page 320 Stephen Fo Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967.

-33 - I PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME j CONNECTION I _E- I H02S H02T H02V H02S J02D H02T J02E H02V J02H J02D J02K J02E J02M J02H J02P J02S J02T J02V i MBB6(1) MBB7 (1) MBB8(1) MBB6(1) or MBB9(1) MBB7 (1) or MBB10(1) MBB8(1) or MBBll (1) MBB9(1) or MBB12(1) MBBlO(1) or MBB13(1) MBB11 (1) or MBB14(1) MB B 15(1) MBB16(1) MBB17 (1) -lw 0.Abmb,"W 19fillb -0 410,,&hit, qqwl 41P -dish.. 'MWI 'W4PP',disks qw, Iddhk.. lqppl 'Ahb. 'Ahlb RW Idghlb "W I j I I i4', I ^1 1-141,,^-.2 A., 4> llo N. lll 10,11 --11, P I /-!;p 1 -14, <>1 I I I I BMBO(1) BMB2(1) BMB2(1) BMB3 (0) BMB3(1) BMB4 (0) BMB4(1) BMB5 (0) BMB5(1) BMB6(0) BMB6(1) BMB7 (0) BMB7(1) BMB8 (0) BMB8 (1) BMB9(1) BMB10(1) BMBll (1) ME35D ME35E ME35F ME35K ME35M ME35P ME35S ME35T ME35V MF35D MF35E MF35H MF35K MF35M MF35P MF35S MF35T MF35V I ] - (In PDP-7A I/O Device) DATA BREAK OUTPUT LINES Corrected page 335 Stephen F. Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967o

-34 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION *3 D08H DATA RQ U -E — T PF3K *3 D08K RQ IN DIRECTON PF3M (IN) (IN) DIRECTION *2 A07P BREAK(B) --- ||- B BREAK PF3P D08M ADDR ACC ACCEPTD PF3S *4 A10D TP6 -- | BT1 MF34S *4 A1OE TP4 - || BT2A MF34T *2 NEG PWR CLR B POWER C13H BEGIN (B) CLEAR MF34V *2 J08M RUN(l) B -.. B RUN PF2S DATA BREAK CONTROL SIGNALS Corrected page 34. Stephen Fo Lundstrom, Engineering Design Report: PDP-7/Modified 338 Display Interface, Concomp Memorandum, The University of Michigan, August 1967. Corrected November 1967o *Note 1: *Note 2: *Note 3: *Note 4: Collector of a Grounded-Emitter Transistor This point not available at normal PDP-7A Interface. Obtained from PDP-7A I/O Device Address given. CHO-Type 173 Multiplexer Addresses. Obtained from I/O Device via Type 173 Multiplexer.

-29 - PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION H15S ACB6 BACO ME34D H15T ACB7 BAC1 ME34E H15V ACB8 BAC2 ME34H J15D ACB9 BAC3 ME34K J15E ACB10 _ - BAC4 ME34M J15H ACB1l _BAC5 ME34P J15K ACB12 | BAC6 ME34S J15M ACB13 -| _ BAC7 ME34T J15P ACB14 _. _ BAC8 ME34V J15S ACB15 l. > BAC9 MF34D J15T ACB16.. __ BAC10 MF34E J15V ACB17 BACll MF34H ii.. l. (In PDP-7A I/O Device) ACCUMULATOR OUTPUTS

-30 - _PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION PROGRAM INTERRUPT 2. ' PF2M INTERRUPT ', r ---- * REQUEST REQUEST *2 *1 *1 D30D I/O SKIP - * SKIP PF2K *2 J08D / P1 I/O P P1 MF34K J08E*2 I/O P2. -- IOP2 MF34M *2 J08H I/O P4 ____ IOP4 MF34P (In PDP-7A I/O Device) PROGRAMMED INPUT-OUTPUT SLOW CYCLE CONTROL *Note 1: Collector of Grounded-Emitter Transistor *Note 2: These points not available on normal PDP-7A I/O Interface

-31 - IPDP- 7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION D06K ADDR-BIT 03 '-1'- ADDR EXT 3 ME30H D06M ADDR-BIT 04 -.~~ ---.- ADDR EXT 2 ME30E D 06 P ADDR-BIT 0 5 ~ -- ADDR EXT 1 ME30D D06S ADDR-BIT 06 DATA ADDR 0 PE3D D06T ADDR-BIT 07 DATA ADDR 1 PE3E D06V ADDR-BIT 0 8 - - ~ - DATA ADDR 2 PE3H D07D ADDR-BIT 09 - -4 DATA ADDR 3 PE3K D07E ADDR-BIT 10 DATA ADDR 4 PE3M D07H ADDR-BIT 11 DATA ADDR 5 PE3P D07K ADDR-BIT 12 ~ ------ DATA ADDR 6 PE3S D07M ADDR-BIT 13_____ DATA ADDR 7 PE3T D07P ADDR-BIT 14 DATA ADDR 8 PE3V D 075S ADDR-BIT 1 5 DATA ADDR 9 P F3 D DO7T ADDR-BIT 16 p-DAT ADDR 10 PF3E DO7V ADDR-BIT 17 so-DATA ADDR 11 PF3H (CHO-TYPE 173 MULTIPLEXER) DATA BREAK ADDRESS LINES

-32 - PDP-7A. PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION D04S DATA-BIT 06 I. H- DATA-BIT 0 PE4D D04T DATA-BIT 07 | r DATA-BIT 1 PE4E D04V DATA-BIT 08 |- DATA-BIT 2 PE4H DO5D DATA-BIT 09 DATA-BIT 3 PE4K DOSE DATA-BIT 10 |,. _ DATA-BIT 4 PE4M D05H DATA-BIT 11 | ___.. DATA-BIT 5 PE4P D05K DATA-BIT 12 | _ DATA-BIT 6 PE4S D05M DATA-BIT 13 |. 1 DATA-BIT 7 PE4T D05P DATA-BIT 14 _ _ | DATA-BIT 8 PE4V DOSS DATA-BIT 15 1 _ _ DATA-BIT 9 PF4D DOST DATA-BIT 16 | _ | DATA-BIT 10 PF4E DOSV DATA-BIT 17 | _ 1 DATA-BIT 11 PF4H ~~~~~~~~~~~~~~~~~~~_.......... ~.............................. i -: - (CHO-TYPE 173 MULTIPLEXER) DATA BREAK INPUT LINES

-33 - i PDP-7A PDP-8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION H02S H02T H02V H02S J02D H02T J02E H02V J02H J02D J02K J02E J02M J02H J02P J02S J02T J02V -— D. MBB6(1) MBB7(1) MBB8(1) MBB6(1) or MBB9 (1) MBB7(1) or MBB10(1) MBB8(1) or MBBll (1) MBB9(1) MBB12(1) MBB10(1) or MBB13(1) MBBll (1) or MBB14(1) MBB15 (1) MBB16(1) MBB17 (1) mwpAlb VBP-.......App---- 10. fthk WPI sh th..-.IIffil.app Calp bo-- chip - Ctot 7*1-, 1_-v 0111' J;Wwpl -fl lav, 101-::A!b rbaw go — Aw K VID 500, I — b Wtob% Looll goAlto 0 - BMBO (1) BMB2(1) BMB2 (1) BMB3 (0) BMB3(1) BMB4 (0) BMB4(1) BMB5 (0) BMB5(1) BMB6 (0) BMB6 (1) BMB7 (0) BMB7(1) BMB8 (0) BMB8 (1) BMB9 (1) BMB10(1) BMBll(1) ME35D ME35E ME35F ME35K ME35M ME35P ME35S ME35T ME35V MF35D MF35E MF35H MF35K MF35M MF35P MF35S MF35T MF35V I II i 4 -4 I (In PDP-7A I/O Device) DATA BREAK OUTPUT LINES

-34 - P D P - 7A PDP- 8 INTERFACE SIGNAL LOGIC LOGIC SIGNAL INTERFACE CONNECTION NAME SYMBOL SYMBOL NAME CONNECTION *3 *1 BREAK D08H DATA RQ -- - REQUEST *3 AO-_ _TRANSFER D08K RQ IN (I ) (IN) DIRECTION P I *2 A07P BREAK(B) ---- -._ B BREAK PF3P D08M ADDR ACC. ACCPTED PF3S ACCEPTED *4 A10D TP6 --- - BT1 MF34S *4 A1OE TP4 B___ BT2A MF34T *2 NEG PWR CLR B POWER C13H BEGIN (B) -"- ^ -- CLEAR MF34V *2 J08M RUN(l) B -- ---— ~* | B RUN PF2S DATA BREAK CONTROL SIGNALS *Note 1: *Note 2: *Note 3: *Note 4: Collector of a Grounded-Emitter Transistor. This point not available at normal PDP-7A Interface. Obtained from PDP-7A I/O Device Address given. CHO-Type 173 Multiplexer Addresses. Obtained from I/O Device via Type 173 Multiplexerc

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