THE UNIVERSITY OF MICHIGAN ANN ARBOR, MICHIGAN THREE-TERMINAL PUNCH-THROUGH DEVICES by H. Yilmaz Technical Report No. 168 Electron Physics Laboratory of Electrical and Computer Engineering Department September 1983

(-~ 1Hamza Yilmaz 9 All Rights Reserved

ABSTRACT The objective of this investigation is to study the gate field controlled barrier injection transit-time (GFC-BARITT) device and static injection transistor (SIT) theoretically and experimentally. The GFC-BARITT device is proposed and its potential is explored. The physics of three-terminal punch-through (TTPT) devices, SIT, metal semiconductor metal (MSM) and n+pn+ GFC-BARITT devices are studied in detail. The particle current injection process for various TTPT devices is examined and identified as diffusion over a gate controlled potential barrier. Dc, small-signal and large-signal ac models for the TTPT devices have been derived by using (1) drift and (2) drift-diffusion approximations. The transit-time effect is included in the small- and large-signal models. Also the small-signal noise properties of the TTPT devices are considered. The potential distribution in the device is calculated by using a two-dimensional Poisson equation solver. The level of carrier injection in GaAs GFC-BARITT devices is lower than that in silicon of InP devices. However, the level of carrier injection in SIT devices is independent of the material. To obtain high current from TTPT devices, high carrier saturation velocity and high carrier injection are required. The forward bias voltage VF and the gate-source distance are the most critical parameters for the operation of these devices. A noniterative large-signal model is proposed. This model was applied to the various FET devices. The results indicate that InP FETs can generate more power than either the GaAs or Si FETs. FETs are treated as a special mode of operation of the SIT device, because either an increase in the channel doping concentration or the channel width of a SIT device results in an FET mode of operation. MSM and n pn GFC-BARITT devices and ring oscillators were fabricated utilizing silicon on sapphire (SOS). The principles of operation of GFC-BARITT devices and their superiority over MOSFETs for digital logic circuits are discussed. -iii

TABLE OF CONTENTS CHAPTER I. CHAPTER II. INTRODUCTION 1.1 Introduction 1.2 Principles of Operation of ThreeTerminal Punch-Through Devices 1.2.1 GFC-BARITT Devices 1.2.la MSM GFC-BARITT Device: Current Transport Mechanism 1.2.2 Static Induction Transistors (SITs) 1.3 Outline of the Present Study DEVICE PHYSICS AND DC CHARACTERISTICS OF GFC-BARITT AND SIT DEVICES 2.1 Device Physics 2.2 The GFC-BARITT Device 2.2.1 Diffusion Effect in the Low Field Region 2.2.2 Dc Current Density of a GFC-BARITT Device 2.2.2a Drift-Diffusion Current Approximation 2.2.2b Drift Current Approximation 2.2.3 Potential Distribution 2.3 Static-Induction Transistor 2.3.1 Physics of the SIT Device 2.3.2 Dc Characteristics of the SIT Device 2.4 Dc Characteristics of a Vertical FieldEffect Transistor 2.5 Thermionic Saturation of the Diffusion Current Page 1 1 2 2 4 11 14 16 16 16 19 28 28 33 36 43 46 47 52 57 -iv

Page CHAPTER III. SMALL- AND LARGE-SIGNAL MODEL 59 3.1 Introduction 59 3.2 Small-Signal Circuit Elements 60 3.2.1 Transconductance 60 3.2.1.1 Silicon Devices 62 3.2.1.1a GFC-BARITT and SIT Devices 62 3.2.1.lb Vertical FETs 62 3.2.1.2 III-V Compound Semiconductor Devices 63 3.2.1.2a GFC-BARITT and SIT Devices 63 3.2.1.2b Vertical FETs 64 3.2.2 Conductance 64 3.2.2.1 Silicon Devices 65 3.2.2.1a GFC-BARITT and SIT Devices 65 3.2.2.1b Vertical FETs 65 3.2.2.2 III-V Compound Semiconductors 65 3.2.2.2a GFC-BARITT Devices and SITs 65 3.2.2.2b Vertical FETs 66 3.2.3 Gate-Source Capacitance 66 3.2.3a GFC-BARITT and SIT Devices 66 3.2.3b Vertical FETs 68 3.2.4 Drain-Gate Feedback Capacitance 68 3.2.4a GFC-BARITT and SIT Devices 68 3.2.4b Vertical FETs 69 3.2.5 Drain-Source Capacitance 69 3.2.5a GFC-BARITT and SIT Devices 69 3.2.5b Vertical FETs 70 -V

Page 3.3 Diffusion Effects on Small-Signal Circuit Parameters 71 3.3.1 The Transconductance 71 3.3.2 The Conductance 72 3.3.3 The Gate-Source Capacitance 72 3.3.4 The Drain-Gate Feedback Capacitance 73 3.3.5 The Drain-Source Capacitance 73 3.4 Carrier Transit Time Effect 74 3.4.1 Silicon Devices 75 3.4.2 III-V Compound Semiconductor Devices 76 3.5 Large-Signal Analysis 77 3.5.1 Introduction 77 3.5.2 Large-Signal Circuit Parameters 78 3.5.2.1 GFC-BARITT and SIT Devices 79 3.5.2.2 Vertical FETs 82 3.5.2.2a Silicon FETs 82 3.5.2.2b III-V Compound Semiconductor FETs 86 3.6 Small-Signal Circuit Properties 88 3.6.1 Admittance Parameters 88 3.6.2 S-Parameters 91 3.6.3 Gain and Gain Bandwidth Product 93 3.6.4 The Stability Analysis 95 3.7 Large-Signal Power and Gain of the TTPT Devices 95 3.8 Noise Analysis 97 3.8.1 Introduction 97 3.8.2 Noise in Punch-Through Diodes 99 3.8.3 Noise Sources of the ThreeTerminal Punch-Through Devices 100 3.8.4 The Noise Figure and the Noise Measure 103 3.8.5 The Noise Temperatures 106 -vi

CHAPTER IV. DEVICE SIMULATION PROGRAM (SIM-GFC) 109 4.1 Introduction 109 4.2 Program Description 110 4.3 Material Parameters 111 4.4 Device Physics 118 4.4.1 The Potential Distribution 118 4.4.2 The Injected Carrier Distribution 127 4.4.3 The Space-Charge Effect 133 4.5 Dc Characteristics 135 4.5.1 The Impurity Concentration Effect 135 4.5.2 Temperature Effect 139 4.5.3 The Geometry Effect 144 4.5.4 Dc and Small-Signal Device Parameters 151 4.6 Small-Signal Performance 166 4.6.1 GFC-BARITT Devices 167 4.6.2 SIT Devices 177 4.7 Large-Signal Performance 197 4.7.1 Results and Discussions of the Large-Signal Operation 204 4.8 Comparison of the Different Devices 218 CHAPTER V. DEVICE FABRICATION AND MEASUREMENTS 221 5.1 Introduction 221 5.2 Material Selection 222 5.2.1 SOS Samples 225 5.3 Device Fabrication 228 5.4 Dc Characteristics 233 5.5 Introduction to Digital Circuit Applications 240 5.5.1 Basic Structure and Principles of Operation 242 5.5.2 Ring Oscillator Fabrication 245 5.5.3 Results and Discussion 246 5.5.4 Delay Time 256 5.5.4.1 A GFC-BARITT Device Inverter 256 5.5.4.2 Injection Control Logic 259 -vii

Page 5.5.5 Conclusion 260 5.6 Comparison of the Theoretical and Experimental Results 265 CHAPTER VI. CONCLUSIONS AND SUGGESTIONS FOR FURTHER STUDY 268 APPENDIX A. FACR METHOD 271 APPENDIX B. SIM-GFC PROGRAM 277 LIST OF REFERENCES 279 -viii

LIST OF FIGURES Figure Page 1.1 Structure of an Ideal GFC-BARITT Device. 3 1.2 MSM GFC-BARITT Device. 5 1.3 MSM GFC-BARITT Device Energy Bands. 7 1.4 Energy Band Diagram at |VDSI > IVFB. 9 2.1 GFC-BARITT Device. 18 2.2 Field, Velocity and Carrier Distributions of a TTPT Device. 27 2.3 A TTPT Device. 29 2.4 SIT Device. (G = Gate, D = Drain and S = Source). 47 2.5 A SIT Device. 50 2.6 Vertical FET Structure. 53 3.1 Small-Signal Equivalent Circuit of a SIT or a GFC-BARITT Device. 61 3.2 Equivalent Circuit Used in Noise Analysis. 104 4.1 Flow Chart. 112 4.2 The Potential Distribution. 121 4.3 A Multi-Channel Surface Gate (Insulator or Schottky) TTPT Device. 126 4.4 Carrier Distribution as a Function of Distance at the Different Points Across the Channel, y and Distance Along the Conduction Path, x. 129 4.5 VF Vrriation as a Function of VDS at Different Gate Voltages (Device S2). 134 4.6 Dc Current of a SIT as a Function of the Channel Doping Concentration (Device S2). 136 -ix

Figure Page 4.7 Dc Current of a GFC-BARITT Device as a Function of the Channel Doping Concentration (Device B1). 137 4.8 The Current Voltage Characteristics of a SIT Operating in FET and Injection (SIT) Modes (Device S1). 141 4.9 A GFC-BARITT Device Current as a Function of the Channel Doping at T = 400~K (Device B1, Compared to Fig. 4.7 at T = 300~K). 143 4.10a The Gate-Source Spacing, WGS, Effect on the I-V Characteristics of a GFC-BARITT Device. 146 4.10b The Gate-Source Spacing, WGS, Effect on the I-V Characteristics of a GFC-BARITT Device. 147 4.11a The I-V Characteristics of the Vertical FETs. 148 4.11b The I-V Characteristics of the Vertical FETs. 149 4.11c The I-V Characteristics of the Vertical FETs. 150 4.12a Small-Signal Parameters of a GFC-BARITT Device as a Function of VDS for Different Values of VGS (Device B2). 153 4.12b Small-Signal Parameters of a GFC-BARITT Device as a Function of the VDS with Different VGS Voltages (Device B2). 154 4.12c The Small-Signal Parameters of a GFC-BARITT Device as a Function of the VDS with Different VGS Voltages (Device B2). 155 4.12d Small-Signal Parameters of a GFC-BARITT Device as a Function of the VDS with Different VGS Voltages (Device B2). 156 4.13a The Small-Signal Equivalent Circuit Parameters of a Silicon FET, S3. 158 4.13b The Small-Signal Equivalent Circuit Parameters of a Silicon FET, S3. 159

Figure 4.13c The Small-Signal Equivalent C of a Silicon FET, S3. 4.13d The Small-Signal Equivalent C of a Silicon FET, S3. 4.14a The Small-Signal Equivalent C a GaAs FET, S4. 4.14b The Small-Signal Equivalent C a GaAs FET, S4. 4.14c The Small-Signal Equivalent C a GaAs FET, S4. 4.14d Tht Small-Signal Equivalent C A GaAs FET, S4. 4.15a The Small-Signal Performance Device, B4, as a Function of Frequencies 0.1 to 0.6 GHz. (V = 0 V) 4.15b The Small-Signal Performance Device, B4, as a Function of Frequencies 0.1 to 0.6 GHz. (VGS = 0 V) 4.15c The Small-Signal Performance.Device, B4, as a Function of Frequencies 0.1 to 0.6 GHz. (VG = 0 V) 4.15d The Small-Signal Performance Device, B4, as a Function of Frequencies 0.1 to 0.6 GHz. (VG = 0 V) 4.15e The Small-Signal Performance Device, B4, as a Function of Frequencies 0.1 to 0.6 GHz. (VGS 0 V).ircuit:ircuit i rcuit;ircuit;ircuit i rcuit of a Si the VDS of a Si the VDS of a Si the VDS of a Si the VD of a Si the VD Parameters Parameters Parameters of Parameters of Parameters of Parameters of GFC-BARITT at Different iGFC-BARITT at Different i GFC-BARITT at Different iGFC-BARITT at Different i GFC-BARITT at Different Page 160 161 162 163 164 165 168 169 170 171 172 -xi -

Figure Page 4.15f The Small-Signal Performance of a Si GFC-BARITT Device, B4, as a Function of the VDS at Different Frequencies 0.1 to 0.6 GHz. (VGs = 0 V) 173 4.16a The Transit-Time Effect on the Small-Signal Device Performance of Device B4. 175 4.16b The Transit-Time Effect on the Small-Signal Device Performance of Device B4. 176 4.17a The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel Doping. 178 4.17b The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel 179 4.17c The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel 180 4.17d The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of 181 4.17e The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of the Channel Doping. 182 4.17f The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of the Channel Doping. 183 4.18a The Small-Signal Performance of a GaAs SIT, S6 as a Function of the VD. (VGs = 0 V) 184 4.18b The Small-Signal Performance of a GaAs SIT, S6. (VGs = 0 V) 185 4.18c The Small-Signal Performance of a GaAs SIT, S6. (VGs = 0 V). 186 4.18d The Small-Signal Performance of a GaAs SIT, S6. (V = 0 V) 187 4.18e The Small-Siqnal Performance of a GaAs SIT, S6. (VGs =0 V) 188 -xii

Figure 4.18f Page 189 The Small-Signal Performance of a GaAs SIT, S6. (VGS = 0 V) 4.19a 4.19b 4.19c 4.19d 4.19e 4.19f 4.20 4.21 The Small-Signal Performance of Function of the Channel Doping, 8 V and VG =-3 V) GS The Small-Signal Performance of Function of the Channel Doping, Frequencies. a SI SIT, S2 as a ND. (VDS= pt+ a Si SIT, S2 as a ND at Different The Small-Signal Performance of a Si SIT, S2 as a Function of the Channel Doping, ND at Different Frequencies. (VDS = VpT + 8 V and VGS = -3 V) The Small-Signal Performance of a Si SIT, S2 as a Function of the Channel Doping, N at Different Frequencies. (VDs = VpT + 8 V and 9GS = -3 V) The Small-Signal Performance of a Si SIT, S2 as a Function of the Channel Doping ND at Different Frequencies. (VDS = VpT + 8 V and VGS = -3V) The Small-Signal Performance of a Si SIT, S2 as a Function of the Channel Doping at Different Frequencies. (VDS = VpT + 8 V and VGS = -3 V) A Large-Signal Amplifier Circuit. The Current and Voltage Waveforms under LargeSignal Conditions. 191 192 193 194 195 196 198 202 4.22a 4.22b The Large-Signal Performance (Device S7) at 5.0 GHz. The Large-Signal Performance (Device S7) at 5.0 GHz. of a GaAs FET of a GaAs FET 206 207 4.22c The Large-Signa (Device S7) at 1 Performance 5.0 GHz. of a GaAs FET 208 4.23a 4.23b 4.23c The Large-Signal Performance (Device S8) at 5.0 GHz. The Large-Signal Performance (Device S8) at 5.0 GHz. The Large-Signal Performance (Device S8) at 5.0 GHz. of an InP FET of an InP FET of an InP FET 209 210 2.11 -xiii

Figure Page 4.24 The Output Power of a Si FET (Device S9) at 5.0 GHz as a Function of the Input Powers. 212 4.25a The Large-Signal Performance of an InP FET (Device S8) as a Function of Frequency. 213 4.25b The Large-Signal Performance of an InP FET (Device S8) as a Function of Frequency. 214 4.25c The Large-Signal Performance of an InP FET (Device S8) as a Function of Frequency. 215 5.1 Profile of the Ion Implanted Impurities. 227 5.2 Fabrication Processes of the MSM and Junction (J) GFC-BARITT Devices. 229 5.3 Ideal Schottky Barrier GFC-BARITT Device. 234 5.4 Fabricated GFC-BARITT Device. 235 + -+ 5.5 n p n Device (Z = 0.2025 cm, LG = 5 pm and LDS = 20 pm). 236 5.6 MSM GFC-BARITT Device. (Z = 500 pm, LSG = 2.5 vm, LGD = 12.5 pm, and 0.5 pm thick). 237 5.7 Insulated Gate n n n SIT Device. (Z = 125 vm, LSG = 3.5 vm, LGS =10 pm, LDS = 30 vim, and 0.5 pm thick). 238 + + 5.8 n p n GFC-BARITT Device. (Z = 125 pm, L = 5 m, LGS = 10 pm, LDS = 30 pm, and 0.5 iG thick). 241 5.9 Inverter Structures. 243 5.10 Fabrication Steps. 247 5.11 Photomicrograph of the Five-Stage Ring Oscillators. 248 5.12 Output Waveforms of the Complementary ICL Ring Oscillator. 249 5.13 Output Waveforms of the CMOS/SOS Ring Oscillator. 250 5.14 Switching Speed of the Injection Controlled Logic Gate as a Function of the Power Dissipation. 251 -xiv

Figure Page 5.15 Switching Speed of the Punch-Through Logic Gate as a Function of Power Dissipation 252 5.16 GFC-BARITT Device Inverter Circuit with a Capacitive Load. 257 5.17 ICL inverter Circuit with a Capacitive Load. 261 5.18 Inverter Structure for Semiconductors with High Electron Mobilities. 263 -XV

LIST OF TABLES Table Page 1.1 Potential Power Devices 14 2.1 Power Performance of SITs 45 4.1 List of the Devices 119 5.1 Energy Bandgap for Various Semiconductor Materials. 224 5.2 Ion-Implantation Data 226 -xvi

LIST OF SYMBOLS A** D Dn Dp,Dn pn E EC EFB ERB E Esat f fT f27 F G Jo=qvsatnp Jp Jn Jso k 1 k 2 LDS LF The effective Richardson's constant. One half of the device thickness. Diffusion coefficient. The hole and electron diffusion coefficients. Electric field. The field at the peak velocity. The field at the forward-biased junction side. The maximum field at the reverse-biased junction side. The field where velocity reaches half of the saturated velocity. Frequency. Cut-off frequency. Frequency where the phase delay becomes 2X. The noise figure. The carrier generation rate. Current density. Hole and electron current densities, respectively. Maximum current density of a BARITT diode. A constant. A constant. Channel length. Length of the depletion layer from the forwardbiased junction side. -xvii

Ln LR LS * m M n n. 1 ninj(I) npo ns nth = ND N N NA ND P PDC P. Pin Po p0 Pt nt ro rs Re Rf Diffusion length for electrons. Length of the depletion layer from the reverse-biased junction side of the n+pn+ diode. Distance between the source and the point where the velocity of carrier saturates. Effective mass of electrons. Noise measure. Electron density. Intrinsic carrier density. Density of the injected carriers at the Ith segment. Minority carrier density at thermal equilibrium. Source doping concentration. SIT. Number of segments or BARITT diodes of a GFC-BARITT device. Number of channels. Impurity concentration of the p-type semiconductor. Impurity concentration of the n-type semiconductor. Hole density. Dissipated power. RF input power. Output power. Hole and electron densities which would exist if the Fermi level coincided with the trap level. A constant which is less than unity. Source resistance. The "real part". Thermal noise of the source parasitic resistance. -xviii

R m t T TOFF TON V v(x) vpVn Vsat Voi Vo2 VTE VB VB1 VB2 VF VFB VF(I) VPTG VGS VT= kT/q WGS Ws x X Yin Thermal noise of the gate parasitic resistance. Time. Temperature in ~K. Turn-off time of an inverter. Turn-on time of an inverter. Voltage. Carrier velocity as a function of the local electric field along the conduction path. Hole and electron drift velocities (dependent upon E). Saturated velocity. Initial output voltage. Final output voltage. Velocity of the thermionic emission over a potential barrier of zero height. Built-in potential of a p-n junction of an MSM BARITT diode. Total barrier height. Built-in potential between the gate and channel. Forward biasing voltage across the source-channel junction. Flat band voltage. Forward bias voltage at the Ith segment. Punch-through voltage for the distance of LDS-LG. Source gate voltage. k is the Boltzmann constant and q is the electronic charge. Distance between the source and the gate. Channel width. Distance that carriers travel in the conduction path. Input admittance. -xix

YL Load admittance. Z Gate width. Zs Impedance of the noise source. a(I) Barrier modulation parameter. ap'an Hole and electron ionization coefficients. Af Frequency bandwidth. ma Power efficiency. nc Collector efficiency. Forward bias due to VDS. <fG Barrier height inducted by the gate-source voltage. fG(I) Potential of the Ith segment along the y-direction due to applied gate-source voltage. +^nl ~ Minimum barrier height of a metal-semiconductor ~nl ~ junction (Schottky barrier). (so Junction potential barrier. 0 Delay angle due to transit time. T PTn Hole and electron lifetimes. p n w Angular frequency. -XX

CHAPTER I. INTRODUCTION 1.1 Introduction This study is concerned with basic device theory and modelling of Three-Terminal Punch-Through (TTPT) devices, such as Gate-FieldControlled Barrier Injection Transit Time (GFC BARITT) and Static Induction Transistor [1] (SIT)devices. Even though the operating principles of these two devices are different, both can be characterized by the same type of mathematical expressions. The theory developed in this study directly pertains to n+pn and Metal Semiconductor-Metal (MSM) GFC-BARITT devices, and n n n SITs. The results can be easily adapted to the analysis of the other device structures, such as p np GFC-BARITT and p p p SIT devices. As a result of the low gate-source capacitance and the parasitic capacitance, and the high transconductance of TTPT devices in general,' they are capable of operation at high frequencies. The experimental studies of SIT devices indicate that they are promising in the areas of high frequency and high power analog circuit applications [2]. Although there has been some experimental work on SIT devices [1] and [3], there have been no published studies on the theoretical capabilities and limitations of TTPT devices. For these reasons, this present study will focus on the theoretical constraints of the maximum frequency of operation of TTPT devices. An experimental study of the switching speed of SOS GFC-BARITT -1

-2 devices to show their feasibility for digital circuit applications and the fabrication of a new MSM GFC-BARITT device are also included. 1.2 Principles of Operation of Three-Terminal Punch-Through Devices There are two types of TTPT devices. These are (a) the minority carrier devices such as the GFC-BARITT and Lateral Punch Through Transistor [4], and (b) the majority carrier devices such as the junction gate SIT and the insulated gate SIT devices. In all these devices, the carrier injection, either majority or minority, is controlled by a third electrode. This electrode can be an insulated gate as in the GFC-BARITT devices, a junction gate as i, SIT devices or an ohmic-contact gate as in Lateral Punch-Through Transistors. In the following sections, the GFC-BARITT and SIT devices will be considered. 1.2.1 GFC-BARITT Devices. The principles of operation of a MSM GFC-BARITT device are presented here for the first time and a procedure for fabrication in silicon on sapphire (SOS). The GFCBARITT device is characterized by a narrow insulated gate close to the forward-biased junction of a two-junction device as shown + -+ + -+ +- + in Fig. 1.1. This structure includes n n n, n p n, p p p, +- + p n p, MSM-type structures, and also some of the space-charge limited triodes [5] and [6]. Depending on the type of structure used, a GFC-BARITT device can be (i) a minority-carrier type (n pn, p n p and MSM structures) or (ii) a majority-carrier type (n n"n+ and p p p structures). A SIT device is a special type of majority

-3 Gate Source Drain Reverse-biased junction Fig. 1.1 Structure of an Ideal GFC-BARITT Device.

-4 carrier device which uses a junction gate instead of an insulated gate. In a minority-carrier type of structure, the carrier injection is controlled by a reverse-biased junction in a punchthrough diode such as that found in MSM, p np or n pn type of BARITT diodes. An insulated gate electrode has been added to a BARITT diode to control the injection through the gate. A twoterminal diode then becomes a three-terminal device with all the features of a transit-time device. The advantages of a threeterminal device over a two-terminal device are: (i) a threeterminal device requires simple circuitry, and (ii) its efficiency is also much higher than that of a two-terminal device. The operation of a pn junction-type GFC-BARITT device can be summarized as the control of the injection of the minority carriers from the source to the channel through an insulated gate. Even though the same principle holds true for the injection of the minority carriers in a MSM GFC-BARITT device, the details of the current transport of a MSM device are different from that of a p-n junction type device. Because of this difference the following section elaborates on the current transport mechanism of a MSM GFCBARITT device. 1.2.la MSM GFC-BARITT Device: Current Transport Mechanism. A MSM BARITT device with an insulated gate in the close vicinity of the forward-biased junction is shown in Fig. 1.2. A MSM BARITT diode allows current to flow when the applied bias voltage exceeds a critical voltage across the drain-source terminals. The critical

-5 G Metal Contact 1 Contact 2 S I Forward biased junction Forward biased junction _L1VD Reverse biased junction Reverse biased junction Fig. 1.2 MSM GFC-BARITT Device.

-6 voltage is referred to as the punch-through (VpT) or the reach through (VRT) voltage at which the depletion regions of the forward and reverse biased junctions are joined together. For voltages in excess of VpT, the barrier height between contact 1 metal (the source) and the semiconductor will be lowered. This is illustrated in Figs. 1.3(a) and 1.3(b). As a result of this lowering of the barrier, electrons from the metal will be injected into the semiconductor by way of thermionic emission. The current transport mechanism of an MSM BARITT diode prior to punch-through has been analyzed in [7] and is outside the scope of this present study. In Fig. 1.3(a), the initial energy band diagram and the barrier heights are indicated. In that figure, pl-IFP is the Schottky barrier height against the holes in the p-type semiconductor. 6nl is the minimum barrier height against the electron injection from metal to semiconductor. )so is the junction potential barrier also against the electron injection. VB1 is the final barrier height for the electron injection at contact 1. At contact 2, the same symbols with index number 2 have the same meaning as those in contact 1. However, in Fig. 1.3(b), the total barrier height against the electrons is reduced. The electron current can be approximated as in Eq. 1.1, by following Sze's treatment [7]: DS = A**T2 DEXP(-V /VT), (1.1) where A** is the effective Richardson's constant, T is the temperature in degrees Kelvin, and VB1 is the total barrier height against

-7 Gate, G Source, S F F VB1 | Drain, D (a) At thermal p1- FP 1 equilibrium. G I I 9s S EFm ~nl EFm EFm D (b) At VDS > VpT (beyond punch-through). Fig. 1.3 MSM GFC-BARITT Device Energy Bands.

-8 electron injection and VT = kT/q where k is the Boltzmann constant and q is the electronic charge. As the voltage is increased further, a point is reached at which the energy band at contact 1 become flat. This is the flat band condition with the corresponding flat band voltage, VFB. For voltages in excess of VFB, the energy band is bent further down. If the length of the p-semiconductor is LDS, the corresponding flat band voltage expression is given by qNA V 2 -(1 2) FB 2c% DS' where NA is the impurity concentration of the p-semiconductor and Es is the semiconductor permittivity. The increase in the applied voltage VDS between the VpT and VFB voltages results in an exponential increase of the electron current. The electron current, however, increases slowly with VDS in excess of VFB. This current increase is due to the barrier lowering effect of the electric field shown in Fig. 1.4. The reduction in barrier height is given by Eq. (1.3): DS ~FB (1.3) 4s DS The minimum barrier height, nl is one of the main differences between a pn junction (n pn or p np ) and a MSM BARITT diode.

-9 Source 1 Contact 1 Drain EFm Contact 2 Fig. 1.4 Energy Band Diagram at IVDS, IVFBI.

-10 Unlike a MSM BARITT diode in which the metallurgy determines the minimum barrier height, the pn junction type BARITT diode has no such characteristic. There is, however, a space-charge limitation to the injection of the minority carriers in the case of a pn junction type BARITT diode. If n1 (Wln = n - A n ) is high, ni ni ni n a MSM BARITT diode biased even at voltages in excess of VpT, does not show its usual exponential current voltage (I-V) characteristic until the avalanche breakdown occurs. This unique characteristic of a MSM diode distinguishes it from other pn junction type diodes. In the discussion given above, the assumption was made that the doping concentration was light enough and the length of the semiconductor was long enough so that the flat band condition occurs before avalanche breakdown occurs at the reverse-biased junction. In this analysis, neither the role of an insulated gate close to the forward biased junction (contact 1), nor the effect of the diffusion of the injected carriers at the low field region on the I-V characteristics have been considered. The following discussion considers the effect of the insulated gate on the I-V characteristics of an M-pS-M BARITT diode. The applied gate voltage will modify the minimum barrier height'i of the forward biased junction of a MSM BARITT device. For a positive gate voltage, the barrier height VB1 and the minimum barrier height of an MSM BARITT diode are lowered. This is why a M-p.S-M GFC-BARITT device is able to conduct higher currents than a conventional M-pS-M BARITT diode of the same size. However, if the gate voltage is negative, the current flow will be reduced.

-11 1.2.2 Static Induction Transistors (SITs). One can characterize a SIT as a three-terminal punch-through device, even though the punch-through occurs between the gate and the drain rather than between the source and the drain. If the channel of a vertical FET is lightly doped, then the whole channel will be depleted at the pinch-off condition. If the drain-source voltage is further increased beyond the pinch-off condition, the FET operates as a SIT, assuming that the drain-gate breakdown does not occur. The SIT is a majority carrier injection-type device. Only the Dc analysis of this device has been undertaken [1]. The Dc current expressions for different approximations are given by 1/2 ~ +r V IDS = Tq L2* An exp [ (1.4) for the thermionic emission approximation and D ___+r_ V_.\ IDS =qA nn exp - V G (1.5) for the diffusion approximation. The following expressions are given for the multi-channel SIT device in [3]: IDS A exp - dy +~~~~-D ~(1.6) (1.6) and

-12 1 =I I DS DS1 DSD for the thermionic approximation and DS = IDS2DS for the diffusion approximation. Where 1/2 DS1 = qns 2kT N D = n IDS2 = q -n D = diffusion coefficient, n Ln = diffusion length N = number of channels, r = a constant which is less than unity, r = source resistance s k = Boltzmann constant, m* = effective mass of electrons, WGS = the distance between the source and the gate A = ZW Z = gate width Ws = channel width n = the source doping concentration = forward bias due to VDS and VG = the source gate voltage. ho

-13 As the published reports indicate, the SIT is a high power device [2], [8]. The major limitation of a SIT device is that its performance is too process-sensitive as reported in [9] and [10]. This makes it difficult to fabricate reproducible SIT devices. The process sensitivity of the SIT as a power device is not as critical as in the case of digital circuit applications. A summary of the principles of operation and limitations of various TTPT devices including SIT devices are listed in Table 1.1. 1.3 Outline of the Present Study The objective of this study is to carry out a theoretical and experimental investigation of the capabilities and limitations of TTPT GFC-BARITT and SIT devices. Analytical equations, mainly circuit models and computer solutions of the analytical device expressions are utilized to determine dc small-signal, noise, and large signal behavior of these devices. In Chapter II, dc expressions for the GFC-BARITT and SIT devices are derived for different semiconductors, dc expressions are given for three different simplified cases: (i) a drift-diffusion approximation, (ii) a drift approximation, and (iii) a thermionic diffusion approximation. In Chapter III, small-signal, noise, and large-signal models for GFC-BARITT and SIT devices are discussed. Also, the effect of the transit time on the performance of these devices are considered. The carrier temperature variation as a function of the electric field, and its effect on the device noise is also accounted for.

Table 1.1 Potential Power Devices Device GFC-BARITT n pn/p np + -+ nn nn / + -+ P P P Type Conduction Modulation Maior Limitation minority carrier injection of minority carriers injection of majority carriers through an insu- insulated gate technology lated gate through an insu- insulated gate technology lated gate — A! majority carrier MSM minority carrier thermionic emission or injection of minority carriers injection of majority carriers through an insulated gate reverse bias pn junction insulated gate technology limited voltage swing SIT + -+ n n n majority carrier Lateral punchthrough transistor minority carrier injection of minority carriers ohmic gate limited voltage swing due to ohmic gate (high gate current)

-15 In Chapter IV, the outline of a computer program is developed which calculates the Dc current voltage characteristics, the small signal circuit gain, and noise, and large-signal circuit gain and efficiency of TTPT devices. In addition, a simple model for the vertical field effect transistors is included in the simulation program (SIM-GFC). All of the calculations can be extended to silicon and/or III-V compound semiconductors, such as GaAs and InP. In Chapter V, the fabrication, design, and testing of a GFC-BARITT device are given. The resulting experimental and theoretical data are then compared. Finally, in Chapter VI, a summary of the results of this work, and some suggestions are given for the further study of the TTPT devices.

CHAPTER II. DEVICE PHYSICS AND DC CHARACTERISTICS OF GFC-BARITT AND SIT DEVICES 2.1 Device Physics This chapter presents a discussion of the physics of two types of punch-through semiconductor devices. These are: (a) A majority carrier device which is called a static induction transistor [1] and (b) A minority carrier device which is proposed and studied for the first time here, the GFC-BARITT device. This is basically a barrier injection transit-time device with a third terminal which controls the injection of the carriers from the source to the channel. Both of these devices are two-dimensional and it is difficult to derive analytical expressions for the device parameters. Therefore, where possible, analytical expressions have been used along with some numerical approximations. Expressions for the dc current and voltage characteristics include a field-dependent velocity expression to account for the effect of the velocity saturation in the drift region and the effect of the carrier diffusion at the low-field region. A simplified solution of the carrier distribution is also given. 2.2 The GFC-BARITT Device Although the device theory that is developed throughout this chapter is general in nature, only the n pn abrupt-junction -16

-17 uniformly doped silicon and GaAs or InP structures will be dealt with in detail. A Gate Field Controlled BARITT device (GFC-BARITT) is a BARITT with an insulated gate. Adding an insulated gate to the source side of the BARITT structure results in a GFC-BARITT device. A typical device structure which is considered in this study is shown in Fig. 2.1(a). A two-dimensional band structure of a GFC-BARITT device is shown in Fig. 2.1(b). The principle of operation of this device is based on the control of the injection of carriers from the source electrode into the fully depleted channel through an insulated gate. This device looks and acts like a BARITT diode from the drain side and responds like a MOSFET from the gate side. Although the operating principle is simple, the description of the characteristics of the device is complicated. In general, this device exhibits the disadvantages of a BARITT diode such as (i) space charge limitation of the injection of the minority carriers (self limitation) and (ii) diffusion effects at the low field region. It also has some advantages over BARITT diodes such as (i) a three-terminal device can be used in microwave and high-speed circuits, (ii) since the gate is insulated, the only limitation on RF input voltage is the gate breakdown voltage and (iii) Class Band C amplifiers can be realized with this device. Changing the polarity of the gate voltage either enhances or suppresses the injection of the minority carriers. As a result the drain-source current can be modulated. The structure shown in Fig. 2.1(a) is an n pn abrupt-junction GFC-BARITT device. One can describe the device operation physically

-18 G S + D (a) Ideal device structure. n n- n D g+ a Insulated gate (b) Two-dimensional energy band diagram. Fig. 2.1 GFC-BARITT Device.

-19 as the injection of carriers from one terminal, modulation of these injected carriers through a second terminal (gate), their drift in a high-field region, and the collection of the carriers at the third terminal. Physically abrupt-junctions are not necessary. They can be either a graded junction or a Schottky barrier but the gate has to be insulated. Throughout this study uniformly doped n pn structures are considered for simplicity. 2.2.1 Diffusion Effect in the Low Field Region. The exact distribution of the injected carriers requires the simultaneous solution of the basic semiconductor device equations. These are Poisson's equation and the hole and electron continuity equations together with several auxiliary equations which relate the basic solution variables (hole density, electron density and voltage) to the electric field, current density and charge generation. The equations are: Principal Equations: v2V = q (n - p - N), (2.1) es^ ~D t:= -div(J /q) + G (2.2) and a= div(Jn/q) + G. (2.3) t n

-20 Auxiliary Equations: E = -grad V, (2.4) Jp/q = PVp - Dp grad p, (2.5) J/q = -n + Dn grad n (2.6) n v n and pn - n2 G pl/ql + anIJn/ql + ( n+ n( ) 2+ t(p (2 7) p nt) n(P +Pt) The variables in Eqs. 2.1 through 2.7 are defined as follows: V = the voltage, p = the hole density, n = the electron density, N = the doping density (positive for donors, negative for acceptors), t = time, J,J = the hole and electron current densities, respectively, p n G = the carrier generation rate, E = the electric field, O D,D the hole and electron diffusion coefficients, p n v,v = the hole and electron drift velocities (dependent upon E),

-21 ap4'n = the hole and electron ionization coefficients, T,T the hole and electron lifetimes, pn n, = the intrinsic carrier density and pt,nt F the hole and electron densities which would exist if the Fermi level coincided with the trap level. The generation recombination term, Eq. (2.7) contains the effects of impact ionization and trapping. Both of the terms will be neglected under the low-field punch-through operating conditions. In this analysis, however, the exact solutions of the basic device equations (Eq. 2.1 through Eq. 2.3) will not be attempted. Instead, Poisson's equation is solved for low injections to determine the potential distribution. Then the barrier height and the location of the point of the carrier injection are determined. From the known potential distribution, the distribution of the injected carriers can be determined by solving only one continuity equation.'Since TTPT devices are monopolar devices, the effects of only the injected carriers are important. Since for an n p n and M-pS-M GFC-BARITT and n n n SIT devices, the electrons are injected carriers, the problem to be solved is n (x,t) 1 pn(xt = _ - div(J), (2.8) where n is the density of the injected carriers.

In the steady state, Eq. (2.8) reduces simply to I div(J ) = 0. (2.9) q n At the low field region, the current density is given by an Jn = qnp(x)nE(x) + qDn (2.10) Assuming that the electric field is a linear function of the distance along the conduction path, x, the electric field can be expressed as 2(V DS+ VB) E(x) = 2D V x,(2.11) L2 DS where VDS is the applied voltage between the drain and the source, VB is the built-in potential of the n p junction between the drain or source and the channel, and LDS is the length of the channel or distance between the drain and the source electrodes. By defining 2(VDS + VB) Eq.~ 2: DS Eq. (2.11) becomes E(x) = yX. (2.12)

-23 Using Eq. (2.12) in the expression of the current density yields J(x) - qnp(x)no E(x) + qDn, (2.13) where uno is the low-field mobility and n' is the first derivative of np(x) with respect to x. In Eq. (2.13), mobility variation along the path of conduction x is omitted for simplicity. This is a valid assumption for the first-order approximation, since Eq. (2.13) is only valid at the low field region. Finally, the continuity equation (Eq. 2.9) results in qDnnpx + qnp(x) oy x + qp np(s) = 0 (2.14) where n"(x) is the second derivative of np(x) with respect to x. After further simplification Eq. (2.14) becomes n"(x) + axn'(x) + anp(x) = 0,(2.15) P P p where 2VDS DSVT VT = kT/q and k is the Boltzmann constant, and T is the temperature in degrees Kelvin. After rearranging and integration Eq. (2.15) over x, the

-24 second-order nonlinear differential equation reduces to a first-order differential equation: d [np(x) + axnp(x)] = 0 dx p p (2.16) Therefore np(x) + oxnp(x) = k P P i~~~~~ (2.17) where k is a constant. Rewriting Eq. (2.17) as in Eq. (2.18): 1 dn (x) dx- + axnp(x) = k dx 1 (2.18) and then rearringing Eq. (2.18) results in dn (x) -nipx + ax dx dx = k dx 1 np(X) 1 (2.19) Now Eq. (2.19) can be integrated over x which yields ln(np(x)) + 1 ax2 - In k p 2( 2 1k I ndx 1 np x (2.20) The right-hand side of Eq. (2.20) can be approximated as k (x/nsat) to obtain an analytical solution where nSat is the carrier density at a point, LS; where the velocity of the carriers saturate. Equation (2.20) then becomes

-25 ln(n (x)/k ) + 0.5 ax2 = k P 2 1 nsat Finally, n (x) can be obtained from Eq. (2.21) and expressed as n (x) = k exp[-0.5 ax2 + k (x/n )] p ^2 1 sat (2.21) (2.22) Applying the boundary conditions to found: Eq. (2.22), k and k can be 1 2 (i) the first boundary is the injection point at x = 0 n(x)x=o = "inj this gives k = ni, (2.23) p 0jl2 inj where ninj is the density of the injected carriers into the channel and (ii) the second boundary is a virtual point where the carrier velocity saturates. This boundary was introduced by McCleer [11] and gives the following: np(X)Ix.L S = nsat sat' nsat ninj exp(-0.5 aL2 + k L/nsat S 1 S sat and k = nsat 0.5 aL. - 1 sat In(ninj/ sat L (2.24)

-26 To clarify the boundary conditions, the electric field [Fig. 2.2(a)] the velocity [Fig. 2:.2(b)] and the density of minority carriers [Fig. 2.2(c)] are shown as a function of distance x in Fig. 2.2. The current density must be the same along the path of conduction, x. Therefore, nsat can be obtained by equating the pure diffusion current at x = 0 to the drift current at x = LS. This gives an ] qDn p = qvsatnsat' (2.25) where vsat is the carrier saturation velocity. Finally, by combining Eqs. (2.22 through 2.24) with Eq. (2.25), a nonlinear expression for nsat can be found as follows: 0.5 aL D D ns S -S n nnj ln(n /n )n (2.26) sat n vsat sat j inj sat inj'(2 where ninj = npo exp[(VF - /G/VT], L = ETH'S 2VD/LSs ETH = sat/1no' VF = the forward biasing voltage across the source-channel junction and G.= the barrier height induced by the gate-source voltage. ~G

-27 E(x) E S x n -LF (a) Electric field. v(x) sat LF 0 (b) Carrier velocity. Ls LDS x LDS LS n s ninj nsat LF L LDS LS (c) Injected carrier. Fig. 2.2 Field, velocity and carrier distributions of a TTPT Device.

-28 2.2.2 Dc Current Density of a GFC-BARITT Device. The expression for the current density DS requires knowledge of the distribution of the carriers and the field along the path of conduction. For an exact solution of the current density, Poisson's equation and the continuity equation must be solved simultaneously with the appropriate boundary conditions. This is true for any semiconductor device. It is, however, extremely difficult to obtain analytical solutions for the current density, potential and carrier distributions. By considering the principle of the device operation, one may obtain quasi-numerical expressions for the current density and electric field. This approach is satisfactory as far as the understanding of a certain device and simplifies the equations considerably. In the course of this study, analytical solutions of the characteristic equations of a device are obtained by making certain simplifications. From Section 2.2.1 the carrier distribution in the device can be used to obtain the current density. In another approach, the diffusion effect is neglected by assuming that all the injected carriers drift along the channel and contribute to the current. In the following sections, two approximations for the current density expression will be given. 2.2.2a Drift-Diffusion Current Approximation. The GFCBARITT device operation is governed by the two-dimensional potential distribution. A device is divided into a number of thin devices as shown in Fig. 2.3(a) where each of them has different injection levels as in Fig. 2.3(b). The next important problem is to find the level

-29 G. n+...... n+ -...n.. -._ _ - D.I.-..... _._. (a) Device segmented into N4 numbers of Ay-thick BARITT diodes. n (x,y) n (x,y) np(x,y) pT np(x,y P n (x,y) p y x:l x x V,,, x 0 (b) Carrier distribution in each segment. Fig. 2.3 A TTPT Device. x

-30 of injection in each segment or Ay-thick BARITT diode. The potential distribution is assumed to be the superposition of the potential along the x-direction and the potential along the y-direction. The superposition assumption will simplify the problem of the two-dimensional potential distribution in a GFC-BARITT device. The potential along the y-direction "gate potential" is then expressed as: 6G(I) = (VGS + VB2 1 - ( ) 0 (2.27 where VGS = the applied gate-source voltage at the surface of the channel, VB2 = the built-in potential between the gate and the channel, N = the number of segments or BARITT diodes of a GFC-BARITT device and }G(I) = the potential of the Ith segment along the y-direction due to the applied gate-source voltage. The potential distribution along the x-direction can be approximated from the BARITT diode expression [12]. In general, it is a quadratic function of x (conduction path). The potential VF(I) at the source side of the device must be known in addition to a general knowledge of the potential variation along x. The combination of VF(I) and wG(I) will give the level of forward biasing of each Ay-thick BARITT diode or segment. The density of injected carriers, ninj can be expressed as: "inj(I) = npo exp( F(I) - G(I))), (2.28) inj P0 kT FG

-31 where n = the steady state density of minority carriers in the po channel (p-type semiconductor), npo = n/NA, VF(I) = the forward bias voltage at the Ith segment. An expression for this will be derived in the next section, NA the impurity concentration of the p-type semiconductor, n nj(I) = the density of the injected carriers at the Ith segment. The current density, JDS(I) of the Ith segment is: JDS(I) = satnsat(I) (2.29) where nsat is given in Eq. (2.26) and vsat is the saturated velocity of the carriers. Rearranging Eq. (2.29) and combining it with the expression for nsat, the JDS(I) expression of the Ith segment becomes JDs(I) = qn..(I) exp[-0.5 aL2 + klL]v, (2.30) ~DSin S 1 S sat where ln(n in(I)/nsat) kl = 0.5 aL - 1 S S The expression in Eq. (2.30) is given for the total current which is equal to the drift current beyond L. If one requires S drift and diffusion currents separately, the distribution function of the carriers in the channel can be used. The diffusion current density would therefore be:

-32 JDS (x,I) diff n p (., I) qDn - x (2.31) or DSi ff(x,I) diff qDn(k - ax)n (x,I) n I I p and the drift current density is JDS ft dri ft or (x,I) (x,I) (2.32) = qpno (x,I) E(x) no p DSdrift dri ft = qnop(x,I) Yx where n (xI) = n. (I) exp[O.5 aX2 + klx] inj 1 For x > Ls, -0 an (x,I) ax (kl - ax)np(x,I) 1 P E(x) = yx, the linear electric field, and = the low field mobility. At every point JDS(I) (x,I) + JDS (x,I) dri ft diff

-33 At x = LS the point diffusion current becomes negligible. Therefore at x > LS, the total current density, JDS(I) is equal to JDS drift (LS,I). Finally, the total current IDS can be obtained from the current density expression of the Ith segment which is given in Eq. (2.30): N IDS = 2ZAy E JDS(I) (2.33) 1= where Z = the width of the device, Ay = D/N, D = the half of the channel width (Ws/2) and N = the number of segments into which the GFC-BARITT device is divided. 2.2.2b Drift Current Approximation. In the previous section the effect of the diffusion was discussed. The velocity of the carriers was assumed to be a linear function of the field at the low field region, but constant at the high field region. This approximation, by itself, may introduce a larger error than by neglecting the diffusion effect. Therefore, in this section the effect of the diffusion is neglected, but the velocity as a nonlinear function of the electric field is considered. A nonlinear velocity expression as a function of the electric field for Si [13] and for III-V compound semiconductors[14] are given as follows. For silicon: E v(E) = vsat E + E (2.34) sat

-34 For III-V compound semiconductors: [PnoE + Ysat(E/Ec)4] v(E) o (2.35) [1 + (E/E )4] where vsat the saturated velocity, Ec =the field at the peak velocity, Esat = the field where velocity reaches half of the saturated velocity, and E = the electric field. The assumptions for the drift current approximation are: (a) Negligible generation-recombination in the depleted channel and hole current (unipolar conduction) are assumed. (b) The device is an n pn structure and is divided into N number of segments as in Section 2.2.1, Fig. 2.3(a). (c) The diffusion effect at the low field region of the device is neglected. (d) The carrier distribution along the conduction path is uniform. (e) The potential of the Ith segment due to the applied gate voltage is qG(I). (f) The forward bias voltage due to the applied voltage between the drain and source terminals is VF(I). The current density of the Ith segment is JDs(x,I) = qnp(x,I)v(E) (2.36)

-35 and n(x,I) = npo exp[(VF(I) -.G(I)/VT] (2.37) The field dependent velocity expressions are given in Eq. (2.34) and Eq. (2.35). The current density expression for Si devices is E JDS(XI) = npsat E + E (2.38) where E = dV/dx, the field along the conduction path, x. The integration of Eq. (2.38) with respect to x results in an average current density expression for the low level injection case as follows: JD q) VDS - - [ V (I)-_ G(I)] l (2.39) saDS(I) ='sat VDS n p kT F(I) - E (239) The current density of GaAs or InP can be found by using Eq. (2.35) for v(E) in Eq. (2.36) and integrating Eq. (2.36) with respect to the conduction path, x. This yields JDS(I) = Jo exp([VF(I) - G(I)] /VT)' (2.40)

-36 where n [0.5 E ERB + 0.2 sat(ERB/E c) Jo q NA and A[1 + 0.2(ER/Ec)4] ERB 2VDS/LDS Finally, the drift current can be obtained either from Eq. (2.39) or from Eq. (2.40) and given by N DS = 2Z D JD( ) (2.41) I=1 The current in a GFC-BARITT device can be calculated either from Eq. (2.41) or from Eq. (2.33), if only V (I) is known. In the next section, an expression for VF(I) of the Ith segment of a GFC-BARITT device will be derived. 2.2.3 Potential Distribution. Each segment of a GFC-BARITT device is a BARITT diode. Therefore, Poisson's equation for each segment can be expressed as -E qA qn(x,I) aE _ -A. - (2.42) ax ES s Equation (2.42) is the general expression which includes the space charge effect (or injected carrier effect) on the field distribution. It is necessary however to solve Eq. (2.42) simultaneously with the current density and the continuity equations. To obtain an

-37 analytic solution of the problem (Eq. 2.42), some simplifying assumptions have been made. These are: (i) The potential along the y-direction is assumed to be constant so one could solve a one-dimensional Poisson's equation. (ii) The injected carrier distribution n (x) is replaced by JDS/v. This gives 3E 2 JD I'x) -- = - NA - D (2.43) ax E A Ev S The expressions for the velocities are given in Eq. (2.34) for Si and in Eq. (2.35) for GaAs or InP. The inclusion of the velocity expression in Eq. (2.35) for III-V compound semiconductors is difficult to implement as it is. A modified expression for the velocity is given by v(E) = Vsat E+ E (2.44) sat where sat = sat/2no and vsat is the saturated velocity of GaAs or InP. Equation (2.44) has the form of Eq. (2.34) and therefore the solution of Eq. (2.43) will be valid for Si, GaAs and InP. Substituting the velocity expression in Eq. (2.43) gives for silicon and GaAs, respectively,

-38 aE _ qNA 1 JDS (I)E + Eat c$ xs sat (2.45) and BE. qNA 1 JDS ( I) TX i. eS sat 1 JDS (xI) Esat - s vsat E (2.46) s "sat L After rearranging Eq. (2.46) (E t) a sE + ii (2.47) where Oi JDS(I) 8 sat and qNA T = _ + a. iS 1 5s From Eq. (2.47) dx = E dE Esatci + iE Finally, the integration results in x = - ((iE at+ ~ E)- i E ln(aiE + E)E 1 i (2.48) (2.49)

-39 Substituting the boundary values gives E a - x 2 Esat ln(aj Es) - E ln( sat E + E) (2.50) sa sat sat i sat Bi 1 Replacing E with -(dV/dx) and integrating both sides of Eq. (2.50) gives LR 1 R2 x1 2 = 1 V 2 V x=-LF i F VR-VB VB-VF a. + 1 2 1 LR Esat [ln(a iEsat)] 1i sat Bi I L x=-LF x L in(ciEsat +BiE)dx (2.51) Replacing dx from Eq. (2.48) and integrating over E results in 2'[L2 - L2F] 2- R ~F VDS. i sat Ln(aiEsat)LDS + 1 isat o4 I(iEsat + BiERB) [1 - ln(aiEsat + iERB)] - (aiEsat - BiEFB) [1 - ln(aiEsat - BiEFB) c2 E2 + sat 24. 1 E[ln(aiEsat + BiERB)]2 - [ln(iEsat iEFB)2 $at RB ~ ~ isat F (2.52)

-40 where L = the length of the depletion layer from the reverse-biased + + junction side of the n pn diode LF the length of the depletion layer from the forward-baised junction side, EFB the field at the forward-biased junction side and ERB = the maximum field at the reverse-biased junction side. Expressions for LF and LR can be obtained from the conventional depletion layer expressions, namely, [2cs(VR + VB) 1/2 LR. =..B (2.53) R L qNA and 2E (VB - VF(I)) 1/2 F.^ J qNA where VDS = VR + VF(I) and LDS I= LRI + ILFI Equation (2.52) can be simplified by neglecting the smaller terms such as (i) IERBI >> EFBI neglect EFB terms, (ii) ILRI >> ILFI + IL-DS >> LF

-41 and (iii) IESatl >> IEFBI. Equation (2.52) then becomes 2 DS 1DS F ~' L~) - LI~slLFI VDS 1 * a + a E 2 sat LDS 1n(aiEsat) 1 iEsat 1 (iEat + RB - in( Esat + iERB)) - Esat (1 - ln(ciEsat)) -ln( iEsat + iERB)2 - [ln(aiEsat)]2 (2.55) and 1/2 L N2s DS \ qN A (VB - VF(I)) /2 2 D s tD1 2'DS pi satLDS i * ln(iEsat) + (i sat E + 8 ER sat sat~i i RB * (1 - ln(iEsat + iERB)) - iEsat(1 - n(aiEsat))t 2 + ~lz'E'zt sat i RB sat 28 I (2.56) where ERB 2VDS/(LD - LF).

-42 The VF(I) value of each segment in a GFC-BARITT device can be obtained by an iterative solution of Eq. (2.54), (2.56) and the current density expression from Section 2.2.1 or 2.2.2. The expression in Eq. (2.56) is valid for all levels of injection. It can, however, be simplified for two extreme cases: (i) Low level injection (ai = 0) can be reduced to a simple expression. (ii) High level injection (a) For a low level injection case,-a similar expression for VF(I) has been reported for a p np BARITT diode [12] as 1/2 (V- V-M)1/2 A LDS VDS &]s (2.57) 2-~s 2 LDS qNA' After rearranging Eq. (2.56) and defining VFBn (NA) L2 (flat band voltage) FB DS (VFB VDS )2 IV | MI V - 4VFB (2.58) where VDS is greater than the reach-through voltage, VRT but is smaller than the flat band voltage, VFB. (b) For the high level injection case, a B i i and

-43 (V - VF(I'))i 2 F q A iDS YDS Esat L 1n( Es)) 2ENA) LDS 2 DSat S i i E E2' sat sat + sa (Eat - n( + EB))- t - ln((E + E)l sat)] ~i -sat ([ln(a(Esat + ERB ))]2 _ [ln(ai Esat )]2 (2.59) The solution of a two-dimensional Poisson's equation is numerically possible within a reasonable time of computation [15], [16]. Instead of the iterative solution of VF(I), the potential distribution in every mesh point in the device can be obtained by using the rapid Poissoh solver and then searching for the maximum barrier height, V (I) - +G(I). The algorithm and the program for the Poisson solver are given in Appendix A. 2.3 Static-Induction Transistor The saturation of the current in conventional FETs is attributed to different mechanisms by different researchers. According to Shockley, pinch-off is the cause of the current saturation [17]. On the other hand, Nishizawa claims that the series channel resistance is responsible for the current saturation of FETs [1]. He then proposed a triode-like operation of a FET by reducing the series channel resistance. Recently, such a device has been realized and triode-like characteristics were reported [1].

-44 Since then many applications of this device have been considered [3], [18]. The SIT has potential applications in high power, high frequency analog areas due to its: (i) high input resistance, (ii) low output resistance, (iii) high transconductance, (iv) small gate time constant and minority carrier storage unlike Bipolar Junction Transistors (BJTs) and (v) negative temperature coefficient at high currents which offers stable operation [3] and a higher breakdown voltage due to the large distance between the gate and the drain. In Table 2.1 the power performance of SITs at different frequencies is shown. This illustrates the potential of SIT devices. In addition to all of these characteristics which favor high-power high-frequency operation there are some physical limitations to high power and high frequency performance of a SIT such as: (i) at high injection levels, there will be majority carrier storage at the low-field injection region; (ii) it is a normally on device and therefore the voltage swing of the input signal is limited; (iii) distributed gate capacitance of a planar SIT is high which limits the high frequency performance, and (iv) the drain current is very sensitive to the lateral diffusion of a vertical SIT which makes it difficult to fabricate reproducible devices. Even though the SIT is a promising device for high power and relatively high frequency applications, it has not attracted enough

-45 Table 2.1 Power Performance of SITs Frequency 8 MHz 200 MHz 1.0 GHz 2.5 GHz 1.0 GHz 100 MHz 700 MHz Power 2 kW 40 W 10 W 10 W 100 W 216 W Efficiency 55 percent Reference [1] [3] [1] [8] [2] [8] [8]

-46 research interest especially in the United States. Recently, there has been a growing interest in SIT devices. The potential distribution [18], [19], [20], applications to digital circuits [21], [22], Dc characteristics [3], [23], [24], possibility of VLSI applications (which is not promising [9], [18]), and applications in microwave circuits [2], [8], [24] of SITs have been studied by different groups. None of these groups has comprehensively studied this device. Most of them have reported the results of their experimental studies. 2.3.1 Physics of the SIT Device. The SIT device is a special case of vertical Junction Gate Field Effect Transistor (J-FET). If a JFET is made of a thin and lightly doped semiconductor, then at a low gate-drain voltage, the whole channel can be depleted before the breakdown occurs. A typical SIT structure is an n+n n one as shown in Fig. 2.4(a). Since the channel is n —type materials, then at low applied voltages between the gate and source it is completely depleted and a barrier at the source side of the channel is created. This barrier is induced electrostatically by the gate-source potential difference. In a long-channel FET this is called the pinch-off mode where current saturates. But since the whole channel is depleted unlike the pinch-off case in FETs, the increase in the drain-source voltage reduces the statically induced barrier at the source side of the channel and exponentially increases the current. The principle of the current conduction is very much like that of a BARITT diode. The only difference is that in a BARITT

-47 (a) A Vertical SIT G S D (b) Two-Dimensional Energy Band Diagram. Fig. 2.4 SIT Device. (G = Gate, D = Drain and S = Source). C c Ev I

-48 diode, minority carriers are injected but'in the case of a SIT majority carriers are injected. The barrier height is shown in Fig. 2.4(b) for an ntn nt SIT. Even though the barrier height and structure of a SIT are different from those of a GFC-BARITT device, the form of the device expressions are the same. Therefore, most of the results of Section 2.2.2 can be used directly for SITs as well as for GFC-BARITT devices. 2.3.2 Dc Characteristics of the SIT Device. At low gatedrain bias conditions, the channel may not be depleted completely. In this case, the device operates as a FET and its characteristic expressions such as the Dc current, small signal, and circuit parameters (gm,gds Cgd and Cds) will be dealt with briefly, because there have been extensive studies of FETs [25], [26] and numerical studies [27], [28] and [29] in the last fifteen years. By replacing the minority carrier density, npo in Section 2.2.2a and Section 2.2.2b, with ND, the Dc current density and current expressions for GFC-BARITT devices become valid for SITs. If the distance between the drain and the source is much larger than the distance between the two gates on both sides Of the source then the potential distribution in a SIT is very much like that of a GFC-BARITT device. The current expressions of a GFC-BARITT device are modified and repeated here for a SIT device. It is assumed that the SIT is divided into a number of N segments such as in a GFC-BARITT device. The current density of the Ith segment for silicon is VatVDS 60 DS(i) = qND (VD + Es exp[(VF(I ) L- G(I))/VT. (2.60) DS sat DS

-49 The VF(I) expressions derived in Section 2.2.3 are not valid for SITs. In the case of a GFC-BARITT device, depletion is between the drain and the source but in the case of a SIT device, the depletion is between the drain and the gate. Therefore, the potential distribution in a SIT is different from that of a GFC-BARITT device. The actual potential distribution can be obtained by numerical solution of the two-dimensional Poisson's equation. It is possible, however, to obtain a simple approximation for VF(I). In Fig. 2.5, along the OM path, the potential is a quadratic function of distance. This potential is (x2 + y2) V(x,y) = (VGS + VDS), (2.61) (Ls + D2) where D is the half of the channel, D = 0.5 WS + WGS. The potential along the x-direction is L (x2 + y2) V(x,y)= LDS (V ) (22) V (X Y) (V (2.62) (LD + y2)12 DS (L2D + D2) At the zero bias case, there is a charge accumulation region on the n -side of the n n junction of a SIT device which is a "Debye length" wide as shown in Fig. 2.5(b). VF(I) is the maximum barrier height value of the Ith segment in a SIT. From Eq. (2.62), assuming that this barrier height occurs at x = XD from the source terminal, then L-D'X (2X, + - D22) VF(I) = DS D N2, (2.63) (L2+ 2)1/2 (VDS)( + D2) DS N2

-50 S I y (a) Structure. n.n+ / ---------- ^ ______ —---- Ec (b) Energy band dia m of an n Fn (b) Energy band diagram of an n n n diode. xD AD x 0 (c) Built-in potetial of an n- i potential of an n n n diode. Fig. 2.5 A SIT Device.

-51 where _ = EsVT)1/2 D 2qND Equation (2.63) along with the G(I) expression given by Eq. (2.28) are used in the current density expression given in Eq. (2.60). A simple expression of the DC current of a SIT device is N IDS = 2Z JDS(I), (2.64) I=1 where JDS(I) is the current density of the Ith segment and is given in Eq. (2.60), JDS(I) in Eq. (2.60) is the result of the drift approximation of the injected carriers. In reality, at the low field region, the diffusion of the majority carriers are also important. The drift-diffusion approximation given in Section 2.1 is valid for SIT devices with a change of carrier type. The results of Section 2.2.2a are modified and given for SIT devices next. The'density of carriers in the saturated velocity region is given by ALS D "sat = 2 ninj -ln(nin/s) (2.65) sat 2vsat n inj Vsat Sinj inj at where ninj = Nd exp(VF(I)) - <G(I))/VT The distribution of the injected carriers in the channel is given by np(x) = n nj exp[-0.5 aX2 + klx], (2.66) P I I ~J ~~~~~~1 where

-52 k1 -[1/L ln(n j/nt) - 0.5 aLS] Nishizawa et al. [3] claim that there is no minority carrier storage effect in a SIT device and therefore it is a high frequency device. It is true that there is no minority carrier storage effect, but there is a majority carrier storage effect which degrades the high frequency performance. An expression of the carrier distribution in Eq. (2.66) clearly indicates that the carrier storage effect will be important at high injection. This means that SIT devices are no exception as far as power and speed or high frequency performance of solid state devices are concerned. The degree of majority carrier storage is given in Eq. (2.66) may not be exact, but nevertheless it physically predicts a phenomenon which is expected. 2.4 Dc Characteristics of a Vertical Field-Effect Transistor A simple analysis of a vertical FET is given in this section for completeness. A more complete model especially for GaAs FETs has been given in detail elsewhere [26]. A one-dimensional analysis of this special FET structure is relatively simpler than those of conventional FET structures since the gate is at the center of the drain and the source electrodes. The FET structure which will be analyzed, is shown in Fig. 2.6. The following assumptions are made: (i) The device is divided into two regions: the first region is LiS long and D-yx wide and is a voltage controlled resistor and DS max

-53 ISource a 0 LG LDS LD DS Drain Fig. 2.6 Vertical FET Structure.

-54 the second section is LDS - L6S long and D wide and is an N-type bulk resistor. (ii) the voltage distribution in Region I is a linear function of conduction path, x VDS V(x) DSx.(2.67) Ls DS (iii) The effect of the velocity saturation is taken into account. (iv) The depletion of the channel along the conduction path, x, is assumed to be gradual. The current transport expression in Region I is given in the following sections for different materials. (a) For a silicon device, DS qN n(E) dV() (2.68) where n(e) sat Esat + E and L6s LG + s i "DS ~ G i L —- qND By rearranging Eq. (2.68) and replacing the field by (dV/dx). a simpler equation is obtained as follows: DS Esat dx + JDS dV = qnND vsat dV (2.69)

-55 Finally, integration of Eq. (2.69) results in the following current density expression: V _DS DS = qNDVDS (2.70) The total drain-source current can be expressed as IDS = 2qZ(D - Yax) JDS * (2.71) Since the FET structure in Fig. 2.6 is symmetrical, the device expressions are derived for a half-width device where y max is the max maximum depletion width in the perpendicular direction of the conduction path, y, from the gate-channel junction. The expression for ymax can be obtained by starting with the conventional depletion approximation: 2= (VGS + Vb + V(x)) ( Yd^~~~~~~ep ~ qN * v(2.72) Ydep (x) =2S(VGqNDb..D.. Rearranging Eq. (2.72) yields Ydep() = Co(V + c x) 1/2 (2.73) where 2s 1/2 c o 0 qND V~S = VGS + Vb2

-56 and c = V /Ls C1 * VDS S Finally, ymax is given by Ymax = y(x)depl (2.74) x=LG Inserting Eq. (2.73) into Eq. (2.74) gives Ymax [c2(V + c LG) /2 (2.75) Then the drain-source terminal current IDS becomes DS IDS = 2qZ ND vsat (D -y ) (2.76) (VDS + EsatLDS) max (b) For a III-V compound semiconductor device an expression for the terminal current IDS can be derived by applying the same procedure as the one used for silicon devices. The current density JDS expression can be obtained from Section 2.2.2a with some minor modifications to Eq. (2.40) and is given by.5 V DS + 0.2 Vat(V /L SE)4 no L' sat DS DS2c JDs = qN - DS (2.77) DD 1 + 0.2 (VDS/LDSEc)4 and the total terminal current is given by

-57 IDS = 2Z(D - Ymax)S * (2.78) The ymax expression given in Eq. (2.75) can be used in Eq. (2.78). 2.5 Thermionic Saturation of the Diffusion Current In the preceding sections, drift-diffusion and drift approximations of the carrier transport have been considered. These transport equations however are incapable of describing the conduction process in the vicinity of the potential barrier maximum. Therefore, the only other mechanism to account for is the thermionic emission. Within the barrier injection range, current flow cannot be regarded as limited only by diffusion through the barrier region; thermionic emission at the barrier maximum must also be taken into account as suggested and done by Persky [12]. The empirical modification of the current transport equation based on the concept of thermionic saturation of the diffusion current [12] is as follows: dn qunnpE + qDn dx J = dn (2.79) [1 + Dn dx /(npvTE)] where vTE = the velocity of the thermionic emission over a potential barrier of zero height and vTE = (kT/2rm*)1/2. vTE must be the limiting velocity in the absence of field-aided drift. Equation (2.79) is considered as a current transport equation instead of the standard drift-diffusion equation, and the following assumptions are made:

-58 (i) the velocity variation with field is neglected so that Einstein's relation can be used; (ii) the space charge field effect of the injected carriers is neglected. (iii) the recombination-generation effect is neglected and (iv) a one-sided abrupt junction is assumed. A new current density expression is obtained for a BARITT diode [12] and is given by, ~ME Dn Jn= qDnns e [ D VD E ] (2.80) where ns = the carrier density at the source terminal and ~ME = (VFB - VDS)2/4(VFBVT). For V27XD << Dn/vTE, Eq. (2.80) reduces to J =qv n e-ME n = vTEs e ME (2.81) The thermionic saturation of the diffusion current becomes important when the doping concentration of the channel > 1017 cm-3. In this approach negligence of the velocity saturation effect may introduce an error which may be comparable to an error introduced by using only the drift diffusion current transport equation. One can conclude that any simplifying assumption will introduce an error to the current transport equation unless the basic device equations are simultaneously solved in a two-dimensional space.

CHAPTER III. SMALL- AND LARGE-SIGNAL MODEL 3.1 Introduction The determination of the circuit and noise properties of a solid-state device is facilitated by the assumption of small-signal conditions. Under small-signal conditions, the Dc equations are usually expressed in first-order Taylor series and their quiescent values and the resulting equations for the perturbation quantities are linearized. This usually results in coupled nonlinear ordinary differential equations [11], [30]. There is another approach for the small-signal modeling of semiconductor devices which is the "Charge Control Analysis" [25]. This approach relates circuit elements with physical processes since there is a one-to-one correspondence between the static charge distribution and the terminal voltages and currents. By assuming that the terminal voltages and currents change sufficiently slowly so that the internal charge distribution can be regarded as a succession of static distributions, the dynamic model of both types of devices (SIT and GFC-BARITT devices) are obtained. This approach is called the quasi-steady-state approximation and was first used for Junction Field-Effect Transistor (JFET) modeling [31]. In the following sections, the small-signal circuit elements of both devices will be derived as a function of the device parameters. The small-signal equivalent circuit which is considered throughout -59

-60 this chapter is shown in Fig. 3.1. Generally, the form of the expressions for SITs and GFC-BARITT devices are the same. This makes it possible to describe the small-signal circuit model of both devices with common expressions. However, this is not possible under all quiescent conditions. Under such conditions, the expression for the circuit element of each device is given separately. Some of the expressions are dependent on the parameters of the semiconductor material. Therefore, whenever it is necessary, expressions are given for devices made of silicon and also of III-V compound semiconductors. In the last section of this chapter, a simple noise analysis of SIT and GFC-BARITT devices will be given. Finally, the effect of the transit time of the drifting carriers along the conduction path between the source and the drain is included. 3.2 Small-Signal Circuit Elements 3.2.1 Transconductance. Transconductance is defined as the variation of the drain-source current with respect to gate voltage at a constant drain-source voltage: A'DS m VGS VS = constant In Chapter II the expression for IDS was given as a function of the terminal voltage VGS and VDS.

-61 R g G R C gs gd I I rd AdA At AIA I I _ad EAl ~ -U )~ 9gds I /i/iuv D TIv rv T- Cds gmVgs _ Rf S Fig. 3.1 Small-Signal Equivalent Circuit of a SIT or a GFC-BARITT Device.

-62 3.2.1.1 Silicon Devices. 3.2.1.1a GFC-BARITT and SIT Devices. For a silicon device, the drift approximation of IDSfor n p n type GFC-BARITT or n n n type SIT devices is v V Z N IDS = 2q sat DS th (VDS + EsatLDs) I=1 exp[(VF(I) F - qG(I))/VT], (3.1) where G(I) = (VG + VB2) (1 - [(I - 0.5)/N]2), nth= npo for a GFC-BARITT device, nP = the minority carrier density at thermal equilibrium. Differentiation of Eq. 3.1 with respect to VGS results in the transconductance expression which does not include the transit-time effect: N gm = GMO I=1 2 I - (1 -"N05 ^exp[(V F(I) -qG(I))/T] (3.2) where MO 2q D vsat GF10 = -2qZ nth VT VDS (VDS + EsatLDs) 3.2.1.lb Vertical FETs. The drain-source current is given in Eq. (2.77) and repeated in Eq. (3.3):

-63 VDS DS = 2qZND Vsat (D - max) (3.3) (VDS + EsatL's) where L'D = Co(VS + VDS) + LG, max = [Co(VG + C LG) - L2]1/2 -max - o' Gs 1 G1 G Co = (2s/qN)1/2 0 s D C1= VDs/LS-' 1 ~DS'S The transconductance expression is obtained from Eq. 3,3 and given in Eq. 3.4: VDs 9m2 NDVsat (V DS C2 ax Ymax (3.4) + EsatLs) 3.2.1.2 III-V Compound Semiconductor Devices. 3.2.1.2a GFC-BARITT and SIT Devices. The current expression is given by IDS N - 2Z D N Jo j= I=l exp[(VF(I) - <G(I))/VT] (3.5) where 4 2VLDS LDS Vsga LDS VDSI J = qnth I 2V LDs 4 5E4+ LDS c L DS th= N for a SIT and nth = /N for a GFC-BRITT device. 1A/N for a GFC-BARITT device. nth niA

-64 The transconductance is then given by N Lj gm -2Z N VD i 1 2- 5)2 J (3.6) ~1 INN2 DS1 where JDS = Jo exp[(VF(I) - G(I))/VT] 3.2.1.2b Vertical FETs. The current expression is given in Eq. 2.79 is as follows: DS = 2Z(D- Ymax) (3.7) 1/2 = [{C(Vs + C LG) - LG * The transconductance is given by Eq. (3.8): C2 g = 2ZJ -- 38) m o ~.(3.8) 2 Ymax 3.2.2 Conductance. Conductance is defined as the variation of the drain-source current with respect to the drain-source voltage as follows: A DIDS gds aV ds DS VS =constant GS Both the SIT and GFC-BARITT devices are high conductance or low output impedance devices.

-65 3.2.2.1 Silicon Devices. 3.22.21a GFC-BARITT and SIT Devices. The derivation of the conductance from the current transport equation is given in Eq. (3.9). This conductance is valid for the GFC-BARITT and SIT devices. E L 2ZD 9V s satLDS)V DS + VDs VN T JDS(I)VF(I), (3.9) gds = (V + E L s)V s S DS satt DS DS u I=l where IDS = the total current given in Eq. 3.1, JDS(I) = the current density and VF(I) = the forward biasing voltage of the Ith segment. 3.22.2.1b Vertical FETs. The conductance is obtained from the derivation of Eq. 2.77 with respect to VDS and given in Eq. 3.10 gds [ EsatLD s 1 LG C0 1 1. gds DS v v +LV (LV 2 LaL y (D ) S-~DS sa DS DS max( -lmax JYa 3.2.2.2 III-V Compound Semiconductors. The conductance expression is different from that of silicon due to the complicated velocity electric field expression. 3.2.2.2a GFC-BARITT and SIT Devices. The current transport equation is given in Eq. 3.5. From that expression, the conductance equation is derived and given in Eq. (3.11):

-66 - 2Z D 1 gds VT N VDS V 2VD s~ DS Jo LDS 1 + - 2V 5E4 + DS c LDS N Z VF(I)JDS(I) + I= I nth-4i LDs ~~ —- ---- 4 Z D N VDS N I:1 (3.11) where JDS(I) is the current density expression for III-V compound semiconductor devices as given in Eq. (2.40). Vsga is the saturated velocity of GaAs or InP and Ec is the electric field where negative differential mobility starts. J is as given in Eq. (3.5). 3.2.2.2b Vertical FETs. The conductance is obtained from Eq. (2.76) for silicon and from Eq. (2.78) for III-V compound semiconductor devices: = 2Z D (D -y ) - 2ZDJDS = DS max DS 3ymax DVDS (3.12) After evaluation, Eq. (3.12) becomes 4 r V 9V th LDS - Z DS Ll4+q5Eh +s VaDS 2V i DS LDS 4 LG C2 _G 0 1 -2ZDJDS L' Y (D - ym -) * (3.13) DS max max 3.2.3 Gate-Source Capacitance. 3.2.3a GFC-BARITT and SIT Devices. under small-signal conditions is: The total gate charge

-67 aQGS(0) QG S(t) = QGS() + aV gs (314) where QGS(O) = the charge at steady state and V (t) = the small-signal gate-source voltage. ags The gate-source capacitance is defined as AQGS(0) C = gs aV GS V =constant DS The gate-source capacitance is the result of the variation of the charge in the channel with respect to the variation of the gate-source voltage. This charge is due to the injection of the carriers from the source into the channel: yV) D N [(V F(I)_G(I))/VT,] GS = qZ(1 + YV) thGZ, (3.15) I=1 where YV is one for a vertical structure or YV is zero for a planar structure. Equation (3.15) does not include the effect of the carrier distribution. In reality, the stored charge in the channel is less than what is found from the drift-approximation of the injected carriers. The effects of the diffusion on the small signal circuir parameters will be analyzed later in this chapter. For simplicity, in this section, diffusion effects will be ignored. The gate-source capacitance is derived from the steady-state channel charge (Eq. (3.15) and given in Eq. (3.16)):

-68 Cgs:C (0)1sO 1_ L eNF, (3.16) gs Cgs()V 1 (I - e5 where Cgs(O) = qZ(D/N)nthLG. For the insulated gate devices, the total capacitance c C C /(Cg + C ) where C is the oxide gst gs OX ox ox capacitance. 3.2.3b Vertical FETs. The gate-source capacitance is due to the charge of the depletion layer. From Section 2.4, Cs is obtained as c = D aF +y ) ___S J 3ydep x) gC 2qZN I (W L S + (Ls- LG) a)< + L P Cgs 2qZND { [WG Ymax) 3VGS (LDS LG) v aG G VGS (3.17) where L_ s 1 ( + V + V -1/2 VDS 2 VGS + b2 + DS Ydep =1 C C2 L adey ) 1 and a Ymax 1 o G ~V 2 V2 L VGS 2 Ydep VGS max LDS 3.2.4 Drain-Gate Feedback Capacitance. 3.2.4a GFC-BARITT and SIT Devices. Under the smallsignal approximation, this capacitance is the variation of the charge at the gate due to the change in the drain-source voltage: AC AQGS(O) gd aVDS VGS=6onstant GSb

0 i epect to results in Differentiation of the GS(0) with respect to DSesu in the following expression for Cgd N VF(I) [(VF(I)-G(I))/VT (3.18) Cgd = T I S= Vertical FETs. The feedback capacitance of the drain-gate is due to the variation of the drain-gate depletion layer with VDS: ^C -.d = 2qZN0maLbSD +Vs G( LVDs LDS LGG (3.19) where 2 l LG 1de G o VS 2 dee G LDS ~LDS C2 L Ymax 1 0CoLaV - 2 Ymax DS an=.c^.V~os-1/2 and +L s aLDS 1 C ( + Vb2 + VDS 2 o GS b2 D' VDS 3.2.5 DrainSOurce Capa c-source 3.2.5a GFC-BiAITT and SIT Devices. capacitance is defined as thurce sect to a change of the drainource

-70 Cds aQDs VDS VG=constant where QDS N D = 2qZnth -LDS I=1 UVF'(I)-G(I))/VTJ e * (3.20) This, however, does not include the diffusion effect. Cds is obtained from Eq. (3.20) as follows: ds = qthNe DS Cds = 2qZnthi~- LDS N 1LE VT I=1 VF(I) VD e DS [(V-F(I)-G(I))/VT].(3.21) By comparing Eq. (3.21) with Eq. (3.18), Cds can be related to Cgd as in Eq. (3.22); Cds LDS LG Cgd (3.22) 3.2.5b Vertical FETs. The drain-source capacitance can be approximated as aQDs DS VGS= constant where QDS = 2qZL (D -Yma)ND and

-71 ds = qZND a (D -y ) LS * (3.23) Cds D 3 DS2qZND Vmax ) S D 3.3 Diffusion Effects on Small-Signal Circuit Parameters In this section, the small-signal circuit parameters are obtained by using the drift-diffusion device expressions of the GFC-BARITT and the SIT device given in Chapter II. Derivation of the small-signal parameters is the same as in the previous sections. Therefore, in this section only the final expressions will be given. 3.3.1 The Transconductance. The drift-diffusion current expression in Eq. (2.24) is differentiated with respect to VGS, and the resulting g expression is given by N DRVGSesx gm = AM [DRVGS exp (USS1 + USS2) + VT V USS2 I=1 L GS exp(USSl + USS2), (3.24) where A W n th AM qZ N VthVsat VZ VTvsat 2 DRVGS 1- ( N5) USS1 = (VF(I) - ~G(I))/VT and USS2 = -0.5 aL2 + k'L S S

-72 3.3.2 The Conductance. The conductance is obtained by differentiating Eq. (2.24) with respect to VDS: ds = -AM F exp(USS USS2) - USS2 exUSS + USS2), gds - AM VDs 3s Vs = VDS DS (3.25) where AM, USS1 and USS2 are defined in Section 3.3.1. 3.3.3 The Gate-Source Capacitance. Cg is obtained from the stored charge in the channel. For the insulated gate devices, the total gate-source capacitance is obtained from the series combination of the insulated gate capacitance and the stored charge capacitance. The stored charge capacitance is N N Cgs- AC VT aVG -exp(USS1) exp(USS3) + exp(USS1) gs -= CT 3VGS I=3 J=1 NN * aVGS (USS3)exp(USS3),(3.26) L L 2 where USS3 = k' J - 0.5a J 1 NN NN = an integer and A WS LG AC - 5ri G AC = qZ~ -th NN Equation (3.26) is valid for L > L if L < LG then after S- G' S replacing LG with LS just in AC, Eq. (3.26) becomes applicable for this case also.

-73 The total capacitance, G, is defined as gst C = C C /(C +C ) gst CoxCgs Cox gs where Cox is the oxide capacitance. 3.3.4 The Drain-Gate Feedback Capacitance. Cgd is also obtained from the stored charge in the channel by differentiating it with respect to VDS: N 1 VF(I) NN Cgd = AC V DS exp(USSl) exp(USS3) + exp(USSl) I=1l u J=1 NN 1 Vs - (USS3)exp(USS3).(3.27) J=l Equation (3.27) is derived for L > LG, for the cases of LG > LS, just in AC, LG has to be replaced by LS. 3.3.5 The Drain-Source Capacitance. Cds is approximated from the Cgd expression by L Cds Cgd (3.28) For LS > LDS, LS should be replaced by LDS. If LS < LG, replace (LG/NN) with (LS/NN) in Eq. (3.27).

-74 3.4 Carrier Transit Time Effect The carriers are injected from the source electrode, drift along the channel and are collected at the drain electrode after a drift time, Td. Because of this drift time, changes in the drain-source current will occur in Td second following the changes in input. This delay causes a phase difference e between the terminal voltage and the terminal current. The drift time is also called a "transit time". It is formulated as LDS Td:'dx (3.29)'Ed v(x) where v(x) = the carrier velocity as a function of the local electric field along the conduction path, and x = the distance that carriers travel in the conduction path. This transit time is included in the device expressions through the assumption of an unattenuated current wave expression in the drift region [28]: ids IDS exp(-jwTd) (3.30) The small signal transconductance and conductance expressions are obtained from the current wave equation in Eq. (3.30), and given in Eq. (3.31) and Eq. (3.32), respectively: * -JTrd1 9 = m e (3.31) and

-75 * -JWTd ds = 9dse (3.32) Assuming a linear electric field distribution along the channel, the Td expression will be evaluated for silicon and for the III-V compound semiconductor devices. 3.4.1 Silicon Devices. The velocity expression of silicon as a function of field is inserted in Eq. (3.29): LDS T.d = f ----- dx -----, (3.33) - 7 E(x) X= LF V E(x) F sat (Esat + E(x)) where E(x) = y x, = 2(VDS + VB)/(LDS - LF)2' LF = the depletion width at the forward biased junction and LDS = the channel length. The integration of Eq. (3.33) results in 1 F 1 DS Td YVsat Esat ln + y(LDS -LF) (3.34) where F 2s (VB -VF) 1/2 F qNA j

-76 for a GFC-BARITT device and LF = the Debye length for a SIT. The transit time effect on gm and gds can be accounted for by inserting Eq. (3.34) into Eq. (3.31) for transconductance and in Eq. (3.32) for conductance. 3.4.2 III-V Compound Semiconductor Devices. The field distribution is a linear function of the conduction path. In this section the only difference is the expression of the carrier velocity which is given in Eq. (2.36) in Chapter II. Following the procedure for silicon devices the conductance and transconductance expressions are derived and given in Eq. (3.35) and Eq. (3.36), respectively. These expressions are in the form of numerical integrations. Explicit expressions could not be derived due to complex carrier velocity expressions for III-V compound semiconductors. Conductance: * -je gds g ds e. (3.35) Transconductance: g = g eje (3.36) where e = wTd and Td' The transit time is given in Eq. (3.37): NN Ei 1 + ( sY/Ec)4r4j4 J l I+( + (s!E )%L+L -- — (3.37) J=1 Pnor + (Vsa)(Y t/Ec)4r4J

-77 where (LDS'-LF) NN 3.5 Large-Signal Analysis 3.5.1 Introduction. The dc analysis of the TTPT SIT and the GFC-BARITT devices have been done by closely following the BARITT diode analysis. The large-signal behavior of these devices are different from those of the BARITT diodes. The negative resistance is essential for the use of a BARITT diode. On the other hand, the TTPT devices amplify the input signal which is applied to the gate and transmit the amplified signal to the output port. The directionality of the three-terminal devices is an advantage over the two-terminal BARITT diodes. The simplified analysis of the BARITT diodes overestimates the efficiency and the power capability of these devices [32], [33]. Numerical analysis [34],[35],[36],[50] and experimental studies [35],[37] have shown that the early predictions for the efficiency and the power capability of the BARITT diodes are orders of magnitude higher than the real values. The three-terminal punch-through devices have the high efficiency capability of the bipolar junction transistors (BJTs) and the high frequency operation capability of the punch-through diodes. A collector efficiency up to 55 percent for a SIT has been reported [2]. In this section, the large-signal analysis is done by making the following assumptions:

-78 (i) The model is valid for operating frequencies below the cut-off frequency which is defined as the frequency where the phase difference between the input signal and the output signal becomes 2T. (ii) The quiescent point is chosen in such a manner that the gate channel junction is not forward biased in the case of a SIT analysis. (iii) A load impedance is calculated to match the predetermined voltage of the device. (iv) The electric field along the channel is assumed to be determined by the dc bias conditions. (v) The change in barrier height at the injection junction follows the input signal. (vi) The space charge effects will be ignored. The small-signal circuit parameters will be modified for the largesignal case. In the next section, the derivation of those parameters is given. 3.5.2 Large-Signal Circuit Parameters. The equivalent circuit model which is used for the small-signal approximation, will be used in the large signal cases also. Instead of calculating circuit elements from the dc device expressions, they are obtained by using the average values of the time-dependent circuit parameters. A similar approach has been used to derive the large-signal circuit parameters of a MESFET from the dc device expressions [38],[39]. The derivation of the large-signal circuit elements is given for silicon and for III-V compound semiconductors in the following sections.

-79 3.5.2.1 GFC-BARITT and SIT Devices. The time-dependent current is given by Eq. (3.38): N VF(I) - G(I ) Ids(t) DSO Z exp - G I=1 T r Vi(I)DERV (I)sin(wt) + V (I)DERVS sin(wt - o),. exp L VT - (.3 where IDSO is the leakage current. DERVGS(I) = 3VF(I)/aVGs and DERVDS = DVF(I)/aVDs.. The Fourier series expansion of Eq. (3.38) separates the dc and ac currents. Considering only the first harmonic, Ids(wt) = a + a cos(wt)+ b sin(wt), (3.39) 1 1 where ao is the average dc current, 2r a = 1 I (Wt) dot 0 2,ff I ds 27r a = - Ir i Ics(wt) cdwt)d 1 T J ds and o 2rr b1 Id (t) sin(ot) dwt 0 The Vinsin(wt)is the input RF voltage and the V sin(wt - ) is the output RF voltage due to the voltage drop across the load impedance under large signal conditions. These two RF voltages can be assumed to be known. From the known terminal voltages, the required load impedance can then be calculated. A detailed explanation of the large signal modeling is given in Section 4.7 of Chapter IV.

-80The Fourier coefficients are IDSO ao 2 2rr 2rr J 0 N I=1 - v Y DERVD exp DSQ ERV DS V - SQ DERVGS(I) T i in ~ exp + V DERV G(I) L T V sin(wt)+ V DERV sin(t - e) - dwt VT DS J (3.40) I (I,J) = rVDSQ ~ DERVDS- VGSQ. DERVGS(I)exp. —...- J i DRV(I. exp + DRV(I) L T ORVGS V sin(wt)+ VT vT DRVDS sin(tt - e) ] (3.41) I2(I,J) = I 1 and sin(wt) cos(wt) (3,42) I3(I,J) = I 1 (3.43) The average dc current IDS is given by Eq. (3.44): IDS IDSO M M L= j=j N I=1 (3.44) The coefficient of cos(wt), a can be expressed as a function 1 of ENTI which is given in Eq. (3.45); ENT1 = M M N J= I = I3(I J) (3.45) and

-81 a = IS ENT1 * (3.46) 1 DSO The coefficient of sin(ot) b is given as a function of ENT2 1 in Eq. (3.48): M N ENT2 = 2 I2(I,J), (3.47) J=1 I=l b = IDS ENT2, (3.48) where IDSO is WS nth IDSO = N V Vsat for the drift diffusion model. It is valid for both Si and III-V compound semiconductors. In the case of the drift model, WS I = J. DSO o N for the III-V compound semiconductors and WS VDS IDSO Z Vsat N VDS + EatLDS th for silicon. The effective gm is given by Eq. (3.49):

-82 meff DERVGS(I) b2 GS 2 1/2 + 2 ) (3.49) The conductance can be found and is similar to the transconductance: a2 1/2 = DERVs b2 + 1 DS 1 2 dse eff (3.50) The gate-source capacitance can be approximated from the time dependent gate charge QGs(ot) WS LG N = N M6 L "Inj^I= NZ M ninj(I)exp I=1 Vin( I) i- sin(wt) + VT V vT sin(wt - e), (3.51) (3.51) where WS LG AC = z q q = AC(b2 + 0.5 a2)1/2DERVGs(I) 1 I Cdeff (3.52) Cdeff = AC(b2 + 0.5a2 )1/2 1 1 DERVDs(I) (3.53) and cdsff Cds(small signal value) 3.5.2.2 Vertical ffETs. 3.5.2.2 Vertical FETs. (3.54) 3.5.2.2a Silicon FETS. The total current Ids(wt) is given by Eq. (3.55):

-83 VDSQ + Vo sin(wt - o) Ids(wt) = AF (D -y (wt)) max [LDSEsat + VDS + + sin(wt - o)] (3.55) where AF = 2ZqNDVat and Ymax (ut) C1/2 (VGQ + Vi sn s t)'/2 The Fourier series expansion of the Ids (t) will result in the dc and the ac currents: IDS 2,ff -- 1 2TT * Ids (t) dwt (3.56) The new numerical integrals can be defined as follows: (VDSO + V0 sin(w \ \ IE1 t - )) r + V0 sin(wt - e)). - /2 (VGs "o'GSQ (LDSEsat + VDSQ + Vin sin wt) 1/2 ait)~~~~~ (3.57) IDS AF V 360 L J=l M ElI = a (3.58) (3.59) AF a: 90 = J=' EI1 cos ( and AF 1 90 M J=l EI1 sin ( 18 180 (3.60)

-84 From the total current, Ieff Ids(Ot) = ao + a cos(wt)+ b a2 If [Lb2 + 1 ]1/2 The effective transconductance The effective transconductance is obtained and sin (wt) 1 (3.61) (3,62) meff is e ff geff DERVGS(I) Ieff (3.63) where DERVGS(I) =- O.5 C1/2 0 The effective conductance is deff DERVS = DS= DERV I DS eff EsDS (3.64) (VDSQ + + + E LS) ( V D S + V 0 s D S The gate charge is QGS(Wt): QGS( t) = 2ZqND[LGY (t) + YGD (t) a ( t)] (3,65)

The source gate capacitance is given by Eq. (3.66): Cgs (t) qND [LG + ClD(VDQ + Vo sin( t - e))1/2] VGQ + Vi sin(wt] GSQ - in (3.66) The effective Cgs at the fundamental frequency is given by Eq. (3.67): (3.67) C gSeff = 2ZqND(EI52 + 0.5EI62)1/2 where - M C1/ EI5 M L +jC F 1/2 L LG +o VDSQ + J=l sin ( j - V 1/2 0I VGSQ +Vinsin M J (VGSQ + Vinsin 7L3) and cl/2 EI6 - - M M 3=1 1/2 L + c1/2 V G o I DSQ + V sin r J -)) * iw v~COS1 C ]o [VGSQ + V1 n /2 sn M The effective Cgd at the fundamental frequency is obtained similar to ggs and given in Eq. (3.68):

-86 C f gdeff = 2ZqND(EI72 + EI82/2)1/2 (3.68) where EI7 = _90 3=1 M EI8 = - z 3=1 EIO12 sin ( M J) EIO1/2 cos ( J) m and gdeff EIO = VGSQ + in sin (M J) 2w VDSQ + Vo sin ( M) The effective Cds at the fundamental frequency is equal to in Eq. (3.69): Cdseff = Cg 9deff (3.69) 3.5.2.2b III-V Compound Semiconductor FETs. The current, transconductance and conductance expressions of the III-V compound semiconductor (III-V C-S) FETs are different than those of the Si FETs. The capacitance expressions are the same as those given in Section 3.5.2.2a. The total time dependent current can be expressed as in Eq. (3.70): Ids(tt): 2Z(D - Ymax)JqND ds max 0 o D' (3.70)

-87 where 2.5p E4EF + v EF4 J = no c Vsga 0 5E 4 + EF4 c V1s(wt) = VDSQ + Vo sin(wt - e) VGs(wt) = VGSQ + Vin sin(wt) and EF = 2VDs(wt)/LDs. By following the usual procedure, Ieff is obtained and given in Eq. (3.71): 2 ZqN / Ieff ZqND (b2 + 0.5 a2)1/ 2 eff M 1 1 (3.71) where M a, = 1 J=l M b, J=1 ET1 = D - ET1 cos ( 2 J) ET1 sin ( J) (Co VGSQ(wt))/ Jo The effective transconductance, g is derived from the mff effective ac current Ieff and given by Eq. (3.72): 9,ff - DERVGS I meff GS eff (3.72)

-88 and finally the effective conductance is given in Eq. (3.73): 9ds DER DS eff (373) eff 3.6 Small-Signal Circuit Properties 3.6.1 Admittance Parameters. An equivalent circuit of a SIT or GFC-BARITT device is shown in Fig. 3.1. In this equivalent circuit, parasitic resistances of the electrodes are included to analyze their effect on the performance of the device. The y-parameters are obtained by a straightforward circuit analysis of the equivalent circuit in Fig. 3.1. These expressions for the y-parameters are: y G (1 - & ), (3.74) 9 1 y = -G *, (3 75) }12 g 2 y = G ~ B, (3,76) 21 Gd 3 y = G(1 - ), (3d77) 22 4 4

-89 where 1 Y1 = - I G x g 11 1 G + g Z X 11 11 pl = A_ G d 2 Gd 2 Z X X Z x 11 21 21 21 G G 3 x z z x 11 11 11 11 12 12 21 G 4 Z X 11 2 X' 32 1 Z 11 z - 12 Z, 2 11 i Gd Gd Z 2 2 -X Z X Z z - z'.)1 221 21 1 11 12 22 I 21-2 33\ Y12 Z - i12 22 Z' 22 z 22 21 zy' 1 zy 1 _ z. Z 11 zy' 2 Y2 = _2_ 2 21

-90 z = X' - XI 11 22 12 Z = x' - XI, y = y' + xy' 12 23 3 13 1 1 2 zy = xy 2 2 Z = X' + X'I Z 21 32 22 22 = X' + X 33 23 X' 12 = 12 Xll 13 = x 3 = xy1 13 =1 X 1 X 11 11 X 32 X32 X 5 3. 31 XI 2X 22 X 222 X3 21 3 I, X33 33 X \X 331 23 XY2 = xy X 2 X 21 21 G = R1 Gd g R d 1 R d d xI = - jCg s - y 1 1 Rm gs, x2 g* + jwiC 1 21 m gs x 12 oCgs 1 3 y1, x22 Gd + j2oCds + jwCgs X =, x = g* +G* + + C xy = 13 Y 23 m ds ds 1 in R x Y1 - g*, X32 G* + jwC xy V 31 p ds ds 2 out Rd xg 1 G* -jC - 33 m rr ds ds y S and (1/Rc)-jCgs, gs_" Y1 1 + m2 C R2 gs c

-91 In the case of the equivalent circuit of the intrinsic device, the y-parameters become much simpler than those given in Eqs. (3.74) through (3.77). The y-parameters for Rm =, R = 0 and Rd = 0 become gs gd Y Rc + j(CgS + Cgd)' (3.78): jmC (3 79) 12 gd Y = jgd (3.79) Y = -(g* + jCgd) (3.80) Y2i - (m gd and Y = 9ds + iJ(Cds + Cgd) (381) where the asterisk implies that the transit time is accounted for in the gm and gd expressions. R is the gate charging c resistance; and it is usually measured. In this case, however, the dc contact resistance will be used. 3.6.2 S-Parameters. At high frequencies the measurements are made in terms of the scattering, s-parameters. Therefore, it is useful to relate measured parameters to intrinsic device parameters. Such expressions are given in a text [40]. In this section, the y-parameters are known, therefore, the s-parameters will be calculated in terms of the y-parameters. The expressions which relate the s-parameters with the y-parameters are:

-92 (1 - y )(1+ Y ) + 2Y21 (1 11l 22 12 )21 s 11 (1 + y )( yI ) - y y 1+y)11 + 22) -Y12 21 (3.82) s 12 S 21 -2y'2 _____ 21 __________ __IL (1 + y' )(1 + y' ) - y' y' 11 22 12 21 -2y (1 + y)(l ) - y ) y 11 22 2 21 (1 + yll)(1 - Y22)+ Yi2Y21 (3.83) (3.84) = (3.85) 22 (1 + y' )(l 11 + y' ) 22 - y' yR 12 21 If only the s-parameters for the devices are known, then the y-parameters can be calculated by using the following expressions given in Reference [40]: y' 11 Y' 12 = y R 11 0 = y R 12 o (1 - si )(1 + _ (i-s).11 (1 + s ) (s 11 22 -2 12 (1 + s )(l +' 1 S ) + S S 22 12 21 + 1) - s s 12 21 (3.86) 9 (3.87) s ) - s s 22 12 21 Y' 21 = y R 21 0 - 2s21 (1 + s )(i + 11 (3.88) s ) - s s 22 12 21

-93 22 2 2 = y R 22 0 (1 + s )( (1 + s )(1 11 - S22) + + ) - 22 S S 1? 2 2 S S 12 21 (3.89) where R = the resistance of the transmission 50 ohm or 75 ohm, etc.) and yj' = the normalized y-parameters. 1ij 3.6.3 Gain and Gain Bandwidth Product. figures of merit for the amplifying devices. signal, one can define two types of gain: (i) Maximum available gain (MAG) line system (i.e., Gain is one of the For the case of small Iy I2 MAG = 2 4 Real (y ) Real (y ) 11 22 (3.90) and (ii) the maximum unilateral gain (MUG). It is given in terms of the s-parameters in Eq. (3.91): Is 12 21- I MUG = (1 - Is 12)( - 2212) 11 22 (3.91) for Is s 11 Is 1 22 and < 1 < 1 s 12 = 0.

-94 In addition to the gain of an amplifying device, its cut-off frequency, noise figure, and noise measure are also important figures of merit. The noise analysis is rather lengthy and will therefore be done in a different section. The cut-off frequency, fT also known as "unity gain-bandwidth product" can readily be calculated in terms of the small-signal circuit parameters: f m (3.92) fT 27(C )* gs Equation (3.92) is derived by assuming a very simplified equivalent circuit for the device. The fT is obtained from the equality of the input and output currents. The resulting Eq. (3.92) may be misleading in many cases as discussed in [41]. Because of the effect of the transit time on g is neglected. Also, the gm used is the dc transconductance; the ac transconductance is expected to be less than the dc value. An alternative expression for the fT is given in Eq. (3.95) and i.s a more physically meaningful one than Eq. (3.92). The phase shift is due to transit time e. G = *OTd. (3.93) The device is useful up to a = 2=: 2-= 27fTI-d (3.94) f -. (3.95) T Td

-95 3.6.4 The Stability Analysis. Under certain terminating conditions, the devices may oscillate due to the internal feedback of the device. The inherent stability conditions are given in Reference [40] and listed below: (i) Is s < 1 - s 2 (3.96) (ii) Is s < 1 - Is 2, (3.97) M21 12 22 3.97) (iii) 21s s < 1 - s 2 - Is 12 + s s - s s. (3.98) 12 21 11 22 11 22 12 21 All three inequalities have to be satisfied simultaneously for the inherent stability of a device. 3.7 Large-Signal Power and Gain of the TTPT Devices An equivalent circuit of the three-terminal punch-through devices is shown in Fig. 3.1. The same equivalent circuit will be used with the large-signal circuit parameters to obtain the output power gain and the efficiency of these devices. The y- and s-parameters of the equivalent circuit are already known from Section 3.6. In the large signal case, the load impedance, ZL, cannot be assumed to match the output impedance of the device, unlike the small-signal case. The load current, iL, can be approximated as: Ieff (3.99) L eff

-96 From Section 3.5, the Ieff is directly used instead of the -g*Vg approximation. The g* is the average transconductance, m gs therefore Vs must be the effective gate voltage. The output power, P, is P = ff/Real(yL) Po Ieff/ L (3.100) and the dissipated power, PDC, is PC V= S I (average) DC DSQ ds (3.101) The collector efficiency, nc, is P 0 Tc p DC (3.102) The added power efficiency, na is given in Eq. (3.103): p. in na n= 0 D -DC (3.103)

-97 The input power, P in is V2 Pi = - Re(yi ) (3.104) in 2 in where the yin is the input admittance as y y 12 21 and is the load admittance. The power gain, is defined as22 and y, is the load admittance. The power gain, Gp, is defined as P P P 0 ~GP~ P=~ in-~.(3.105) in Then finally the power gain expression is given in Eq. (3.106): 2V Ie G = o eff (3.106) V2 Real (Y ) gs in 3.8 Noise Analysis 3.8.1 Introduction. The noise contributions to the small-signal current and voltage of the injection type devices, specifically for BARITT diodes, arises from two main sources: (i) the shot noise due to the randomness of the injection process at the forward biased junction discussed in [42] through [44] and (ii) diffusion noise due to the carrier velocity fluctuations in the dirft-diffusion region of a BARITT diode and analyzed in [42], [43], and [45].

-98 SIT and GFC-BARITT devices are also injection type devices, therefore the noise analyses of a BARITT diode can be extended to SIT and GFC-BARITT devices. In the case of the three-terminal SIT and GFC-BARITT devices, the gate noise current has to be derived in addition to the drain-source noise currents. A formal procedure to derive the gate noise current of FETs has been given by Van der Ziel [46]. Following the approach of Van der Ziel, an expression for the noise current of the gate is obtained. Only the major part of the gate noise is considered because Van der Ziel has derived the gate noise from the coupling of the drain source noise current through the gate electrode. In addition to this coupling noise, there is another source of noise which is due to the gate-channel interface. This is especially important for the insulated gate device at low frequency operation [47], [48]. The noise due to the insulator semiconductor interface is also important for GaAs MESFETs because there is a thin insulating film on the surface of the GaAs which excludes the area of the gate electrode [49]. The noise figures of the insulated gate FETs and MESFETs have been compared and it has been noted that )these devices have almost identical noise figures at microwave frequencies [50]. One can therefore conclude that the noise due to the insulator-semiconductor interface is negligible at microwave frequencies. In the following sections, then, noise sources of SIT and GFC-BARITT devices will be analyzed at high frequencies.

3.8.2 Noise in Punch-Through Diodes. The modeling of a device (SIT or GFC-BARITT) is done by dividing the device into N-numbers of segments. Each segment is a BARITT diode. This approach will be assumed for noise analysis also. There are a number of studies on the noise analysis of the BARITT diodes [11], [42] through [44], which can be applied to the Ith segment of a SIT or a GFC-BARITT device. In this study, Statz's [43] analysis will be followed and applied to a SIT or a GFC-BARITT device. The total mean-square open-circuit noise voltage, including the shot noise in the injection region and the diffusion noise in the drift-diffusion region of a BARITTdiode has been derived [43] and given in Eq. (3.107): 4qv tJoAf 2D L Il sat o 1- cos e n DS sin o |^| ^"st^ "_J^ ~2V3 - )], (3.107) n vi w2A L2 22 2 S Sat V W2A CX + W s....at where w = 2rf, f = the frequency, Af = the frequency bandwidth, J= qvsatnp, the current density, A = the cross-sectional area of a BARITT diode, a(I) = the barrier modulation parameter, a(I) = /(2 )/kTND ln(Jso/ ) J J = the maximum current density of a BARITT diode and e = the phase angle.

-100 3.8.3 Noise Sources of the Three-Terminal Punch Through Devices, Equation (3.107) is modified to express the open-circuit noise voltage between the drain and the source terminals of the Ith segment of a SIT or a GFC-BARITT device. ds = s4qvsat fJD (I) L1 - cos 2DnL sin, (3 108) l Vds2 I: s/N = - 6 (3.108) n ZV^/N. W2 aX(I)2 +,,2 = 2 e v3 s s sat where 2: \ I)' = ]j kTN'Dk (Ti ) and DS (VB/VT) dSo q Vsat -— N e(yB/ ND e DSo sa + D (VDS+ Esat iDS 3 where VB = the builIt-in poteRntial of the source channel juntion, ZWs/N = the cross-sectional area of the Ith BARITT diode, LDS - the length of the channel Since the noise voltage of the Ith segment of the device is known from Eq. (3.108), the noise voltage of the whole device can be calculated. To derive an expression for the noise figure, th-: -short-circuit noise currents of the three-terminal device must be known. The short-circuiL drain-source noise current is obtained from Eq. (3.108) as:

-101 N i7 1 = 2: iL)CT1 Vi s' (3.109) dsn ds dn I=1 n where 9ds(I) = the small signal conductance of the Ith segment. By inserting Eq. (3.108) into Eq. (3.109), then the mean square shortcircuit noise current can be explicitly expresses as in Eq. (3.110): N 1i = 2 gdsatJ(I) 1 - cos 8 n I=1 mZWs/N 2(I)2 + o2e2 s sat + |Dn L (1.(3.110) To find an expression for the gate noise current, i, only the portion of voltage variation along the channel will be couped the portion of voltage variation along the channel will be coupled through the gate capacitance, Cg, because the gate electrode of a SIT or a GFC-BARITT device, LG is normally much shorter than the channel length, LDS. To be specific, the entire shot noise will be coupled through the gate-source capacitance; however, only the (LG/LDS) fraction of diffusion noise will be coupled. In Eq. (3.108) the first term is due to shot noise and the second one is due to the diffusion noise. Following Van der Ziel's approach [46], the gate charge due to the coupling of the noise voltage of the channel is:

-102 qgs ns [qgs V' (I ) Cgs dsn, C2 IV,'2 (I) I gs dsn (3.111) or (3.112) is coupled through where V, implies that some portion of the Vds n n the gate capacitance. It is defined as L) = Vds(I) LDS I dsdf DS di ff + Vs shot (3.113) Vs is given explicitly in Eq. (3.114) below; Iv 12 (I)I dsn 4q sat J () 1 - cos e (2ZWS/N D a(I)2 + W22s L2 G-DS DS 2DnLDS (1 s sat sin e)]' (3.114) The gate current is assumed to be i = wqgs (3.115) The mean square gate noise current then becomes 1I 1 ns N I=1 1=1 w2C2 IV2 (I)1 gs dsn (3.116)

-103 where |Vs2 (I)I is given in Eq. (3.114). Finally, by inserting n Eq. (3.114) into Eq. (3.116), the mean square gate noise current expression becomes li:2- l CN -2 v ^ satf 1 - cos 8 =gs 2Z WC J (I) gsn gs wi La(I)2 + W262 12 2D +-6- ---- 1 i sin e (3.117) s sat 3.8.4 The Noise Figure and the Noise Measure. The noise figure of the device can be derived from an equivalent circuit of a SIT or a GFC-BARITT device as shown in Fig. 3.2. In Fig. 3.2 it is assumed that a SIT or a GFC-BARITT device can be represented with a noiseless intrinsic small signal model with two noise sources, ig and id Other noise sources which gsn n are neglected, are: (i) the noise due to the interface of the gate and the channel [47], [48], [51] and (ii) the generation-recombination noise which could arise from both bulk and surface effects [25], [52] through [55]. The noise figure, F, and the noise measure, M, are defined in Eq. (3.118) and Eq. (3.119), respectively. F can be defined as F = the total available output noise power (3.118) the portion of the noise power at the output due to the source alone

-104 em R - + m gm g + I I Zs )e, + Fig. 3.2 Equivalent circuit used in noise analysis.

-105 The noise figure as a figure of merit is not by itself a sufficient guide for the selection of an amplifying device. A low noise amplifier may also have a low gain and can thus defer the noise problem to a subsequent amplifier stage. Not accounting for the network gain is a shortcoming of the noise figure definition. This is overcome by introducing the M, which is defined by Haus [51] and given in Eq. (3.119) as M = F- 1 1 - 1/gain (3.119) The F expression for the common-source biasing conditions is given [26] for the equivalent circuit shown in Fig. 3.2; F = 1 + 1 s Rm + Rf + I zt gsn + IZI 12 TW TW ids n - 2 Re[ Zt cr(i Ii I 2Re [t TW Cr gsn (3ds.12 (3.120) where TW ZI Zt zt Zs R m Rf Re a 4kToaf, 4 (1 +Y Zt)/Y, Z +Rm + R f, =the impedance of the noise source, =thermal noise of the gate parasitic resistance, the thermal noise of the source parasitic resistance and = the "real part".

-106 Cr is the correlation factor and is defined as: i* i gs ds n gSn n C = - 1gs dsn and R = the input resistance which can be chosen from Eq. (3.120) in such a manner as to optimize the noise figure. The correlation coefficient Cr is obtained by assuming: N gsn = N ~I JW~~ I 1/2 (i) igSn: jCgs V- (3.121) I=1 and N (ii) idn 9gd (I)lV 1S 2 (3.122) n I=n=1 The small signal conductance 9ds(I) is a complex parameter, because of the transit effect on the drifting carriers along the channel. Under these assumptions, an expression for the correlation coefficient is obtained and given in Eq. (3.123) 2C =ds-jsy (3.123) erare I=1 If t ns) 3.8.5 The Noise Temperatures. The importance of the noise temperature of the carriers in the channel has been emphasized in [56]. The carrier temperature at high field is not equal to the lattice temperature of the semiconductor. The increase in the

-107 carrier temperature increases the noise contribution of the carriers in the drift region. The empirical expressions of the electron temperature as a function of the electric field have been given for silicon [57] and for gallium arsenide (GaAs) [58]. These expressions are given in Eq. (3.124) for silicon and in Eq. (3.125) for GaAs. One has to be cautious in using these equations as the general theoretical expressions, because these are semi-empirical expressions. For silicon: T = To[0.5(1 + /1+ 4E/Eat + (E/Esat)2] (3.124) and for GaAs Tn = T1 + 6(E/Eat)3], (3.125) where To = the room temperature. The carrier temperature expressions are electric field dependent, and in a detailed noise analysis, therefore one has to include the carrier temperature expressions into the channel noise expression. However, in this study an average carrier temperature value will be used for simplicity. Despite the fact that: (i) the above expressions are not general and are only semi-empirical, and (ii) the use of an average temperature will introduce an error into the carrier temperature value itself, one would however

-108 expect improvement for the calculations of the intrinsic noise sources with the field dependent carrier temperature over the constant carrier temperature case. Assuming an average field E = (VDS/LDs), Eq. (3.124) and Eq. (3.125) finally become: For silicon: DS 1 DS 1 T. - T 0. 51 + 1 + 4 + L E (3.126) n ~ [ k LS Esat i LDS sat and for GaAs: T = T 1 + 6 D 1 t - (3.127) n ~ L DS Esat

CHAPTER IV. DEVICE SIMULATION PROGRAM (SIM-GFC) 4.1 Introduction SIM-GFC is a program which has been developed to solve the device expressions given in Chapters II and III. It can simulate a GFC-BARITT device, SIT and a vertical FET (which is treated as a special case of a SIT device). SIM-GFC consists mainly of subroutines which are the solutions to the various analytical expressions developed earlier for the various devices. Even though it includes some numerical solutions it is an inexpensive program. SIM-GFC has four levels: (i) VF(I) is approximated for each segment directly for each gate- and the drain-source voltage in Level 1. This is the fastest and simplest level. (ii) Analytical expressions of the two-dimensional potential distribution are solved point-by-point to find VF(I) in Level 2. (iii) Level 3 includes the numerical solution of the two-dimensional Poisson's equation. A Fourier Analysis and Cyclic Reduction (FACR) algorithm is used, because it is the fastest algorithm to solve the two-dimensional Poisson's equation [16]. The effect of the space charge is neglected. (iv) Level 4 calculates the small and large signal parameters from the given dc current-voltage data. This level is useful for simulation of the performance of the SIT and GFC-BARITT devices. In all the device expressions, the forward bias voltage of the source-channel junction is the most critical parameter and the most difficult to -109

-110 obtain analytically. Therefore, if experimental data is used to obtain the forward bias voltage, accuracy of the small and large signal device parameters will be improved. In each level, SIM-GFC evaluates the dc, small signal, and large signal device parameters, and then calculates the maximum available gain, maximum frequency of operation, power output, collector efficiency, the noise figure and noise measure of the chosen device (a SIT or a GFC-BARITT device). The program handles three different types of semiconductor materials: silicon, GaAs, and InP. The details of the SIM-GFC program will be given in Section 4.2. The material parameters as a function of the doping concentration and temperature are given in Section 4.2. The results of the simualtion of the various device characteristics are presented in Section 4.3 through Section 4.7 and a comparison of the various TTPT devices is given in Section 4.8. 4.2 Program Description SIM-GFC is written to solve and evaluate all the device expressions which were derived in Chapters II and III. Some of those expressions are in analytical form and some are in numerical form. It consists of many function subroutines which make it easy to expand the program. The program has four levels. To increase the efficiency of programming, most of the subroutines are used in all four levels. Levels 1,2 and 3 have the same functions as far as device simulation is concerned. The only difference is that, in Level 1,

-111 a simple analytical expression for the forward bias voltage, VF(I), is used and the effect of the space charge is neglected. In Level 2, the two-dimensional potential distribution expression is solved for point-by-point to find VF(I) at each x and y point. In Level 3, to obtain VF(I) a numerical two-dimensional Poisson's equation solver; POT1 subroutine [16] is used. In Level 4, a practical case is considered; the device parameters are indirectly calculated from the experimentally measured dc current-voltage values and VF voltages are obtained from the known dc values. The small and large signal parameters are then obtained from the calculated VF values. The flow chart of the SIM-GFC program is shown in Fig. 4.1. A summary of the functions of the SIM-GFC program is given in Appendix B. 4.3 Material Parameters In order to simulate devices under different operating conditions, such as different impurity concentrations and temperatures, the expressions for the material properties must include the effects of those parameters. In the SIM-GFC program, the intrinsic carrier density, the energy band gap, the mobility expression, saturation velocity and the breakdown field expressions are updated for different temperatures and impurity concentrations. Some of these expressions are semi-empirical. The material parameters as a function of temperature are as follows:

-112 Calculated small and large signal circuit elements (a) Main program of SIM-GFC. Fig. 4.1 Flow Chart.

-113 EXPERM Read IDS, VGS V Mode 1 Dr (b) EXPERM subroutine. Calculate Small and Large Signal Circuit Elements 9gm gds' Cgs Cds and Cds Fig. 4.1 Flow Chart.

-114 SSIG I Calculate y-parameters of the device equivalent circuit: Y, Y, 2Y 11 12 21 22 Call Small Small Calculate 1Signal - S1 S 1., SS21 and S22 Large Determine fT, 1AG, MUG, Choose load impedance, f2' noise figure and then calculat Yi, YD noise measure efficiency, gain and power Update for doping or the voltage Update for the different frequencies Call plots RETURN / (c) SSIG subroutine. Fig. 4.1 Flow Chart.

-115 (A) Energy band gap: A semi-empirical expression is given in Eq. (4.1) for silicon, in Eq. (4.2) for GaAs and in Eq. (4.3) for InP [59]. For silicon EG(T) = 1.16- 7.02 x 10-4x T2/(T + 1108). (4.1) For GaAs EG(T) = 1.52 - 5.8 x 10-4 x T2/(T + 300). (4.2) For InP EG(T) = 1.42 - 5.8 x 10-4 T2/(T + 300). (4.3) (B) Intrinsic Carrier Density: The temperature variation of the intrinsic carrier density expressions for Si, GaAs and InP is the same [30]. Only the values of the expressions for different materials are different. For silicon 1 -EG(T)/2kT ni(T) = 1.328. 10-3. T1 5 e G 2 (4.4) For GaAs 1.5 -EG(T)/2kT ni(T) = 2.82. 10-3. T e (4.5)

-116 For InP 1.5 -EG(T)/2kT ni(T) = 7.808 ~ 10-4 ~ T1 eG(T)/k (4.6) (C) Saturation Velocity and Mobility: The temperature dependent mobility and velocity expressions are empirical [59]. Primarily the mobility of the carriers has a very complex expression and is semi-empirical. This is because the quality of the crystal, density of the defects and the amount and type of contamination are different for different growth systems. The semi-empirical expressions of the saturation velocity and the mobility as a function of temperature are given below. For silicon: The saturation velocity expression is given in Eq. (4.7): vsat = 2.4 x 107/[1 + 0.8 exp (T/600~K)]. (4.7) sat The mobility expression for electrons is given in Eq. (4.8): un(T) = 2.4n(T = 300~K)/(1 + 0.8 exp(T/600~K)). (4.8) For GaAs: The saturation velocity expression is vsat(T) = vsat(T = 300K) (T/3000K ). (4.9) S~~~~~t SBL~~~~~~(49

-117 The mobility expression is in(T) = in(T = 300~K) * (T/300~K)-1. (4.10) For InP: The saturation velocity and the mobility expressions are given in Eq. (4.11) and Eq. (4.12), respectively: Vat(T) = v (T = 300~K). (T/300~K)-1 (4.11) sat sat and ln (T) = n(T = 300~K). (T/300~K)1, (4.12) where vsat(T= 300~K) and Pn(T = 300~K) are the room temperature values of the velocity and the mobility respectively. The material parameters as a function of impurity concentration are: (A) Mobility: An empirical expression is given for Si, GaAs, and InP in Eq. (4.13). It has been reported that this expression can accurately predict the mobility as a function of the impurity concentration [60]. pn(ND) = pn(1016)/[l + (ND/T1)], (4.13) where uin(1016) means the mobility of the semiconductor with carrier concentration of 10 16cm3.

-118 (B) Breakdown Field: The breakdown electric field is obtained from the avalanche breakdown voltage expression given in [30]. The breakdown field expression is given by Eq. (4.14) which is valid for any semiconductor: E 3/4 3/8 qN 1/2 BEF 15.492 1121 D (414) Equation (4.14) includes the temperature effect on the breakdown field through the temperature variation of the energy band gap EG. 4,4 Device Physics The physics of the various devices has been investigated through a study of the potential distribution, the carrier injection and the effect of the space charge. In the following sections each subject has been analyzed in detail. The various devices considered throughout this chapter are listed in Table 4.1. The various dimensions are shown in the associated illustration. 4.4.1 The Potential Distribution. The potential distribution inside the device (a TTPT device) is calculated by the solution of the two-dimensional Poisson's equation in Level 3. The potential minimum in the vicinity of the source electrode is nonuniform across the device thickness as shown in Fig. 4.2. The effect of the gate voltage and its polarity on the potential minimum, VF, is shown in Fig. 4.2(a)-(b). The two-dimensional Poisson's equation is solved numerically by using this fast Poisson's equation solver, POT1. There is, however, a limitation on the polarity of the gate voltage for the junction-gate and the ohmic-gate type devices. The

ND Symbol Device (cm-3) List Z LDS (cm) (Pm) Table 4.1 of the Devices LG WGS WS (pm)(jm) (pm) WG Ds Tox (pm) (pm) (pm) Type of Device Material S1 SIT B1 GFC-B S2 SIT B2 GFC-B B3 GFC-B S3 SIT S4 SIT S5 SIT B4 GFC-B S6 SIT S7 SIT S8 SIT 1015 1 4 1014 1015 51015 5x1015 5x1015 5xlO15 1014 2x1015 5x1016 101' 13.92 13.92 13.92 13.92 13.92 13.92 13.92 13.92 0.2085 0.187 13.92 13.92 5 2 1.3 20 2 2.3 20 2 2.3 5 2 1.3 5 2 0.3 5 2 2.3 5 2 2.3 5 2 2.3 20 10 0.5 12 2 4.0 5 2 0.2 20 2 0.1 3 4 0.6 — vertical 3 -- -- 0.1 vertical 3 0 0.6 -- vertical 3 -- -- 0.1 vertical 3 -- 0.1 vertical 3 4 0.6 -- vertical 3 4 0.6 -- vertical 3 4 0.6 - vertical 0.5 - - 0. 1 lateral 4.0 - _- - - vertical 1.0 4.0 0.6 vertical 0.5 4.0 0.6 vertical Si Si Si Si Si Si GaAs InP Si GaAs GaAs Si I __J ___m tO I

-120 Table 4.1 (cont.) 0 s-)

-121 to SAm TnV 2sX X 33JB 410D (a) Small negative gate voltage, VGS. Fig. 4.2 The Potential Distribution.

-122 33A 4Ua 9aI fl7A I Zi x 33,U 4UB (b) Large negative VGS. Fig. 4.2 The Potential Distribution.

-123 T72 2O A x (c) Small positive VGS' Fig. 4.2: The Potential Distribution.

-124-:1) am.04UB 4. SB na 2 as X 33aD 4LO (d) Large positive VGS. Fig. 4.2: The Potential Distribution.

-125 gate voltage should have a polarity which prevents a current flow through the gate in the case of the non-insulated gate devices. On the other hand, if the gate is insulated, the gate voltage can be used either to reduce or to increase the potential barrier at the vicinity of the source as illustrated in Fig. 4.2. In Fig. 4.2(b), the gate voltage increases the barrier height; Fig. 4.2(c)-(d) illustrate the barrier reduction effect of''the gate voltage in'the case of the insulated devices. In the solution of the two-dimensional Poisson's equation, the effect of the injected carriers is neglected. That is why Fig. 4.2(c) and Fig. 4.2(d) show a negative barrier height indicating that the forward bias voltage is larger than the built-in potential VB of the source-channel junction. This is physically impossible, because there is always an induced barrier height present due to the injected carriers which prevents the formation of a negative barrier height. Figure 4.2(c) and (d) indicate that it is possible to reduce the barrier height through an applied gate voltage, even under the punch-through condition.. The non-uniformity of the barrier height across the device thickness is common to all cases: positive or negative applied gate voltages. The potential distributions in Fig. 4.2 are given for the vertical double-gate devices. The effect of the gate voltage on the built-in potential becomes insignificant, if the gates are placed far from the source electrode. Another ineffective gate control structure is the one with a surface gate as shown in Fig. 4.3.

-126 Si02 G G G G G S S S / S S LW k I IM 3 I A I L I S~~~~~~ ~L K'~~ iiS~.-~ - D Fig. 4.3 A Multi-Channel Surface Gate (Insulator or Schottky) TTPT Devi ce.

-127 If a shallow n source structure is used, such a structure may be used in power applications of the TTPT devices. To achieve a high blocking gain, a planar structure with a self-aligned gate-source must be used, such as the one shown in Fig. 1.1. Blocking gain, gBs is defined as the ratio of VDS and the gate voltage, VGS, which turns off the device. VDS gB VGS I DSo 4.4.2 The Injected Carrier Distribution. The carrier distribution in the punch-through devices has been assumed to be uniform [1], [3]. In BARITT diodes, McCleer [11] has shown the importance of the diffusion effect. In any type of injection device the carrier diffusion effect in the vicinity of the injecting junction limits the carrier transport. The diffusion effect is important even for majority carrier injection type devices such as SITs because of the carrier storage effect. The diffusion of the carriers becomes insignificant if the transport of the carriers is limited by the drift mechanism. This means that there is no barrier against the carrier inection (in the case of ohmic contacts), if the carrier transport is limited by the drift mechanism. The effect of the diffusion varies for different semiconductors. This can be analyzed by considering the current continuity requirement. The diffusion current at the injection point is equal to the drift current beyond the carrier velocity saturation point. Then the current continuity requires that D inj = qsats (415) qDn LEF qsatns,

-128 where LEF is the effective diffusion length, ninj is the density of the injected carriers at the injection point, nsat is the density of the carriers beyond the velocity saturation point, and vsat is the sat saturation velocity of the carriers. After rearranging Eq. (4.15), nsat can be obtained: (Dn/vsat) sat ninj L EF in Eq. (4.16), LEF can only be larger than or equal to (Dn/vsat) Lef is determined by the field distribution in the device which can be assumed as material independent. From the analysis of Eq. (4.16), it can be conlcuded that in semiconductors with high diffusion coefficients (high low field mobility) and low saturation velocity, the drift is the limiting mechanism. Thus the drift approximation can be used to describe the current transport in high mobility semiconductor TTPT devices, such as GaAs and In1 xGa As/InP. The diffusion is more important in low mobility semiconductors such as silicon. Therefore, the drift-diffusion approximation must be used to describe the current transport of silicon TTPT devices. The carrier distribution for a Si device shown in Fig. 4.4(a), for an InP device in Fig. 4.4(b) and for a GaAs device in Fig. 4.4(c). All the devices are GFC-BARITT devices of the same size and for the same bias voltage. The analysis of the carrier distributions confirms the conclusions which resulted from consideration of Eq. (4.16). The ninj/nsat ratio for each device is different. It is highest for the silicon device and lowest for the GaAs device. This means that the carrier distribution in the Si device is highly nonuniform

-129 0 O CO (M 0.30 X(C l) (X104) 0.40 (a) Si device. Fig. 4.4 Carrier Distribution as a Function of Distance at the Different Points Across the Channel, y and Distance Along the Conduction Path, X. The Reality Scales are 1014 for Carrier Density and 10-4 for x.

-130 O (C (N C. 0 o4 - -- U.UU U.08 0.i6 0.24 0.32 0.4C );(cM) (XIO4) (b) InP device. Fig. 4.4 Carrier Distribution as a Function of Distance at the Different Points Across the Channel, y and Distance Along the Conducting Path, x. The Real Scales Are 1014 for Carrier Density and 10-4 for x.

-131 0 0 c) Go y=o (substrate) 0. H C) flo 0 Ld.H cr (O y=W 0 S ~.OO 0.02 0.04 0.06 0.08 0o.10 XICM) (X)104) (c) GaAs device. Fig. 4.4 Carrier Distribution as a Function of Distance at the Different Points Across the Channel, y and Distance Along the Conduction Path, x. The Real Scales are 106 for Carrier Density and 104 for x.

-132 due to the diffusion effect. On the other hand, in the GaAs device, the carrier distribution is uniform beyond a very short low field region. The distance at which carrier velocity saturates, is shorter in the GaAs devices than the Si devices due to the low electric field requirement to saturate the velocity of the carriers. The InP device falls between the Si and the GaAs devices as would be expected. The same results have been confirmed for the SIT devices. Therefore, the conclusions which are given for GFC-BARITT devices can be generalized for all the TTPT devices. One additional conclusion can be drawn from the analysis of Fig. 4.4. Besides the (ninj/nsat) ratios, the injection level is also different for each semiconductor device. Since all the devices have the same size and bias voltages, a comparison of the n.nj in Si, InP and GaAs devices is justified. The density of the injected carriers ninj is lowest for the GaAs devices and highest for the Si devices. The reason for the different n.nj is the difference in the built-in potentials due to the different energy band gaps (EG) of the semiconductor at y. GaAs has the highest built-in potential because it has the highest EG (1.43 eV). The barrier height in the majority carrier injection type devices (SITs) is formed by the low and high carrier concentrations and the gate induced potential barrier. The carrier injection in SIT devices will not be affected by the energy band gap of the semiconductors. It is typically a minority carrier injection device property.

-133 4.4.3 The Space-Charge Effect. The space-charge effect on the device characteristics has been investigated in Level 4 of the SIM-GFC program. It is an indirect approach to a complicated problem. Physically, the injected carriers will induce a barrier against the carrier injection. The "injected carrier induced-barrier" becomes significant when the density of the injected carriers is equal to or larger than the ionized impurity concentration of the channel. Therefore, it is expected that at high injection conditions, the rate of injection will slow down. This translates to a forward bias voltage (VF) variation with respect to the drain-source Voltage, VDS. The forward bias voltage, VF, must vary slowly with an increase in VDS at high level injection condition. From the source current, IDS, and voltage, VDS, data in Level 4 of the SIM-GFC program the corresponding VF value for each given IDS and VDS values has been determined and plotted. The VF as a function of VDS for a SIT reported in Reference [24] is shown in Fig. 4.5. Figure 4.5 illustrates the space-charge effect on the VF variation as a function of VDS. It is clear that the increase in VF with VDS slows down at high VDS values or high current values. If the effect of the injected carriers is negligible, VF must increase linearly with the increase in VDS. This phenomenon has been observed in GFC-BARITT devices also. It can be concluded that the injected carriers slow down the further injection. This effect manifests itself in the VF variation as a function of VDS. The effect of the injected carriers is

0 o Ta t' i-6.00 moo —-am I 0.00 202 400 60.00 VDS(VOLTS) Fig. 4.5: VF Variation as a Function of VDS at Different Gate Voltages (Device S2).

-135 strongly dependent on the distribution of these carriers. For instance, if the injected carriers are stored in the vicinity of the injection junction, the effect of the space-charge limitation (injected carrier effect on the injection) will become significant at relatively low injection levels. This means that the space charge limitation becomes effective at high current levels for semiconductors with high diffusion coefficients such as GaxIn xAs GaAs and InP. 4.5 Dc Characteristics In this section, the effects of the doping concentration, temperature and the device geometry on the device characteristics have been investigated. The same size SIT and GFC-BARITT devices have been studied to understand the similarities and the differences between these two devices. 4.5.1 The Impurity Concentration Effect. SIT and GFC-BARITT devices with the same size and biasing have been studied. The active region doping is increased with equal increments. For each substrate doping level, the dc I-V characteristics and small-signal device parameters have been calculated and the results are plotted as a function of the doping concentration. The current plots for a SIT in Fig. 4.6 and for a GFC-BARITT device in Fig. 4.7 are shown. The gate voltage, VGS was kept fixed, but VDS was varied for each doping level. VDS is composed of the punch-through voltage of-the LDS long channel, VpT, andia fixed incremental voltage, AVDs. VpT varies with the doping concentration. However, AVDs and the size are held constant.

-136 Q H 0. 9 1.7 2.5 3,3 4,1 4.9 Channel Doping (1014 cm-3) Fig. 4.6 Dc Current of a SIT as a Function of the Channel Doping Concentration (Device S2).

-137 2.9 3.9 4.9 Channel Doping (1014 cmM3) Fig. 4.7 Dc Current of a GFC-BARITT Device as a Function of the Channel Doping Concentration (Device B1).

-138 The analysis of Fig. 4.6 indicates that the current, IDS of a SIT increases with an increase in the doping concentration. The rate of increase in IDS is not however, only due to the increase is the number of majority carriers in the channel. It is rather due to a combination of two factors: (a) direct increase in the density of the major carriers with the channel doping and (b) increase in VDS due to VpT increase. If the first effect were dominant, IDS would increase linearly with the doping concentration. Figure 4.6 shows an exponential growth of IDS with the doping. It is a typical current increase with the increase in VDS. Therefore, the second effect, VDS increase, is the main source of the current growth shown in Fig. 4.6. The dc current of a GFC-BARITT device, on the other hand, decreases with an increase in the channel doping as seen in Fig. 4.7. Two main factors contributing to the current decay are: (as the reduction in forward bias voltage VF and (b) the decrease in the number of the minority carriers in the channel, with the increasing doping concentration. Even though the drain source voltage VDS increases with the increasing VpT, the increase in the flat band voltage, VFB, is much larger than the increase in VDS. VF is proportional to the (VFB/VDs)2/4VFBe Therefore, an increase in VFB will reduce VF. The second contributor to minority carrier density, npo, is np = n2/(channel doping) Ppo I "

-139 Since the intrinsic density, ni, is fixed, an increase in the channel doping decreases npo in the channel. The current IDS increases with the number of the injected minority carrier density n where [VF-~G]/VT "p = "po e A low injection due to low VF and npo results in a low current. Figure 4.7 shows an exponential decrease in current, IDS, with increasing doping concentration, which implies that the reduction in VF is the main cause of this rapid IDS decrease. The effect of the channel doping concentration on the drain-source current, IDS, is different for SIT and GFC-BARITT devices. The IDS of a SIT increases with an increase in the channel doping concentration. The IDS increase in a SIT device is expected to be linear with the doping concentration for a fixed VDS. The IDsof a GFC-BARITT device, on the other hand, decreases exponentially with the doping concentration which is mainly due to the decrease of the forward biasing voltage, VF. 4.5.2 Temperature Effect. The performance of power devices at high temperature is important, especially for device reliability. If any device has a positive temperature coefficient, the device current will increase with the increasing temperature, and finally, a thermal runaway will occur. Thermal runaway will result in the destruction of the device. In Section 4.3, the temperature-dependent material parameters, were given and have been implemented into the SIM-GFC program.

-140 The temperature effect on the device characteristics analyzed in this section is valid for low level injection. In Fig. 4.8(a) and Fig. 4.8(b), the temperature effect on IDS of a SIT device is shown for T = 300~K and T = 400~K. The device size and the bias have been chosen in such a way that a SIT device operates in a mixed mode as a FET at low gate biases, VGS, and as a SIT at high VGS. The comparison of Fig. 4.8(a) and Fig. 4.8(b) indicates that the SIT mode at low level injection has a positive temperature coefficient, and the FET mode is less temperature sensitive, (has a smaller positive temperature coefficient). In Fig. 4.9, a GFC-BARITT device IDS at 400'~K temperature is shown. In Fig. 4.7, the same size GFC-BARITT device IDS at 300~K temperature was given. A comparison of the two figures reveals that the GFC-BARITT device has a positive temperature coefficient. The IDS at 400~K is almost two hundred times that of IDS at 300~K. The IDS increase with the temperature increase in larger in GFC-BARITT devices than in SIT devices. The injected carrier density as a function of temperature for a GFC-BARITT device is given in Eq. 4.18 and for a SIT device in Eq. 4.19. The intrinsic carrier density is given by ni(T) = noT15 exp[-EG(T)/2kT], (4.17) where n is a constant and is different for various semiconductors, o and T is the temperature in degrees Kelvin. The injected carrier density for a GFC-BARITT device is

-141 cU co H YOFF- 4045.724E-10 X1FFa 2.15243816 co.V = -2.0 V GS -3.00 -4.00 -. f -., gL y ^ i -10.00 _wo~0 o D30.00VO 50.L o VDS(VOLTS) 70,00 90.00 (a) I-V Characteristics at T = 300~K. Fig. 4.8 The Current Voltage Characteristics of a SIT Operating in FET and Injection (SIT) Modes (Device S1).

-142 (b) I-V Characteristics at T = 400~K. Fig. 4.8 The Current Voltage Characteristics of a SIT Operating in FET and Injection (SIT) Modes (Device Si).

-143 CT 5) H H 0.9 1.9 Channel 2.9 3.9 4.9 Doping (1014 cm-3) 5.9 Fig. 4.9 A GFC-BARITT Device Current as a function of the Channel Doping at T = 400~K (Device B1 Compared to Fig. 4.7 at T = 300~K).

-144 ninj(T) = (n2(T)/ND) exp[(VF - G)/kT] (4.18) and for a SIT device, ninj(T) = ND exp[(VF - G)/kT (4.9) At low level injection, both the minority and majority carriers density increase with temperature. In Eq. (4.17), the n.(T) is strongly temperature dependent. The n nj in Eq. (4.18) includes the square of n.(T), therefore the n.nj in GFC-BARITT device is even more strongly temperature dependent. In Eq. (4.19), the ninj increases with temperature, if the (VF - fG) is negative. When the (VF- lG) becomes positive, the ninj will decrease with increasing temperature. The ninj in Eq. (4.18), however, starts to decrease at much higher temperature for a positive (VF - <G). It can be concluded that the TTPT devices have a positive temperature coefficient at low level injection, and a negative temperature coefficient at medium and high level injection. 4.5.3 The Geometry Effect. The geometry of the device affects its performance. The most critical element of the device geometry is the spacing, WGS, between the source and the gate. It is essential to place the gate close to the carrier injection point near the source. If the gate if far from the injection point, the gate voltage cannot perturb the barrier height so as to modulate IDS.

-145 It is shown in Fig. 4.10(a) for a GFC-BARITT device with a WGS of 1.3 pm and in Fig. 4.10(b) for a device with a WGS of 0.3 Pm. A comparison of Fig. 4.10(a) and Fig. 4.10(b) indicates that an increase in WGS diminishes the gate voltage control over IDS. As seen in Fig. 4.10(a), an increasing gate voltage does not affect IDS as much because WGS is larger. On the other hand, in Fig. 4.10(a), IDS is controlled with a small gate voltage due to the small WGS (0.3 pm). The effect of WGS on a SIT device is different from that of a GFCBARITT device. If WGS becomes too large, A GFC-BARITT device will operate like a BARITT diode (a two-terminal device) but in the case of a SIT device, it is always a three terminal device, except the mode of its operation changes from carrier injection to ohmic conduction type. In other words, a SIT device with a large WGS will operate as a FET. A SIT device will operate under various conditions such as large channel thickness, Ws and heavy channel doping. A SIT device operation as a FET is demonstrated in Fig. 4.11. The simple FET model as SIM-GFC conceptually predicts the device characteristics such as the negative resistance of the I-V characteristics of the III-V compound semiconductor FETs. The I-V characteristics of the same size Si FET in Fig. 4.11(a), GaAs FET in Fig. 4.11(b) and InP FET in Fig. 4.11(c) are shown. The importance of the high low-field mobility becomes apparent from the comparison of the I-V characteristics. At low bias, VDS, voltage, the GaAs FET has the highest current, IDS, and transconductance, gm. At high VDS, however, the InP FET performance is the best due to its high peak and high

-146 a a (0 0 H 0 9. 5 VDS (Volts) (a) The I-V Characteristics with 1.3 pm WJGS Spacing (Device B2). Fig. 4.10 The Gate-Source Spacing, WIGS Effect on the I-V Characteristices of a GFC-BARITT Device.

-147 12,5 17.5 22.5 27.5 32.5 37.5 VDS (Volts) (b) The I-V Characteristics with 0.3 pm WGS Spacing (Device B3). Fig. 4.10 The Gate-Source Spacing, WGS9 Effect on the I-V Characteristics of a GFC-BARITT Device.

-1480 0 0 aa Si.Devi e-1.O -2.10 -3.00 0 / /' -4.00 0 0.4 2.4 4.4 6.4 8.4 10.4 VDS (Volts) (a) Si Device, S3. Fig. 4.11 The I-V Characteristics of the Vertical FETs.

-149 3.7 5.7 VDS (Volts) (b) GaAs device, S4. Fig. 4.11 The I-V Characteristics of the Vertical FETs.

-150 7.7 11.7 15.7 19.7 VDS (Volts) (c) InP device, S4. Fig. 4.11 The I-V Characteristics of the Vertical FETs.

-151 saturation velocity. A GaAs FET saturates at low bias voltages and its peak carrier velocity is lower than that of the InP FET. The I-V characteristics of the GaAs, InP and Si SIT devices (in SIT device mode) has also been studied. The performance of these three devices is not signficantly different from one another. It can be concluded that WGS is the most critical geometrical parameter which determines the mode of the device operation. For large WGS, a GFC-BARITT device operates as a FET. The III-V compound semiconductor punch-through devices are not significantly advantageous over silicon devices. The real advantages of these semiconductors over silicon becomes significant for the non-punch-through devices which utilize the low field mobility such as FETs. 4.5.4 Dc and Small-Signal Device Parameters. Dc and smallsignal device parameters, IDS, gm' gds' Cgs Cgd and Cds have been calculated to describe the small-signal equivalent circuit of the TTPT devices and FETs. The dc I-V characteristics of the TTPT devices and FETs have been analyzed under various operating conditions in the preceding sections. The IDS of a TTPT device increases exponentially with a VDS increase, but the IDS of a FET saturates at high VDS voltages. The VDS where IDS saturates is the highest for an INp FET in comparison with GaAs and Si FETs. The III-V compound semiconductor FETs show a common negative dc resistance effect in their I-V characteristics.

The small-signal device parameters of the TTPT devices increase also exponentially with the dc drain-source voltage with the exception of Cds. The effect of the stored charge in the channel due to the injected carriers are included in the calculation of the gate-source, Cgs and drain-gate, Cdg, capacitances. In the insulated gate TTPT devices, Cg, is a series combination of the insulated gate capacitance and the channel capacitance. The total source-gate capacitance Cs of an insulated gate TTPT GFC-BARITT device is smaller than the C of an ohmic or Schottky gate TTPT gs device. On the other hand, the blocking gain (VDs/VGs) of a GFCBARITT device is smaller than the blocking gain of the other TTPT devices (SITs and lateral punch-through transistors). The reason for the low blocking gain of a GFC-BARITT device is due to the voltage division between the insulated gate capacitance and the channel capacitance. The small-signal device parameters of a GFC-BARITT device are given in Fig. 4.12 as a function of the dc bias voltages, VD and VWS. As shown in Fig. 4.12, the increase in VDS increases gm' gds' Cgs and Cdg exponentially. However, an increase in VGS, decreases these parameters. The small-signal parameters of the other TTPT devices are not shown because their variations as a function of VDS and VGS are similar to the plots shown in Fig. 4.12(a) through 4.12(d). III-V compound semiconductor TTPT devices do not show any more interesting characteristics.than those for silicon.

-153 f2.5 17.5 22.5 27.5 32.5 37.5 VDS (Volts) (a) The transconductance. Fig. 4.12 Small-Signal Parameters of a GFC-BARITT Device as a Function of VDS for Different Values of VGS (Device B2).

-154 5 VDS (Volts) (b) The conductance. Fig. 4.12 Small-Signal Parameters of a, GFC-BARITT Device as a Function of VDS for Different Values of VGS (Device B2).

-155 5 15 2 2 12.5 17.5 22.5 27.5 32(5 37.5 VDS (Volts) (c) The gate-source capacitance. Fig. 4.12 Small-Signal Parameters of a GFC-BARITT Device as a Function of VDS for Different Values of VGS (Device B2).

-156 C3" -o 0 Uco DS GS I G - 12.5 17.5 22.5 27.5 32.5 37.5 VDS (Volts) (d) The gate-drain feedback capacitance. Fig. 4.12 Small-Signal Parameters of a GFC-BARITT Device as a Function of VDS for Different Values of VGS (Device B2).

-157 The small-signal device characteristics of a SI FET are shown in Fig. 4.13(a) through 4.13(d). The transconductance and conductance of the III-V compound semiconductor FETs show the effect of the dc negative resistance as seen in Fig. 4.14(a) and Fig. 4.14(b). In Fig. 4.13(a) and Fig. 4.14(a), the transconductances follow the dc current variation as a function of VDS and VGS. The conductance of an FET decreases with increasing bias voltages VDS, and VGS as shown in Fig. 4.13(b) and Fig. 4.14(b). In Fig. 4.14(b) the conductance, g.d, increases from the +3 volt point to +4 point due to the dc negative resistance effect. Beyond the bias voltage where the current, IDS, saturates, the gds decreases rapidly. In Fig. 4.13(c) through (d) and 4.14(c) through (d), the capacitances decrease with increasing VDS and VGS, because these capacitances, Cgs and Cdg are the parallel plate capacitances of the depletion regions. From the analysis of the dc current and small signal device characteristics of the various TTPT devices and FETs it can be concluded that using III-V compound semiconductors to fabricate SIT or majority carrier injection type GFC-BARITT devices is not as advantageous as silicon. The current ratio of a III-V compound semiconductor SIT and a Si SIT (RIDS) is approximately equal to the ratio of their saturation velocities (RVsat): vsat of III-V compound semiconductor vsat of silicon Vsat

-158 0.4 2.4 4.4 5.4 7.4 9.4 VDS (Volts) (a) The transconductance. Fig. 4.13 The Small-Signal Equivalent Circuit Parameters of a Silicon FET, S3.

-159 0.4 1.4 3.4 5.4 VDS (Volts) 7.4 9.4 (b) The conductance. Fig. 4.13 The Small-Signal Equivalent Circuit Parameters of a Silicon FET, S3.

-160 -0 Tfo 0 c vC -_ 2.0 6.0 10.0 14.0 18.0 22.0 V Volts) DS (c) The gate-source capacitance. Fig. 4.13 The Small-Signal Equivalent Circuit Parameters of a Silicon FET, S3.

-161 Ui C] 0 0 04 do To or3 ia CO a (0 I40 I In o - N 0 = 0.0 V -2.0 6.0 10.0 14.0 VDS (Volts) 18.0 22.0 (d) The gate-drain capacitance. Fig. 4.13 The Small-Signal Equivalent Circuit Parameters of a Silicon FET, S3.

-162 1.7 3.7 5.7 VDS (Volts) (a) The transconductance. Fig. 4.14 The Small-Signal Equivalent Circuit Parameters of a GaAs FET, S4.

-163 8.9 12.9 16.9 20.9 VDS t(Volts) (b) The conductance. Fig. 4.14 The Small-Signal Equivalent Circuit Parameters of a GaAs FET, S4.

-164 0.9 4.9 8.9 12.9 16.9 20.9 VDS (Volts) (c) The gate-source capacitance. Fig. 4.14 The Small-Signal Equivalent Circuit Parameters of a GaAs FET, S4.

-165 0C) 0 d- I -Vs (:olts) -2. 0 GaAs ET, S4.-3 0 -4. 0 In 0.9 4.9 8.9 12.9 16.9 20.9 V (Volts) (d) The gate-drain capacitance. Fig. 4.14 The Small-Signal Equivalent Circuit Parameters of a GaAs FET, S4.

-166 The same RIDS figure of merit to select a material for a SIT device is not valid for the GFC-BARITT or the minority carrier injection type punch-through devices. The carrier injection in silicon GFC-BARITT devices is higher than in those of the III-V compound semiconductor devices. In other words, the critical factor in GFC-BARITT devices is the injection of the carriers and not the drift of those carriers as in the case of the majority carrier devices. The GaAs and InP GFC-BARITT devices can be used to achieve high power and frequency operations. Also, these devices can operate at high temperatures due to their high energy band gaps. The biggest advantage of using a III-V compound semiconductor over silicon is to fabricate FETs. This can be seen from the comparison of the small signal parameters of the Si and GaAs FETs in Fig. 4.13 and Fig. 4.14, respectively. The Cs for a Si and a GaAs FET is the same but the gm of a GaAs FET is almost 2.2 times higher than the gm of a Si FET which results in the higher frequency operation of the GaAs FETs. 4.6 Small-Signal Performance The small-signal circuit performance of the SIT and GFC-BARITT devices have been investigated as a function of the dc bias voltage. VDS, the channel doping concentration and the frequency. The small-signal circuit performance of the TTPT devices is evaluated in terms of the cut-off frequency, maximum available gain, maximum unilateral gain, noise figure, noise measure and the 360 degree phase frequency.

-167 4.6.1 GFC-BARITT Devices. The performance of a GFC-BARITT device improves as a function of the dc bias, VDS. The maximum available gain, the maximum unilateral gain and the cut-off frequency increase with VDS. The small-signal transconductance increases exponentially with VDS and this improves the gain and the cut-off frequency. The 360-degree phase frequency is inversely proportional to the transit time. The transit time decreases with increasing VDS. As a result, the 360-degree phase frequency also increases with VDS. The noise figur an t ae and the noise measure decrease with VDS The noise measure is not only a function of the noise figure, but it is also a function of the gain. Even if the noise figure is small, the noise measure increases with decreasing gain. It reaches its limiting value of the noise figure minus one (F-l) at high gain. The performance of a GFC-BARITT device does not improve indefinitely as a function of VDS, due to the space charge limitation which occurs at high bias voltages. In Fig. 4.15, the gain, the noise figure and the noise measure are shown as a function of both the operating frequency (0.1-0.6 GHz) and the dc bias, VDS. The cut-off and 360-degree phase frequencies are also shown as a function of VDS. The smallsignal characteristics were calculated using values of VF which were calculated from the measured dc I-V characteristics of a Si GFCBARITT device which was fabricated in this laboratory. The increase in the operating frequency decreases the gain and the noise figure but increases the noise measure. The noise figure increases slowly with VDS, because the noise temperature increases with the electric

-168 3.8 3.6 3.4 f2,7 (GHz) 3.2 3.0 2.8~. -- 20.0 22.0 24.0 26.0 28.0 30.0 VDS (Volts) (a) 360-degree phase angle frequency, f2.' Fig. 4.15 The Small-Signal Performance of a Si GFC-BARITT Device, B4, as a Function of VDS. (VGS = 0 V)

-169 L3- y / 0 27 -3 20 22 24 26 28 30 VDS (Volts) (b) The maximum unilateral gain. Fig. 4.15 The Small-Signal Performance of a Si GFC-BARITT Device, B4, as a Function of VDS (VGS = 0 V)

-170 22 17 0.2 12 0.3/ ~CE ~~~~~0. -2 -3 20 22 24 26 28 30 VDS (Volts) (c) The,aximum available gain. Fig. 4.15 The Small-Signal Performance of a Si GFC-BARITT Device, B4, as a Function of VDS at Different Frequencies. (VGs = 0 V)

-171 10.5 8.5 6.5 N LL 4- 4.5 c) 2.5 0.5 20 22 24 26 VD (Volts) DS 28 30 (d) The cut-off frequency, fT. Fig. 4.15 The Small-Signal Performance of a Si GFC-BARITT Device, B4, as a Function of VDS. (VG = 0 V)

-172 3. 1 3.06 f = 0.1 GHz ]|~0 2.982 0.3 0.4 0.5 2.94 2.94 2.90. i 20 22 24 26 28 30 VDS (Volts) (e) The noise figure. Fig. 4.15 The Small-Signal Performance of a Si GFC-BARITT Device, B4, as a Function of VDS at Different Frequencies. (VG = 0 V)

-173 20 "16 * / 0.4 0.3 0.2 I \,,I0. 12 S.4 20 22 24 26 28 30 DS (Volts) (f) The Noise Measdre. Fig. 4.15 The Small-Signal performance of a Si QFC-BARITT Device, B4, as a Function of VDS at Different Frequencies. (VGs = 0 V.)

-174 field which is also directly proportional to VDS. The noise measure in Fig. 4.15(f) decreases with VDS due to the higher maximum available gain (MAG) at high VDS values. The 360-degree phase frequency is a useful figure of merit to point out the significance of the transit time effect. The cut-off frequency is defined as the frequency at which the current gain becomes unity. It becomes a useful figure of merit for the devices if the transit time is small. It is important to determine the 360-degree phase frequency in addition to the cut-off frequency of high power, high frequency devices. If the 360-degree phase frequency (f2 ) is larger than the conventional cut-off frequency (fT), the effect of the transit time on the device characteristics may be neglected. If, however, the f2 is smaller than or equal to fT, the negligence of the transit time effect may result in an overestimation of the device performance. The effect of the transit time on gm and gds has been neglected and the calculated small-signal gain noise figure and measure are shown in Fig. 4.15. The same device characteristics have been calculated by inclusion of the transit time effect and the new results are seen in Fig. 4.16. The transit time lowers the cut-off frequency, fT, but its effect on the maximum available gain, MAG, is small, because the transit time effect is cancelled in the MAG expression Iy 12 ~MAG = 21' MAG = 4 Real(y ) Real(y ) 11 22 The y includes e-j'Td through gm. The y includes e-JWTd through gd5 21 m 22

-175 20 16 f = O.1 GHz 12 0.2 0.3.4 0.5 0.6 40 42 44 46 48 50 VDS (Volts) (a) The MAG. Fig. 4.16 The Transit-Time Effect on the Small-Signal Device Performance of Device B4. (VGS = 0 V.)

-176 4. 39 V.' YOFF= 2029.5750E+02 ~0.5 XOFF= 40. 0o.6U T 3. 1 44- 1.7 (C) 0.9 0.1 40 42 44 46 48 50 VDS (Volts) (b) The cut-off frequency, fT' Fig. 4.16 The Transit-Time Effect on the Small-Signal Device Performance of Device B4. (VGs = 0 V.)

-177 The effect of the channel doping concentration on the performance of the devices is shown in Fig. 4.17. The f2 increases with increasing channel doping concentration because the size of the device is fixed. Increasing the impurity concentration increases the electric field in the depleted channel and, as a result, the transit time decreases. The maximum available gain (MAG) and the maximum unilateral gain (MUG) decrease with the impurity concentration. On the other hand, the noise measure, M, increases with ND. The rise in M is due to the degradation of MAG at high impurity concentrations, and not due to a rise of the noise figure. In Fig. 4.17(d), fT decreases with ND unlike that of f2. In this case, the upper frequency limit of the device is determined by the unity current gain because the transit time effect is negligible. 4.6.2 SIT Devices. The f2, MAG, MUG, fT, noise figure and the noise measure are shown in Fig. 4.18 as a function of the dc bias, VDS. An analysis of Fig. 4.18 indicates that f2 increases with VDS up to 30 V. For.VDs in excess of 30 V, f2 degrades due to the electric field dependence of the GaAs carrier velocity. The MAG, MUG and fT increase, with VDS as in the case of the GFC-BARITT device. The noise figure and noise measure decrease with VDS. The frequency dependence of these parameters follow the pattern of the GFC-BARITT devices given in Section 4.6.1. As can be seen from Figs. 4.17(a) and 4.18(a), the f2 of Si SIT devices does not vary in the same manner as f2 for GaAs devices. 2qT

4.2 4.1 4.0 N 4- 3.9 3.8 3.7 0.9 1.7 2.5 3.3 4.1 4.9 ND (1014 cm-3) (a) The 360-degree phase frequency, f2. Fig. 4.17 The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel Doping. (VGS = 2.0 V.)

-179 34 26 18 f = 0.1 GHz 0.4/ 00.0 0.9 1.7 2.5 3.3 4.1 4.9 ND (1014 cm-3) (b) The MUG. Fig. 4.17 The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel Doping at Different Frequencies.

-180 44 34 24 c(3 CD E 14 4 -6. f = 0.1 GHz 0. 0. 0.9 1.7 2.5 3.3 ND (1014 cm-3) 4.1 4.9 (c) The MAG. Fig. 4.17 The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel Doping at Different Frequencies.

-181 100 80 60 N LL40 4- - 0 2 20 0.9 1.7 2.5 3.3 4.1 4.9 ND (1014 cm-3) (d) The cut-off frequency. Fig. 4.17 The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel Doping. (VGS = -2.0 V and VDS AVDs + VpT.)

-182 7.0 6.0 a 5.0 w UcI) * 4.0 3.0 3.0 2.0 I 0.9 1.7 2.5 3.3 ND (1014 cm-3) 4.1 4.9 (e) The noise figure. Fig. 4.17 The Small-Signal Performance of aGFC-BARITT Device, B1, as a Function of the Channel Doping.

-183 16 12 8 ca -O w 4 0 r0 z 0 -4 0.9 1.7 2.5 3.3 ND (1014 cm-3) 4.1 4.9 (f) The noise measure. Fig. 4.17 The Small-Signal Performance of a GFC-BARITT Device, B1, as a Function of Channel Doping at Different Frequencies.

-184 6.2 5.4 4.6 3.8 4- 3.0 2.2 10 30 50 70 90 110 V (Volts) DS (a) The f21. Fig. 4.18 The Small-Signal Performance of a GaAs SIT, S6 as a Function of VDS. (VGS = 0 V)

-185 54 46 0.2 0.3 38 0.4 0.5 0.6 2 30 22 14 10 30 50 70 90 110 VDS (Volts) (b) The MUG. Fig. 4.18 The Small-Signal Performance of a GaAs SIT, S6. (VG = 0 V)

-186 54 46 38 30 -0, 22:1 14 10 30 50 70 V (Volts) DS 90 110 (c) The MAG. Fig. 4.18 The Small-Signal Performance of a GaAs SIT, S6. (VG= 0 V,)

-187 1008 808 N I 5 608 oJ 44-P 3 408 208 8.0 10 30 50 VDS (Volts) 70 90 110 (d) The fTFig. 4.18 The Small-Signal Performance of a GaAs SIT, S6. (VGs = 0 V)

-188 3.0 2.996 9 QQO L.37 L. -\\ \ - a ),' 2.988, 2.986 2.980, 10 30 50 70 90 110 VDS (Volts) (e) The Noise Figure. Fig. 4.18 The Small-Signal Performance of a GaAs SIT, S6. (VG= GS 0 v)

-189 0.15 0.10 0.05' 0.' ar S.Z 0.00 a) (A) *r0 0.05 0.10 10 30 50 70 VDS (Volts) 90 110 (f) The Noise Measure. Fig. 4.18 The Small-Signal Performance of a GaAs SIT, S6. (VGs = 0 V)

-190 There is a significant difference in the performance variation of a SIT and a GFC-BARITT device with impurity concentration. In Fig. 4.19, it is seen that the f2,' MAG, MUG and fT rise with VDS. However, the noise figure, F, and measure, M, decreased with ND due to an increase in the gain. The results of the small signal performance of the TTPT devices can be summarized as follows: (i) The MAG, MUG and fT of the minority carrier injection type TTPT devices decrease with channel doping concentration at fixed dc bias voltages, but the f2, and the noise measure rise with it for fixed device bias and geometry. This is because increasing impurity concentration lowers the carrier injection which results in a low transconductance. (ii) On the other hand, the MAG, MUG, f27 and fT increase with ND for Si majority carrier injection TTPT devices. The noise measure is lowered however due to the increasing MAG. (iii) A higher dc bias voltage for both minority and majority carrier injection type TTPT devices results in a higher MAG, MUG, f2 and fT' but lower noise measure. The improvement in the small signal device properties with dc bias does not continue indefinitely, carrier storage at high injection level limits the device performance. The variation of f2, of the III-V compound semiconductor SIT device as a function of VDS follows the drift velocity variation as a function of the electric field. (iv) The MAG and MUG decrease, but the noise figure and noise measure increase with the increasing frequency of operation.

-191 4.0 3.9 3.8 3.7 CD 4-" 3.6 3.5 0.9 1.9' 2.9 3.9 4.9 5.9 N (1014 cm-3) (a) The f2, Fig. 4.19 The Small-Signal Performance of a Si SIT, S2, as a Function of Channel Doping, ND. (V = VpT + 8 V and VGS = -3 V. )

-192- -191 39 35 f = 0.I1 GHz 31 0.2 27. 2:3 tEZ ogl0. 23 0. —_ _ _ 4.4~ 19 i 0.9 1.9 2.9 3.9 4.9 5.9 ND (1014 cm-3) (b) The MUG. Fig. 4.19 The Small-Signal Performance of a Si SIT, S2 as a Function of the Channel Doping, ND at Different Frequencies. (VDs VpT + 8 V and VGS = -3 V.)

-193 -19263 f = 0.1 GHz 55 0.2 47 cC 39 0.5.6 31 23 0.9 1.9 2.9 3.9 4.9 5.9 ND (1014 cm-3) (c) The MAG. Fig. 4.19 The Small-Signal Performance of a Si SIT, S2 as a Function of the Channel Doping, ND at Different Frequencies. (VDS VpT + 8 V and VGS = -3 V.)

-194 -193200 160 120 N u 80 Cr / o / LL 4c) 40 0.9 1.9 2.9 3.9 4.9 5.9 ND (1014 cm-3) (d) The fT. Fig. 4.19 The Small-Signal Performance of a Si SIT, S2 as a Function of Channel Doping, ND (VDs = VpT + 8 V and VGS = -3 V).

-195 10 I8 | f = 0.1 GHz 8 0.2: 6 0.3 rI v;3^I U4 0.4 0.5 0.6 0.9 1.7 2.5 3.3 4.1 5.9 ND (1014 cm-3) (e) The Noise Figure. Fig. 4.19 The Small-Signal Performance of a Si SIT, S2 as a Function of Channel Doping ND at Different Frequencies. (VDS = VpT + 8 V and VGS = -3 V.)

-196 10 If ^^^ —— f = 0.1 GHz 8 0. 2 33 6 tZ ~ ~ — 0.4 0.6 4, 2 0.9 1.7 2.5 3.3 4.1 4.9 N (1014 cm-3) (f) The Noise Measure. Fig. 4.19 The Small-Signal Performance of a Si SIT, S2 as a Function of Channel Doping at Different Frequencies. (VD = VpT + 8 V and VGS = -3 V.) GS

-197 4.7 Large-Signal Performance The large signal performance of TTPT devices is calculated in conjunction with the circuit shown in Fig. 4.20. The blocking capacitances, Cin and CO are large so that, at the operating frequencies they will be short circuits. The y-parameters represent the average device response within a period. The input and output admittances of the device are given in Eq. 4.20 and 4.21, respectively: Y12Y21 Y. = Y (4-20) in l Y +Y (4.20) 22 L and Y Y y - y _ 12 21 Y Y 12 21 (4.21) o 22 Y + Y where YL is the load and YS is the source, admittances. These expressions were given originally in Reference [40]. For inherent stability of the amplifier, the real part of the input and output admittances must be positive. The elements of large-signal equivalent circuit of a device vary with the input signal and the resulting output signal. Device and circuit interaction makes it very difficult to obtain a large signal model for the solid state electronics devices in general. In some cases, the large signal characteristics of a device are directly obtained from a device simulation [14], [36]. This is, however, a very expansive and complicated way. It is almost impossible to solve the device equation numerically for more than two-dimensional cases.

-198 VGSQ' V1 Yl, V i in /vY Y Y21 Y22 _ S S Device Z. = 1/Y = 1/Y in in o 01 Fig. 4.20 A Large-Signal Amplifier Circuit.

-199 There are some semi-empirical large signal models for GaAs FETs to reduce iterative circuit design of the power amplifiers and oscillators [38], [39]. In one of these models [38], expressions for an instantaneous equivalent circuit in terms of terminal voltages have been established from the measured bias dependence of the small signal S-parameters. The major drawback of this model is that it requires extensive measurement of the S-parameters at all the possible dc bias conditions that the RF signal can sweep. Also, S-parameter measurements are not easy. Another model [39] is the derivation of RF equivalent circuit elements in terms of signal voltages, based on static characteristics of an FET such as dc drain current voltage curves and the RF input voltage. The major drawback of this model is that it requires iterative solution of the nonlinear equivalent circuit elements and the output RF voltage. The parameters all of which are used in the latest model, are easy to measure. The large-signal model based on static FET characteristics can be described as follows: (i) Input RF voltage, Vin(t) and YL were known. (ii) Initial values for nonlinear elements (gm' g9ds and cgs) were assumed. (iii) The parasitic inductances and capacitance, Cgd Cds and the contact resistances were assumed to be independent from variations of RF voltages. (iv) YS and the output RF voltage, V (t) and the phase difference between the input and the output voltages, were calculated from the known nonlinear elements and Y.

-200 (v) Expressions for the nonlinear elements (g 9 gds and c ) were derived as the functions of V. (t), V (t) and e. (vi) From the known Vin(t), Vo(t) and e, the values of 9m' gds and C were revised. gs (vii) By using the revised values of the nonlinear elements, Y-parameters and the new values for V (t) and e were calculated which will again change the nonlinear element values. When this process converges, the equivalent circuit of GaAs FET is then obtained for given V. (t) and YL values. (viii) The source admittance, YS was kept matched to the device input admittance as it varied with input power and YL. Finally, the input and output powers were calculated by using known terminal voltages, (Vn(t), V (t)), Y and YL In the present study, a new method for the large-signal modelling of the solid state electronics devices have been proposed to overcome some of the problems of large signal modelling such as S-parameter measurements and/or time consuming, iterative computation. The method can be summarized as follows: (i) Vin(t) is known, Vin(t) = Vgs sin wt. (ii) Vo(t) is also assumed known, and its magnitude is taken as a fraction of dc voltage, VDSQ Vo(t) = kVDSQ sin(wt + e), where k is a fraction of one, 0 < k < 1.0 and e is the phase angle.

-201 (iii) Any reasonable angle value can be assigned for e, but it is assumed that e = 2fTfTd where f is the frequency of operation and Td is the drift-transit-time. Figure 4.21 illustrates the phase relation among the drain-source RF current, Ids(t) Vo(t) and V n(t). (iv) Instantaneous drain-source current, Ids(t) and nonlinear equivalent circuit elements are calculated at the fundamental frequency of operation, since the input and the output RF voltages are known. (v) The effective values of gm gds' cgs' cgd and cds are obtained, then Y-parameters of the device are obtained. (vi) The real parts of the load and output admittances I eff Real (YL) + Real(Yo) = kVf L 0 k~V~DSQ where Ieff is the effective value of the drain source current i ds(t) (vii) The source admittance, YS, which is slightly mismatching input admittance, Y in Yin is given by Eq. (4.20). Ideally, YS should be conjugate matched to Yin. Instead YS = conjugate - (Real Y 2 ) Y conjugate Y 1- (Real2 + 0.n5 I e/kVD SQ 22' f eS

-202 V(t) Vds(t) VDSQ ot e (a) The input, Vgs(t) and output, Vds(t). ids(t) IDSQ ir/2 r 37r/2 2Tr At (b) The current, Ids. Fig. 4.21 The Current and Voltage Waveforms under Large-Signal Conditions.

-203 (viii) From known YSS the output admittance, Yo can be obtained from Eq. (4.21). (ix) Finally, YL can be determined by assuming a conjugate match of the imaginary parts of YL and Y _eff YL = w e Y. (4.22) L kVs Q 0 (x) The input and output RF powers and the dc power dissipation can be calculated from known YS' Y, Vin(t) and Ieff P = I2f/Real(Y). (4.23) o eff/ L' (xi) If the calcuated YL is not reasonable meaning if the real part of Eq. (4.22) is negative, then choose different values for the output RF voltage and repeat the steps from (i) to (x). This approach eliminates the need fo the iterative solutions of the equivalent circuit parameters (Cgm, gds Cgs Cdg, and Cd) of the device. In the present approach the RF terminal voltages Vo(t) and Vin(t) are assumed, then the device characteristics are estimated. Therefore, large-signal device characteristics can be calcualted without the use of the iterative computation method. Summarized, the large-signal model is applicable to large-signal amplifier design utilizing various devices including FETs, TTPT devices and Bipolar Junction Transistors (BJTs). The main advantage of this approach is to relate the device physics directly to the circuit design. Therefore, the large-signal behavior of a device

-204 can be used as a guideline for the actual design of an amplifier. As a result, the turnaround time of an actual circuit design may be shorter. Since the averages of the large signal effects on the device parameters are included, along with the various simplifying assumptions, the calculated results are expected to be guidelines for the actual circuit design. The calculated results will be much closer to the experimental results if the basic model is adequate, such as including the contact resistances and the various parasitic capacitances and inductances. The large-signal circuit expressions are given in Chapter III. In the next section the large-signal power gain, collector efficiency and output power are given. 4.7.1 Results and Discussion of Large-Signal Operation. The large signal performance of the various devices has been investigated by using the model described in the preceding section. The collector efficiency, c', output power Po and power gain Gp of the FET have been calculated as a function of the input power and frequency of the RF input signal. The large signal performance of the FET is less sensitive to the output RF voltage Vo(t), than to the input voltage, Vin(t). On the other hand, the large-signal performance of the TTPT devices is equally sensitive to the output, V (t) and input, Vin.(t) voltages. Any large-signal calculations of the TTPT devices must include the space charge effect of the injected carriers. Otherwise the results will be erroneous. Therefore, only the large-signal calculations of FETs are given.

-205 The variation of the forward biasing voltage, VF of a TTPT device as a function of the drain-source and the gate-source voltages must be obtained from the measured dc I-V characteristics. Then the calculated VF values can be listed in a table or as a two-dimensional array with VGS as it y-coordinate and VDS as its x-coordinate. During the large-signal computations, the magnitude of VGS(t) and Vds(t) is obtained at each integration time interval, and then the corresponding VF can be read directly from the VF table. The large-signal model has been used to investigate the largesignal performance of various FETs. As a demonstration, the collector efficiency, the output power and the power gain of GaAs and InP FETs at an operating frequency of 5.0 GHz are shown in Fig. 4.22 and Fig. 4.23, respectively. The output power as seen in Fig. 4.22(b) or in Fig. 4.23(b) saturates with increasing input power. While the collector efficiency and the output power increase with input power, the power gain decreases with it. As it is predicted earlier in this chapter, InP FETs perform better than the GaAs FETs under small and large signal operating conditions, From the comparison of Fig. 4.22(b) and Fig. 4.23(b) it can be concluded that InP FETs give 30 percent higher output power than comparable GaAs FETs. The output power for the same size Si FET gives much lower output power as seen in Fig. 4.24. Also the power gain of the InP FET is the highest. The nc, Po and Gp of an InP FET as a function of the operating frequency are shown in Fig. 4.25. In Fig. 4.25(a) the collector efficiency and in Fig. 4.25(b) the output power do not vary with frequency. The reason being that the large-signal model is responsible

-206 m100 0.02 004 0.06 0.08 10 INPUT POWER(RTTS) (X101) (a) Collector Efficiency. Fig. 4.22 The Large-Signal Performance of a GaAs FET (Device S7) at 5.0 GHz.

-207 004 006 0.08 INPUT POUER(WATTS) (X10) 010 (b) Output Power. The Large-Signal Performance of a GaAs FET (Device S7) Fig. 4.22 at 5.0 GHz.

-208 0 0 It It.oo 0.02 004 0,06 0.08 INPUT POWER(RTTS) (X101) 0.10 (c) Power Gain. Fig. 4.22 The Large-Signal Performance of a GaAs FET (Device S7) at 5.0 GHz.

-209 uOO 0.02 0.04.06 0.08.10 INPUT POUER(WRTTS) (X101) (a) Collector Efficiency. Fig. 4.23 The Large-Signal Performance of an InP FET (Device S8) at 5.0 GHz.

-210 004 0.06 0108 INPUT POUERWITTS) (X10).10 (b) Output Power. Fig. 4.23 The Large-Signal Performance of an InP FET (Device S8) at 5.0 GHz.

-211 0.2 004 0.06 0.08 INPUT POWERWRTTS) (X101) 0.10 (c) Power Fig. 4.23 Gain. The Large-Signal Performance of an InP FET (Device S8) at 5.0 GHz.

tDOO D08 016 024 0.32 040 INPUT POWER(WATTS) (X10W) The Output Power of a Si FET (Device S9) at 5.0 GHz as a Function of the Input Power. Fig. 4.24

-213 4.39 3.39 2.39 44LU 0 1.39 03I I 0.0 4.0 8.0 16.0 20.0 Frequency (GHz) (a) Collector efficiency. Fig. 4.25 The Large-Signal Performance of an InP FET (Device S8) as a Function of Frequency. (The Collector Efficiency Is Equal to COL-EFF-1.0.)

-214 5.4 1 4.4 34 0 Cl_.D 2.4 - 1.4 C I - - - - —,- -,i, I D 4 8 12 16 20 Frequency (GHz) (b) Output power. Fig. 4.25 The Large-Signal Performance of an InP FET (Device S8) as a Function of Frequency. (The Real Output Power Is 1 Watt Less than the Value Shown on the Power Axis.)

-215 0 tj 0 4 8 12 16 20 Frequency (GHz) (c) Power Gain. Fig. 4.25 The Large-Signal Performance of an InP FET (Device S8) as a Function of Frequency.

-216 not the properties of the FETs. The effective drain-source current of an FET varies only with Vin(t), if VDSQ + V0(t) is more than the voltage which saturates the drain-source current. Also, at each frequency of operation the load impedance is calculated to keep the magnitude of the RF output voltage constant. Therefore the output power and the collector efficiency of a FET do not vary with the frequency of operation, but the gain does. The power gain as a function of frequency is shown in Fig. 4.25(c). The power gain decreases with increasing frequency of operation. However, beyond a 10.0 GHz frequency of operation the gain oscillates and the real part of the input impedance becomes negative. This means that the solution is not valid beyond 10.0 GHz. The magnitude of the output voltage must be varied. The large-signal performance of TTPT devices has also been investigated using the approximate forward bias voltage VF. The results of the large-signal calculations for the TTPT devices are inadequate due to the approximated VF and therefore were not included here.. Nevertheless, these results indicate the trends of the large signal performance of the TTPT devices which are: (i) The input power increases rapidly as a function of either the input RF voltage, Vin(t) or the output RF voltage, Vo(t). The input capacitance increases with the carrier injection. The real part of the input admittance increases as the square of Cgs as shown in Eq. (4.24): 2 2 C R Real(Y i) n -- - (4.24) 1 + E2C2 R2 gs c

-217 The Real(Y in) causes high input power which is not desirable. The TTPT devices can produce high output power with a reasonable gain, if the voltage swing is increased and the carrier injection is reduced by applying high IVGSQI and IVDSQI. (ii) The output power and efficiency of the TTPT devices are sensitive to the phase difference between the V. (t) and Vo(t). (iii) These devices also show the output power saturation for high input powers. (iv) The gain decreases with both increasing input power and frequency. (v) The output power and the collector efficiency decrease with increasing frequency, but increase with increasing input power. The results of the large-signal computations can be summarized as follows: (i) The large-signal model was demonstrated for FETs and predicts the trends of performance correctly. (ii) The proper choice of the output voltage swing can prevent the operation of a FET in the linear region. Also, by choosing the magnitude of the input RF voltage to be less than or equal to the quiescent votlage, VGSQ, the problem of the forward biasing of the gate-soruce junction can be prevented. (iii) The InP or a semiconductor with a high saturation velocity is the best material to fabricate high frequency and high power FETs. (iv) The input capacitance of the TTPT devices increases exponentially with the input RF voltage which causes high input power. For the high power and high frequency operation of the TTPT,

-218 the output voltage swing, Vds, must be increased and the carrier injection must be decreased to obtain a low Cgs, by applying a large IVGSQI ~ (v) The exponential I-V characteristics of the TTPT devices makes these devices very sensitive to the phase difference between the Vo(t) and the V. (t). It may cause some difficulty to design amplifying circuits with these devices. 4.8 Comparison of the Different Devices The similarities and differences of the TTPT devices among themselves are outlined first. Then they are compared with the FETs. The properties of the various devices determine their area of application. The TTPT devices are the lateral punch-through transistor [4], GFC-BARITT and SIT devices [3]. The lateral punch-through and GFC-BARITT devices are the same except for their gates. The gate of a GFC-BARITT device is insulated and the input voltage swing is limited only by the breakdown voltage of the gate-source or the gate-drain whichever occurs first. However, the gate of a lateral punch-through transistor is ohmic. The gate source junction must be biased such that this junction is reverse biased at all times, to prevent current flow through the gate. The same limitation is also applicable to the SIT devices. The gate type is especially important for digital Integrated Circuit (IC) applications. Insulated gates make it easy to form an inverter circuit. The junction or ohmic gate type devices such as

-219 lateral punch-through transistors, SITs and MESFETs, require complicated circuitry to obtain level shifting to prevent the forward biasing of the source-gate junction. The principles of. operating of the GFC-BARITT devices and the lateral punch-through transistors are identical. The insulated gate electrodes make GFCBARITT devices superior over others for applications in digital ICs. The insulated gate, however, reduces the transconductance of the device. Meanwhile, the total gate-source capacitance of a GFCBARITT device is smaller than other TTPT devices. The SIT devices have higher current and transconductance compared to the same size GFC-BARITT devices at the same bias conditions. If the channel doping concentration of a SIT and a GFC-BARITT device is the same the draingate breakdown voltages of these devices will be the same. The gatesource voltage swing of the SIT devices is limited by the gate-source forward biasing rather than the gate-source breakdown voltages, because the forward biased gate-source junction in the case of analog circuit applications increases the input power and the gate-source capacitance. Since the gate-source junction is forward biased, most of the input power is dissipated at the input, therefore the output power saturates when the gate-source junction becomes forward biased. The output power of a GFC-BARITT device also saturates but at higher input power or RF voltage. The gate insulator must be protected against the static charge. The saturation of the output power is also observed in MESFET amplifiers [39]. The TTPT devices are high field devices. Even though the saturation velocity is the most important material parameter for the

-220 TTPT devices improved performance, the III-V compound semiconductor TTPT devices are not superior to their silicon counterparts due to their high diffusion coefficients which results with low storage capacitance and high built-in potential which enables high RF voltage swing. Since the saturation velocities of silicon and III-V compound semiconductors are almost equal, the performance improvement of the III-V compound semiconductor TTPT devices are not expected to be significant. The FETs utilize the low electric field mobilities. Therefore GaAs or InP MESFETs can operate at much higher frequencies than their silicon counterparts due to the higher mobilities of the III-V compound semiconductors. The results of the comparison of the various devices can be summarized as follows: (i) The insulated gate GFC-BARITT devices are better than the other TTPT devices with the junction or ohmic type gate for the digital and analog circuit applications. (ii) The TTPT devices have high power capability at lower microwave frequencies than the FETs. (iii) FETs can operate at higher frequencies than the TTPT devices, because FETs utilize the high mobility of the III-V compound semiconductors. (iv) The performance of the TTPT devices is less material dependent than that of the FETs.

CHAPTER V. DEVICE FABRICATION AND MEASUREMENTS 5.1 Introduction In order to demonstrate the properties of the GFC-BARITT devices discussed previously, several devices were fabricated. These included structures such as (i) n+p n and (ii) M-p-Si-M. First, single devices utilizing Silicon On Sapphire (SOS) were fabricated to study the dc characteristics and to compare the experimental results with the theory developed in a previous chapter. The requirement for an insulated gate limits GFC-BARITT devices to silicon. The formation of a gate insulator on most of the III-V compound semiconductors is technologically difficult [61]. This was the main reason for choosing SOS as a material to fabricate these devices. Some considerations for material selection for TTPT devices are given in a later section. This chapter is organized as follows: In Section 5.2 the technological problems related to different semiconductors are discussed. In Section 5.2.1, the chosen material, SOS, is analyzed. The fabrication procedure for the GFC-BARITT and insulated gate SIT devices are given in Section 5.3. The results of the dc measurements of single TTPT devices are analyzed in Section 5.4. In Section 5.5 the digital circuit applications of the GFC-BARITT device and the injection controlled logic are discussed. The basic inverter structures and principles are given in Section 5.5.1 In order to characterize the switching speed of the inverters, some ring -221

-222 oscillators have been fabricated. The fabrication procedure of the ring oscillator circuits are different from those for single device fabrication. In Section 5.5.2 the fabrication procedure for the ring oscillators is given. A discussion of the switching characteristics of the inverter circuits is presented in.Section 5.5.3. The theoretical expressions for the gate delay time for various inverters are given in Section 5.5.4. The conclusions which have been reached from the experimental study of the various inverters are summarized in Section 5.5.5. Finally, a comparison of the theoretical results which were presented in Chapter IV, with the experimental results obtained in Chapter V, are presented in Section 5.6. 5.2 Material Selection In this study, SOS was chosen due to the simplicity of the technology associated with it. The well known silicon technology increases the yield and shortens the fabrication period for the realization of GFC-BARITT devices. With the present technology of III-V compound semiconductors, GFC-BARITT devices can also be fabricated. The depletion-type Metal-Insulator Semiconductor FET (MISFET) utilizing gallium arsenide (GaAs) [62], indium phosphide (InP) [63] and the ternary compound of GaAs and InP, InlxGaxAs [64] have been reported. The fabrication of the enhancement type GaAs MISFET is still considered to be a technological problem. The formation of the gate insulator for the enhancement type GaAs MISFET (E-MISFET) is not very likely because of basic physical properties and is not due to technological problems because the

-223 GaAs technology is the most advanced among the technologies of the III-V compound semiconductors. The operation of InP [63] and recently Inlx GaxAs [64] E-MISFETs have been reported. The gate insulator technology which has been successful for InP and InlxGaxAs E-MISFETs, has not been successful for GaAs E-MISFETs. It can be concluded that the fabrication of an E-MISFET requires a semiconductor with a narrow energy bandgap (EG), narrower than the EG of GaAs. The energy bandgaps for various semiconductors are listed in Table 5.1. GaAs has the largest EG, and the lowest intrinsic carrier concentration which results in the largest built-in potential between the source and the channel. The large built-in potential, VB, requires a large band bending at the interface of the insulated gate and the channel. A large gate voltage is therefore necessary to bend the energy band and lower VB at the source and the channel. The resulting large electric field, E, may cause (i) larger gate leakage current, (ii) local breakdown at the interface of the GaAs and the insulated gate due to interface nonuniformities, and (iii) charging of the interface states. The combined effects of the large electric field on the gate and the channel interface can prevent the inversion of the surface of p-GaAs. In the case of a D-MISFET the channel can be depleted with a smaller gate voltage because the depth of the depletion is independent of the energy bandgap. Therefore, any device can be fabricated from GaAs, if, and only if, it requires the depletion of the carriers. GaAs D-MISFETs have been reported with various gate insulators [65-68] which confirms the point raised above.

-224 Table 5.1 Energy Bandgap for Various Semiconductor Materials In Ga As/InP~~~ Material E (eV) G In xGaxAs/InP 0.75 0.75 Si 1.12 InP 1.3 GaAs 1.43 Intrinsic Carrier Density (cm-3) D-MISFET -5.2 x 1012 yes 1.49 x 1010 8.7 x 107 2.18 x 106 yes yes yes E-MISFET yes yes yes no E-MISFET yes yes yes no

-225 Therefore,it can be concluded that it is possible to fabricate GaAs GFC-BARITT devices as well as InP, Si or Inl Gax/InP, since the function of the gate in a GFC-BARITT device is to induce a barrier to reduce the injection of the carriers from the source to channel. Nevertheless, SOS has been chosen due to its well known technology. 5.2.1 SOS Samples. The silicon-on-sapphire samples which were implanted were obtained from Hughes Research Laboratories. The information on the ion-implantation is listed in Table 5.2. The ionimplantation information given in Table 5.2 was employed to calculate the impurity concentration. The initial impurity distribution before any high temperature processing was estimated by following Gibbon's formulation [69] and is shown in Fig. 5.1. The impurity distribution is approximated by a Gaussian function which is given in Eq. (5.1): (x - R)2 (np f(Xp p - Rp)2 n (x ) - _ -.exp - - ---, (5.1) p p / 2- f- 2cU2 p P where ~ is the ion dose, a is the standard deviation in the projection range, and Rp is the projection range. The impurity distributions in Figs. 5.1(a) and in Fig. 5.1(b) will change during the annealing at 925~C and more importantly during the dry-oxidation of the gate and/or diffusion of the n drain and source terminals. The calculation of the final impurity distribution is rather complicated and will not be attempted here. Instead, an average doping concentration of 1014 cm-3 will be assumed for both p-type and n-type examples. The oxidation time at 1000~C is 90 minutes.

-226 Table 5.2 Ion-Implantation Data Annealing Ion Material Impurity Ion Dose Energy Temp. Time 0.5 pm SOS Boron 1010 cm-2 80 keV 925~C 30 min 0.5 pm SOS Phosphorous 1010 cm-2 200 keV 925~C 30 min......,.~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

-227 15 l0 1014 E 1013 10 103 <D S-,, 1012 - 4-) 1011 0.( X (a) Boron profile. I E U <) r-.r40.0a C — E =3 E x 0.0 0.1 0.2 0.3 0.4 0.5 depth of the silicon film (b) Phosphorus profile. Fig. 5.1 Profile of the Ion Implanted Impurities.

-228 The impurity distribution will be almost uniform across the thin silicon film. The enhanced diffusion of the ion-implanted boron and phosphorous in the silicon film is known to exist [70]. Therefore, the uniform impurity distribution is justifiable. 5.3 Device Fabrication Two different procedures have been developed to fabricate (i) a junction (J)-type GFC-BARITT (JGFC-BARITT) device and (ii) a Schottky Barrier (SB) GFC-BARITT (SBGFC-BARITT) device. An insulated gate SIT device can be fabricated by using the JGFC-BARITT device procedure with the n-type silicon film on sapphire. The main difference between the fabrication of the SB GFC-BARITT and the JGFC-BARITT devices is the formation of the drain and the source electrodes. Therefore, all the processing steps of the device fabrication are described, and the special steps for different devices are pointed out. Step 1: figure 5.2 shows the various steps employed for device fabrication. The wafers were first cleaned by following a standard cleaning procedure and then dry oxidized at 10000C for 90 minutes to obtain a 900 8 film of SiO2. Immediately after oxidation, a 0.23 pm thick Si3N4 film is deposited at 773~C in a CVD reactor. After the CVD Si3N4 deposition, the positive photoresist (PR) AZ1350B was spun-on the samples to protect the active device areas as shown in Fig. 5.2(a). Using PR as a mask, Si3N4 was etched for 11 minutes in a plasma composed of 200 CF4:25 02 with 1.25 kW power and 13.5 MHz frequency. Following the

-229 0.5 I'm AZ1350B 0.23 1m Si3N4 ~ 4 / s g90oo Si02.. "_ - - - 0.5 m Si 13 mils A1203 (a) First photoresist mask to define active area. S.. -' ~: ~L*... —_ p —Si Al 0.(b) Wafer seen after the etching of Si3N4 and SiO2. SiO./ S i Si N 34 Si p —Si 2 (Group A) LI~~ Al2~3 203 (d) Device isolation done by mesa etching (Group B). 3100 si0N 0.2 pm sio2 P-Si -Si Al 203 (e) After ne drain-source diffusion. Fig. 5.2 Fabrication Processes of the MSM and Junction (J) GFCBARITT Devices.

-230 Fig. 5.2 (cont.) 0.23 im Cr/Al 114, -;- -. -, ",,,,,,,,,,'-% x -, x xx Vd.'.. -, I "d M. *v ^,';.1.)u-Si- i1 Al 2 3 ) A1203 [ (f) After Schottky barrier drain-source formation. 0.2 Hm A1 n_ p-Si n Al1203 (g) Gate definition for junction drain-source device. n0? m Al aate 0.23 pm Cr/Al Source i:... A_..^^J^^ g^.. ^>..... -1 p-S i ~ -' Drain ALL" Al 203, - (h) Gate definition for MSM device (final device) (i) Metallization of the J-GFC-BARITT device.

-231 plasma etching, a thin dry oxide was etched for one minute in buffered hydrofluoric acid (HF). At the end of Step 1, the wafer is as shown in Fig. 5.2(b). Step 2: The samples were cleaned again and some of them were oxidized at 1000~C for four hours in atmospheric steam (Group A). The other samples were etched for two minutes in a chemical etchant at 85~C (Group B). Group A and Group B are shown in Fig. 5.2(c) and Fig. 5.2(d) respectively. The chemical etchant was composed of 50 milligrams of potassium hydroxide (KOH), 50 centileters deionized water (DIH2O) and 10 centiliters of isopropyl alcohol. Step 3: The drain and source windows are opened by using the previously defined plasma etching. The injection junctions were formed (i) by diffusing phosphorous at 950~C for five minutes for the JGFC-BARITT and + + n n n SIT devices and (ii) by depositing Cr and then Al for SB GFCBARITT devices. In Fig. 5.2(e) the junction type and in Fig. 5.2(f) the Schottky barrier type devices are shown. To form the Schottky barrier on silicon 300 8 Cr and 2000 i A1 were deposited. Without a thin Cr film, the Al resulted in very low barrier height Schottky contacts. The devices with only Al drain and source electrodes were essentially resistors.

-232 Step 4: To deposit the gate electrodes, PR was used as a mask and the PR in the gate region was removed. In other words, the PR protects the rest of the device other than the gate electrode regions. A Si3N4 layer was plasma etched as in Step 1. After etching, a 0.3 pm thick Al film was evaporated over the samples. The metal from the PR protected areas of the wafers were lifted off in an acetone solution with one-minute ultrasonic agitation. In Fig. 5.2(g) the JGFC-BARITT device with a narrow gate is shown. At this point, the processing of the SB GFC-BARITT device is complete. Step 5: The metallization of the JGFC-BARITT device is the final step of the device fabrication. The finished device is shown in Fig. 5.2(i). Steps 1 through 5 describe the process steps of insulated gate SIT as well as GFC-BARITT devices. It is apparent that the mesa-etch isolation and the Schottky barrier injecting junction devices are less process involved and faster to fabricate. Figures 5.2(d) through 5.2(i) show only the processing steps for mesa-etch isolated or Group B wafers. The processing steps for the local oxidation process isolated or Group A wafers are the same as those of Group B. The technology to fabricate TTPT devices which is outlined in this study, is far from being the optimum one. The source of a JGFC-BARITT device can be self-aligned to prevent the overlap between the gate metal and the source electrode. In the present

-233 Schottky barrier GFC-BARITT device process, the distance between the source and gate is determined by the alignment tolerance (misalignment) of the mask-aligner. This results in low yield. Nevertheless a sufficient number of the junction and the Schottky barrier type GFC-BARITT devices were operational to test the dc characteristic. The Schottky barrier GFC-BARITT devices shown in Fig. 5.2(h) are especially inefficient, because the injection area is shallow. A better SB GFC-BARITT device structure is shown in Fig. 5.3. Photomicrographs of the fabricated devices are shown in Fig. 5.4. 5.4 Dc Characteristics The fabricated devices were probed and the dc current-voltage (I-V) characteristics were displayed on a curve tracer. In Fig. 5.5, the I-V characteristics of an n p n GFC-BARITT device are shown. As seen in Fig. 5.5(a), this device operates like an enhancement-type MOSFET with positive applied gate voltages. However, at high drain-source, VDS, voltage (IVDsI > IVpTI), the JGFC-BARITT device shows exponential I-V characteristics. For negative gate voltages, the device also shows exponential I-V characteristic as seen in Fig. 5.5(b). The Metal p-Si Metal (MSM) GFC-BARITT device characteristics are shown in Fig. 5.6(a) for positive gate voltages and in Figl 5.6(b) for negative gate voltages. The gate length of the SB GFC-BARITT devices is 5 pm and the length of the channel between the drain and the source is 20 pm. Therefore, the E-MOSFET operation

-234 A1 Si 3N4 G Sputtered Si02 S *\:;.......*,~ D Cr/A1 l'..::.:;.:''::..:-n- or p-';;IA A1203 (Sapphire) Fiq. 5.3 Ideal Schottky Barrier GFC-BARITT Device.

-235 ~;. iiiI * 1 IL (a) Die photomicrograph. (b) Enlarged photomicrograph of a single device. Fig. 5.4 Fabricated GFC-BARITT Devices.

Vertical: 0.1 mA/div Horizontal: 5 V/div Gate bias: 2.0 V/step (a) Turn-on characteristics. Vertical: 0.1 mA/div Horizontal: 5 V/div Gate Bias:2.0 V/step (b) Turn-off characteristics, Fig. 5.5 n p n Device (Z 0.2025 cm, LG = 5 vmn and LDS 20 wun. OS

-237 U....I lp Ii UME. UE...1 I EU.. iiE p-pp 111 Eu I j (4, pj~~~~~mwlog.~ ~ ~ 111 11 11.1M1M Vertical: 0.2 mA/div Horizontal: 10 V/div Gate bias:; 5.0 V/step (a) Turn-on characteristics. Vertical: 0.2 mA/div Horizontal: 10 V/div Gate bias: -5 V/step (b) Turn-off I-V characteristics. Fig. 5.6 MSM GFC-BARITT Device. (z = 500 im, LSG = 2.5 pm, LGD 12.5 im, and 0.5 min thick.

-238 of the GFC-BARITT device cannot be observed in Fig. 5.6(a) at low VDS (|VDSI < |VpTI). The SB GFC-BARITT devices with Cr/Al drain source contacts were operational. However, alumimum contacts used as Schottky barriers did not work. To the best of our knowledge, this is the first study of a M-p-Si-M punch-through structure. There have been published reports on M-n-Si-M punch-through diodes (M-n-Si-M BARITT diode) [7] and p-channel SB-MOSFETs [30], [71] through [73]. Most recntly, n-channel SB-MOSFETs with molybdenum drain-source contacts have been fabricated in our laboratory [73]. + - + In Fig. 5.7 the I-V characteristics of an n n n Insulated Gate (IG) SIT or a majority carrier GFC-BARITT device are shown. This device operated as an IGFET for positive gate voltages as shown in Fig. 5.7(a). Negative gate voltages deplete the channel and induce a barrier height for electron injection in the vicinity of the source electrode. At low VDS voltages, the gate induced barrier height prevents carrier injection. However, at high VDS voltages, this barrier height is reduced by VDS. Therefore, the current is negligible at low VDS voltages and increases exponentially at high VDS voltages as seen in Fig. 5.7(b). In all the devices tested, the terminal which is closer to the gate is biased as a source electrode and the other terminal is biased as a drain electrode. The devices were fabricated asymmetrically deliberately in order to test the function of the gate-source distance. The theoretical study concluded that the control of the injection required a gate electrode which is located near the injection point. This theory was proven experimentally by

-239 Vertical: 0.2 mA/div Horizontal: 5 V/div Gate bias: 5 V/step (a) Turn-on characteristics. Vertical: 0.2 mA/div Horizontal: 5 V/div Gate bias: -5 V/step (b) Turn-off characteristics. +- + Fig. 5.7 Insulated Gate n n n SIT with Z = 125 vm, LSG = 3.5 pm, LGS 10 uim, L = 30,im, and 0.5 pm thick. DS

-240 biasing the terminal far from the gate as the source and biasing the one closer to the gate as the drain. The I-V characteristics of a normally biased device is shown in Fig. 5.8(a). After interchanging the source and the drain terminals, the resulting I-V characteristics are shown in Fig. 5.8(b). As can be seen in Fig. 5.8(b), if the source is far from the gate, the gate voltage cannot modulate the drain-source current, IDS. All the devices tested in this study required a small distance between the source and the gate electrodes to control IDS through an insulated gate. 5.5 Introduction to Digital Circuit Applications Two fast inverter schemes for the semiconductor on insulator (SOI) system have been proposed. The switching speed of a Complementary Metal Oxide Semiconductor on SOI (CMOS/SOI) or specifically CMOS/SOS logic can be increased by replacing the slow p-channel MOSFET with a faster device. A p-channel MOSFET is slower than the n n n depletion-type MOSFET (or IGFET) due to its lower hole mobility as given in [74]. A p-channel MOSFET can be replaced by (i) a gate-field controlled (GFC) diode and (ii) a GFC-BARITT device which can result in a faster inverter due to their high current capabilities. The concept of the insulated gate effect on the diode characteristics was developed by Grove [55]. Recently, a vertical GFC-diode/SOI has been reported [75]. To the best of our knowledge the planar GFC-diode/SOS has been reported for the first time in this work. In the following sections, the principles of operation of a GFC-diode/SOS called Injection Controlled Logic (ICL) and a

-241 - Vertical: 0.05 mA/div Horizontal: 10 V/div Gate bias: -2 V/step (a) Source and gate closer than the gate and drain. Vertical: 0.01 mA/div Horizontal: 10 V/div Gate bias: -5 V/step (b) Drain and gate closer. Fig. 5.8 n p GFC-BARITT Device with Z = 125 pm, LSG = 5 pm, LG = 10 Pm, SG G LDS = 30 pm, and 0.5 pm Thickness

-242 GFC-BARITT device/SOS inverters, fabrication of ring-oscillator circuits and an analysis of the experimental results are given. 5.5.1 Basic Structure and Principles of Operation. A new complementary logic scheme is illustrated in Fig. 5.9(a). An ICL inverter has two components which are: (i) an n n n insulated gate field effect transistor (IGFET) and (ii) a n n p gate field controlled diode (GFC-diode). The negative one of the two power supplied, -Vss, is connected to the source of the IGFET, and the positive power supply is connected to the emitter of the GFC-diode. The insulated gates of both devices are joined together at the input terminal. The drain of the IGFET which is also the base of the GFC-diode is the output terminal. A basic ICL inverter is an + - + + n n n n p structure with two insulated gates on the n -regions as shown in Fig. 5.9(a). The drain of the IGFET and the base of the GFC-diode are common for both devices (common drain-base structure). A CMOS/SOS inverter is also given in Fig. 5.9(b) to compare with the ICL/SOS inverter. The operation of an ICL inverter is as follows: If the input voltage, Vin is high (or positive) the n+n n IGFET is turned on and, it acts as a resistance. As a result, the output voltage, Vo, will charge up to the voltage level of the source of the IGFET, (-Vs). If Vin is low (or negative), the IGFET is turned off, but the n n p GFC-diode is turned on. A negative gate voltage will allow the carrier injection from p -emitter to n n -base. Therefore, V0, for this case, will charge up to the voltage level of the emitter of the GFC-diode (+VDD). The Vo charges up to +VDD rather than

-243 VIN I -Vss!S Vo vy ^T~vyy^ I VDD I f/l 1nnIn5 I Dn++n ) Sapphire (A1302) / (a) Injection controlled logic. VIN (b) CMOS/SOS logic. Fig. 5.9 Inverter Structures.

-244 VDD-VB where VB is the built-in voltage of the n p junction, because VB vanishes at the interface of the SiO2 gate insulator and the n -base. The GFC-diode is always forward biased, but the carrier injection is controlled through an insulated gate. If the gate voltage, Vin is negative, the GFC-diode will be turned on, and if Vin is positive, then the GFC-diode will be turned off. The CMOS/SOS inverter structure is shown in Fig. 5.9(b). The dotted lines are for the overlapping gate structure which is necessary for the operation of the E-type p-channel MOSFET. The solid lines are for the narrow gate one which is the ideal GFC-BARITT for the SOS inverter. A CMOS/SOS inverter structure was used to fabricate a five-stage ring oscillator circuit. The switching speed of the conventional CMOS/SOS and the GFC-BARITT device (GFC-BARITT/SOS) inverter have been evaluated using the CMOS/SOS inverter ring oscillators. At low drain source bias conditions, the inverter structure shown in Fig. 5.9(b) operates as a CMOS inverter. When the applied voltage (VDD) exceeds the punch-through voltage (VpT) of the p-channel, the same structure operates as a GFC-BARITT/SOS inverter. More specifically, the p-MOSFET is replaced by the GFCBARITT device at VDD in excess of VpT. The operation of a GFC-BARITT/SOS is not as simple as the CMOS/SOS inverter. The principles of operation of a GFC-BARITT SOS inverter are as follows. When the input voltage is positive, the GFC-BARITT device will be turned off. Meanwhile the n n n IGFET will be turned on. As a result, the output will charge up to -Vss voltage. If Vin becomes negative, the gate induced barrier against the carrier

-245 injection in the GFC-BARITT device will vanish. Therefore the GFC-BARITT device will be conducting, while the IGFET is turned off. In an ideal GFC-BARITT/SOS structure, the output voltage of the inverter, Vo will charge up to VDD - VpT. However, in a GFC-BARITT/SOS structure with an overlapping gate, Vo will be charged up to VDD - VpT by the GFC-BARITT device current. Beyond this level, Vo will be charged up to VDD - VTH by the p-channel MOSFET, where VTH is the threshold voltage of the enhancement type MOSFET. 5.5.2 Ring Oscillator Fabrication. Injection-controlled logic ring oscillator circuits have been fabricated on the 0.5 micrometer (pm) thick silicon on sapphire samples described previously. A simple four-mask.fabrication process which was used to fabricate the ICL/SOS and CMOS/SOS ring oscillators, is described below. The n-type SOS samples which were describes in Section 5.2.1 were used to fabricate ring oscillator circuits. The samples were cleaned, and active device areas were defined by using a 0.5 pm thick AZ1350B photoresist as a mask and etching the unprotected silicon in a plasma composed of 200 CF4:2502 at 13.5 MHz frequency and 1.25 kW power. After plasma etching, the active device areas were oxidized in dry 02 at 1000~C for 90 minutes to form 900 R thick SiO2 for the gate insulation. Immediately after the oxidation, 0.45 pm thick polysilicon is deposited at 668~C in the CVD reactor. The n -diffusion windows were defined by using AZ1350B photoresist as a mask and etching the polysilicon in a 200 CF4:2502 plasma. Consequently, the 900 R thick SiO2 covering the n -diffusion windows was etched in a buffered HF solution. Prior to the diffusion the cleaned samples were phosphorus prediffused for four minutes.

-246 Immediately after the diffusion, 0.3 pm thick SiO2 was deposited at 810~C in the CVD reactor. This oxide layer was used as a mask to protect the n diffusion and the n polysilicon gate regions. The p -emitter windows are defined in a similar manner to the n -window formation. After the boron prediffusion at 950~C for five minutes, the 0.3 pm Si02 was removed completely. The final step was the 0.3 pm thick aluminum evaporation and the definition of the metal connections. The processing sequence of the five-stage ring oscillators is shown in Fig. 5.10(a) through 5.10(f). The die microphotographs of the ring oscillator and some test circuits are shown in Fig. 5.11(a) and 5.11(b). This is a self-aligned gate process. The gate lengths of all the devices in the ICL/SOS and CMOS/SOS ring oscillators were 20 pm and the gate widths were 100 Pm. 5.5.3 Results and Discussion. The fabricated ring oscillators with 20 pm gate lengths and 100 im gate widths were biased at VDD = 10 V and VSS = -10 V. The output waveforms of an ICL/SOS ring oscillator and of a CMOS/SOS ring oscillator are shown in Figs. 5.12 and 5.13, respectively. The average delay time as a function of the power dissipation is calculated, and given in Fig. 5.14 for an ICL/SOS inverter and in Fig. 5.15 for a CMOS/SOS inverter. The average delay time is 19.6 ns for an ICL/SOS inverter and 30 ns for a CMOS/SOS inverter at +15.0 V. However, the power dissipation is higher than the power dissipation of a CMOS/SOS inverter. The symmetry of the output waveforms in Fig. 5.12 indicates that the n n p GFC diode is as fast as the n nn IGFET. If the

-247 AZ1350B.,. —,..-.':..'-:_ O.. - 0.5 pm n ) Sapphire (A1203) (a) Active device definition. 900 R SiO2: "n-:Sapphire Sapphire (b) Thin SiO2 growth.....1 J: -:':;".: 0O.45 Pm poly-Si /kv.vv n -rr, \.. Sapphire (c) CVD poly-Si gate. F,l, /~~~~~ n -rr Sapphire n. -,,- rn c;n (d) Drain and sou irce window openings and diffusion. u.> PM lvu Z - p of -P ^l y -z S* n+-poly-Si Sapphire'"2 (e) CVD SiO2 deposition to protect n diffusion. m, +n In - n+i n~ +1 Sapphire (f) Metallization and finished device. Fig. 5.10 Fabrication Steps.

-248 (a) Die photomicrograph. I (b) Magnified photomicrograph of the oscillator circuits. Fiq. 5.11 Photomicrograph of the Five-Stage Ring Oscillators.

-249 Vertical:2V/div Horizontal:100 ns/div Fig. 5.12 Output Waveforms of the Complementary ICL Ring Oscillator.

-250 Vertical:0.5 V/div Horizontal:200 ns/div Fig. 5..13 Output Waveforms of the CMOS/SOS Ring Oscillator.

1.2 1.1 1.0 0.9 0.8 u I 0 S._ C) E.0 4-)'s CD 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0.1.3.5.7.9 1.1 1.3 1.5 1.7 1.9 Power dissipation (mW) Fig. 5.14 Switching Speed of the Injection Controlled Logic Gate as a Function of the Power Dissipation.

-252 100 90 80 70. ~ \ = 60- \ 50\ 40 3z 320- 1010- ~ 21.5 V 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 Power dissipation (mW) Fig. 5.15 Switching Speed of the Punch-Through Logic Gate as a Function of Power Dissipation.

-253 switching speed of the one device is faster than the other, the resulting output waveform of the ring oscillator will be nonsymmetrical, as in the case of CMOS/SOS ring oscillator shown in Fig. 5.13. In Fig. 5.13, rise time of the output waveform is 1.5 times longer than the fall time which is an indication of an inverter with one fast and one slow switching device. Since the mobility of the holes is lower than the mobility of the electrons as given in [74], + -+ a n n n IGFET will be faster than the same size p-channel MOSFET. As shown in this study, replacing the p-channel MOSFET in a CMOS/SOS with a faster device, GFC-diode, the average gate delay can be significantly reduced. In addition to the short gate delay time, the area consumed by this new, ICL/SOS inverter is also smaller than the area consumed by the CMOS/SOS. Since an n n n IGFET is common for SOS/CMOS and ICL logic, the difference in performance between these two logic circuits is due to the p n p MOSFET and the n n p GFC-diode. The current capability of an n n p GFC-diode is higher than that of a thin p resistance of a p n p MOSFET. In the n n p GFC-diode, carriers are injected from the 0.5 pm thick diode, but in a p n p MOSFET the current passes through only a few hundred Angstrom thick inversion layer. More current means faster charging of the output capacitance. The GFC-diode circuits can switch faster than the MOSFET circuits because (i) the mobility of the injected carriers in the GFC-diode is high (bulk mobility of the silicon film) while the carrier mobility in an inversion layer of a MOSFET is lower than the bulk mobility, and (ii) the total current of a GFC-diode is higher

-254 due to the larger injection area (film thickness) as opposed to a few 100 R thick current path of a MOSFET. Figure 5.15 shows the effect of the punch-through phenomenon on the switching characteristics of a logic gate. Beyond the indicated "21.5 volts" the n region of the p n p MOSFET of the CMOS/SOS inverter is completely depleted. The p-channel MOSFET now operates as a GFC-BARITT device [76]. A current is provided through the p n p GFC-BARITT device by the injection of the holes from the p source into the depleted channel. Therefore, the GFC-BARITT device can supply a higher current than the same size MOSFET. This is the reason why Fig. 5.15 shows a sudden drop in the delay time (up to 10 ns) at a bias voltage in excess of the punch-through voltage. The delay time of a GFC-BARITT/SOS inverter can be further reduced by using a recessed gate. For instance, a GFC-BARITT device with 1 pm long gate and 20 pm drain-source distance, is expected to have a delay time of 500 ps. By reducing LDS to 5 pm, the delay time is estimated to be less than 100 ps. *A delay time of 75 ps for a punch-through MOSFET inverter on a 1015 cm-3 doped p-Si has been reported [77]. It is possible to achieve even faster switching speeds with the scaled down GFC-BARITT device on SOS inverters. The distance between the drain and the source, LDS, does not have to be in the micron or submicron range, it can be four or five pm. Only the gate length has to be in the micron or submicron range. In a GFC-BARITT device or in a MOSFET, the switching speed of the device is limited by the charging time of the output capacitance (including parasitics). LDS determines the

-255 transit time of the device which is much shorter than the switching (or gate delay) time. Therefore, for a short switching time, any device should have a high current capability and a small output capacitance. The inverter structure in Fig. 5.9(b) has recessed gates (dotted lines) for the small output capacitance, insulator substrate for small parasitic capacitances, and punch-through operation for high currents. Such a structure with a submicron gate length can be a fast logic gate, much faster than a MOSFET of the same size. Assuming a 0.5 pm thick SOS is used to fabricate a 5 pm drain source length and 1 pm gate length GFC-BARITT device and 5 pm gate length MOSFET, the speed fo the GFC-BARITT device is estimated to be 100 times faster than that of a MOSFET. A qualitative expression for the ratio of switching speeds of these devices is given by Eq. (5.2) Active GFC-BARITT Length of layer Switchig s d f device drain source Pthin film thickness Switching speed of OSFET Length of surface Inversion device offset gate layer thickness (5.2) Using an insulator substrate, sapphire in this case, has some disadvantages. If the processing parameters are not carefully chosen, such as the depths of the n and especially the injecting junctions, p, the leakage currents will be high which results in high power dissipation. The reason for the high power dissipation of the ICL inverters in Fig. 5.14, is the high leakage current. If the depths of the n and p diffusions are shorter than the thickness of the

-256 silicon film on sapphire, the leakage current will be increased with the increase of the applied bias voltage. This is, however, a relatively simple technological problem. As shown in Section 5.5.5 the switching time of a logic gate (inverter) is determined by the average current of the individual devices, and the output capacitance. Therefore either inverter structure can be used to fabricate digital integrated circuits on III-V compound semiconductors. The GFC-diode in the ICL inverter and the GFC-BARITT device in the GFC-BARITT inverter are injection type devices and not gate-controlled resistances (FETs). In a FET, the current is directly proportional to the carrier mobility. The low mobility effect in injection devices (GFC-diode and -BARITT device) can be compensated for easily by the increase of the forward bias voltage. This means that the low mobility semiconductors can be used to fabricate high-speed switching devices. The role of the insulated gate in injection type devices is to deplete the channel, not to invert it. Therefore, it can be concluded that the two inverter schemes (ICL and GFC-BARITT) device inverters satisfy all the necessary physical and technological requirements to realize III-V compound semiconductor digital integrated circuits. 5.5.4 Delay Time. A simple approach is given below to calculate the delay time of an inverter with a capacitive load. The common delay time approximation is to find the charging or discharging times of the output capacitance with an average device current [78]. 5.5.4.1 A GFC-BARITT Device Inverter. An inverter circuit with a capacitive load is shown in Fig. 5.16. The turn-on time, TON,

-257 +VDD GFC-BARITT device Vo VIN.. IGFET co -Vss Fig. 5.16 GFC-BARITT Device Inverter Circuit with a Capacitive Load.

-258 is defined as the charging time of the output capacitance, Co, through the GFC-BARITT device: CV T - ON I I (5.3) where Vo is the output voltage and charges CO and can be expressed as V IoDEXP[kl(V I is the average current which 1 VDD - Vo) - k2VIN]dVo I 1 01 (5.4) V 02 V 01 dV 0 where V is the initial output voltage and V02 is the final output 01 02 voltage which is less than VDD. Io, k and k are constants. If the 1 2 gate length LG is less than the distance between the source and the drain, LDS, the maximum output voltage, V02 is equal to the difference between VDD and VpTG (punch-through voltage for the distance of LDS' LG). Therefore, V02 VDD VPTG qND VPTG = 2 (LDS - LG)2 D LD (5.5) where

-259 If the gate extends from the source to the drain electrode, the capacitance is initially charged by a GFC-BARITT device when the output reaches VDD - VpT. In this case, the GFC-BARITT device operates in a MOSFET mode and it will charge the output capacitance up to VDD - VTHThe main advantage of the GFC-BARITT device logic over a MOSFET logic is that initially the GFC-BARITT can supply a higher current than a MOSFET, which results in a shorter switching time. When the GFC-BARITT is turned on by applying a gate voltage in addition to the punch-through barrier lowering effect, the gate voltage further lowers the barrier against carrier injection. The output level of a GFC-BARITT device inverter is lower than that of a MOSFET inverter. 5.5.4.2 Injection Control Logic. The delay time of the ICL can be estimated from the average charging and discharging time of the output capacitance also: TON CV 00 I 1 (5.6) where I the average current of the controlled diode can be expressed as Vo-VBB = ~o Io exp(klVk2VGS)dV (5.7) I V"o (5.7) I 0 0 dVo

-260 The turn-off time can be calculated by considering the discharging of the IGFET in the ICL circuit shown in Fig. 5.17. It is given by CoVo OFF I'(5.8) 2 where I is the average current of the IGFET and can be expressed as 2 -Vo 01 IS dVo I = o (5.9) V Both of these logic structures GFC-BARITT/SOS and ICL/SOS +- + have the common n n n IGFET as an active load. The turn-off or switching-off time for these two logic inverters is the same and is determined by the discharge time of the IGFET. There will be however a small difference in discharge time due to the difference of the output voltage levels in the ICL/SOS and GFC-BARITT/SOS. inverters. 5.5.5 Conclusion. A new ICL inverter scheme has been proposed and its principle of operation has been demonstrated. An ICL/SOS inverter with 19.6 ns and a CMOS/SOS conventional inverter of the same size with 30 ns gate delay time were fabricated. The iCL/SOS inverter is not only 1.5 times faster, but is also smaller than the CMOS/SOS inverter. On the other hand, a GFC-BARITT device inverter is even faster, 10 ns delay time, then an ICL. The reason

-261 - +VDD V IN F -H -A GFC-diode Vo IGFET C0 IA - Vss Fig. 5.17 ICL Inverter Circuit with a Capacitive Load.

-262 for the high power dissipation of the ICL/SOS inverter is the high leakage current at the silicon and sapphire interface. The leakage can be significantly reduced by making certain that the depths of the n and p regions are not shorter than the thickness of the silicon film on sapphire. As it is demonstrated in this study, there are two other possible high speed logic schemes other than a CMOS/SOS which are (i) an ICL/SOS and (ii) a GFC-BARITT/SOS. The feasibility of ICL and GFC-BARITT device digital integrated circuits on III-V compound semiconductors was discussed, and it is concluded that it is possible to realize III-V compound semiconductor digital circuits with existing technologies simply by replacing the enhancement type MISFET with either GFC-BARITT devices or a GFC diode as shown in Fig. 5.18(a) and (b), respectively. These suggested logic schemes operate in a similar manner to a depletion/enhancement MOS logic. The reason for using the logic schemes shown in Fig. 5.18(a) and (b) is to utilize the high mobility electrons of III-V compound semiconductors. In Fig. 5.18(a) and (b), the n n n IGFET must not be turned off at any time for the proper functioning of the inverter. As a result of this normally on n n n IGFET, power dissipation will be high. Figure 5.18(a) and (b) represent a compromise between speed and power dissipation. Even though the switching speed of a complementary logic structure from III-V compound semiconductors which is similar to the structure in Fig. 5.9, are not expected to be as fast as the one in Fig. 5.18 due to the low hole mobility. The power delay product of a complementary logic structure

-263 V 0 V IN DD GND (a) GFC-BARITT device logic. Vo GND I (b) GFC diode logic. Fig. 5.18 Inverter Structure for Semiconductors with High Electron Mobil ities.

-264 may be better than that of a structure shown in Fig. 5.18. Since GFC-BARITT device and GFC-diode can supply high hole current with a small gate-source capacitance, a III-V complementary structure which + + consists of one n n n IGFET and one GFC-BARITT device or one GFC-diode, can switch 1n (III-V)/in (Si) times faster than their Si counterparts, The advantages of using an insulated gate III-V compound semiconductor logic circuit over a MESFET logic are summarized as follows: (i) For a small scale circuit GaAs MESFET logic circuits result in very impressive switching speeds, but MESFET circuits are not tolerant of process parameter variations [79]. Insulated gate structures have high tolerances against active layer thickness and the non-uniformity of the gate insulator. (ii) Due to the forward-biasing problem of a Schottky gate, the logic swing of a MESFET logic is limited, but for insulated gate logic it ri not. (iii) It is not possible to fabricate a complementary low power MESFET logic circuit. The high power will limit the level of integration of the MESFET logic. On the other hand, GFC-BARITT devices or GFC-diode logic circuits can easily be coupled and the unit cell can be much smaller, therefore GFC-BARITT device or GFC-diode logic circuits can be integrated on a large scale easily. (iv) The MESFET logic is limited to GaAs because it is much harder to form a Schottky gate on other III-V compound semiconductors with smaller energy band gap such as InP and Inl xGaxAs. However, in the case of insulated gate devices there is no such limitation.

-265 It can be concluded that the GFC-BARITT device and GFC-diode have some very promising digital circuits for high speed and low power circuit applications. 5.6 Comparison of the Theoretical and Experimental Results All of the experimentally observed device characteristics were qualitatively predicted by the device theory, such as the mixed FET and punch-through operation of a SIT device, negative resistance in III-V compound semiconductor FETs and the geometry dependence of the device characteristics of all of the TTPT devices. In addition to the prediction of the experimental results, the effects of the various material parameters on the device performance have been studied. A simple and inexpensive simulation program, SIM-GFC, given in Chapter IV was proven to be a good tool for understanding the various punch-through devices. It is possible to predict the device performance under various operating conditions such as different temperatures, and also to evaluate the effect of the different material parameters before fabricating the device. In Chapter IV the results of the computer simulation have indicated that the distance between the source and the gate is critical in controlling the injection of'the carriers. If the gate is far from the source, the drain-source current cannot be modulated through a gate electrode. The experimental results of the GFC-BARITT device support the theoretical prediction. In Fig. 5.18, it is shown that a gate that is far from the source cannot control IDS.

-266 The experimental studies that were published about SIT devices can be explained theoretically. For instance, the field effect and the exponential characteristics of a SIT device are correctly predicted by the device theory and the results of the computer simulation are given in Chapter IV. The negative resistance in the I-V characteristics of the III-V compound semiconductor FET is an experimentally well-known fact. The impurity dependence of the mobility has been included in the theoretical calculations. As a result, the effect of the negative resistance on the I-V characteristics of the FETs with highly doped channels becomes negligible. In other words, the negative resistance effect is more pronounced for the lightly doped FETs. It is also known that the negative resistance in GaAs power MESFETs can be reduced using a highly doped material. In addition to the study of the device physics, an accurate modeling of the device is also provided in SIM-GFC programs. The first three levels of the simulation program are devoted to the study of the basic device properties. The fourth level, however, is devoted to the accurate device modeling. To eliminate the errors in the calculation of the device parameter due to the simplifying assumptions, the critical variables such as forward bias voltage, VF, is obtained from the measured dc I-V characteristics and used in the expressions for the small and large signal circuit elements. Tile approximate(l VF values even with a small error, will induce, unacceptably large errors to the values of the calculated device parameters (Cgs, 9m' gds' Cgd). Because the device parameters

-267 are exponentially dependent on the forward bias voltage. The most critical parameter is VF. The extraction of this parameter from the measured dc I-V characteristic improves the device modelling and avoids the large discrepancies between the measured and the calculated device performance. It can be concluded that the device theory predicts all the observed device properties conceptually. To avoid unacceptable errors in calculations of the equivalent-circuit parameters of the TTPT devices, the most critical parameter, VF, is obtained from the measured dc I-V characteristics. The computer program SIN-GFC contains the solution of a very general and flexible analytical device expression, and also an accurate model of the TTPT devices.

CHAPTER VI. CONCLUSIONS AND SUGGESTIONS FOR FURTHER STUDY In the course of this dissertation the following conclusions have been reached: 1. The principles of the operation of minority and the majority carrier TTPT devices are similar. They all involve control of the injected carriers via a junction, an ohmic or an insulated gate electrode. 2. Common device expressions can be used to calculate various TTPT device characteristics (Chapter II). 3. The barrier height of the injecting'jnctions is nonuniform across the source-channel junction. As a result of the non-uniform VF, the current density is also non-uniform across the device thickness. This is true for all TTPT devices. 4. The level of the carrier injection in the GFC-BARITT devices is material dependent. At the same bias conditions, the carrier injection in the same size GFC-BARITT device made of a semiconductor with a smaller energy band gap such as Si is higher than that made of a larger energy band gap material such as InP and GaAs. The carrier injection in SIT devices is not energy band gap dependent. 5. The TTPT devices utilize the saturation velocity, therefore using semiconductors other than silicon to fabricate a TTPT device is not significant. 6. FETs were considered as a special mode of operation of SITs. At low bias voltages, GaAs FETs give the best performance, -268

-269 highest gm and cut-off frequency, but at high bias voltages, InP FETs can operate at the highest frequency and gain due to its higher peak velocity and saturation velocity than those of GaAs FETs. 7. The most critical geometrical parameter in TTPT devices is the source-gate spacing, WGS. If WGS is large, the drain-source current cannot be modulated through the gate voltage. 8. An increase in channel doping concentration decreases the drain-source current, IDS, and the breakdown voltages in GFC-BARITT devices. At high channel doping concentrations, the SIT device operates as a conventional FET. In any mode of operation of a SIT device, increased channel doping reduces the drain-gate and sourcegate breakdown voltages. 9. A small signal model for TTPT devices was developed including the noise figure. 10. A simple non-iterative large signal model was also proposed and demonstrated for the conventional FET device. 11. The principles of operation of various GFC-BARITT devices such as junction and Schottky barrier drain-source type GFC-BARITT devices on Silicon on Sapphire (SOS) have been proven (Chapter V). It was also shown that the GFC-BARITT devices are better than other TTPT devices for digital IC applications. 12. The switching speed if GFC-BARITT devices on SOS was shown to be faster than that of the same size MOSFET, due to its high current capability. In this study, the understanding of the various TTPT and FET device characteristics have been accomplished and their use in highspeed digital circuit applications was proposed and demonstrated.

-270 There are, however, several additional topics which need further exploration. Some of these topics are: 1. A full two-dimensional simulation program to study the potential and also the carrier distribution in TTPT devices. 2. Experimental study of the small and large signal properties of TTPT devices. 3. Fabrication of the same size GaAs, InP and Si TTPT devices to compare their performances. 4. Development of a practical large signal model to use as a design tool for microwave circuit design. 5. Fabrication of small size devices to determine the maximum switching speed of the GFC-BARITT device. 6. Application of III-V compound semiconductor TTPT devices in various high-frequency and high-speed circuits. 7. Study of a GFC-BARITT device as a gate-controlled negative resistance device.

APPENDIX A. FACR METHOD The Fourier Analysis/Cyclic Reduction (FACR) direct method is based on performing a Fourier analysis in one direction (say the xdirection) followed by the solution of the harmonic equations in the other direction, using cyclic reduction [16]. If the boundary conditions are simple enough, then sines and cosines are the eignefunctions of the operator and the harmonic equations are uncoupled. The harmonic equations can then be solved separately and rapidly. Hence, the algorithm is as follows: The harmonic components of the charge are obtained from Fourier analysis of the given charge. Given the harmonic components of the charge, the harmonic equations for the harmonic components of the potential can be solved. The desired potential is then obtained by Fourier synthesis. The simplest finite-difference approximation to Poisson's equation in two dimensions is that obtained from the "five-point" difference formula, namely, ( ts - t2t st + s+1,t s,t( -1 - 2s.t + st+) Hx Hy st s (A.1) O < s < Nx, O < t < Ny where Hx is the mesh spacing along the x-axis, and Hy is the mesh spacing along the y-axis, pst is the potential, and Pst is the charge at each mesh point. -271

-272 To simplify the mathematical description of the method, it is assumed that the mesh is a square (Hx = Hy), and the boundary conditions are periodic in the x-direction and given values in the y-direction. The original difference equations may then be written as ~t-l + Ap.t + ~t+i = qt' O < t < Ny, (A.2) where the vectors t and qt are the potential for the'row t' of the mesh: and right-hand side t pot lit ~Nx-l,t k* ^ q ot qt = lt qNx-1lt The steps of the FACR algorithm are: (i) odd/even reduction, (ii) Fourier analysis on even lines, (iii) recursive cyclic reduction (iv) Fourier synthesis on even lines and (v) solution on the odd lines. FORTRAN programs written by Hockney, POT1 uses FACR to solve the two-dimensional Poisson's equation.

-273 1. Odd/even reduction: Consider the three neighboring t-2 + Att-1 + t qt-1 + At + ft+l equations = t= q t even, (A.3) pt + Aqt+l + t+2 = t+l From the above equations odd lines can be omitted and formulas in Eq. (A.3) is reduced to a single one as in Eq. (A.4): t-2 + (21 - A2). t + t+2 * = qt (A.4) where A is the "five-point" difference operator. The modification is performed by the subroutine RHSE in POT1. 2. Fourier analysis on even lines: A real finite Fourier analysis is performed on the even-line equations according to the transformation: Nx/2-1 1 tc + c (-1)s + s,t 2 2 o,t 2 Nx,2,t k=l c.cos 2rk.s k,t Nx + skt.sin 27n k k,t Nx (A.5)

-274 where the harmonic components are given by Nx-1 c _ 2 7 -2 2r ks ck,t Nx E st cs s Nx S=o and Nx-1 s 2 p 2 ks k,t Nx E st sin NxS=o This is a linear matrix transformation on the original data. Substituting (A.5) into the even-line equations (A.4) and using the finite orthogonality relations of the harmonics one obtains kk,t-2 Xk k,t + k,t+ = t t even, (A.6) * where q and q refer to either the sine or cosine harmonic and 2Trk 4Trk = -2(8 - 8 cos x + cos N) Ny and Nx are the numbers of mesh points along the y-axis. This step is performed by the subroutine FOUR67. 3. Recursive cyclic reduction. The equation (A.6) forms a tridiagonal system and can be solved by the recursive application of the process of cyclic reduction. The cyclic reduction method is better that the Gaussian elimination method for the periodic boundary conditions (less storage). Subroutine CRED does the cyclic reduction in POT1. 4. Fourier synthesis on even lines. The recursive cyclic reduction determines the value of all the harmonic amplitudes of the potential on the even lines of

-275 the mesh. A Fourier synthesis is performed on the even lines to obtain the values of the potential on those lines. Subroutine FOUR67 does the Fourier synthesis. 5. Solution on the odd lines. The solution for the potential on the odd lines can be found from the original odd-line equations in Eq. (A.1) by putting the known values of the neighboring even lines on the right-hand side. Subroutine RHSO rearranges (A.1) by putting known values to the right-hand side and CRED cyclic reduction subroutine is used to solve the potentials on even lines. The program POT1 calculates the two-dimensional potential distribution on a rectangular (x,y) mesh (Nx i Ny) where the mesh spacing may be unequal (Hx f Hy). The number of points computed may be either (N - 1), N or (N + 1), depending on the boundary conditions. In any case, N is restricted to a power of two (Nx = 2IX, Ny = 2IQY The boundary conditions are (i) IBCX = 1. The potential has given values placed on 6o,f and (Nx,t before calling to subroutine POT1. (ii) IBCX = 2. The field is zero at s = 0 and s = Nx. It converts the charges qo,t to qNx-l,t on mesh points zero to Nx-l, to values of potential. (iii) IBCX = 3. All variables are periodic in x, -s,t = 9 Nx-s,t' The routine converts the charges qot to qNx-l,t' initially given on mesh points zero to Nx-l, to values of potential.

-276There are similar definitions for IBCY = 1,2,3. The required inputs to the program are values of IQX, IQY, Hx, Hy, IBCX, IBCY and the charge distribution.

APPENDIX B. SIM-GFC PROGRAM The SIM-GFC program can be used to study the various properties of TTPT devices and FETs. SIM-GFC program can simulate: (A) Different devices; (i) GFC-BARITT device (ii) SIT and (iii) FET. (B) Different device structures; (i) Geometry (ii) Doping (iii) Junction type (iv) Gate type, and (v) Gate insulator type in GFC-BARITT device (C) Different semiconductor devices (i) Silicon (ii) GaAs (iii) InP, and (iv) Others (D) Doping effect on device (i) Performance (mobility and velocity) (ii) Breakdown voltage (iii) Mobility and velocity -277

-278 (E) Different operation temperature effect on (i) Intrinsic carrier density (ii) Energy band gap (iii) Mobility and velocity (F) Dc and small signal equivalent circuit (i) Id vs VDS of a function of VGD (ii) GM, GDS (iii) CGS, CGD' CDS (G) Small signal device performance (i) Maximum available gain (ii) Maximum unilateral gain (iii) Cut-off frequency (g m/-Cgs) (iv) 360 degrees phase difference in frequency (v) Noise figure (vi) Noise measurement (H) Large-signal circuit elements (i) Average ac current in one RF cycle (ii) Average GM, GDS (iii) Average CGS, CGD, CDS (I) Large signal device performance (i) Collector efficiency (ii) Added power efficiency (iii) Power gain

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