Aggressive execution engines for surpassing single basic block execution.

Abstract

The increasing density of VLSI circuits has motivated research into ways to utilize large area budgets to improve computational performance. One promising approach is the exploitation of instruction-level parallelism. This technique is effective only if the amount of instruction-level parallelism present in real applications warrants it, and hardware can be designed to exploit it without sacrificing aggressive cycle times. Early studies suggested that sufficient parallelism exists in numeric applications, and more recent research efforts have concluded that sufficient parallelism exists in real, non-scientific applications to justify processors that will execute more than two instructions per cycle. These studies indicate significant performance improvements are possible using aggressive hardware designs today. Furthermore, they offer the possibility for substantial future gains from exploiting instruction-level parallelism using new microarchitectural models. This dissertation explores instruction-level parallelism and microarchitectural mechanisms to efficiently exploit it beyond what is currently thought to be available. The contributions of this dissertation include an extensive investigation into the availability of instruction-level parallelism, new techniques for exploiting the available parallelism, and insight into simulation methodologies. Preliminary trace-driven investigations demonstrate that a significant amount of parallelism is available for exploitation if the machine is designed to provide sufficient fetch bandwidth and high branch prediction accuracy. Experimental results indicate that dynamic scheduling provides a critical tolerance of imperfect memory hierarchies, but most dynamic selection mechanisms and instruction buffer organizations are adequate. In addition, an aggressive state maintenance mechanism provides a modest but consistent performance advantage. More aggressive hardware-based branch handling techniques provide modest performance improvements at significant hardware costs. These techniques demonstrate that further performance increases can be expected, but suggest that compiler support is required to reduce the hardware costs.