Ultra Low Power Analog Circuits for Wireless Sensor Node System.

Abstract

This thesis will discuss essential analog circuit blocks required in ultra-low power wireless sensor node systems. A wireless sensor network system requires very high energy and power efficiency which is difficult to achieve with traditional analog circuits. First, 5.58nW real time clock using a DLL (Delay Locked Loop)-assisted pulse-driven crystal oscillator is discussed. In this circuit, the operational amplifier used in the traditional circuit was replaced with pulsed drivers. The pulse was generated at precise timing by a DLL. The circuit parts operate in different supply levels, generated on chip by using a switched capacitor network. The circuit was tested at different supply voltage and temperature. Its frequency characteristic along with power consumption were measured and compared to the traditional circuit. Next, a Schmitt trigger based pulse-driven crystal oscillator is discussed. In the first chapter, a DLL was used to generate a pulse with precise timing. However, testing results and recent study showed that the crystal oscillator can sustain oscillation even with inaccurate pulse timing. In this chapter, pulse location is determined by the Schmitt trigger. Simulation results show that this structure can still sustain oscillation at different process corners and temperature. In the next chapter, a sub-nW 8 bit SAR ADC (Successive Approximation Analog-to-Digital Converter) using transistor-stack DAC (Digital-to-Analog Converter) is discussed. To facilitate design effort and reduce the layout dependent effect, a conventional capacitive DAC was replaced with transistor-stack DAC with a 255:1 multiplexer. The control logic was designed with both TSPC (True Single Phase Clock) and CMOS logic to minimize transistor count. The ADC was implemented in a 65nm CMOS process and tested at different sampling rates and input signal frequency. Its linearity and power consumption was measured. Also, a similar design was implemented and tested using 180nm CMOS process as part of a sensor node system. Lastly, a multiple output level voltage regulator using a switched capacitor network for low-cost system is discussed.