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Energy-Efficient Acceleration of Asynchronous Programs.

dc.contributor.authorChadha, Gaurav
dc.date.accessioned2016-06-10T19:31:45Z
dc.date.availableNO_RESTRICTION
dc.date.available2016-06-10T19:31:45Z
dc.date.issued2016
dc.date.submitted
dc.identifier.urihttps://hdl.handle.net/2027.42/120780
dc.description.abstractAsynchronous or event-driven programming has become the dominant programming model in the last few years. In this model, computations are posted as events to an event queue from where they get processed asynchronously by the application. A huge fraction of computing systems built today use asynchronous programming. All the Web 2.0 JavaScript applications (e.g., Gmail, Facebook) use asynchronous programming. There are now more than two million mobile applications available between the Apple App Store and Google Play, which are all written using asynchronous programming. Distributed servers (e.g., Twitter, LinkedIn, PayPal) built using actor-based languages (e.g., Scala) and platforms such as node.js rely on asynchronous events for scalable communication. Internet-of-Things (IoT), embedded systems, sensor networks, desktop GUI applications, etc., all rely on the asynchronous programming model. Despite the ubiquity of asynchronous programs, their unique execution characteristics have been largely ignored by conventional processor architectures, which have remained heavily optimized for synchronous programs. Asynchronous programs are characterized by short events executing varied tasks. This results in a large instruction footprint with little cache locality, severely degrading cache performance. Also, event execution has few repeatable patterns causing poor branch prediction. This thesis proposes novel processor optimizations exploiting the unique execution characteristics of asynchronous programs for performance optimization and energy-efficiency. These optimizations are designed to make the underlying hardware aware of discrete events and thereafter, exploit the latent Event-Level Parallelism present in these applications. Through speculative pre-execution of future events, cache addresses and branch outcomes are recorded and later used for improving cache and branch predictor performance. A hardware instruction prefetcher specialized for asynchronous programs is also proposed as a comparative design direction.
dc.language.isoen_US
dc.subjectAsynchronous program performance and energy-efficiency
dc.subjectHardware-software co-design
dc.titleEnergy-Efficient Acceleration of Asynchronous Programs.
dc.typeThesisen_US
dc.description.thesisdegreenamePhD
dc.description.thesisdegreedisciplineComputer Science and Engineering
dc.description.thesisdegreegrantorUniversity of Michigan, Horace H. Rackham School of Graduate Studies
dc.contributor.committeememberNarayanasamy, Satish
dc.contributor.committeememberMahlke, Scott
dc.contributor.committeememberZhang, Zhengya
dc.contributor.committeememberWenisch, Thomas F.
dc.subject.hlbsecondlevelComputer Science
dc.subject.hlbtoplevelEngineering
dc.description.bitstreamurlhttp://deepblue.lib.umich.edu/bitstream/2027.42/120780/1/gauravc_1.pdf
dc.owningcollnameDissertations and Theses (Ph.D. and Master's)


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