Vertical Integration of Germanium Nanowires on Silicon Substrates for Nanoelectronics.

Abstract

Rapid development of semiconductor industry in recent years has been primarily driven by continuous scaling. As the size of the transistors approaches tens of nanometers, we are faced with challenges due to technological and economic reasons. To this end, unconventional semiconductor materials and novel device structures have attracted a lot of interests as promising candidates to replace the Si-channel MOSFET and help extend Moore’s law. In this dissertation, we focus on chemically-synthesized germanium nanowires, and investigate their potential as electronic devices, especially when vertically integrated on a Si substrate. The contributions of the work are as follows: First, the Vapor-Liquid-Solid method for growing Ge nanowires on (111) Si substrates is explored. In addition to the growth of vertical, taper-free, intrinsic Ge nanowires, strategies for doping the nanowires, forming a radial heterojunction and controlling growth sites are also discussed. Second, the Ge/Si heterojunction obtained via nanowire growth is examined by transmission electron microscopy. We confirm the epitaxial nature of the heterojunction despite the 4% lattice mismatch and determine the transition width to be 10-15 nm. Vertical heterodiodes with independently-tuned doping profile in both Ge and Si are demonstrated. Different devices are obtained, including: (1) a rectifying diode with >1,000,000 on/off ratio and ideality factor of 1.16; (2) a tunnel diode with room temperature negative differential resistance, peak current density of 4.57 kA/cm2 and reversed-bias tunnel current of 3.2 µA/µm; (3) a non-ohmic contact due to large valence band offset between Ge and Si. All observed behaviors are very well supported by theoretical analysis of the devices. In addition, a vertical junctionless transistor with Ge/Si core/shell nanowire channel and surrounding gate is demonstrated. High performance p-type transistor behavior with on state current density of 750 µA/µm and mobility of 282 cm2/V∙s is achieved. Moreover, an analytical model is developed to quantitatively explain the measured data and excellent agreement is obtained. Finally, progress towards the realization of a nanowire tunnel transistor is reported. A physical model for nanowire tunnel transistors is proposed. Preliminary experimental results verified that the device concept works although further optimization is still required to boost its performance.