Resonant -tunneling diodes in high-performance digital circuit applications.

Abstract

This dissertation presents research on the application of resonant-tunneling diodes (RTDs) in multivalued-logic circuits and very-high-speed digital circuits. An RTD-based signed-digit full adder cell is presented in which carry propagation along a chain of adders is eliminated by means of a redundant arithmetic algorithm. RTDs enable efficient implementation of sophisticated multivalued-logic functions. The two-peak negative-differential-resistance (NDR) characteristics of two RTDs connected in series are used to easily detect four voltage threshold levels of a multivalued input signal. The proposed concept was successfully demonstrated via a prototype in which RTDs were connected as external devices to a custom-designed CMOS integrated circuit. A second, fully integrated, prototype was developed using MOS-NDR in a standard CMOS process. MOS-NDR is a new prototyping technique for circuits that combine MOS transistors and NDR devices where NDR characteristics are emulated using only enhancement-mode n-channel MOSFETs. This was the first demonstration of the MOS-NDR technique in multivalued logic applications. A simulation-based study is presented in which performance of bistable logic circuits combining RTDs and III--V transistors is measured as experiment parameters vary. The circuit topology, the type and speed of transistors, and the driven output load are some of the parameters used in the experiments. There are two basic types of topologies for RTD bistable logic circuits: <italic>quantum bistable logic</italic>, where the state acquired after each clocking event is determined by the interaction between RTDs and transistors, and <italic>balanced pair logic</italic>, where the logic state depends on the interaction of two or more RTDs. Two types of compound-semiconductor transistors were considered in the study, namely, heterostructure bipolar transistors and high-electron-mobility transistors. The results of the study indicate that the best circuit configuration combines the balanced-pair logic with high-electron-mobility transistors. The experimental simulation framework developed for this study is not tied to any particular technology or circuit technique, and it can thus be used as a general-purpose tool for circuit evaluation and comparison.