True single-phase adiabatic circuitry for high-performance, low-energy VLSI.

Abstract

Adiabatic design is a promising approach to the realization of VLSI circuits with extremely low energy dissipation. In adiabatic logic families, energy dissipation is kept low by steering currents across devices with low voltage drops and by recycling any undissipated energy stored in capacitors. Due to their complex control requirements, however, adiabatic circuits typically use multiple phase sinusoidal clocks with multiple clock generators. They can thus exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock phase management problems. In this thesis, we present True Single-phase Energy-recovery Logic (TSEL), the first-ever adiabatic logic family that operates with a true single-phase sinusoidal clocking scheme. We also present Source Coupled Adiabatic Logic (SCAL) and Source Coupled Adiabatic Logic with Diode-connected transistors (SCAL-D), two source-coupled variants of TSEL with improved voltage scalability and energy efficiency. To evaluate the energy efficiency and speed potential of TSEL and SCAL, we designed 8-bit Carry-Lookahead Adders (CLAs) in these two logic families, other adiabatic logic styles, and conventional static CMOS using a 0.5 mum standard CMOS process. In HSPICE simulations with post-layout extracted parasitics, our CLAs in TSEL and SCAL function correctly for operating frequencies exceeding 200MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, our single-phase CLAs are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates in the 10--200MHz range, our SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in adiabatic families PAL and 2N-2P, and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts. To demonstrate the practicality of SCAL-D, we used it to design an 8-bit multiplier and associated BIST logic in a 0.5 mum standard CMOS process. Our design was fabricated through MOSIS. Although our multiplier was designed as conservatively as possible, at the expense of ignoring some energy consumption or performance optimizations, it outperformed corresponding designs in static CMOS operating with supply voltages scaled for minimum energy dissipation. In HSPICE simulations with distributed RC parameters extracted from layouts, our SCAL-D multiplier was 1.4 to 3.6 times more energy efficient than 2-, 4-, and 8-stage pipelined multipliers in static CMOS in the 50--200MHz range. The correct operation of our 8-bit SCAL-D multiplier was verified experimentally for operating frequencies up to 130MHz. Moreover, its power dissipation was measured in the 40--130MHz range for a sinusoidal power-clock of amplitude 3.0V and a constant supply voltage of 3.0V. Measured energy consumption correlated well with HSPICE simulation results for the same operating frequencies, power-clock amplitude, supply voltage, and biasing voltages.