Noise modeling, evaluation and noise -tolerant design of very deep submicron VLSI circuits.

Abstract

Continuous semiconductor technology scaling has brought the digital circuit noise problem to the forefront. This dissertation investigates the noise problem from three aspects: study the sources of noises and develop fast and accurate noise models; study impacts of noises on digital circuit functionality and performance; and develop effective circuit techniques to improve the noise tolerance of VLSI systems. The first part of this dissertation addresses the noise modeling problem for interconnect coupling noises, the dominant source of noises in deep submicron VLSI chips. We have developed a complete framework for crosstalk noise modeling in the presence of multiple aggressors. A coupling-point admittance based circuit reduction technique has been proposed for modeling quiet aggressor nets. We have also developed a tree branch reduction method modeling effects of resistive shielding. Furthermore, a double-pole based formula has been derived for analytical modeling of reduced circuits leading to much improved accuracy than existing methods. The second part of this dissertation studies the impact of' noises on circuit functionality. We have proposed a maximum square based dynamic noise margin calculation method and developed associated noise margin models to reduce the pessimism of static noise analysis. It is further noted that existing worst-case noise margin based analysis is becoming overly pessimistic. Therefore, we have developed a novel multiple dynamic noise margin based method, which allows lending or borrowing of noise margins between subsequent logic stages. This method avoids excessive flagging of false noise violations and thereby greatly reduces design convergence time. The third part of this dissertation describes a novel technique to resolve noise violations by improving the noise tolerant of critical logic gates. We have identified a key property of the keeper network of dynamic logic gates, which opens the possibility for circuit noise immunity improvement without a proportional increase in gate delay. We have used a class of circuits having the folded-back I-V characteristic in the keeper network of dynamic logic gates and demonstrated that the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained.