Low energy memory design.

Abstract

The increasing demand for data intensive applications has increased the needed memory for each computation. Thus, the contribution of the memory hierarchy to the total power dissipation of a computer system is increasing. This thesis focuses on low power VLSI design methodologies that reduce the power dissipation of DRAM and SRAM. DRAM is used extensively in typical portable devices owing to its high density and thus is one of the major dissipative modules of such hand-held devices in standby mode. We propose a method to reduce DRAM data retention power for performing periodic refresh by increasing the effective refresh period. Our approach exploits the large difference in required refresh period of DRAM cells to reduce the DRAM data retention power. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst-case data retention times. Long periods are used to accommodate cells with small leakage. We propose a polynomial time refresh period search algorithm along with a low overhead implementation. We discuss the effect of process variation on the power savings. Experimental results show power savings in the 4x range. Owing to its high operating speed, large amounts of SRAM are used as on-chip memories and constitute a large portion of the processor dissipation. We present energy recovery techniques for lowering SRAM dissipation by reusing the energy stored in the highly capacitive wires such as word and bit lines. Powered by a single-phase sinusoidal <italic>power-clock</italic>, a special resonant power source implementing energy recovery, our SRAM delivers read and write operations with single-cycle latency. A simple control circuit is used to maintain driver operation in synchrony with the power-clock waveform. Feedback from the driver output to the control circuit ensures that our driver remains efficient, independent of the access pattern. A test chip designed and tested to demonstrate the practicality of our scheme shows correct operation of energy recovery memory. The efficiency of the power-clock generator is largely influenced by the variance of its load capacitance. We have developed methods to provide an unperturbed power-clock that relies on reducing the effective or actual memory load variance. For the various variants of our energy recovery technology, power savings are in the 1.7x--2x range.