Analysis and minimization of leakage current.
Lee, Dongwoo
2005
Abstract
Among several metrics for system performance, power consumption has become a major criterion. As voltage and process are scaled down, leakage power has become more significant. Aggressive scaling of operating voltage and process requires the reduction of threshold voltage (<italic>V<sub>t</sub></italic>) and gate oxide thickness (<italic>T<sub>ox</sub></italic>) for good circuit performance. These reduced <italic>V<sub>t</sub></italic> and <italic>T<sub> ox</sub></italic> result in a dramatic increase in subthreshold leakage current (<italic>I<sub>sub</sub></italic>) and gate tunneling leakage current (<italic> I<sub>gate</sub></italic>). In addition to standby mode, leakage power during runtime mode needs to be considered in high performance designs. In our research, we developed a new circuit level estimation method for <italic> I<sub>gate</sub></italic>. The interaction between <italic>I<sub>sub</sub></italic> and <italic>I<sub>gate</sub></italic> is considered in this analysis, as is the impact of <italic>I<sub>gate</sub></italic> on circuit behavior. Based on this analysis, we propose a new <italic>I<sub>gate</sub></italic> minimization technique through state assignment and pin reordering. Because <italic>I<sub> gate</sub></italic> depends on the position of conduction devices, pin reordering results in the substantial reduction of <italic>I<sub>gate</sub></italic>. In addition, we proposed a new approach for leakage current minimization including both <italic>I<sub>sub</sub></italic> and <italic>I<sub>gate</sub></italic>. Our proposed method combines the input state dependence of leakage current and dual-<italic>V<sub>t</sub></italic>/dual-<italic>T<sub>ox</sub></italic> technology. The simultaneous state, <italic>V<sub>t</sub></italic> and <italic> T<sub>ox</sub></italic> assignment approach uses the basic observation that with a specific input state only some of transistors which are responsible for <italic>I<sub>sub</sub></italic> or <italic>I<sub>gate</sub></italic> need to be assigned to high-<italic>V<sub>t</sub></italic> or thick-<italic> T<sub>ox</sub></italic> under delay constraint. This allows for a significant improvement in leakage-delay trade-off. Heuristics for the proposed approaches achieve 5X (for <italic>I<sub>sub</sub></italic> only) and 6X (for both <italic> I<sub>sub</sub></italic> and <italic>I<sub>gate</sub></italic>) leakage reduction over traditional methods. Finally, a new runtime leakage minimization approach is proposed. Instead of fixed input states, we introduce the use of state probabilities. We combine <italic> V<sub>t</sub></italic>-<italic>T<sub>ox</sub></italic> assignment with state probabilities in order to improve the leakage-delay trade-off in runtime mode. For further leakage reduction, circuit resynthesis is also introduced. The proposed state probability-aware method improves leakage current by an average of 30% over the traditional state probability-unaware method. The proposed method, combined with circuit resynthesis, achieves an average of 57% runtime leakage reduction.Subjects
Analysis Dual Threshold Voltage Gate Current Leakage High-performance Circuits Leakage Current Minimization Oxide Thickness
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