Power reduction in digital systems through local resonant clocking and dynamic threshold MOS.

Abstract

Growing power dissipation and clock instability are resisting the continued scaling of high-performance microprocessors. Power dissipation currently exceeds 100 W, even after incorporating power reduction techniques (such as clock gating and dynamic voltage and frequency scaling) once implemented solely in low-power microprocessors. In high-performance microprocessors, about 20-25% of power is dissipated in the last latch stage of the clock distribution, about 5% in the global clock distribution, and another 50% in the logic switching. Jitter, a clock instability measurement, is becoming a larger percent of the clock period; it increased from 3% to 5% of the clock cycle from IBM's POWER4 to its POWER5 microprocessors. The added buffering and de-skew logic needed to distribute the clock, and the shorter clock period, caused the increase. Local resonant clocking and Dynamic-Threshold MOS (DTMOS) are methods proposed to reduce clock power dissipation and fitter, and logic switching power, respectively. In this local resonant clock, the global clock distribution is replaced by a harmonic oscillator, whose capacitance is composed of the local parasitic clock distribution. Clock energy resonates between the capacitance of the local clock distribution and the inductors of the harmonic oscillator, providing a combined clock generation and distribution with low-jitter and low-power. In this work, the theory of local resonant clocking is developed including its sources of instability. Using off-chip inductors, a small 140-MHz local resonant clock was built and tested in an IBM 0.13-mum Silicon-on-Insulator (SOI) technology. Measurements show it dissipates 8% less power than a comparable traditional distribution at an equivalent frequency. Its best-case period jitter, with random data switching through the circuits in the clock load, is 42 ps, compared to 104 ps in the traditional distribution. Based on my results, additional studies of skew management and synchronization of multiple clock domains are warranted; several local resonant clocks would be needed to cover the clock distribution of a microprocessor. In DTMOS, the body of the SOI transistor is dynamically controlled during circuit operation, providing low leakage when the transistor is off, and high current when it is on. Simulations and measurements of implemented circuits, using 0.13 gm SOI, demonstrate that DTMOS can be faster and more energy efficient than CMOS under combinations of the following conditions: <italic>V_dd</italic> < 0.8 V, 0.5 < <italic>V_bs</italic> < 0.7 V, the transistor width is greater than 20x minimum, there are large capacitive loads, and high fan-in. This dissertation demonstrates that local resonant clocking and DTMOS should be considered as tools for reducing power and improving clock stability in VLSI systems.