Constructive multi-level synthesis by way of functional properties.

Abstract

Conventional logic synthesis technology has been a critical factor in improving design productivity over the past decade and a half. It is now widely acknowledged that this trusted technology evolve to handle the challenges and opportunities of finer-featured fabrication processes. Ideally, the time wasting iteration between logic and layout synthesis in today's design methodologies could be eliminated by fusing these two stages simultaneously optimizing the logical structure as well as spatial placement of a circuit. This, however, may be a tall order due to the computational complexity of these tasks. We propose an alternative goal: to more directly relate the functional structure of a logic specification to the ultimate topological and physical structures of its physical realization. Our synthesis approach is based on three novel ideas. First, synthesis is done incrementally by interleaving technology-independent optimization with technology mapping to a specific library. The second novel idea, is that the content of a cell library (the functional variety of its primitives) can be pre-computed to improve quality of synthesized circuit. We develop a symbolic decomposition theory that identifies the types of logic functions that must be available in a cell library to guarantee desirable decompositions of a set of logic specifications. And thirdly, we exploit the semantic structure of a specification (symmetry in particular) during decomposition and mapping to obtain compact implementations. Specifically, a variety of symmetries is quickly identified and used to guide the synthesis process. Our strategy enables us to obtain a high quality circuits, with improved delay. The improved quality of the implementations is the result of a coordinated strategy that incrementally infers decomposition decisions from a functional structure.