Resonant clock generation and distribution.

Abstract

Resonant clocking is an attractive alternative to conventional clocking due to its significant potential for reducing clock power. Typically, resonant clock systems rely on sinusoidal clock signals to synchronize timing elements. Clock generation and distribution are particularly important in these systems, because unlike their conventional counterparts, they do not use square clock waveforms or buffers. We have evaluated clock skew in resonant H-shape clock distribution networks with sinusoidal waveforms. We suggest a number of practical design guidelines for low-skew and low-power resonant clocking through a systematic investigation of the impact of width, spacing, and loading of the clock tree on clock skew and power. Simulation results show that compared to conventional clock distribution methodologies in high performance processors, properly designed resonant clocking provides low power and comparable or better skew. Furthermore, simultaneous improvements in skew and power of resonant clocking are possible through width scaling. Energy dissipation and timing properties of conventional and resonant clock system are also explored. Our results show that a resonant clock network consumes 82% less power than its conventional buffered clock counterpart while maintaining better skew and delay. Considering the power of the clock network and flip-flops, the resonant clock system can achieve 51% to 61% less power than the conventional system, depending on input data switching activities. A resonant clock network comprising of an array of distributed clock domains and generators is also explored to overcome synchronization issues in large-scale resonant clock distribution. We have designed a deskewing circuit to synchronize two resonant clock domains. The methodology can achieve less than 7ps skew between the two clock domains. To further explore resonant clocking, we have also designed and evaluated a two-phase resonant clock generation and distribution chip with programmable driver and loading in a 0.13mum process. Test results show that the resonant clock system can achieve 45% relative power savings over conventional <italic> CV</italic><super>2</super>. When running off-resonance by 10%, power dissipation increases by 3% and clock amplitude drops by 3%. Imbalanced loading impacts power and amplitude by less than 2%. When shifting from balanced to imbalanced loading, skew increases by 6% of cycle time.