Low -power VLSI design under multiple sources of uncertainty.

Abstract

While technology scaling has enabled the design of complex information systems, uncertainty in the VLSI design process has emerged as one of the significant challenges to the successful application of these systems in the nanometer regime. This loss of predictability is primarily due to process variations that occur due to a mismatch between the manufactured parameters on the chip and the design specifications. Larger numbers of transistors combined with high area densities have resulted in wires being in close proximity of one another thereby producing increased amounts of signal interference. In addition, for future technologies, soft errors arising due to cosmic particle strikes significantly influences the signal integrity of the chip. At the same time, chip power consumption has increased exponentially over the past few technology nodes. For sub-100nm feature sizes, leakage constitutes a major fraction of the total power dissipation. The presence of variability further exacerbates this problem since leakage current has exponential relationships with the process parameters. It has therefore become necessary to consider power consumption as a first-class design constraint in CMOS design. In our research, we focus on the modeling and design of low-power VLSI systems while accounting for multiple sources of uncertainty. First, we present a statistical chip-leakage current model that describes the dependence of the leakage current distribution on different process parameters. Using this model, we then develop an integrated approach for parametric yield analysis when both frequency and power limits are imposed on a design. Next, we present two approaches towards low-power interconnect design. For on-chip busses, we propose a method that combines bus encoding and selective use of dual-Vth devices to minimize the total (dynamic and leakage) power. For short-range signal nets we present a buffer insertion algorithm that produces entire tradeoff surfaces so that the designer can pick an optimal solution point. Finally, we present an efficient linear-time algorithm for soft-error rate (SER) analysis of combinational logic circuits. We use this analysis engine to propose sensitivity-based optimization approaches for mitigating logic SER at the circuit level.