Exploiting interactions between integrated circuit design and manufacturing.

Abstract

In this thesis, three major issues related to process variation in integrated circuits in the subwavelength lithography regime are investigated; (1) pattern-dependent linewidth variation under defocus, (2) impact of metal fills on interconnect for chemical-mechanical polishing (CMP) to suppress inter-layer dielectric (ILD) thickness variation, and (3) non-rectilinear gate and diffusion shape for post-lithography simulations (PLS). Critical dimension (CD) variation caused by defocus in the lithographic process is largely systematic with CD of dense lines increasing through focus while isolated lines decrease. In this thesis, we propose a new design methodology that allows explicit compensation of focus-dependent CD variation in particular, either within a cell or across cells in a critical path. Results indicate that designing with a self-compensated cell library incurs 12% area penalty and 6% leakage increase over a baseline library while compensating for focus-dependent CD variation. Both the heuristic and MILP optimization approaches show 3% area penalty while maintaining timing. Inserting dummy metal fill to improve ILD thickness planarity after CMP is an essential part of the modern design process. However, the inserted fill shapes impact the performance of signal interconnect by increasing capacitance. We analyze and model the impact of the floating metal dummy on signal capacitance with various parameters. Based on an analysis of fill impact on capacitance, we propose simple capacitance increment models both for intra-layer dummy and inter-layer dummy that lead to high accuracy and efficiency in post-fill parasitic extraction. Existing CAD tools and device models cannot handle complicated non-rectilinear geometries although as-printed transistor shapes are no longer perfect rectangles due to effects such as line edge roughness. We present a transistor-level optimization method involving reshaping the channel to create an optimized device that is superior in both delay and leakage to the original device by employing a location-dependent threshold voltage model. The impact of diffusion rounding on circuit performance is also investigated. Simple weighting function models for I_on and I_off to account for the diffusion rounding effects are proposed. The power and performance characteristics of devices with line-end shortening (LES) are studied. Our simulations indicate that LES does not always affect device functionality.