Gallium arsenide MESFET static RAM design for embedded applications.

Abstract

This work describes circuit structures and design methodologies needed to achieve higher performance, lower power, process tolerant embedded static RAMs and digital circuits using E/D MESFETs in GaAs. A novel current mirror memory cell (CMMC) is presented that achieves memories with a smaller cell area, faster read and write times, and more reliable operation than is possible using a conventional memory cell. This cell achieves the maximum suppression of leakage currents using a single 2-V supply voltage. We describe two SRAM implementations and their testing results. Fault models and testing procedures are presented for the CMMC. Several circuit design and characterization methodologies are described that are needed to achieve robust circuits in processing technologies with low noise margins. We present a low-power logic style, called Power Rail Logic (PRL), which can achieve up to 40% lower power-delay products than equivalent DCFL circuits. Test results for a demonstration vehicle for this logic style are presented. We also present the Aurora RAM Compiler (ARC) that uses the process tolerant design methodologies, the new memory cell, and the new logic style described in this thesis. The compiler iteratively optimizes an SRAM using HSPICE for calculating delays, power dissipation, and signal noise margins. The compiler was built using a flexible design framework that can easily adapt with minimal effort to characterize memories in different MESFET processes.