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Design of ultrafast digital circuits using quantum electronic devices.

dc.contributor.authorMohan, Sundararajarao
dc.contributor.advisorMazumder, Pinaki
dc.date.accessioned2016-08-30T17:10:40Z
dc.date.available2016-08-30T17:10:40Z
dc.date.issued1995
dc.identifier.urihttp://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqm&rft_dat=xri:pqdiss:9527703
dc.identifier.urihttps://hdl.handle.net/2027.42/129550
dc.description.abstractQuantum electronic devices such as resonant tunneling diodes (RTDs) and transistors (RTTs) have very high switching speeds and certain unique I-V characteristics that can be used to design ultrafast and compact digital circuits. This thesis describes the design of several basic circuits based on the Negative Differential Resistance (NDR) characteristics of these devices and the use of these basic circuits in larger systems. Circuit design methodologies and design tools including a circuit simulator and a design optimizer are presented. The new NDR device models presented here are internal models incorporated into the NDR-SPICE circuit simulator, along with algorithms for improved convergence in the presence of piecewise continuous NDR characteristics. Five-fold speed improvements over the conventional macro-modeling approach have been observed and the accuracy of the simulation has been verified through measurements on several circuits. The NDR-SPICE simulator has been used in the design and validation of new logic families based on compact self-latching circuits. The true-bistable logic family implements complex functions such as a self-latching majority function in a single gate consisting of four active devices. In conjunction with the high intrinsic switching speeds of the resonant tunneling devices, this increased functionality leads to very high system speeds because of reduced interconnect delay and smaller number of logic stages. A new logic style known as nanopipelining has been developed to take full advantage of the high switching speeds and self-latching property of the true-bistable logic gates. A nanopipelined binary adder has been designed to achieve throughputs of one 32-bit addition every 1.6 ns using just around 30 gates. This design style has been extended to combinations of the more easily manufacturable RTDs with HBTs and FETs.
dc.format.extent162 p.
dc.languageEnglish
dc.language.isoEN
dc.subjectCircui
dc.subjectCircuits
dc.subjectDesign
dc.subjectDevic
dc.subjectDevices
dc.subjectDigital
dc.subjectElectronic
dc.subjectQuantum
dc.subjectResonant Tunneling
dc.subjectUltrafast
dc.subjectUsing
dc.titleDesign of ultrafast digital circuits using quantum electronic devices.
dc.typeThesis
dc.description.thesisdegreenamePhDen_US
dc.description.thesisdegreedisciplineApplied Sciences
dc.description.thesisdegreedisciplineComputer science
dc.description.thesisdegreedisciplineElectrical engineering
dc.description.thesisdegreegrantorUniversity of Michigan, Horace H. Rackham School of Graduate Studies
dc.description.bitstreamurlhttp://deepblue.lib.umich.edu/bitstream/2027.42/129550/2/9527703.pdf
dc.owningcollnameDissertations and Theses (Ph.D. and Master's)


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