Architectural macro-modeling of processor memory components.

Abstract

It is important for contemporary computer architects to rapidly assess the performance of their designs. Existence of accurate models for processor components goes a long way towards making this possible. In this thesis, macro-modeling techniques that have been developed for single gates are extended to model processor memory components. Specifically, multi-ported register files and content addressable memories are considered. Models for area, delay, and power dissipation are developed. The macro-models for area are based on layout geometry and register file organization--number of inputs, outputs, and total bit capacity. The macro-models for delay and power combine layout geometry and organization with circuit equations. The resulting macro-models relate register file organizations directly to area, delay, and power dissipation. Several register file layouts were designed and created. The areas were measured and their delay were determined from SPICE simulations. These figures were compared to the macro-models and were shown to agree fairly closely. The macro-models are thus able to provide the designers with a technique to quickly explore the impact of architectural alternatives such as the organization of a register file or content addressable memory on cost (area), speed (delay), or power dissipation. Research in computer architecture has rarely considered the limits imposed by the physical properties of the circuit technology on the performance. In this thesis we have started this process by developing models for the processor memory components, particularly multi-port register files. To illustrate how they can be used we evaluate the performance of some published super-scalar architectures which ignore the effects of multi-port register files. We show that the large numbers of ports needed to support a multi-function unit super-scalar processor can slow the cycle time significantly.