Modern DRAM architectures.

Abstract

Dynamic Random Access Memories (DRAM) are the dominant solid-state memory devices used for primary memories in the ubiquitous microprocessor systems of today. In recent years, processor frequencies have grown at a rate of 80% per year, while DRAM latencies have improved at a rate of 7% per year. This growing gap has been referred to as the Memory Wall. DRAM architectures have been going through rapid changes in order to reduce the performance impact attributable to this increasing relative latency of primary memory accesses. This thesis examines a variety of modern DRAM architectures in the context of current desktop workstations. The DRAM examined include those which are available today, as well as a number of architectures which are expected to come to market in the near future. Two simulation methodologies are used in comparing system architectures. DRAM models common to both methodologies have been developed for these experiments, and are parameterizable to allow for variation in controller policy and timing. Detailed statistics about the DRAM activity are maintained for all simulations. Experiments examining the underlying performance enhancing characteristics of each architecture are described, with attention to parameters and results. The choice of DRAM architecture and controller policy are shown to significantly affect the execution of representative benchmarks. A 75% reduction in access latency (128 Byte L2 line) from a PC 100 architecture, and a 34% reduction in execution time from a PC 100 architecture result from using a cache enhanced DDR2 architecture. More significant results examine which aspects of the DRAM contribute to the increase in performance. Bus utilization, effective cache hit rate, frequency of adjacent accesses mapping into a common bank, controller policy performance, as well as access latency are examined with regard to their impact upon execution time. Not only are the highest performance DRAM determined, the factors contributing to their low latencies and execution times are also identified.