Electrical characteristics of top-gate staggered amorphous silicon thin-film transistors.

Abstract

Top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) have advantages for reducing gate-line resistance, simplifying fabrication processes, and reducing a-Si:H film thickness for active-matrix liquid-crystal displays (AMLCDs). In this work, a detailed investigation is conducted of top-gate a-Si:H TFTs. From the analysis of static electrical characteristics, we established that the source/drain ohmic-contact quality of top-gate a-Si:H TFTs can be comparable to that obtained for bottom-gate a-Si:H TFTs, with a contact resistance value of about 0.18 $\Omega$-cm$\sp2$. For an a-Si:H TFT-LCD technology using TFTs with a channel length of 10 $\mu$m, the series resistance contributes about 25% to the total drain-to-source resistance. We have demonstrated that top-gate a-Si:H TFTs having a high-performance ($\mu\sb{FE}\approx0.75$ cm2/Vsec, $V\sb{T}$ = 3.5 V, and $S \approx 0.55$ V/dec) can be fabricated over large-area ($400 \times 500$ mm$\sp2$) glass substrates with an a-Si:H thickness of 1300A. We have also shown that electrical performance of top-gate a-Si:H TFTs is not affected by the a-SiNx:H thickness. However, the electrical performance of TFTs degrades as the a-Si:H film thickness is reduced. From the dynamic characteristics study, analytical expressions are derived to compare the calculated data with the experimental results. A good agreement between the experimental and calculated results have been obtained for our devices. Our results indicate that top-gate a-Si:H TFTs charging performance is a-Si:H thickness dependent. We have also shown that the feed-through voltage characteristics of top-gate a-Si:H TFTs can be well described by the simple equations, if the intrinsic capacitance and the overlap capacitance are incorporated into the analytical equations. The electrical instability of top-gate a-Si:H TFTs is investigated by bias-stress-stress experiments with different stress time, stress voltage, and stress temperature, and semi-empirical equations are established to describe the threshold voltage shift ($\rm\Delta V\sb{T}$). In addition, the experimental results indicate that, positive gate-bias stress mainly causes defect creation, while negative gate-bias stress induces both deep-gap states creation and charge trapping that compensate each other in terms of the threshold voltage shift. The deep-gap states are Si dangling bonds localized at or near the a-Si:H/a-SiNx:H interface.