Design considerations for low phase jitter clock generators.
Stetson, Philip Sean
1998
Abstract
Clock distribution networks are becoming increasingly more difficult to design in each successive microprocessor generation. The increased die size, power dissipation, system complexity, and device density all contribute to the problem. Both clock skew and phase jitter are primary issues in the clock distribution network design. This work examines the problem of phase jitter and contains an in-depth discussion of microprocessor clock generation. The basic fundamentals of phase-locked techniques are discussed, followed by a discussion on the origination and propagation of phase jitter within a phase-locked loop clock generator. An analytical method for estimating phase jitter is explained. A circuit-level phase jitter simulation methodology, developed as part of this research work, is discussed. The method produces a more accurate estimate of the phase jitter than the analytical method, and provides a means to include oscillator phase jitter within phase-locked loop transient simulations. The research includes two detailed clock generator designs. Design trade-offs and circuit techniques for low voltage, low phase jitter circuits are discussed. The current-steering amplifier is introduced as a key circuit in such designs. Measured test results are reported for two phase-locked loop clock generator designs. A Complementary GaAs clock generator achieves 800 MHz operating frequency at a 1.5 V power supply with 120 ps peak-to-peak phase jitter. This clock generator represents the first ever such design implemented in the CGaAs technology. The reported performance exceeds that of several CMOS designs reported during the same timeframe. The design was presented at the 1996 GaAs IC Symposium. A 0.5 $\mu$m CMOS clock generator, designed for low-voltage and low-phase jitter applications, achieves 700 MHz operation at a 1.8 V power supply, and 9.35 ps of RMS cycle-to-cycle phase jitter. The clock generator was implemented in Hewlett Packard's 0.5 $\mu$m CMOS process through the MOSIS fabrication service. The design aggressively pushes the technology and attains its performance through low-voltage, noise-tolerant circuit design techniques. An alternative to phase-locked loop clock generators is explored. The delay-locked loop topology is applied to clock generation with the addition of a frequency multiplication stage. The phase jitter inherent to the delay-line is compared to that inherent in an oscillator. The results show that the phase jitter of these blocks is highly dependent upon the particular delay stage used in the design. The current-steering amplifier is shown to provide lower phase jitter with a delay-line than with an oscillator. The delay-locked loop is shown to be a viable clock generator topology.Subjects
Clock Generators Considerations Delay Locked Loops Design Gallium Arsenide Low Phase Jitter
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