Simulation and emulation of digital integrated circuits containing resonant tunneling diodes.

Abstract

In this dissertation, a framework for evaluating the resonant tunneling diode (RTD) technology using a combination of simulation and prototyping methods is proposed. For quasi-static simulation of RTD circuits, we use SPICE. After adding the RTD's physics-based model to SPICE's device library, it becomes obvious that the Newton-Raphson method used in the simulator along with the convergence aids like Gmin-stepping and source-stepping are not adequate for handling the negative differential resistance (NDR) in the RTD's current-voltage characteristics. Both direct current (DC) and transient simulation of RTD circuits encounter convergence problems in SPICE. To solve these problems, we suggest several methods and modify the source code of SPICE (version 3f5) to implement them. Our methods include a current iteration method, a new continuation method, an automatic time-step adjustment method and a modification of SPICE's voltage prediction scheme for solving DC and transient convergence problems. RTDs being the fastest switching semiconductor devices, digital circuits built using them are expected to operate at speeds of 10--100 GHz and possibly beyond. While quasi-static simulation of RTD circuits can be used for verifying circuit concepts at slow speeds, using such methods to simulate circuits operating at extremely high speeds is meaningless. Interconnect effects such as crosstalk, dispersion, reflection, and ringing will dominate circuit behavior. What is necessary is a full-wave simulation of these circuits based upon the solution of Maxwell's curl equations in three-dimensions. To this end, we have developed VEDICS---a time-domain full-wave simulator for RTD-HBT (heterojunction bipolar transistor) circuits that can run on a distributed network of workstations. This simulator, based upon the FD-TLM method, combines lumped nonlinear device models with the interconnects and package walls. We present an example of analyzing the layout effects of multi-gigahertz RTD-HBT circuit using VEDICS. For system-level appraisal of RTD circuit concepts such as <italic>nanopipelining </italic>, a prototyping technique is of central importance. With respect to RTD-CMOS circuits, we investigate the currently available methods of prototyping and present our own particular method which is vastly superior to the state-of-the-art. Using MOSFET-based RTD emulation circuits, we propose an inexpensive way to fabricate large-scale circuits using standard CMOS processes.