A low-cost, high-bandwidth I /O transceiver based on switched -current techniques.

Abstract

Modern microprocessors require high-bandwidth, low-power interfaces to memory in order to fully realize the benefits of IC scaling. There is significant pressure to increase both I/O signal counts and frequencies in order to maximize system performance. The main obstacles to increasing the number of I/O signals are package cost and power dissipation, while timing and noise limit the data transfer rates. This work examines these problems in light of projections for I/O signal counts and frequencies. The objective of the work is to reduce the cost of chip-to-chip high-bandwidth signaling while addressing these future constraints. The types of noise present in a high-frequency I/O interface are discussed, followed by an in-depth discussion of research in I/O transceiver design. A complementary gallium arsenide (CGaAs) multichip module (MCM) implementation of the PowerPC architecture is described. The CGaAs technology has low integration levels that require high chip I/O counts. Early work exploring the semiconductor and packaging technologies is described, including the design of three CGaAs test chips and a prototype MCM. The culmination of the CGaAs work is the design of an I/O interface having a novel switched-current transceiver and low-jitter delay-locked-loop (DLL). The primary metric to be optimized was the bandwidth/power ratio; the goal was to bring Gb/s signaling into the low-milliwatt range. This goal was met with a switched-current I/O transceiver. Simulations indicate that the design can support bit-rates up to 1.2 Gb/s/pin while dissipating 4.5 mW from a 1.5 V supply. A low-jitter 500 MHz CGaAs DLL was designed to provide receiver clocking. The challenges surrounding low-jitter circuit design are discussed in light of the low voltage headroom afforded in CGaAs. Simulations predict that the DLL design would dissipate 25 mW of power from a 1.5 V supply at 500 Mhz, with 88 pS of peak-to-peak jitter. A 0.5 mum CMOS implementation of the switched-current transceiver circuit is presented. The transceiver actively terminates a transmission line to its characteristic impedance using an active current mirror. Relying on small current signals, the transceiver generates little self-induced noise, and requires little voltage headroom. A dynamic biasing network is described that compensates for process variations and low-frequency supply noise. Measured results indicate that the CMOS circuit can support a 910 Mb/s data-rate, while dissipating 6 mW from a 2.5 V supply. With the dynamic biasing network enabled, the receiver is functional between minimum and maximum supply voltages of 2.25 V(880 Mb/s, 5 mW) and 3 V (1.05 Gb/s, 9 mW) respectively. The circuit meets the objectives and provides high-bandwidth at a low cost in power, complexity, and area.