Low-power Volatile and Non-volatile Memory Design

Abstract

Embedded memories play a pivotal role in VLSI systems to support the increasing need of data storage in various applications. With technology scaling, memory cell size gets significantly minimized in order to boost the storage capacity. Over half of area in advanced VLSI systems are occupied by embedded memories, especially 6T SRAM which provides fastest performance than others. However, VDDmin of 6T SRAM doesn't scale well in advanced technologies. As a result, 6T SRAM dominates power consumption in advanced VLSI systems like data centers and IoTs which have growing need for large amount of low-power memories. This thesis presents several circuit and system solutions to reduce power consumption of different types of embedded memories, varying from volatile SRAM to non-volatile memories such as NOR flash and STT-MRAM. We first describe a 5T SRAM with one transistor less than conventional 6T SRAM. It not only achieves 7.2% area saving than 6T but also improves read margin by decoupling read/write paths. With single-port read with improved read VDDmin, access energy gets significantly reduced. 4Mb of 5T SRAM is applied to a face-recognition machine-learning accelerator. Second, a 4+2T SRAM cell that uses the N-well as a write wordline is proposed with 15% area saving than 8T SRAM. Decoupled differential read paths significantly improve read noise margin, achieving 0.25V VDDmin and 4fJ/bit access energy. Moreover, reliable multi-word activation is realized for in-memory-computing and BCAM/TCAM applications. Third, we present a 1Mb sub-100μW embedded NOR flash for battery-powered miniature sensor-node system. Multiple low-power circuit techniques are applied to the high-voltage generation and delivery system and a margin-doubled cross-sampling current sense amplifier is proposed. Measurements in a 90nm embedded flash technology show 30× and 22× lower program and erase energy, respectively, compared with a standard flash compiler macro. Fourth, a low-power STT-MRAM in 28nm technology is described. A single-cap based offset-cancelled sense amplifier is proposed to improve sensing margin, and in-situ self-termination write method is used to save write power. We achieve 2.8ns read access time, and over 30% write power consumption is reduced with the proposed write method. Finally, we explore the feasibility of applying the emerging non-volatile spintronic memory devices into two analog computing applications: analog-to-digital converter and neural network. The analog-to-digital converter using racetrack nanowire can be 1000× smaller than conventional implementation using CMOS. With compact racetrack converter as the neuron, spin rectified-linear and recurrent neural networks can be realized.