Design of Digital FMCW Chirp Synthesizer PLLs Using Continuous-Time Delta-Sigma Time-to-Digital Converters

Abstract

Radar applications for driver assistance systems and autonomous vehicles have spurred the development of frequency-modulated continuous-wave (FMCW) radar. Continuous signal transmission and high operation frequencies in the K- and W-bands enable radar systems with low power consumption and small form factors. The radar performance depends on high-quality signal sources for chirp generation to ensure accurate and reliable target detection, requiring chirp synthesizers that offer fast frequency settling and low phase noise. Fractional-N phase locked loops (PLLs) are an effective tool for synthesis of FMCW waveform profiles, and advances in CMOS technology have enabled high-performance single-chip CMOS synthesizers for FMCW radar. Design approaches for FMCW chirp synthesizer PLLs need to address the conflicting requirements of fast settling and low close-in phase noise. While integrated PLLs can be implemented as analog or digital PLLs, analog PLLs still dominate for high frequencies. Digital PLLs offer greater programmability and area efficiency than their analog counterparts, but rely on high-resolution time-to-digital converters (TDCs) for low close-in phase noise. Performance limitations of conventional TDCs remain a roadblock for achieving low phase noise with high-frequency digital PLLs. This shortcoming of digital PLLs becomes even more pronounced with wide loop bandwidths as required for FMCW radar. To address this problem, this work presents digital FMCW chirp synthesizer PLLs using continuous-time delta-sigma TDCs. After a discussion of the requirements for PLL-based FMCW chirp synthesizers, this dissertation focuses on digital fractional-N PLL designs based on noise-shaping TDCs that leverage state-of-the-art delta-sigma modulator techniques to achieve low close-in phase noise in wide-bandwidth digital PLLs. First, an analysis of the PLL bandwidth and chirp linearity studies the design requirements for chirp synthesizer PLLs. Based on a model of a complete radar system, the analysis examines the impact of the PLL bandwidth on the radar performance. The modeling approach allows for a straightforward study of the radar accuracy and reliability as functions of the chirp parameters and the PLL configuration. Next, an 18-to-22GHz chirp synthesizer PLL that produces a 25-segment chirp for a 240GHz FMCW radar application is described. This synthesizer design adapts an existing third-order noise-shaping TDC design. A 65nm CMOS prototype achieves a measured close-in phase noise of -88dBc/Hz at 100kHz offset for wide PLL bandwidths and consumes 39.6mW. The prototype drives a radar testbed to demonstrate the effectiveness of the synthesizer design in a complete radar system. Finally, a second-order noise-shaping TDC based on a fourth-order bandpass delta-sigma modulator is introduced. This bandpass delta-sigma TDC leverages the high resolution of a bandpass delta-sigma modulator by sampling a sinusoidal PLL reference and applies digital down-conversion to achieve low TDC noise in the frequency band of interest. Based on the bandpass delta-sigma TDC, a 38GHz digital FMCW chirp synthesizer PLL is designed. The feedback divider applies phase interpolation with a phase rotation scheme to ensure the effectiveness of the low TDC noise. A prototype PLL, fabricated in 40nm CMOS, achieves a measured close-in phase noise of -85dBc/Hz at 100kHz offset for wide loop bandwidths >1MHz and consumes 68mW. It effectively generates fast (500MHz/55us) and precise (824kHz rms frequency error) triangular chirps for FMCW radar. The bandpass delta-sigma TDC achieves a measured integrated rms noise of 325fs in a 1MHz bandwidth.