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Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform

dc.contributor.authorAjayi, Tutu
dc.contributor.authorCherivirala, Yaswanth
dc.contributor.authorKwon, Kyumin
dc.contributor.authorKamineni, Sumanth
dc.contributor.authorSaligane, Mehdi
dc.contributor.authorFayazi, Morteza
dc.contributor.authorGupta, Shourya
dc.contributor.authorChen, Chien-Hen
dc.contributor.authorSylvester, Dennis
dc.contributor.authorBlaauw, David
dc.contributor.authorDreslinski, Ronald
dc.contributor.authorCalhoun, Benton
dc.contributor.authorWentzloff, David
dc.date.accessioned2021-01-16T20:10:37Z
dc.date.available2021-01-16T20:10:37Z
dc.date.issued2020-08-16
dc.identifier.urihttps://hdl.handle.net/2027.42/165331
dc.description.abstractWe present FASoC, the world’s first autonomous mixed-signal SoC framework driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog blocks using a cell-based design methodology. Our approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different processes and requires no human in the loop, dramatically accelerating design time.en_US
dc.description.sponsorshipThis material is based on research sponsored by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650 18 2 7844. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon.en_US
dc.language.isoen_USen_US
dc.publisherIEEEen_US
dc.subjectAnalog synthesis, analog generator, SoC generatoren_US
dc.titleFully Autonomous Mixed Signal SoC Design & Layout Generation Platformen_US
dc.typeConference Paperen_US
dc.typePosteren_US
dc.subject.hlbsecondlevelElectrical Engineering
dc.subject.hlbsecondlevelComputer Science
dc.subject.hlbtoplevelEngineering
dc.description.peerreviewedPeer Revieweden_US
dc.contributor.affiliationumcampusAnn Arboren_US
dc.description.bitstreamurlhttp://deepblue.lib.umich.edu/bitstream/2027.42/165331/1/Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.pdf
dc.identifier.source2020 IEEE Hot Chips 32 Symposium (HCS)en_US
dc.description.filedescriptionDescription of Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.pdf : Main article
dc.description.depositorSELFen_US
dc.owningcollnameElectrical Engineering and Computer Science, Department of (EECS)


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