Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform
dc.contributor.author | Ajayi, Tutu | |
dc.contributor.author | Cherivirala, Yaswanth | |
dc.contributor.author | Kwon, Kyumin | |
dc.contributor.author | Kamineni, Sumanth | |
dc.contributor.author | Saligane, Mehdi | |
dc.contributor.author | Fayazi, Morteza | |
dc.contributor.author | Gupta, Shourya | |
dc.contributor.author | Chen, Chien-Hen | |
dc.contributor.author | Sylvester, Dennis | |
dc.contributor.author | Blaauw, David | |
dc.contributor.author | Dreslinski, Ronald | |
dc.contributor.author | Calhoun, Benton | |
dc.contributor.author | Wentzloff, David | |
dc.date.accessioned | 2021-01-16T20:10:37Z | |
dc.date.available | 2021-01-16T20:10:37Z | |
dc.date.issued | 2020-08-16 | |
dc.identifier.uri | https://hdl.handle.net/2027.42/165331 | |
dc.description.abstract | We present FASoC, the world’s first autonomous mixed-signal SoC framework driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog blocks using a cell-based design methodology. Our approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different processes and requires no human in the loop, dramatically accelerating design time. | en_US |
dc.description.sponsorship | This material is based on research sponsored by Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA) under agreement number FA8650 18 2 7844. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Analog synthesis, analog generator, SoC generator | en_US |
dc.title | Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform | en_US |
dc.type | Conference Paper | en_US |
dc.type | Poster | en_US |
dc.subject.hlbsecondlevel | Electrical Engineering | |
dc.subject.hlbsecondlevel | Computer Science | |
dc.subject.hlbtoplevel | Engineering | |
dc.description.peerreviewed | Peer Reviewed | en_US |
dc.contributor.affiliationumcampus | Ann Arbor | en_US |
dc.description.bitstreamurl | http://deepblue.lib.umich.edu/bitstream/2027.42/165331/1/Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.pdf | |
dc.identifier.source | 2020 IEEE Hot Chips 32 Symposium (HCS) | en_US |
dc.description.filedescription | Description of Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform.pdf : Main article | |
dc.description.depositor | SELF | en_US |
dc.owningcollname | Electrical Engineering and Computer Science, Department of (EECS) |
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