Implementations of Low-Power uProcessor System for Miniaturized IoT Applications

Abstract

Thanks to technical progress in integrated circuits, dominant computing classes have shrunk in size throughout the history of computing. As a result, handheld portable devices have the largest market volume among all the computer classes to date. In view of this miniaturizing trend, it is likely that millimeter-scale computers become the next widely used computer class. Miniaturized wireless sensing devices will be enablers for the Internet of Things (IoT), including many practical applications such as health monitoring and industrial sensing. Due to the small form factor, however, these types of devices have limited battery size and capacity, therefore energy efficient operation is a key requirement. Also, they are used in a wide range of environments leading to varying operating conditions, with different performance requirements across time. Consequently, dynamic and/or application-specific power management techniques are necessary for these types of devices. In this context, this dissertation focuses on implementing low-power μprocessor systems with novel power management techniques for miniaturized wireless sensors to achieve energy efficiency and extend their lifetime.

First, this dissertation presents a dynamic power management technique for the IoT μprocessor, which enables on-chip closed-loop minimum-energy-point tracking and hence guarantees energy-optimal operation at all times. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the implemented system dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware overhead. Secondly, this dissertation presents a µprocessor system designed for use in mm-scale sensing platforms for high temperature applications. It features a deep sleep-mode that allows the complete system to retain full 16-kB SRAM contents with 0.54µW at 125˚C, which is 26× lower than the baseline design. A custom SRAM was designed and used for low leakage. The last two parts present essential sub-blocks required for low-power μprocessor systems: a wide-range level converter and a switched-capacitor DC-DC converter. Since the low-power digital systems often employ sub-threshold or near-threshold design techniques, a wide-range level converter is needed to interface between the blocks. By using the leakage biasing technique, the proposed level converter offers robust operation across a wide range of low and high supply voltages as well as PVT variations. An integrated DC-DC converter is also necessary for the low-power digital systems to support multiple power domains. In this dissertation, a switched-capacitor DC-DC generation tool is presented as a part of efforts in analog design automation. Based on the theoretical analyses, the proposed DC-DC generation tool directly finds the optimal design parameters and generates a netlist and its layout automatically from the given input specifications.