CMOS mm-Wave Digital Beamformer Receiver with Parallelized Continuous-Time Band-Pass Delta-Sigma ADCs

Abstract

Large-scale beamforming is an essential technology for emerging wireless communication systems. Beamforming mitigates the significant path loss at the mm-wave frequencies, enables spatial filtering, multiplexing, and substantially relaxes the TX power and RX sensitivity requirements. Although there has been significant progress on analog mm-wave beamforming, there are relatively few works on integrated digital-beamforming systems. Digital beamforming offers superior beam-pattern accuracy, inherent flexibility, fast steering, and the ability to generate multiple, simultaneous beams without duplicating frontend circuitry. However, there are several significant challenges to implementing a practical mm-wave digital beamforming system: 1) element-ADC performance is a performance bottleneck, especially the linearity; 2) sensitive mm-wave and analog signal lines are susceptible to local crosstalk from high-speed, high-swing digital buses; 3) enormous raw data rates demand high-speed and high-throughput digital processing; and 4) power and area are strict design constraints and therefore low-power and compact receiver slices are essential. In this thesis, we address these challenges. First, we introduce the concept of a parallelized ADC using the multi-phase-sampling technique. The parallel elemental multi-phase-sampling sub-ADC array not only improves SNDR but also provides inherent FIR filtering. The measured parallel ADC SNDR improves by 7dB thanks to harmonic suppression, thermal noise averaging, and reduced jitter sensitivity. Second, we present a prototype 16-element 1GHz IF digital beamformer with parallel element sub-ADC arrays. The accurate measured beam-patterns confirm the advantages of digital beamforming, and the measured 77dB SFDR proves the harmonic suppression from the multi-phase-sampling technique. Third, we report a 16-element fully integrated 28GHz digital beamformer, combined with a custom 8-layer LTCC substrate incorporating a 4x4 patch antenna array for a fully integrated 16-element single-chip 28GHz mm-wave-to-digital beamforming system. The inductor-less mm-wave frontend and 4x parallel continuous-time band-pass delta-sigma ADC arrays enable compact mm-wave-to-digital conversion. Direct ADC sampling of a high 1GHz IF facilitates single-phase mm-wave LO distribution and moves the I/Q mixing into the digital domain. Optimum bump and RX slice placement shorten both LO and mm-wave signal routing and reduce signal loss. The prototype generates four independent, simultaneous beams. Over-the-air measurements confirm accurate 3D beam-patterns, indicate a measured overall noise figure of 7dB, and QAM-4 EVM of -18dB. Fourth, we introduce a frequency-interleaving technique to expand the element continuous-time band-pass delta-sigma modulator ADC bandwidth. The prototype 28nm CMOS chip achieves measured SNDR/ SFDR of 37dB/44dB at 300MHz BW, supporting a high input frequency of 1.5GHz while consuming only 38mW. This work demonstrates that frequency-interleaving breaks the power-bandwidth barrier of CT DSMs. Finally, we discuss the advantages and challenges of a tiled beamforming system to support even more elements in future beamforming systems.