Analog In-Memory Computing on Non-Volatile Crossbar Arrays

Abstract

Analog compute-in-memory with resistive random-access memory (ReRAM) devices promises to overcome the data movement bottleneck in data-intensive AI and machine learning. ReRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMM), which is a vital operation in these applications. First, we introduce analog compute-in-memory on non-volatile crossbar arrays. Significant challenges exist towards building a complete system to achieve efficient analog VMM. We discuss the challenges at the device, mixed-signal circuit, and system levels. We provide an overview of non-volatile memory technology suited for analog compute-in-memory applications. Finally, we contrast digital and analog crossbar implementations. Second, we demonstrate the first complete, fully integrated analog-ReRAM CMOS coprocessor. A passive 54x108 ReRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the ReRAM crossbar. The single-chip CMOS prototype includes a RISC processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface to the passive ReRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18µm CMOS prototype with a post-processed ReRAM array demonstrates several key functions of machine learning including online learning. The mixed-signal core consumes 64mW at an operating frequency of 148MHz. The total system power consumption, considering the mixed-signal circuitry, the digital processor, and the passive ReRAM array is 307mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W. Finally, we demonstrate a 65nm CMOS RISC-V-based DNN accelerator SoC with four integrated ReRAM CIM macros. We tackle the current state of the art on multiple fronts including 8-bit ADC-assisted bit-serial processing for high throughput and energy efficiency, and CIM macro mixed-signal circuit design for full characterization of foundry integrated low-current multi-level ReRAM. For demonstration, we train and map the LeNet 1 DNN architecture onto ReRAM devices on a single chip and run inference. This SoC achieves 14.63 TOPS/W maximum efficiency and 96.8% classification accuracy on the MNIST dataset.