Towards Free, Open, and Ubiquitous Hardware Design

Abstract

In 1965, Gordon Moore posited that the number of transistors on an integrated circuit would double every 18 months. With some adjustments, the prediction largely remained true for decades and revolutionized technology as we know it. A lesser-known contributor to Moore's Law was the “Mead and Conway Revolution'' in VLSI, initiated by Carver Mead and Lynn Conway. Prior to this revolution, integrated circuit design was mostly done manually and required deep expertise from top-level integration all the way down to fabrication effects. Mead and Conway transformed this manufacturing knowledge into a set of design rules which were fit for use in automation. This innovation enabled integrated circuit design to scale with computers rather than humans, and effectively kick-started the electronic design automation (EDA) industry.

Moore's Law is reaching a slow but inevitable end as transistor counts take longer and longer to double. Because chips can no longer rely on foundry improvements to improve performance, architectural innovations need to pick up the slack. Certain domains such as machine learning, genomics, graph processing, drug discovery, financial trading, and others have turned to hardware acceleration. EDA software has not seen such focus and is at risk of stagnating chip development. In this dissertation, I discuss key issues limiting the pace of innovation in hardware design, including complexity of design integration, inaccessibility of EDA tools, and lagging EDA tool performance. Then, I present three of my works which address these issues: Celerity, OpenROAD, and SpeEDAr. These works represent a multi-faceted approach to speed up design innovation by improving design methodologies, providing open-source EDA tooling, and improving end-to-end EDA tool performance.

Celerity addresses the issue of long hardware design schedules and integration of complex systems-on-chip (SoCs). Methodologies are presented which sped up chip development to 9 months: approximately half of a normal design schedule. At the time of publication, the resulting chip design produced a single-chip record 695 Giga RISC-V instructions/s, a record CoreMark benchmark score of 825,320 and a record CoreMark score/MHz of 580.25. Celerity outperformed prior manycore works in energy efficiency by 4.2× and normalized area efficiency by 1.8×.

OpenROAD tackles the long-standing issue of closed-source EDA software. OpenROAD is the first and only open-source EDA software capable of producing design-rule-clean chips in advanced sub-20nm nodes. OpenROAD also includes the OpenROAD Design Suite, a diverse EDA benchmarking suite composed of real-world designs. To date, OpenROAD has enabled over 100 designs to be taped out, including by many designers with no prior chip design experience.

Lastly, I present a characterization of OpenROAD. This is the first known full EDA flow characterization to date. This characterization reveals that the implementation flow runtime is dominated by detailed routing (40%) and synthesis (30%). I then present SpeEDAr, an accelerator for detailed routing which accounts for the detailed router's unique costing while prior work does not. SpeEDAr achieves a mean 67× speedup on the detailed router's graph search, which translates to a mean 1.2× end-to-end flow speedup.