Quantitative Measurement and Development of Back-end Processing System-on-Chip for the Pixelated CdZnTe Detector

Abstract

CdZnTe (CZT) detector technology using pixelated anodes is a promising alternative to High-purity Germanium (HPGe) detectors in gamma-ray spectroscopy. Our research group at the University of Michigan has demonstrated that these 3-dimensional positions sensitive (3-D) CZT detectors can achieve close to HPGe energy resolution at room temperatures. Aside from the energy resolution, the detection efficiency is also of great importance. The efficiency characteristics of CZT detector using Integrated Detector Electronics AS (IDEAS) VAS/TAT ASIC system and Brookhaven National Laboratory (BNL)’s analog ASIC have been investigated previously, and the first half of this work focused on the efficiency characteristics of the latest digital ASIC-based CZT detector systems.

The intrinsic detection efficiency of a 20mm×20mm×15mm CZT detector from 59 keV to 2614 keV was measured and compared with simulation results. A detailed simulation package modelling the physical processes, digital readout electronics and event reconstruction has been developed to explain the mismatch between measurements and simulations, in order to diagnose the cause of the efficiency deficit. Several efficiency loss mechanisms are revealed. The efficiency loss due to the guard ring and anode side inaccurate reconstruction are the most important factors. Other miscellaneous efficiency loss mechanisms were investigated too. This study presents the most accurate efficiency benchmark experiment on the digital ASIC-based CZT detector. It is the first in-depth study on the efficiency response of 3-D CZT detectors, including near pixel effects.

The hardware design of current detectors are based on the concept of “system on board”. The discrete electrical components are integrated on the board-level. The dimension of the assembled systems and the overall power consumption are usually not optimal. With careful engineering, the disadvantages of ”system-on-board” can be minimized, but after all, these hardware are not tailored to the specific application. The room for further improvement and optimization are limited. Similar to how any modern technologies evolve, the constant desire to increase the performance, decrease the physical dimension and reduce the power consumption require higher-level integration. The “system-on-chip” (SoC), where components are integrated on a single silicon die, becomes the most suitable solution for the next-generation radiation detector.

A back-end data processing SoC for 3-D CZT detector has been designed at University of Michigan (UM) and named as the DAQ/DSP ASIC. The SoC methodology provides the convenience to combine different circuit and processing functionalities together on a single piece of silicon, therefore provides extra room for power-performance-area (PPA) improvement. The area of the final silicon die is 4.32mm×4.32mm and it is packaged into a 60-pin QFN package. An ASIC design workflow and the script system were built around various design software programs. The workflow covers the full life cycle of the ASIC design and can be used in the future projects. Two hardware platforms and a data acquisition software are developed to test the fabricated DAQ/DSP ASIC. Several problems have been identified during the test. Their causes are understood with the help of simulation and will be corrected in the next design iteration.