Investigation of p-type Oxide Semiconductor Thin Film Transistors for Complementary Metal Oxide Semiconductor Technologies

Abstract

Today we are living through the fourth industrial revolution with new innovative technologies such as artificial intelligence, internet of things, autonomous robots, and other technologies. With the advent of these new technologies, the development of hardware needed to support them becomes ever more important. It requires not only the continuous advancement of conventional Si-based computing technology but also the flexibility to support novel technologies. To enable the continuous development of hardware technology, thin film electronics – especially, thin film transistors or TFTs – that are characterized by large area deposition, low temperature processing, as well as low complexity and cost are being actively investigated. Oxide semiconductors are a promising material for these TFT applications. Their unique properties such as wide bandgap, which leads to low leakage current, high breakdown voltage, and optical transparency, enable them to be used in new application areas. While n-type oxide semiconductors have been commercialized in display backplanes and are a quite mature technology, the absence of p-type oxide semiconductor TFTs with performance equivalent to n-type TFTs limits the further development of oxide semiconductor technology. Cuprous oxide (Cu2O) is a well-known p-type oxide with high mobility up to 100 cm2V−1s−1 and wide bandgap of ~2.6 eV. Building on this context, in this thesis p-type Cu2O thin film transistors were investigated for complementary metal-oxide semiconductor device technologies. In general, TFT performance can be improved by reducing the TFT non-idealities and making the thin film itself have high mobility. Using RF-sputtered Cu2O, I first investigated device-level issues to understand what limits device performance. The Cu2O TFT performance was limited by high contact resistance and high interface traps/bulk defects. Second, to increase the mobility of the Cu2O thin film itself, the hole scattering mechanisms were studied. I found that in polycrystalline Cu2O thin films, the hole mobility is mainly limited by neutral impurity and grain boundary scattering. Third, since process temperature is an important factor in determining the film’s electrical properties, I studied the effect of various Cu2O thin film processes on the electrical properties, given a constrained thermal budget. Finally, since the Hall mobility of the Cu2O thin film is already ~10 cm2V−1s−1 while field effect mobility is << 1 cm2V−1s−1, I proposed methods to address the device issues identified earlier. To reduce the ohmic contact resistance to p-type Cu2O, a nitrogen-doped Cu2O source/drain interlayer was introduced. Since nitrogen is a p-type dopant in Cu2O, the addition of this layer alleviates Fermi-level pinning. In addition, dielectric engineering was performed to evaluate the interface trap density with high-k dielectrics, using both bottom gate and top gate TFT architectures. Furthermore, the effect of passivation of the Cu2O TFT on back-channel defects and device stability was investigated.