Exploiting Reconfiguration and Co-Design for Domain-Agnostic Hardware Acceleration

Abstract

Hardware accelerators have become permanent features in the post-Dennard computing landscape, displacing conventional processors for a variety of applications. Not only have semiconductor power and performance limitations become more stringent, but the demand for computing power has accelerated at an unprecedented pace. Data and compute-intensive application domains -- such as machine learning, vision, and bioinformatics -- require processing power orders of magnitude greater than what general-purpose processors can provide. The requirements of emerging applications, in conjunction with the limitations associated with conventional processors, have resulted in industry-wide efforts to develop new application-specific integrated circuit (ASIC) designs. Nevertheless, conventional ASIC accelerators sacrifice programmability for the sake of performance and energy-efficiency -- a non-ideal state of affairs.

To address the problems above, this thesis introduces an end-to-end hardware-software concept for a semi-specialized accelerator that retains ASIC-like characteristics without sacrificing software programmability. In particular, we propose hardware-software co-design techniques to (1) exploit workload characteristics in programmable accelerators via rapid hardware reconfiguration, and (2) develop a compiler stack that generates optimized, auto-parallelized application kernels.

Chapter I discusses why hardware acceleration is needed, the current landscape of ASIC and general-purpose processor hardware, and identifies challenges associated with building accelerators that are both programmable and efficient. Chapter II introduces an initial design concept for a rapidly-reconfigurable programmable accelerator, and discusses challenges associated with the paradigm. Based on learnings from Chapter II, Chapter III proposes key enhancements to improve performance and resolve key hardware bottlenecks, and presents results from a fabricated prototype chip. Chapter IV discusses software development challenges inherent with our hardware approach, and introduces an end-to-end optimizing compiler to automatically generate kernels that exploit the proposed accelerator architecture.