Circuits and Techniques for Cell-based Analog Design Automation of Low Dropout Regulators

Abstract

As semiconductor technology advances, circuit design becomes more difficult due to increased short channel effects and low breakdown voltages of FETs. In addition, as we move to FinFET technologies there are additional layout constraints, added due to complex lithography techniques like double/quad patterning and separate exposure masks for minimum features, making the manual layout process more time consuming. While digital CAD tools can automatically synthesize a digital design from a Verilog description and then automatically generate the layout (gds file), analog circuit design and layout generation remains a significant bottleneck for automating the design of complete system on chips (SoCs). An automated design and implementation flow for analog circuits, similar to that of standard digital flow (digital synthesis and auto place/route) would greatly improve the SoC design efficiency and reduce implementation cycle times from months to only a few hours.

This work focuses on implementing an LDO Generator tool which can automatically output a low dropout regulator (LDO) design based on user specifications and automatically place/route the design to output the LDO layout (gds file) for a given process design kit (PDK). The key idea in implementing this tool is to identify the analog functionalities required to achieve voltage regulation and push these analog functionalities to smallest circuit structures (called auxiliary cells). These auxiliary cells can be used as building blocks of the LDO design. Once the auxiliary cells are defined for the LDO, we use the standard digital flow to implement different LDO designs and characterize their post-pex performance (model generation). Based on these models, we then automate the layout generation of a LDO that meet the user input specifications.

To implement a synthesizable LDO, we adopted the digital LDO architecture as the baseline design, which uses an array of small power transistors that operate as current switches. The use of power transistors as current switches facilitates low VDD power management and process scalability which makes digital LDOs a potential candidate for power management especially in lower technology nodes. In addition to the power transistor array, we have used a clocked comparator that could be implemented using only standard digital cells. With the “Current Switch” and the “Comparator” as the auxiliary cells, and a bidirectional shift register as the LDO controller, an automatic LDO Generator tool was developed. However only the DC specifications (Vin, Vref, maximum load current & dropout) can be synthesized using the baseline design.

In addition, a synthesizable PID controller has been proposed and demonstrated in this work to improve the transient performance of a digital LDO. This synthesizable PID controller architecture is used to automate an LDO design from transient specifications (maximum undershoot/overshoot, minimum transient time & output capacitance). Furthermore, a hybrid LDO architecture with integrated analog control loop is proposed to enhance the PSRR performance of the LDO and realize a universal LDO architecture.